UCC27517AQDBVRQ1 [TI]
Single-Channel High-Speed Low-Side Gate Driver (with 4-A Peak Source and Sink); 单通道高速低侧栅极驱动器（具有4 -A峰值源和汇）
| 型号： | UCC27517AQDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single-Channel High-Speed Low-Side Gate Driver (with 4-A Peak Source and Sink) |
| 文件： | 总26页 (文件大小：936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC27517A-Q1
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SLVSC88A –AUGUST 2013–REVISED SEPTEMBER 2013
Single-Channel High-Speed Low-Side Gate Driver
(with 4-A Peak Source and Sink)
Check for Samples: UCC27517A-Q1
1
FEATURES
APPLICATIONS
•
•
Qualified for Automotive Applications
•
•
•
•
Automotive
AEC-Q100 Qualified With the Following
Results:
Switch-Mode Power Supplies
DC-to-DC Converters
–
–
–
Device Automotive Qualified Grade 1
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C6
Companion Gate-Driver Devices for Digital-
Power Controllers
•
•
Solar Power, Motor Control, UPS
•
Low-Cost Gate-Driver Device Offering Superior
Replacement of NPN and PNP Discrete
Solutions
Gate Driver for Emerging Wide Band-Gap
Power Devices (such as GaN)
DESCRIPTION
•
•
4-A Peak-Source and Sink Symmetrical Drive
The UCC27517A-Q1 single-channel high-speed low-
side gate-driver device effectively drives MOSFET
and IGBT power switches. With a design that
inherently minimizes shoot-through current, the
UCC27517A-Q1 sources and sinks high peak-current
pulses into capacitive loads offering rail-to-rail drive
capability and extremely small propagation delay
typically 13 ns.
Ability to Handle Negative Voltages (–5 V) at
Inputs
•
•
Fast Propagation Delays (13-ns typical)
Fast Rise and Fall Times (9-ns and 7-ns
typical)
•
•
4.5 to 18-V Single-Supply Range
Outputs Held Low During VDD UVLO (ensures
glitch-free operation at power up and power
down)
The UCC27517A-Q1 device handles –5 V at input.
The UCC27517A-Q1 provides 4-A source and 4-A
sink (symmetrical drive) peak-drive current capability
at VDD = 12 V.
•
•
•
TTL and CMOS Compatible Input-Logic
Threshold (independent of supply voltage)
Hysteretic-Logic Thresholds for High-Noise
Immunity
TYPICAL APPLICATION DIAGRAMS
Non-Inverting Input
Dual Input Design (choice of an inverting (IN–
pin) or non-inverting (IN+ pin) driver
configuration)
Q1
UCC27517A-Q1
4.5 V to 18 V
R1
V+
1
2
3
VDD
GND
IN+
OUT
5
–
Unused Input Pin can be Used for Enable
or Disable Function
C1
IN+
IN-
4
•
•
Output Held Low when Input Pins are Floating
Input Pin Absolute Maximum Voltage Levels
Not Restricted by VDD Pin Bias Supply
Voltage
Inverting Input
•
•
Operating Temperature Range of –40°C to
+140°C
Q1
UCC27517A-Q1
4.5 V to 18 V
R1
V+
1
2
3
VDD
GND
IN+
OUT
5
5-Pin DBV (SOT-23) Package Option
C1
IN-
4
VIN-
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
UCC27517A-Q1
SLVSC88A –AUGUST 2013–REVISED SEPTEMBER 2013
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DESCRIPTION (CONTINUED)
The UCC27517A-Q1 operates over a wide VDD range of 4.5 V to 18 V and wide temperature range of –40°C to
140°C. Internal Undervoltage Lockout (UVLO) circuitry on VDD pin holds the output low outside VDD operating
range. The ability to operate at low voltage levels such as below 5 V, along with best-in-class switching
characteristics, is especially suited for driving emerging wide band-gap power-switching devices such as GaN
power-semiconductor devices.
UCC27517A-Q1 features a dual-input design which offers flexibility of implementing both inverting (IN– pin) and
non-inverting (IN+ pin) configurations with the same device. Either the IN+ or IN– pin are used to control the
state of the driver output. The unused input pin is used for the enable and disable functiona. For safety purpose,
internal pullup and pulldown resistors on the input pins ensure that outputs are held low when input pins are in
floating condition. Hence the unused input pin is not left floating and must be properly biased to ensure that
driver output is in enabled for normal operation.
The input-pin threshold of the UCC27517A-Q1 device is based on TTL and CMOS compatible low-voltage logic
which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds
offers excellent noise immunity.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
UCC27517A-Q1 Product Summary
PEAK CURRENT
(SOURCE, SINK)
PART NUMBER
PACKAGE
INPUT THRESHOLD LOGIC
CMOS and TTL-Compatible
(low voltage, independent of VDD
bias voltage)
4-A, 4-A
(Symmetrical Drive)
UCC27517ADBVQ1
SOT-23, 5 pin
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ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply voltage range
OUT voltage
VDD
–0.3
20
DC
–0.3 VDD + 0.3
V
Repetitive pulse less than 200 ns(4)
IOUT_DC (source/sink)
IOUT_pulsed (source/sink)
–2 VDD + 0.3
Output continuous current
Output pulsed current (0.5 µs)
IN+, IN–(5)
0.3
4
A
V
–5
20
2500
1500
150
Human Body Model, HBM
ESD
Charged Device Model, CDM
Operating virtual junction temperature range, TJ
Storage temperature range, TSTG
–40
–65
150
°C
Soldering, 10 sec.
Reflow
300
Lead temperature
260
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device-handling procedures.
(4) Values are verified by characterization on bench.
(5) Maximum voltage on input pins is not restricted by the voltage on the VDD pin.
THERMAL INFORMATION
UCC27517A-Q1
THERMAL METRIC(1)
SOT-23 DBV
5 PINS
216
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
136.6
43.4
°C/W
ψJT
20.5
ψJB
42.6
θJCbot
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
NOTE
Under identical power dissipation conditions, the DRS package will allow to maintain a
lower die temperature than the DBV. θJA metric should be used for comparison of power
dissipation capability between different packages (Refer to the APPLICATION
INFORMATION Section).
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
–40
0
TYP
MAX
18
UNIT
V
Supply voltage range, VDD
12
Operating ambient temperature range
Input voltage, IN+ and IN–
140
18
°C
V
ELECTRICAL CHARACTERISTICS
VDD = 12 V, TA = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified
terminal.
PARAMETER
BIAS Currents
TEST CONDITION
VDD = 3.4 V
TA = 25°C
MIN
TYP
MAX UNITS
IN+ = VDD, IN– = GND
40
25
20
100
75
160
IDD(off)
Startup current
IN+ = IN– = GND or IN+ = IN– = VDD
IN+ = GND, IN– = VDD
145
115
µA
60
Under Voltage Lockout (UVLO)
3.91
3.70
4.20
4.20
4.5
VON
Supply start threshold
TA = –40°C to 140°C
4.65
V
Minimum operating
voltage after supply start
VOFF
3.45
0.2
3.9
0.3
4.35
0.5
VDD_H
Supply voltage hysteresis
Inputs (IN+, IN–)
Input signal high
threshold
Output high for IN+ pin,
Output low for IN– pin
VIN_H
VIN_L
2.2
2.4
Output low for IN+ pin,
Output high for IN– pin
V
A
Input signal low threshold
1
1.2
1
VIN_HYS Input signal hysteresis
Source/Sink Current
Source/sink peak
ISRC/SNK
CLOAD = 0.22 µF, FSW = 1 kHz
±4
current(1)
Outputs (OUT)
VDD = 12 V
IOUT = –10 mA
50
60
5
90
130
10
VDD–VO
H
High output voltage
VDD = 4.5 V
IOUT = –10 mA
mV
VDD = 12
IOUT = 10 mA
VOL
ROH
ROL
Low output voltage
VDD = 4.5 V
IOUT = 10 mA
6
12
VDD = 12 V
IOUT = –10 mA
5
7.5
11
Output pullup
resistance(2)
VDD = 4.5 V
IOUT = –10 mA
5
Ω
VDD = 12 V
IOUT = 10 mA
0.5
0.6
1
Output pulldown
resistance
VDD = 4.5 V
IOUT = 10 mA
1.2
(1) Ensured by Design.
(2) ROH represents on-resistance of P-Channel MOSFET in pullup structure of the output stage of the UCC27517A-Q1.
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ELECTRICAL CHARACTERISTICS (continued)
VDD = 12 V, TA = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified
terminal.
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNITS
Switching Time
VDD = 12 V
CLOAD = 1.8 nF
8
16
7
12
22
11
tR
Rise time(3)
VDD = 4.5 V
CLOAD = 1.8 nF
VDD = 12 V
CLOAD = 1.8 nF
tF
Fall time(3)
VDD=4.5V
7
11
ns
23
CLOAD = 1.8 nF
VDD = 12 V
5-V input pulse CLOAD = 1.8 nF
4
4
4
4
13
15
13
19
IN+ to output propagation
delay(3)
tD1
VDD = 4.5 V
5-V input pulse CLOAD = 1.8 nF
26
23
30
VDD = 12 V
CLOAD = 1.8 nF
IN– to output propagation
delay(3)
tD2
VDD = 4.5 V
CLOAD = 1.8 nF
(3) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4.
High
INPUT
(IN+ pin)
Low
High
IN- pin
Low
90%
OUTPUT
10%
tD1 tr
tD1 tf
Figure 1. Non-Inverting Configuration
(PWM Input to IN+ pin (IN– pin tied to GND))
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High
INPUT
(IN- pin)
Low
High
IN+ pin
Low
90%
OUTPUT
10%
tD2 tf
tD2 tr
Figure 2. Inverting Configuration
(PWM input to IN– pin (IN+ pin tied to VDD))
High
INPUT
(IN- pin)
Low
High
ENABLE
(IN+ pin)
Low
90%
OUTPUT
10%
tD1 tr
tD1 tf
Figure 3. Enable and Disable Function Using IN+ Pin
(Enable and disable signal applied to IN+ pin, PWM input to IN– pin)
High
INPUT
(IN+ pin)
Low
High
ENABLE
(IN- pin)
Low
90%
OUTPUT
10%
tD2 tf
tD2 tr
Figure 4. Enable and Disable Function Using IN– Pin
(Enable and disable signal applied to IN– pin, PWM input to IN+ pin)
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DEVICE INFORMATION
UCC27517A-Q1 Functional Block Diagram
VDD
IN+
3
1
5
VDD
OUT
VDD
200 kW
230 kW
IN-
4
2
VDD
GND
UVLO
UCC27517A-Q1 DBV
(Top View)
VDD
1
5
OUT
GND
IN+
2
3
IN-
4
Table 1. TERMINAL FUNCTIONS
TERMINAL
I/O
FUNCTION
PIN NUMBER
NAME
1
VDD
I
Bias supply input.
Ground. All signals reference to this pin. For the UCC27516, TI recommends to
connect pin 2 and pin 3 on PCB as close to the device as possible.
2
3
GND
–
Non-inverting input. When the driver is used in inverting configuration, connect IN+
to VDD in order to enable output, OUT held LOW if IN+ is unbiased or floating
IN+
I
Inverting input. When the driver is used in non-inverting configuration, connect IN–
to GND in order to enable output, OUT held LOW if IN– is unbiased or floating
4
5
IN–
I
OUT
O
Sourcing/Sinking current output of driver.
Table 2. Device Logic Table
IN+ PIN
IN– PIN
OUT PIN
L
L
L
H
L
L
H
L
L
L
H
L
H
x(1)
H
Any
x(1)
Any
(1) x = Floating Condition
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TYPICAL CHARACTERISTICS
STARTUP CURRENT
vs
TEMPERATURE
OPERATING SUPPLY CURRENT
vs
TEMPERATURE (Output Switching)
0.12
0.11
0.1
4
3.5
3
IN+=Low,IN−=Low
IN+=High, IN−=Low
0.09
0.08
0.07
0.06
0.05
VDD = 12 V
CLoad = 500 pF
fsw = 500 kHz
2.5
2
VDD = 3.4 V
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G001
G013
Figure 5.
Figure 6.
SUPPLY CURRENT
vs
TEMPERATURE (Output in DC On/Off condition)
UVLO THRESHOLD VOLTAGE
vs
TEMPERATURE
0.5
0.4
0.3
0.2
0.1
4.6
4.4
4.2
4
IN+=Low,IN−=Low
IN+=High, IN−=Low
UVLO Rising
UVLO Falling
3.8
3.6
VDD = 12 V
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G002
G003
Figure 7.
Figure 8.
INPUT THRESHOLD
vs
TEMPERATURE
OUTPUT PULLUP RESISTANCE
vs
TEMPERATURE
3.5
3
8
7
6
5
4
VDD = 12 V
CLoad = 1.8 nF
Turn−On
Turn−Off
RoH
2.5
2
VDD = 12 V
Iout = 10 mA
1.5
1
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G014
G004
Figure 9.
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT PULLDOWN RESISTANCE
RISE TIME
vs
vs
TEMPERATURE
TEMPERATURE
1
8
7
6
5
4
VDD = 12 V
CLoad = 1.8 nF
ROL
0.8
0.6
0.4
0.2
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G000
G000
Figure 11.
Figure 12.
FALL TIME
vs
TEMPERATURE
INPUT TO OUTPUT PROPAGATION DELAY
vs
TEMPERATURE
10
9
20
15
10
5
VDD = 12 V
CLoad = 1.8 nF
Turn−On
Turn−Off
8
7
VDD = 12 V
6
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G000
G006
Figure 13.
Figure 14.
OPERATING SUPPLY CURRENT
PROPAGATION DELAYS
vs
vs
FREQUENCY
SUPPLY VOLTAGE
20
18
16
14
12
10
8
20
18
16
14
12
10
8
VDD=4.5V
VDD=12V
VDD=15V
6
4
CLoad = 1.8 nF
Turn−On
Turn−Off
2
0
6
0
100
200
300
400
500
600
700
0
4
8
12
16
20
Frequency (kHz)
Supply Voltage (V)
G010
G007
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
RISE TIME
vs
FALL TIME
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
20
15
10
5
10
8
6
4
2
0
4
8
12
16
20
0
4
8
12
16
20
Supply Voltage (V)
Supply Voltage (V)
G008
G009
Figure 17.
Figure 18.
APPLICATION INFORMATION
Introduction
High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to
effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power-semiconductor devices. Further,
gate drivers are indispensable when there are times that the PWM controller cannot directly drive the gates of
the switching devices. With advent of digital power, this situation is often encountered because the PWM signal
from the digital controller is often a 3.3-V logic signal, which is not capable of effectively turning on a power
switch. A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in
order to fully turn on the power device and minimize conduction losses. Because traditional buffer-drive circuits
based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations, lack
level-shifting capability, the circuits prove inadequate with digital power. Gate drivers effectively combine both the
level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-
frequency switching noise by locating the high-current driver physically close to the power switch, driving gate-
drive transformers and controlling floating power-device gates, reducing power dissipation and thermal stress in
controllers by moving gate-charge power losses into itself. Finally, emerging wide-bandgap power-device
technologies, such as GaN based switches, which are capable of supporting very high switching frequency
operation, are driving very special requirements in terms of gate-drive capability. These requirements include
operation at low VDD voltages (5 V or lower), low propagation delays and availability in compact, low-inductance
packages with good thermal capability. In summary gate-driver devices are extremely important components in
switching power combining benefits of high-performance, low cost, component count and board space reduction
with a simplified system design.
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UCC27517A-Q1 Summary
The UCC27517A-Q1 gate driver represents Texas Instruments’ latest generation of single-channel low-side high-
speed gate-driver devices featuring high-source and high-sink current capability, industry best-in-class switching
characteristics and a host of other features (Table 4), all of which combine to ensure efficient, robust, and reliable
operation in high-frequency switching power circuits.
Table 3. UCC27517A-Q1 Summary
PEAK CURRENT (SOURCE,
PART NUMBER
PACKAGE
INPUT THRESHOLD LOGIC
SINK)
UCC27517ADBVQ1
SOT-23, 5 pin
CMOS and TTL-Compatible
(low voltage, independent of VDD
bias voltage)
4-A, 4-A
(Symmetrical Drive)
Table 4. UCC27517A-Q1 Features and Benefits
FEATURE
BENEFIT
High Source, Sink Current Capability
4 A, 4 A (Symmetrical)
High current capability offers flexibility in employing the UCC27517A-
Q1 to drive a variety of power switching devices at varying speeds
Best-in-class 13-ns (typ) Propagation delay
Extremely low-pulse transmission distortion
Expanded VDD Operating range of 4.5 V to 18 V
Flexibility in system design
Low VDD operation ensures compatibility with emerging wide-
bandgap power devices such as GaN
Expanded Operating Temperature range of –40°C to 140°C
(See RECOMMENDED OPERATING CONDITIONS table)
VDD UVLO Protection
Outputs are held low in UVLO condition, which ensures predictable
glitch-free operation at power up and power down
Outputs held low when input pins (INx) in floating condition
Safety feature, especially useful in passing abnormal condition tests
during safety certification
Ability of input pins to handle voltage levels not restricted by VDD pin System simplification, especially related to auxiliary bias supply
bias voltage architecture
CMOS and TTL compatible input threshold logic with wide hysteresis Enhanced noise immunity, while retaining compatibility with
in UCC27517A-Q1 (VIN_H – Well suited for slow input-voltage
signals, with flexibility to program 70% VDD, VIN_L – 30% VDD)
microcontroller logic-level input signals (3.3 V, 5 V) optimized for
digital power
Ability to handle –5 VDC at input pins
Increased robustness in noisy envirnments
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Typical Application Diagram
Typical application diagrams of the UCC27516 and UCC27517A-Q1 devices are shown in Figure 19 and
Figure 20 to illustrate use in non-inverting and inverting driver configurations.
Non-Inverting Input
Q1
UCC27517A-Q1
4.5 V to 18 V
R1
V+
1
2
3
VDD
GND
IN+
OUT
5
C1
IN+
IN-
4
Figure 19. Using Non-Inverting Input
(IN– is grounded to the enable output)
Inverting Input
Q1
UCC27517A-Q1
4.5 V to 18 V
R1
V+
1
2
3
VDD
GND
IN+
OUT
5
C1
IN-
4
VIN-
Figure 20. Using Inverting Input
(IN+ is tied to VDD enable output)
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VDD and Undervoltage Lockout
The UCC27517A-Q1 has internal Undervoltage Lockout (UVLO) protection feature on the VDD-pin supply-circuit
blocks. Whenever the driver is in UVLO condition (for example when VDD voltage is less than VON during power
up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs LOW, regardless of
the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis helps
prevent chatter when low VDD – supply voltages have noise from the power supply and also when there are
droops in the VDD-bias voltage when the system commences switching and there is a sudden increase in IDD
.
The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching
characteristics, is especially suited for driving emerging GaN wide-bandgap power-semiconductor devices.
For example, at power up, the UCC27517A-Q1 driver output remains LOW until the VDD voltage reaches the
UVLO threshold. The magnitude of the OUT signal rises with VDD until steady-state VDD is reached. In the non-
inverting operation (PWM signal applied to IN+ pin) shown in Figure 21, the output remains LOW until the UVLO
threshold is reached, and then the output is in-phase with the input. In the inverting operation (PWM signal
applied to IN– pin) shown in Figure 22 the output remains LOW until the UVLO threshold is reached, and then
the output is out-phase with the input. In both cases, the unused input pin must be properly biased to enable the
output. Note that in these devices the output turns to high-state only if IN+ pin is high and IN– pin is low after the
UVLO threshold is reached.
Because the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface-
mount components is highly recommended. A 0.1-μF ceramic capacitor should be located as close as possible to
the VDD to GND pins of the gate driver. In addition, a larger capacitor (such as 1 μF) with relatively low ESR
should be connected in parallel and close proximity, in order to help deliver the high-current peaks required by
the load. The parallel combination of capacitors should present a low impedance characteristic for the expected
current levels and switching frequencies in the application.
VDD Threshold
VDD
IN-
VDD Threshold
IN+
IN-
IN+
OUT
OUT
Figure 21. Power-Up (Non-Inverting Drive)
Operating Supply Current
Figure 22. Power-Up (Inverting Drive)
The UCC27517A-Q1 features very low quiescent IDD currents. The typical operating-supply current in
Undervoltage-Lockout (UVLO) state and fully-on state (under static and switching conditions) are summarized in
Figure 5, Figure 6 and Figure 7. The IDD current when the device is fully on and outputs are in a static state (DC
high or DC low, refer Figure 7) represents lowest quiescent IDD current when all the internal logic circuits of the
device are fully operational. The total supply current is the sum of the quiescent IDD current, the average IOUT
current due to switching and finally any current related to pullup resistors on the unused input pin. For example
when the inverting input pin is pulled low additional current is drawn from VDD supply through the pull-up
resistors (refer to DEVICE INFORMATION for the device Block Diagram). Knowing the operating frequency (fSW
and the MOSFET gate (QG) charge at the drive voltage being used, the average IOUT current can be calculated
as product of QG and fSW
)
.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias
voltages under 1.8-nF switching load is provided in Figure 15. The strikingly-linear variation and close correlation
with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device attesting to
the high-speed characteristics of IOUT
.
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Input Stage
The input pins of the UCC27517A-Q1 are based on a TTL and CMOS compatible input-threshold logic that is
independent of the VDD supply voltage. With typical high threshold = 2.2 V and typ low threshold = 1.2 V, the
logic-level thresholds can be conveniently driven with PWM-control signals derived from 3.3-V and 5-V digital-
power controllers. Wider hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL-
logic implementations, where the hysteresis is typically less than 0.5 V. These devices also feature tight control
of the input-pin threshold-voltage levels which eases system-design considerations and ensures stable operation
across temperature. The very low input capacitance on these pins reduces loading and increases switching
speed.
The device features an important safety function wherein, whenever any of the input pins are in a floating
condition, the output of the respective channel is held in the low state. This is achieved using VDD-pullup
resistors on all the inverting inputs (IN– pin) or GND-pulldown resistors on all the non-inverting input pins (IN+
pin), (refer to DEVICE INFORMATION for the device Block Diagram).
The device also features a dual-input configuration with two input pins available to control the state of the output.
The user has the flexibility to drive the device using either a non-inverting input pin (IN+) or an inverting input pin
(IN–). The state of the output pin is dependent on the bias on both the IN+ and IN– pins. Refer to the input/output
logic truth table (Table 2) and the Typical Application Diagrams, (Figure 19 and Figure 20), for additional
clarification.
Once an input pin has been chosen for PWM drive, the other input pin (the unused input pin) must be properly
biased in order to enable the output. As mentioned earlier, the unused input pin cannot remain in a floating
condition because, whenever any input pin is left in a floating condition, the output is disabled for safety
purposes. Alternatively, the unused input pin can effectively be used to implement an enable/disable function, as
explained below.
•
•
•
In order to drive the device in a non-inverting configuration, apply the PWM-control input signal to IN+ pin. In
this case, the unused input pin, IN–, must be biased low (eg. tied to GND) in order to enable the output.
–
Alternately, the IN– pin can be used to implement the enable/disable function using an external logic
signal. OUT is disabled when IN– is biased high and OUT is enabled when IN– is biased low.
In order to drive the device in an inverting configuration, apply the PWM-control input signal to IN– pin. In this
case, the unused input pin, IN+, must be biased high (eg. tied to VDD) in order to enable the output.
–
Alternately, the IN+ pin can be used to implement the enable/disable function using an external logic
signal. OUT is disabled when IN+ is biased low and OUT is enabled when IN+ is biased high.
Finally, note that the output pin is driven into a high state only when IN+ pin is biased high and IN– input is
biased low.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly-varying input signals, especially in situations where the device
is located in a mechanical socket or PCB layout is not optimal:
•
High dI/dt current from the driver output coupled with board layout parasitics causes ground bounce. Because
the device features just one GND pin, which may be referenced to the power ground, the differential voltage
between input pins and GND is modified and triggers an unintended change of output state. Because of fast
13-ns propagation delay, high-frequency oscillations ultimately occur, which increases power dissipation and
poses risk of damage.
•
•
1-V input-threshold hysteresis boosts noise immunity compared to most other industry-standard drivers.
In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1
nF) between input pin and ground very close to the driver device is necessary. This helps to convert the
differential mode noise with respect to the input-logic circuitry into common-mode noise and avoid unintended
change of output state.
If limiting the rise or fall times to the power device is the primary goal, then an external resistance is highly
recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate-driver device package and transferring the gate driver into the external resistor.
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Enable Function
As mentioned earlier, an enable or disable function is easily implemented in the UCC27517A-Q1 using the
unused input pin. When IN+ is pulled down to GND or IN– is pulled down to VDD, the output is disabled. Thus
IN+ pin is used like an enable pin that is based on active-high logic, while IN– can be used like an enable pin that
is based on active-low logic.
Output Stage
The UCC27517A-Q1 is capable of delivering 4-A source, 4-A sink (symmetrical drive) at VDD = 12 V. The output
stage of the UCC27517A-Q1 device is illustrated in Figure 23. The UCC27517A-Q1 features a unique
architecture on the output stage which delivers the highest peak-source current when most needed during the
Miller-plateau region of the power-switch turnon transition (when the power-switch drain/collector voltage
experiences dV/dt). The device output stage features a hybrid pullup structure using a parallel arrangement of N-
Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant when
the output changes state from low to high, the gate-driver device delivers a brief boost in the peak-sourcing
current enabling fast turnon.
VCC
ROH
RNMOS, Pull Up
Gate
Voltage
Boost
OUT
Anti Shoot-
Through
Circuitry
Input Signal
Narrow Pulse at
each Turn On
ROL
Figure 23. UCC27517A-Q1 Gate Driver Output Structure
The ROH parameter (see ELECTRICAL CHARACTERISTICS) is a DC measurement and is representative of the
on-resistance of the P-Channel device only, since the N-Channel device is turned on only during output change
of state from low to high. Thus the effective resistance of the hybrid pullup stage is much lower than what is
represented by ROH parameter. The pulldown structure is composed of a N-Channel MOSFET only. The ROL
parameter (see ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of true
impedance of the pulldown stage in the device. In the UCC27517A-Q1, the effective resistance of the hybrid
pullup structure is approximately 1.4 × ROL
.
The driver-output voltage swings between VDD and GND providing rail-to-rail operation because of the MOS
output stage which delivers very low dropout. The presence of the MOSFET-body diodes also offers low
impedance to switching overshoots and undershoots. This means that in many cases, external Schottky-diode
clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current
without either damage to the device or logic malfunction.
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Power Dissipation
Power dissipation of the gate driver has two portions as shown in Equation 1.
P
= P + P
DC SW
DISS
(1)
The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver. The
quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference
voltage, logic circuits, protections, and also any current associated with switching of internal devices when the
driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through
etc). The UCC27517A-Q1 features very low quiescent currents (less than 1 mA, refer Figure 7) and contains
internal logic to eliminate any shoot-through in the output-driver stage. Thus the effect of the PDC on the total
power dissipation within the gate driver can be safely assumed to be negligible.
The power dissipated in the gate-driver package during switching (PSW) depends on the following factors:
•
Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD due to low VOH drop-out).
•
•
Switching frequency.
Use of external-gate resistors.
When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias
supply is fairly easy. The energy that must be transferred from the bias supply to charge the capacitor is given by
Equation 2.
1
2
EG
=
CLOADVDD
2
Where
•
•
CLOAD is load capacitor
VDD is bias voltage feeding the driver
(2)
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by Equation 3.
2
LOAD DD SW
P
= C
V
f
G
where
•
ƒSW is the switching frequency
(3)
The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the
device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when
charging a capacitor. This is done by using the equation, QG = CLOAD x VDD, to provide the following equation for
power:
2
LOAD DD SW
P
= C
V
f
= Q V f
g DD SW
G
(4)
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This power PG is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on or
turned off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other
half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is
employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package.
With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of
driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the
higher resistance component). Based on this simplified analysis, the driver power dissipation during switching is
calculated in Equation 5.
æ
ç
è
ö
ROFF
RON
PSW = 0.5´QG ´ VDD´ fSW
´
+
÷
ROFF + RGATE RON + RGATE ø
where
•
•
ROFF = ROL
RON (effective resistance of pull-up structure) = 1.4 x ROL
(5)
Low Propagation Delays
The UCC27517A-Q1 features best-in-class input-to-output propagation delay of 13 ns (typ) at VDD = 12 V. This
promises the lowest level of pulse-transmission distortion available from industry-standard gate-driver devices for
high-frequency switching applications. As seen in Figure 14, there is very little variation of the propagation delay
with temperature and supply voltage as well, offering typically less than 20-ns propagation delays across the
entire range of application conditions.
Thermal Information
The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package is summarized in the section of the datasheet. For
detailed information regarding the thermal information table, please refer to the Application Note from Texas
Instruments entitled IC Package Thermal Metrics (SPRA953).
The UCC27517A-Q1 is offered in SOT-23, 5-pin package (DBV). The table summarizes the thermal performance
metrics related to the package. θJA metric should be used for comparison of power dissipation between different
packages. The ψJT and ψJB metrics should be used when estimating the die temperature during actual
application measurements.
The DBV package heat removal occurs primarily through the leads of the device and the PCB traces connected
to the leads.
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PCB Layout
Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27517A-Q1 gate driver incorporates short-propagation delays and
powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of
the power switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak-current capability
is even higher (4-A, 4-A peak current is at VDD = 12 V). Very high di/dt causes unacceptable ringing if the trace
lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended
when designing with these high-speed drivers.
•
Locate the driver device as close as possible to the power device in order to minimize the length of high-
current traces between the output pins and the gate of the power device.
•
Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal
trace length to improve the noise filtering. These capacitors support high-peak current being drawn from VDD
during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and
chip capacitors is highly recommended.
•
The turnon and turnoff current-loop paths (driver device, power MOSFET and VDD bypass capacitor) should
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is
established in these loops at two instances — during turnon and turnoff transients, which will induce
significant voltage transients on the output pin of the driver device and gate of the power switch.
•
•
•
Wherever possible parallel the source and return traces, taking advantage of flux cancellation.
Separate power traces and signal traces, such as output and input signals.
Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver should be connected to the other circuit nodes such as source of power switch or the ground of
PWM controller at one, single point. The connected paths should be as short as possible to reduce
inductance and be as wide as possible to reduce resistance.
•
•
Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well.
In noisy environments, tying the unused input pin of the UCC27517A-Q1 to VDD (in case of IN+) or GND (in
case of IN–) using short traces in order to ensure that the output is enabled and to prevent noise from
causing malfunction in the output is necessary.
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REVISION HISTORY
Changes from Original (August 2013) to Revision A
Page
•
Changed document status from Product Preview to Production Data ................................................................................. 1
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PACKAGE OPTION ADDENDUM
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6-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
UCC27517AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
EAGQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27517A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Sep-2013
Catalog: UCC27517A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27517AQDBVRQ1 SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Sep-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
180.0 180.0 18.0
UCC27517AQDBVRQ1
5
3000
Pack Materials-Page 2
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Single-Channel High-Speed Low-Side Gate Driver With Negative Input Voltage Capability
TI
UCC27518A-Q1_15
Single-Channel High-Speed Low-Side Gate Driver With Negative Input Voltage Capability
TI
UCC27518AQDBVRQ1
Single-Channel High-Speed Low-Side Gate Driver With Negative Input Voltage Capability
TI
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