UCC27524A1QDGNRQ1 [TI]
具有 5V UVLO 和负输入电压处理能力的汽车 5A/5A 双通道栅极驱动器 | DGN | 8 | -40 to 140;
| 型号： | UCC27524A1QDGNRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 5V UVLO 和负输入电压处理能力的汽车 5A/5A 双通道栅极驱动器 | DGN | 8 | -40 to 140 栅极驱动 驱动器 |
| 文件： | 总33页 (文件大小：2165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC27524A1-Q1
ZHCSGK8 –APRIL 2017
UCC27524A1-Q1 具有负输入电压能力的
双路 5A 高速低侧栅极驱动器
1 特性
3 说明
1
•
•
符合汽车应用 要求
具有符合 AEC-Q100 标准的下列结果：
UCC27524A1-Q1 器件是一款双通道、高速、低侧栅
极驱动器器件，能够高效地驱动金属氧化物半导体场效
应晶体管 (MOSFET) 和绝缘栅双极型功率管 (IGBT)
电源开关。UCC27524A1-Q1 器件是 UCC2752x 系列
的一个型号。为了增加稳定耐用性，UCC27524A1-Q1
器件在输入引脚上增加了直接处理 –5V 电压的能力。
UCC27524A1-Q1 器件是一款双路非反相驱动器。
UCC27524A1-Q1 器件采用的设计方案可最大程度减
少击穿电流，从而为电容负载提供高达 5A 的峰值拉/
灌电流脉冲，以及轨到轨驱动能力和极小的传播延迟
（典型值为 13ns）。除此之外，此驱动器的特性使得
两个通道间的内部传播延迟相匹配，这一特性使得此驱
动器非常适合于 诸如 同步整流器等对于双栅极驱动有
严格时间设置要求的应用。这还使得两个通道可以并
联，以有效地增加电流驱动能力或者使用一个单一输入
信号驱动两个并联开关。输入引脚阈值基于 TTL 和
CMOS 兼容低压逻辑，此逻辑是固定的并且与 VDD 电
源电压无关。高低阈值间的宽滞后提供出色的抗扰度。
–
–
器件温度 1 级
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 H2
–
器件组件充电模式 (CDM) ESD 分类等级 C4B
•
•
•
•
•
•
•
•
工业标准引脚分配
两个独立的栅极驱动通道
5A 峰值驱动源电流和灌电流
针对每个输出的独立支持功能
与电源电压无关的 TTL 和 CMOS 兼容逻辑阈值
针对高噪声抗扰度的滞后逻辑阈值
在输入端处理负电压 (-5V) 的能力
输入和允许引脚电压电平不受 VDD 引脚偏置电源电
压的限制
•
•
4.5V 至 18V 单电源供电范围
VDD 久压闭锁 (UVLO) 期间输出保持低电平（确保
加电和掉电时的无干扰运行）
•
•
•
•
•
•
•
快速传播延迟（典型值 13ns）
快速上升和下降时间（典型值 7ns 和 6ns）
两通道间的延迟匹配时间典型值为 1ns
能够并联两个高驱动电流输出
器件信息(1)
器件型号
封装
封装尺寸（标称值）
MSOP-PowerPAD
UCC27524A1-Q1
3.00mm x 3.00mm
（8）
当输入浮动时，输出保持低电平
MSOP-8 PowerPad™封装
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
-40°C 至 +140°C 的运行温度范围
Dual Non-Inverting Inputs
UCC27524A1-Q1
2 应用
ENA
INA
1
2
3
4
8
7
6
5
ENB
•
•
•
•
•
汽车
开关模式电源
OUTA
VDD
直流到直流转换器
电机控制，太阳能
GND
INB
用于诸如 GaN 等新兴宽带隙电源器件的栅极驱动
OUTB
Copyright
© 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSDH6
UCC27524A1-Q1
ZHCSGK8 –APRIL 2017
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Switching Characteristics.......................................... 6
7.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
9
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
11.3 Thermal Considerations........................................ 24
12 器件和文档支持 ..................................................... 25
12.1 社区资源................................................................ 25
12.2 商标....................................................................... 25
12.3 静电放电警告......................................................... 25
12.4 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
8
4 修订历史记录
日期
修订版本
注意
2017 年 4 月
*
初始发行版。
2
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UCC27524A1-Q1
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ZHCSGK8 –APRIL 2017
5 说明 （续）
出于保护目的，当输入引脚处于悬空状态时，UCC27524A1-Q1 期间的输入引脚上的内部上拉和下拉电阻器确保输
出被保持在低电平。UCC27524A1-Q1 器件 采用 特有使能引脚（ENA 和 ENB）以更好地控制此驱动器的运行 滤
波器的理想选择。这些引脚内部上拉至 VDD 电源以实现高电平有效逻辑运行，并且可保持断开连接状态以实现标准
运行。
UCC27524A1-Q1 器件采用 MSOP-PowerPAD-8 和暴露焊盘 (DGN) 封装。
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6 Pin Configuration and Functions
DGN Package
8-Pin MSOP-PowerPAD
Top View
ENA
INA
1
8
7
6
5
ENB
2
3
4
OUTA
VDD
GND
INB
OUTB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Enable input for Channel A: ENA is biased LOW to disable the Channel A output regardless of the INA state.
ENA is biased HIGH or left floating to enable the Channel A output. ENA is allowed to float; hence the pin-
to-pin compatibility with the UCC2732X N/C pin.
ENA
1
I
Enable input for Channel B: ENB is biased LOW to disables the Channel B output regardless of the INB
state. ENB is biased HIGH or left floating to enable Channel B output. ENB is allowed to float hence; the pin-
to-pin compatibility with the UCC2752A N/C pin.
ENB
8
I
GND
INA
3
2
-
I
Ground: All signals are referenced to this pin.
Input to Channel A: INA is the non-inverting input in the UCC27524A1-Q1 device. OUTA is held LOW if INA
is unbiased or floating.
Input to Channel B: INB is the non-inverting input in the UCC27524A1-Q1 device. OUTB is held LOW if INB
is unbiased or floating.
INB
4
I
OUTA
OUTB
VDD
7
5
6
O
O
I
Output of Channel A
Output of Channel B
Bias supply input
4
Copyright © 2017, Texas Instruments Incorporated
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ZHCSGK8 –APRIL 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–2
MAX
UNIT
V
Supply voltage
VDD
20
VDD + 0.3
VDD + 0.3
0.3
DC
V
OUTA, OUTB voltage
Repetitive pulse < 200 ns(2)
V
Output continuous source/sink current
IOUT_DC
A
Output pulsed source/sink current (0.5 µs) IOUT_pulsed
INA, INB, ENA, ENB voltage(3)
5
A
–5
20
V
Operating virtual junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Values are verified by characterization on bench.
(3) The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.
7.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX
18
UNIT
Supply voltage, VDD
4.5
–40
–2
12
V
°C
V
Operating junction temperature
Input voltage, INA, INB
140
18
Enable voltage, ENA and ENB
–2
18
V
7.4 Thermal Information
UCC27524A1-Q1
THERMAL METRIC(1)
HVSSOP (DGN)
UNIT
8 PINS
71.8
65.6
7.4
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.4
ψJB
31.5
19.6
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VDD = 12 V, TA = TJ = –40 °C to 140 °C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the
specified terminal (unless otherwise noted,)
PARAMETER
BIAS CURRENTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Startup current,
(based on UCC27524 Input
configuration)
VDD = 3.4 V, INA = VDD, INB = VDD
VDD = 3.4 V, INA = GND, INB = GND
55
25
110
75
175
145
IDD(off)
μA
UNDER VOLTAGE LOCKOUT (UVLO)
TJ = 25 °C
3.91
3.7
4.2
4.2
4.5
VON
Supply start threshold
V
TJ = –40 °C to 140 °C
4.65
Minimum operating voltage
after supply start
VOFF
3.4
0.2
3.9
0.3
4.4
0.5
V
V
VDD_H
Supply voltage hysteresis
INPUTS (INA, INB, INA+, INA–, INB+, INB–), UCC27524A1-Q1 (DGN)
Output high for non-inverting input pins
Output low for inverting input pins
VIN_H
Input signal high threshold
1.9
2.1
2.3
V
Output low for non-inverting input pins
Output high for inverting input pins
VIN_L
Input signal low threshold
Input hysteresis
1
1.2
0.9
1.4
1.1
V
V
VIN_HYS
0.7
OUTPUTS (OUTA, OUTB)
ISNK/SRC Sink/source peak current(1)
CLOAD = 0.22 µF, FSW = 1 kHz
IOUT = –10 mA
±5
A
V
V
Ω
Ω
VDD-VOH High output voltage
0.075
0.01
7.5
VOL
ROH
ROL
Low output voltage
Output pullup resistance(2)
IOUT = 10 mA
IOUT = –10 mA
2.5
5
Output pulldown resistance
IOUT = 10 mA
0.15
0.5
1
(1) Ensured by design.
(2) ROH represents on-resistance of only the P-Channel MOSFET device in the pullup structure of the UCC27524A1-Q1 output stage.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Rise time(1)
Fall time(1)
TEST CONDITIONS
CLOAD = 1.8 nF
MIN
TYP
7
MAX
18
UNIT
ns
tR
tF
CLOAD = 1.8 nF
6
10
ns
INA = INB, OUTA and OUTB at 50%
transition point
tM
Delay matching between 2 channels
1
4
ns
ns
Minimum input pulse width that
changes the output state
tPW
15
25
tD1, tD2 Input to output propagation delay(1)
tD3, tD4 EN to output propagation delay(1)
CLOAD = 1.8 nF, 5-V input pulse
CLOAD = 1.8 nF, 5-V enable pulse
6
6
13
13
23
23
ns
ns
(1) See the timing diagrams in Figure 1 and Figure 2
6
Copyright © 2017, Texas Instruments Incorporated
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ZHCSGK8 –APRIL 2017
High
Input
Low
High
Enable
Low
90%
Output
10%
tD3
tD4
UDG-11217
Figure 1. Enable Function
High
Input
Low
High
Enable
Low
90%
Output
10%
tD1
tD2
UDG-11219
Figure 2. Input-Output Operation
Copyright © 2017, Texas Instruments Incorporated
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7.7 Typical Characteristics
4
3.5
3
Input=VDD
Input=GND
0.14
0.12
0.1
VDD = 12 V
0.08
0.06
fSW = 500 kHz
CL = 500 pF
VDD=3.4V
150
2.5
−50
−50
0
50
100
0
50
100
150
Temperature (°C)
Temperature (°C)
G001
G002
Figure 3. Start-Up Current vs Temperature
Figure 4. Operating Supply Current vs Temperature
(Outputs Switching)
0.6
5
Input=GND
Input=VDD
UVLO Rising
UVLO Falling
0.5
0.4
0.3
0.2
4.5
4
3.5
3
Enable=12 V
VDD = 12 V
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G012
G003
Figure 5. Supply Current vs Temperature (Outputs In DC
On/Off Condition)
Figure 6. UVLO Threshold vs Temperature
2.5
2.5
2
2
1.5
1
VDD = 12 V
VDD = 12 V
1.5
1
Input High Threshold
Input Low Threshold
Enable High Threshold
Enable Low Threshold
0.5
−50
0.5
−50
0
50
100 150
0
50
100
150
Temperature (°C)
Temperature (°C)
G004
G005
Figure 7. Input Threshold vs Temperature
Figure 8. Enable Threshold vs Temperature
8
Copyright © 2017, Texas Instruments Incorporated
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ZHCSGK8 –APRIL 2017
Typical Characteristics (continued)
7
1
0.8
0.6
0.4
0.2
VDD = 12 V
IOUT = −10 mA
VDD = 12 V
IOUT = 10 mA
6
5
4
3
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G006
G007
Figure 9. Output Pullup Resistance vs Temperature
Figure 10. Output Pulldown Resistance vs Temperature
10
9
VDD = 12 V
CLOAD = 1.8 nF
VDD = 12 V
CLOAD = 1.8 nF
9
8
7
6
5
8
7
6
5
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G008
G009
Figure 11. Rise Time vs Temperature
Figure 12. Fall Time vs Temperature
18
18
Turn−on
Turn−off
EN to Output High
EN to Output Low
16
14
12
10
8
16
14
12
10
8
VDD = 12 V
CLOAD = 1.8 nF
VDD = 12 V
CLOAD = 1.8 nF
−50
0
50
100
150
−50
0
50
100
150
Temperature (°C)
Temperature (°C)
G010
G011
Figure 13. Input to Output Propagation Delay vs
Temperature
Figure 14. En to Output Propagation Delay vs Temperature
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Typical Characteristics (continued)
60
22
18
14
10
6
VDD = 4.5 V
VDD = 12 V
VDD = 15 V
Input to Output On delay
Input to Ouptut Off Delay
EN to Output On Delay
EN to Output Off Delay
50
40
CLOAD = 1.8 nF
Both channels switching
30
20
10
0
CLOAD = 1.8 nF
0
100 200 300 400 500 600 700 800 900 1000
Frequency (kHz)
4
8
12
16
20
Supply Voltage (V)
G013
G014
Figure 15. Operating Supply Current vs Frequency
Figure 16. Propagation Delays vs Supply Voltage
18
10
CLOAD = 1.8 nF
CLOAD = 1.8 nF
14
10
6
8
6
4
4
8
12
16
20
4
8
12
16
20
Supply Voltage (V)
Supply Voltage (V)
G015
G016
Figure 17. Rise Time vs Supply Voltage
Figure 18. Fall Time vs Supply Voltage
2.5
VDD = 4.5 V
Enable High Threshold
Enable Low Threshold
2
1.5
1
0.5
−50
0
50
100
150
Temperature (°C)
G017
Figure 19. Enable Threshold vs Temperature
10
Copyright © 2017, Texas Instruments Incorporated
UCC27524A1-Q1
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ZHCSGK8 –APRIL 2017
8 Detailed Description
8.1 Overview
The UCC27524A1-Q1 device represents Texas Instruments’ latest generation of dual-channel, low-side, high-
speed, gate-driver devices featuring a 5-A source and sink current capability, industry best-in-class switching
characteristics, and a host of other features listed in Table 1 all of which combine to ensure efficient, robust, and
reliable operation in high-frequency switching power circuits.
Table 1. UCC27524A1-Q1 Features and Benefits
FEATURE
BENEFIT
Best-in-class 13-ns (typ) propagation delay
Extremely low-pulse transmission distortion
Ease of paralleling outputs for higher (2 times) current capability,
ease of driving parallel-power switches
1-ns (typ) delay matching between channels
Expanded VDD Operating range of 4.5 to 18 V
Flexibility in system design
Expanded operating temperature range of –40 °C to +140 °C
(See Electrical Characteristics table)
Flexibility in system design
Outputs are held Low in UVLO condition, which ensures predictable,
glitch-free operation at power-up and power-down
VDD UVLO Protection
Protection feature, especially useful in passing abnormal condition
tests during safety certification
Outputs held Low when input pins (INx) in floating condition
Pin-to-pin compatibility with the UCC27324 device from Texas
Instruments, in designs where Pin 1 and Pin 8 are in floating
condition
Outputs enable when enable pins (ENx) in floating condition
Enhanced noise immunity, while retaining compatibility with
microcontroller logic-level input signals (3.3 V, 5 V) optimized for
digital power
CMOS/TTL compatible input and enable threshold with wide
hysteresis
Ability of input and enable pins to handle voltage levels not restricted System simplification, especially related to auxiliary bias supply
by VDD pin bias voltage
architecture
Ability to handle –5 VDC (max) at input pins
Increased robustness in noisy environments
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8.2 Functional Block Diagram
VDD
VDD
200 kW
200 kW
ENA
1
8
ENB
VDD
INA
OUTA
2
7
VDD
400 kW
VDD
VDD
UVLO
6
5
GND
INB
3
4
VDD
OUTB
400 kW
8.3 Feature Description
8.3.1 Operating Supply Current
The UCC27524A1-Q1 devices feature very low quiescent IDD currents. The typical operating-supply current in
UVLO state and fully-on state (under static and switching conditions) are summarized in Figure 3, Figure 4, and
Figure 5. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, see
Figure 4) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully
operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current because of
switching, and finally any current related to pullup resistors on the enable pins (see Functional Block Diagram).
Knowing the operating frequency (fSW) and the MOSFET gate (QG) charge at the drive voltage being used, the
average IOUT current can be calculated as product of QG and fSW
.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages
under 1.8-nF switching load in both channels is provided in Figure 15. The strikingly linear variation and close
correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device
attesting to its high-speed characteristics.
12
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Feature Description (continued)
8.3.2 Input Stage
The input pins of the UCC27524A1-Q1 gate-driver devices are based on a TTL and CMOS compatible input-
threshold logic that is independent of the VDD supply voltage. With typically high threshold = 2.1 V and typically
low threshold = 1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from
3.3-V and 5-V digital power-controller devices. Wider hysteresis (typ 0.9 V) offers enhanced noise immunity
compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V.
UCC27524A1-Q1 devices also feature tight control of the input pin threshold voltage levels which eases system
design considerations and ensures stable operation across temperature (refer to Figure 7). The very low input
capacitance on these pins reduces loading and increases switching speed.
The UCC27524A1-Q1 device features an important protection feature that holds the output of a channel when
the respective pin is in a floating condition. This is achieved using GND pulldown resistors on all of the non-
inverting input pins (INA, INB), as shown in the device block diagrams.
The input stage of each driver is driven by a signal with a short rise or fall time. This condition is satisfied in
typical power supply applications, where the input signals are provided by a PWM controller or logic gates with
fast transition times (<200 ns) with a slow changing input voltage, the output of the driver may switch repeatedly
at a high frequency. While the wide hysteresis offered in UCC27524A1-Q1 definitely alleviates this concern over
most other TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or
fall times to the power device is the primary goal, then an external resistance is highly recommended between
the output of the driver and the power device. This external resistor has the additional benefit of reducing part of
the gate-charge related power dissipation in the gate driver device package and transferring it into the external
resistor itself.
8.3.3 Enable Function
The enable function is an extremely beneficial feature in gate-driver devices, especially for certain applications
such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative
current circulation and to improve light-load efficiency.
The UCC27524A1-Q1 device is equipped with independent enable pins (ENx) for exclusive control of each
driver-channel operation. The enable pins are based on a non-inverting configuration (active-high operation).
Thus when ENx pins are driven high, the drivers are enabled and when ENx pins are driven low, the drivers are
disabled. Like the input pins, the enable pins are also based on a TTL and CMOS compatible, input-threshold
logic that is independent of the supply voltage and are effectively controlled using logic signals from 3.3-V and 5-
V microcontrollers. The UCC27524A1-Q1 devices also feature tight control of the enable-function threshold-
voltage levels which eases system design considerations and ensures stable operation across temperature (refer
to Figure 8). The ENx pins are internally pulled up to VDD using pullup resistors as a result of which the outputs
of the device are enabled in the default state. Hence the ENx pins are left floating or Not Connected (N/C) for
standard operation, where the enable feature is not needed. Essentially, this floating allows the UCC27524A1-Q1
device to be pin-to-pin compatible with TI’s previous generation of drivers (UCC27323, UCC27324, and
UCC27325 respectively), where Pin 1 and Pin 8 are N/C pins. If the channel A and Channel B inputs and outputs
are connected in parallel to increase the driver current capacity, ENA and ENB are connected and driven
together.
8.3.4 Output Stage
The UCC27524A1-Q1 device output stage features a unique architecture on the pullup structure which delivers
the highest peak-source current when it is most needed during the Miller plateau region of the power-switch
turnon transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pullup
structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the
N-Channel MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon. This is
accomplished by briefly turning-on the N-Channel MOSFET during a narrow instant when the output is changing
state from Low to High.
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Feature Description (continued)
VCC
ROH
RNMOS, Pull Up
Gate
Voltage
Boost
OUT
Anti Shoot-
Through
Input Signal
Circuitry
Narrow Pulse at
each Turn On
ROL
Figure 20. UCC27524A1-Q1 Gate Driver Output Structure
The ROH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the on-
resistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC
condition and is turned-on only for a narrow instant when output changes state from low to high. Note that
effective resistance of the UCC27524A1-Q1 pullup stage during the turnon instant is much lower than what is
represented by ROH parameter.
The pulldown structure in the UCC27524A1-Q1 device is simply composed of a N-Channel MOSFET. The ROL
parameter (see Electrical Characteristics), which is also a DC measurement, is representative of the impedance
of the pulldown stage in the device. In the UCC27524A1-Q1 device, the effective resistance of the hybrid pullup
structure during turnon is estimated to be approximately 1.5 × ROL, estimated based on design considerations.
Each output stage in the UCC27524A1-Q1 device is capable of supplying 5-A peak source and 5-A peak sink
current pulses. The output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the
MOS-output stage which delivers very low drop-out. The presence of the MOSFET-body diodes also offers low
impedance to switching overshoots and undershoots which means that in many cases, external Schottky-diode
clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current
without either damage to the device or logic malfunction.
The UCC27524A1-Q1 device is particularly suited for dual-polarity, symmetrical drive-gate transformer
applications where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being
driven complementary to each other. This situation is because of the extremely low drop-out offered by the MOS
output stage of these devices, both during high (VOH) and low (VOL) states along with the low impedance of the
driver output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux
imbalance. The low propagation delays also ensure accurate reset for high-frequency applications.
For applications that have zero voltage switching during power MOSFET turnon or turnoff interval, the driver
supplies high-peak current for fast switching even though the miller plateau is not present. This situation often
occurs in synchronous rectifier applications because the body diode is generally conducting before power
MOSFET is switched on.
14
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Feature Description (continued)
8.3.5 Low Propagation Delays And Tightly Matched Outputs
The UCC27524A1-Q1 driver device features a best in class, 13-ns (typical) propagation delay between input and
output which goes to offer the lowest level of pulse-transmission distortion available in the industry for high
frequency switching applications. For example in synchronous rectifier applications, the SR MOSFETs are driven
with very low distortion when a single driver device is used to drive both the SR MOSFETs. Further, the driver
devices also feature an extremely accurate, 1-ns (typical) matched internal-propagation delays between the two
channels which is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC
application, a pair of paralleled MOSFETs can be driven independently using each output channel, which the
inputs of both channels are driven by a common control signal from the PFC controller device. In this case the 1-
ns delay matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum
of turnon delay difference. Yet another benefit of the tight matching between the two channels is that the two
channels are connected together to effectively increase current drive capability, for example A and B channels
may be combined into a single driver by connecting the INA and INB inputs together and the OUTA and OUTB
outputs together. Then, a single signal controls the paralleled combination.
Caution must be exercised when directly connecting OUTA and OUTB pins together because there is the
possibility that any delay between the two channels during turnon or turnoff may result in shoot-through current
conduction as shown in Figure 21. While the two channels are inherently very well matched (4-ns Max
propagation delay), note that there may be differences in the input threshold voltage level between the two
channels which causes the delay between the two outputs especially when slow dV/dt input signals are
employed. The following guidelines are recommended whenever the two driver channels are paralleled using
direct connections between OUTA and OUTB along with INA and INB:
•
Use very fast dV/dt input signals (20 V/µs or greater) on INA and INB pins to minimize impact of differences
in input thresholds causing delays between the channels.
•
INA and INB connections must be made as close to the device pins as possible.
Wherever possible, a safe practice would be to add an option in the design to have gate resistors in series with
OUTA and OUTB. This allows the option to use 0-Ω resistors for paralleling outputs directly or to add appropriate
series resistances to limit shoot-through current, should it become necessary.
VDD
VDD
200 kW
200 kW
ENA
INA
1
2
8
7
ENB
ISHOOT-THROUGH
OUTA
VDD
Slow Input Signal
VIN_H
(Channel B)
VDD
400 kW
VIN_H
(Channel A)
VDD
VDD
UVLO
6
5
GND
INB
3
4
VDD
OUTB
400 kW
Figure 21. Slow Input Signal Can Cause Shoot-Through Between Channels During Paralleling
(Recommended DV/DT is 20 V/Μs or Higher)
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Feature Description (continued)
Figure 22. Turnon Propagation Delay
Figure 23. Turnon Rise Time
(CL = 1.8 nF, VDD = 12 V)
(CL = 1.8 nF, VDD = 12 V)
Figure 24. . Turnoff Propagation Delay
(CL = 1.8 nF, VDD = 12 V)
Figure 25. Turnoff Fall Time
(CL = 1.8 nF, VDD = 12 V)
16
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8.4 Device Functional Modes
Table 2. Device Logic Table
UCC27524A1-Q1
ENA
ENB
INA
INB
OUTA
OUTB
H
H
H
H
L
L
L
H
L
L
L
H
L
H
H
H
L
H
H
L
H
H
H
H
H
L
L
L
Any
x(1)
L
Any
x(1)
L
Any
x(1)
x(1)
x(1)
x(1)
Any
x(1)
x(1)
x(1)
x(1)
L
L
L
L
L
H
L
H
L
H
L
H
H
H
H
H
(1) Floating condition.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to
effect the fast switching of power devices and reduce associated switching-power losses, a powerful gate-driver
device employs between the PWM output of control devices and the gates of the power semiconductor devices.
Further, gate-driver devices are indispensable when it is not feasible for the PWM controller device to directly
drive the gates of the switching devices. With the advent of digital power, this situation is often encountered
because the PWM signal from the digital controller is often a 3.3-V logic signal which is not capable of effectively
turning on a power switch. A level-shifting circuitry is required to boost the 3.3-V signal to the gate-drive voltage
(such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer-drive
circuits based on NPN/PNP bipolar transistors in a totem-pole arrangement, as emitter-follower configurations,
prove inadequate with digital power because the traditional buffer-drive circuits lack level-shifting capability.
Gate-driver devices effectively combine both the level-shifting and buffer-drive functions. Gate-driver devices also
find other needs such as minimizing the effect of high-frequency switching noise by locating the high-current
driver physically close to the power switch, driving gate-drive transformers and controlling floating power-device
gates, reducing power dissipation and thermal stress in controller devices by moving gate-charge power losses
into the controller. Finally, emerging wide band-gap power-device technologies such as GaN based switches,
which are capable of supporting very high switching frequency operation, are driving special requirements in
terms of gate-drive capability. These requirements include operation at low VDD voltages (5 V or lower), low
propagation delays, tight delay matching and availability in compact, low-inductance packages with good thermal
capability. In summary, gate-driver devices are an extremely important component in switching power combining
benefits of high-performance, low-cost, component-count, board-space reduction, and simplified system design.
9.2 Typical Application
ENB
UCC27524A1-Q1
ENA
1
2
3
4
ENA
ENB
OUTA
VDD
8
7
6
5
INA
INA
V+
GND
INB
GND
INB
OUTB
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 26. UCC27524A1-Q1 Typical Application Diagram
18
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Typical Application (continued)
9.2.1 Design Requirements
When selecting the proper gate driver device for an end application, some desiring considerations must be
evaluated first in order to make the most appropriate selection. Among these considerations are VDD, UVLO,
Drive current and power dissipation.
9.2.2 Detailed Design Procedure
9.2.2.1 VDD and Undervoltage Lockout
The UCC27524A1-Q1 device has an internal undervoltage-lockout (UVLO) protection feature on the VDD pin
supply circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output
low, regardless of the status of the inputs. The UVLO is typically 4.25 V with 350-mV typical hysteresis. This
hysteresis prevents chatter when low VDD supply voltages have noise from the power supply and also when
there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase
in IDD. The capability to operate at low voltage levels such as below 5 V, along with best in class switching
characteristics, is especially suited for driving emerging GaN power semiconductor devices.
For example, at power up, the UCC27524A1-Q1 driver-device output remains low until the VDD voltage reaches
the UVLO threshold if enable pin is active or floating. The magnitude of the OUT signal rises with VDD until
steady-state VDD is reached. The operation in Figure 27 shows that the output remains low until the UVLO
threshold is reached, and then the output is in-phase with the input.
Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface
mount components is highly recommended. A 0.1-μF ceramic capacitor must be located as close as possible to
the VDD to GND pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low
ESR must be connected in parallel and close proximity, in order to help deliver the high-current peaks required
by the load. The parallel combination of capacitors presents a low impedance characteristic for the expected
current levels and switching frequencies in the application.
VDD Threshold
VDD
EN
IN
OUT
UDG-11228
Figure 27. Power-Up Non-Inverting Driver
9.2.2.2 Drive Current and Power Dissipation
The UCC27524A1-Q1 driver is capable of delivering 5-A of current to a MOSFET gate for a period of several-
hundred nanoseconds at VDD = 12 V. High peak current is required to turn the device ON quickly. Then, to turn
the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the
operating frequency of the power device. The power dissipated in the gate driver device package depends on the
following factors:
•
Gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close
to input bias supply voltage VDD due to low VOH drop-out)
•
Switching frequency
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Typical Application (continued)
•
Use of external gate resistors
Because UCC27524A1-Q1 features very low quiescent currents and internal logic to eliminate any shoot-through
in the output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be
negligible.
When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias
supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given
by Equation 1.
1
2
EG
=
CLOADVDD
2
where
•
•
CLOAD is the load capacitor
VDD2 is the bias voltage feeding the driver
(1)
20
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Typical Application (continued)
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss
given by Equation 2.
2
LOAD DD SW
P
= C
V
f
G
where
•
fSW is the switching frequency
(2)
(3)
With VDD = 12 V, CLOAD = 10 nF and fSW = 300 kHz the power loss is calculated with Equation 3.
2
= 10nF´12V ´300kHz = 0.432W
P
G
The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the
gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the
added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF
states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to
switch the device under specified conditions. Using the gate charge Qg, the power that must be dissipated when
charging a capacitor is determined which by using the equivalence Qg = CLOADVDD to provide Equation 4 for
power:
2
LOAD DD SW
P
= C
V
f
= Q V f
g DD SW
G
(4)
Assuming that the UCC27524A1-Q1 device is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at
VDD = 12 V) on each output, the gate charge related power loss is calculated with Equation 5.
P
= 2x60nC´12V ´300kHz = 0.432W
G
(5)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half
of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated
when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the
driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external
gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate
resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component).
Based on this simplified analysis, the driver power dissipation during switching is calculated as follows (see
Equation 6):
æ
ç
è
ö
÷
ø
R
R
ON
OFF
P
= 0.5´Q ´ VDD´ f ´
SW
+
SW
G
R
+ R
R
+ R
ON GATE
OFF
GATE
where
•
•
ROFF = ROL
RON (effective resistance of pullup structure) = 1.5 x ROL
(6)
In addition to the above gate-charge related power dissipation, additional dissipation in the driver is related to the
power associated with the quiescent bias current consumed by the device to bias all internal circuits such as
input stage (with pullup and pulldown resistors), enable, and UVLO sections. As shown in Figure 4, the quiescent
current is less than 0.6 mA even in the highest case. The quiescent power dissipation is calculated easily with
Equation 7.
P
= I
V
Q
DD DD
(7)
Assuming , IDD = 6 mA, the power loss is:
= 0.6 mA ´12V = 7.2mW
P
Q
(8)
Clearly, this power loss is insignificant compared to gate charge related power dissipation calculated earlier.
With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the
quiescent consumption:
P
0.432 W
G
I
~
=
= 0.036 A
DD
V
12 V
DD
(9)
21
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Typical Application (continued)
9.2.3 Application Curves
Figure 28 and Figure 29 show the typical switching characteristics of the UCC27524A1-Q1 device.
CL = 1.8 nF, VDD = 12 V
CL = 1.8 nF, VDD = 12 V
Figure 29. Typical Turnoff Waveform
Figure 28. Typical Turnon Waveform
10 Power Supply Recommendations
The bias supply voltage range for which the UCC27524A1-Q1 device is rated to operate is from 4.5 V to 18 V.
The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the
VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the
VON supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end
of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a
stress rating). Keeping a 2-V margin to allow for transient voltage spikes, the maximum recommended voltage for
the VDD pin is 18 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD_H.
Therefore, ensuring that, while operating at or near the 4.5-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below
the VOFF threshold which must be accounted for while evaluating system shutdown timing design requirements.
Likewise, at system startup, the device does not begin operation until the VDD pin voltage has exceeded above
the VON threshold.
The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin.
Although this fact is well known, recognizing that the charge for source current pulses delivered by the OUTA/B
pin is also supplied through the same VDD pin is important. As a result, every time a current is sourced out of the
output pins, a corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that
local bypass capacitors are provided between the VDD and GND pins and located as close to the device as
possible for the purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is a must. TI
recommends having 2 capacitors; a 100-nF ceramic surface-mount capacitor which can be nudged very close to
the pins of the device and another surface-mount capacitor of few microfarads added in parallel.
22
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11 Layout
11.1 Layout Guidelines
Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device
operation and design robustness. The UCC27524A1-Q1 gate driver incorporates short propagation delays and
powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of
power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is
even higher (5-A peak current is at VDD = 12 V). Very high di/dt causes unacceptable ringing if the trace lengths
and impedances are not well controlled. The following circuit layout guidelines are strongly recommended when
designing with these high-speed drivers.
•
Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the output pins and the gate of the power device.
•
Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal trace
length to improve the noise filtering. These capacitors support high peak current being drawn from VDD during
turnon of power MOSFET. The use of low inductance surface-mounted-device (SMD) components such as
chip resistors and chip capacitors is highly recommended.
•
The turnon and turnoff current loop paths (driver device, power MOSFET and VDD bypass capacitor) must be
minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established
in these loops at two instances during turnon and turnoff transients which induces significant voltage
transients on the output pin of the driver device and Gate of the power MOSFET.
•
•
•
Wherever possible, parallel the source and return traces to take advantage of flux cancellation
Separate power traces and signal traces, such as output and input signals.
Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM
controller at one, single point. The connected paths must be as short as possible to reduce inductance and
be as wide as possible to reduce resistance.
•
•
Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well
Exercise caution when replacing the UCC2732x/UCC2742x devices with the UCC27524A1-Q1 device:
–
–
The UCC27524A1-Q1 device is a much stronger gate driver (5-A peak current versus 4-A peak current).
The UCC27524A1-Q1 device is a much faster gate driver (13-ns/13-ns rise and fall propagation delay
versus 25-ns/35-ns rise and fall propagation delay).
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UCC27524A1-Q1
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11.2 Layout Example
Power stage
current
Output loop of driver
bias
loop
(bypass capacitor)
Figure 30. UCC27524A1-Q1 Layout Example
11.3 Thermal Considerations
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a gate driver device to be useful over a particular temperature
range the package must allow for the efficient removal of the heat produced while keeping the junction
temperature within rated limits. For detailed information regarding the thermal information table, please refer to
Application Note from Texas Instruments entitled, Semiconductor and IC Package Thermal Metrics (SPRA953).
Among the different package options available for the UCC27524A1-Q1 device, power dissipation capability of
the DGN package is of particular mention. The HVSSOP-8 (DGN) package offers a means of removing the heat
from the semiconductor junction through the bottom of the package. This package offers an exposed thermal pad
at the base of the package. This pad is soldered to the copper on the printed circuit board directly underneath
the device package, reducing the thermal resistance to a very low value. This allows a significant improvement in
heat-sinking over that available in the D package. The printed circuit board must be designed with thermal lands
and thermal vias to complete the heat removal subsystem. Note that the exposed pads in the HVSSOP-8
package are not directly connected to any leads of the package, however, the PowerPAD is electrically and
thermally connected to the substrate of the device which is the ground of the device. TI recommends to
externally connect the exposed pads to GND in PCB layout for better EMI immunity.
24
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12 器件和文档支持
12.1 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.2 商标
PowerPad, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
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版权 © 2017, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC27524A1QDGNRQ1
ACTIVE
HVSSOP
DGN
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 140
7524
Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27524A1QDGNRQ1 HVSSOP DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HVSSOP DGN
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
UCC27524A1QDGNRQ1
8
2500
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DGN 8
3 x 3, 0.65 mm pitch
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE PACKAGE
C
5.05
4.75
TYP
A
0.1 C
SEATING
PLANE
PIN 1 INDEX AREA
6X 0.65
8
1
2X
3.1
2.9
1.95
NOTE 3
4
5
0.38
8X
0.25
3.1
2.9
0.13
C A B
B
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95
9
1.1 MAX
8
0.15
0.05
1
0.7
0.4
0 -8
A
20
DETAIL A
TYPICAL
1.846
1.646
4225480/B 12/2022
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK
(1.57)
SOLDER MASK
DEFINED PAD
SYMM
8X (1.4)
(R0.05) TYP
8
8X (0.45)
1
(3)
NOTE 9
SYMM
(1.89)
9
(1.22)
6X (0.65)
5
4
(
0.2) TYP
VIA
SEE DETAILS
(0.55)
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4225480/B 12/2022
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
DGN0008G
PowerPADTM VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
(R0.05) TYP
8X (1.4)
8
1
8X (0.45)
(1.89)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
5
4
METAL COVERED
BY SOLDER MASK
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
(4.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
1.76 X 2.11
1.57 X 1.89 (SHOWN)
1.43 X 1.73
0.125
0.15
0.175
1.33 X 1.60
4225480/B 12/2022
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
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