UCC27538 [TI]
2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver;
| 型号： | UCC27538 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver 栅 双极性晶体管 |
| 文件： | 总37页 (文件大小：1035K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
www.ti.com
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
2.5-A and 5-A, 35-VMAX VDD FET and IGBT Single-Gate Driver
Check for Samples: UCC27531 , UCC27533, UCC27536 , UCC27537, UCC27538
1
FEATURES
APPLICATIONS
•
Low Cost Gate Driver (offering optimal
solution for driving FET and IGBTs)
•
•
•
•
•
•
•
Switch-Mode Power Supplies
DC-to-DC Converters
•
Superior Replacement to Discrete Transistor
Pair Drive (providing easy interface with
controller)
Solar Inverters, Motor Control, UPS
HEV and EV Chargers
Home Appliances
•
•
•
TTL and CMOS Compatible Input Logic
Threshold, (independent of supply voltage)
Renewable Energy Power Conversion
SiC FET Converters
Split Output Options Allow for Tuning of Turn-
On and Turn-Off Currents
DESCRIPTION
Inverting and Non-Inverting Input
Configurations
The UCC2753x family of devices are single-channel,
high-speed, gate drivers capable of effectively driving
MOSFET and IGBT power switches by up to 2.5-A
source and 5-A sink (asymmetrical drive) peak
current. Strong sink capability in asymmetrical drive
boosts immunity against parasitic Miller turn-on effect.
The UCC2753x device can also feature a split-output
configuration where the gate-drive current is sourced
through OUTH pin and sunk through OUTL pin. This
pin arrangement allows the user to apply independent
turn-on and turn-off resistors to the OUTH and OUTL
pins respectively and easily control the switching slew
rates.
•
•
Enable with Fixed TTL Compatible Threshold
High 2.5-A Source and 2.5-A or 5-A Sink Peak
Drive Currents at 18-V VDD
•
•
Wide VDD Range From 10 V up to 35 V
Input and Enable Pins Capable of
Withstanding up to -5-V DC Below Ground
•
Output Held Low When Inputs are Floating or
During VDD UVLO
•
•
Fast Propagation Delays (17-ns typical)
Fast Rise and Fall Times
(15-ns and 7-ns typical with 1800-pF Load)
The driver has rail-to-rail drive capability and
extremely small propagation delay typically 17 ns.
•
•
Under Voltage Lockout (UVLO)
The input threshold of UCC2753xDBV is based on
TTL and CMOS compatible low-voltage logic, which
is fixed and independent of VDD supply voltage. The
1-V typical hysteresis offers excellent noise immunity.
Used as a High-Side or Low-Side Driver (if
designed with proper bias and signal isolation)
•
•
•
Low Cost, Space Saving 5-Pin or 6-Pin DBV
(SOT-23) Package Options
The driver has EN pin with fixed TTL compatible
threshold. EN is internally pulled up; pulling EN low
disables driver, while leaving it open provides normal
operation. The EN pin can be used as an additional
input with the same performance as the IN, IN+, IN1,
and IN2 pins.
UCC27536 and UCC27537 Pin-to-Pin
compatible to TPS2828 and TPS2829
Operating Temperature Range of -40°C to
140°C
UCC2753x (top view)
UCC27531
UCC27533
UCC27536
UCC27537
UCC27538
EN
IN
1
2
3
6
5
OUTH VDD
1
2
3
5
OUT EN
GND
1
2
3
5
VDD
EN
GND
IN+
1
2
3
5
1
2
3
6
5
OUTH
IN2
VDD VDD
GND
OUTL
IN1
VDD
OUT
OUT GND
4
GND
IN+
4
IN-
IN-
4
4
4
OUTL
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION(CONT.)
Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the
application diagram, timing diagram and input and output logic truth table.
Internal circuitry on VDD pin provides an under voltage lockout function that holds output low until VDD supply
voltage is within operating range.
The UCC2753x driver is offered in a 5-pin or 6-pin standard SOT-23 (DBV) package. The device operates over
wide temperature range of -40°C to 140°C.
ORDERING INFORMATION(1)
OPERATING
TEMPERATURE RANGE
TA
PEAK CURRENT
(SOURCE AND SINK)
INPUT THRESHOLD
LOGIC
PART NUMBER
PACKAGE(2)
UCC27531DBV
UCC27533DBV
UCC27536DBV
UCC27537DBV
UCC27538DBV
SOT-23, 6-PIN
SOT-23, 5-PIN
SOT-23, 5-PIN
SOT-23, 5-PIN
SOT-23, 6-PIN
2.5 A and 5 A
2.5-A/5-A
TTL/CMOS –Compatible
(low-voltage, independent
of VDD bias voltage)
2.5-A/2.5-A
2.5-A/5-A
-40°C to +140°C
2.5-A/5-A
(1) DBV package uses Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to
be compatible with either lead free or Sn/Pb soldering operations.
(2) For the most up-to-date packaging information see the TI web site.
ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
over operating free-air temperature range (unless otherwise noted)
MIN
-0.3
MAX
UNIT
Supply voltage range,
Continuous
VDD
35
OUTH, OUTL, OUT
OUTH, OUTL, OUT (200 ns)
-0.3 VDD +0.3
-2 VDD +0.3
V
Pulse
Continuous IN, EN, IN+, IN-, IN1,
IN2
-5
27
27
Pulse IN, EN, IN+, IN-, IN1, IN2 (1.5
µs)
-6.5
V
Human body model, HBM (ESD)
Charged device model, CDM (ESD)
4000
1000
150
Operating virtual junction temperature range, TJ
Storage temperature range, Tstg
-40
-65
150
°C
Soldering, 10 sec.
Reflow
300
Lead temperature
260
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
2
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Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
www.ti.com
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
THERMAL INFORMATION
UCC27533,
UCC27536,
UCC27537
UCC27531,
UCC27538
THERMAL METRIC
UNITS
DBV
5 PINS
178.3
109.7
28.3
DBV(1)
6 PINS
178.3
109.7
28.3
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
θJCtop
θJB
°C/W
ψJT
ψJB
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
14.7
14.7
27.8
27.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
V
Supply voltage range, VDD
Operating junction temperature range
Input voltage, IN, IN+, IN-, IN1, IN2
Enable, EN
10
-40
-5
18
32
140
25
°C
V
-5
25
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UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are
positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition
specifications are at 25°C.
PARAMETER
Bias Currents
TEST CONDITION
MIN
TYP
MAX
UNITS
VDD = 7.0, IN, EN=VDD
100
200
300
IDDoff
IDDoff
IDDoff
IDDoff
IDDoff
Startup current (UCC25731)
Startup current (UCC27533)
Startup current (UCC27536)
Startup current (UCC27537)
Startup Current (UCC27538)
IN, EN = GND
100
100
100
100
100
100
100
100
100
217
200
217
217
217
200
217
200
200
300
300
300
300
300
300
300
300
300
VDD = 7.0, IN+ = GND, IN- = VDD
IN+ = VDD, IN- = GND
VDD = 7.0, IN- = GND, EN = VDD
IN- = VDD, EN = GND
VDD =7.0, IN+, EN = VDD
IN+, EN = GND
μA
VDD = 7.0, IN1, IN2=VDD
IN1, IN2=GND
Under Voltage Lockout (UVLO)
VON
Supply start threshold
8.0
7.3
8.9
8.2
0.7
9.8
9.1
Minimum operating voltage
after supply start
VOFF
VDD_H
V
V
Supply voltage hysteresis
Input (IN, IN+, IN1, IN2)
Input signal high threshold,
Output High, IN- = LOW, EN=HIGH, IN2 or IN1 =
HIGH (other is INPUT)
VIN_H
1.8
0.8
2.0
2.2
1.2
output high
Input signal low threshold,
output low
Output Low, IN- = LOW, EN=HIGH, IN2 or IN1 =
HIGH (other is INPUT)
VIN_L
1.0
1.0
VIN_HYS
Input signal hysteresis
Input (IN-)
Input signal high threshold,
output low
VIN_H
Output low, IN+ = HIGH, EN = High
Output high,, IN+ = HIGH, EN = High
1.7
0.8
1.9
2.1
1.2
Input signal low threshold,
output high
V
V
VIN_L
1.0
0.9
VIN_HYS
Input signal hysteresis
Enable (EN)
VEN_H
VEN_L
Enable signal high threshold
Enable signal low threshold
Output High
Output Low
1.7
0.8
1.9
1.0
0.9
2.1
1.2
VEN_HYS Enable signal hysteresis
4
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Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
www.ti.com
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are
positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition
specifications are at 25°C.
PARAMETER
Outputs (OUTH/OUTL)
TEST CONDITION
MIN
TYP
MAX
UNITS
Source peak current (OUTH)/
sink peak current (OUTL)(13)
ISRC/SNK
CLOAD = 0.22 µF, f = 1 kHz
-2.5/+5
A
VDD -
0.12
VDD -
0.07
VOH
VOL
VOL
OUTH, high voltage
OUTL, low voltage
IOUTH = -10 mA
IOUTL = 100 mA
IOUTL = 100 mA
VDD -0.2
0.065
0.125
V
OUTL, Low Voltage
UCC27536
0.130
0.23
TA = 25°C, IOUT = -10 mA
11
7
12
12
12.5
20
ROH
ROL
ROL
OUTH, pull-up resistance (15)
OUTL, pull-down resistance
TA = -40°C to 140°C, IOUT = -10 mA
TA = 25°C, IOUT = 100 mA
0.45
0.3
0.9
0.6
0.65
0.65
1.3
0.85
1.25
1.7
Ω
TA = -40°C to 140°C, IOUT = 100 mA
TA = 25°C, IOUT = 100 mA
OUTL, pull-down resistance
UCC27536
TA = -40°C to 140°C, IOUT = 100 mA
1.3
2.3
Switching Time
tR
Rise time
CLOAD = 1.8 nF
15
7
tF
Fall time
CLOAD = 1.8 nF
tF
Fall Time UCC27536DBV
Turn-on propagation delay
Turn-off propagation delay
CLOAD = 1.8 nF
10
17
17
tD1
tD2
CLOAD = 1.8 nF, IN, IN+ = 0 V to 5 V
CLOAD = 1.8 nF, IN, IN+ = 5 V to 0 V
26
26
ns
Inverting turn-off propagation
delay
tD3
tD4
CLOAD = 1.8 nF, IN- = 0 V to 5 V
CLOAD = 1.8 nF, IN- = 5 V to 0 V
17
20
28
28
Inverting turn-on propagation
delay
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UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
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Timing Diagram
Figure 1.
UCC27531: (OUTPUT = OUTH tied to OUTL) INPUT = IN, (EN = VDD), or INPUT = EN, (IN = VDD)
UCC27537: (OUTPUT = OUT) INPUT = IN+, (EN = VDD), or INPUT = EN, (IN+ = VDD)
UCC27538: (OUTPUT = OUTH tied to OUTL) INPUT = IN1, (IN2 = VDD), or INPUT = IN2, (IN1 = VDD)
High
INPUT
(IN+ pin)
Low
High
IN- pin
Low
90%
OUTPUT
10%
tD1 tr
tD2 tf
Figure 2. UCC27533: (OUTPUT = OUT) INPUT = IN+
UCC27536: (OUTPUT = OUT) INPUT = EN
High
INPUT
(IN- pin)
Low
High
Enable pin
Low
90%
OUTPUT
10%
tD2 tf
tD2 tr
Figure 3. UCC27533: (OUTPUT = OUT) ENABLE = IN+
UCC27536: (OUTPUT = OUT) ENABLE = EN
6
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UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
www.ti.com
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
DEVICE INFORMATION
Block Diagram
VDD
IN
2
3
6
5
VDD
VREF
EN
1
4
OUTH
OUTL
VDD
GND
UVLO
Figure 4. UCC27531
(EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, in pull-down resistance to GND = 230 kΩ)
VDD
IN+
3
1
5
VDD
OUT
VREF
IN-
4
2
VDD
GND
UVLO
Figure 5. UCC27533
(IN- pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, IN+ pull-down resistance to GND = 230 kΩ)
VDD
EN
1
5
4
VDD
OUT
VREF
VREF
IN-
3
2
VDD
GND
UVLO
Figure 6. UCC27536
(EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, IN- pull-up resistance to VREF = 500 kΩ)
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UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
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VDD
EN
1
5
4
VDD
OUT
VREF
IN+
3
VDD
UVLO
GND
2
Figure 7. UCC27537
(EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, IN+ pull-down resistance to GND = 230 kΩ)
VDD
IN1
2
1
6
4
VDD
IN2
5
OUTH
OUTL
VDD
UVLO
GND
3
Figure 8. UCC27538
(IN1 pull-down resistance to GND = 230 kΩ, IN2 pull-down resistance to GND = 230 kΩ)
8
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Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
www.ti.com
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
DEVICE INFORMATION
Typical Application Diagrams
UCC27531
OUTH
EN
IN
1
2
3
6
OUTL
+
5
VDD
GND
4
GND
Bouncing Up
to -6.5 V
18 V
+
–
ISENSE
VCE(sense)
Controller
VCC
+
–
Figure 9. Driving IGBT Without Negative Bias
UCC27531
EN
IN
OUTH
OUTL
GND
1
2
3
6
5
4
+
VDD
+
–
18 V
13 V
+
–
Figure 10. Driving IGBT With 13-V Negative Turn-Off Bias
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UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
www.ti.com
UCC27533
IN-
IN+
4
3
1
OUT
GND
5
2
+
VDD
+
–
18 V
13 V
+
–
Figure 11. Single Output Driver
E/2
+
–
Isol.
UCC2753x
Isol.
UCC2753x
Controller
Isol.
UCC2753x
Isol.
UCC2753x
E/2
+
–
Figure 12. Using UCC2753x Drivers in an Inverter
10
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UCC27533, UCC27536
UCC27537, UCC27538
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SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
DEVICE INFORMATION
UCC2753x Product Matrix
Table 1. UCC2753x Product Matrix
UCC27531
2.5 A
UCC27533
2.5 A
UCC27536
2.5 A
UCC27537
2.5 A
UCC27538
2.5 A
ION PEAK
IOFF PEAK
PACKAGE
IN
5 A
SOT-23-6
Single
5 A
2.5 A
5 A
5 A
SOT-23-5
Dual
SOT-23-5
Single
SOT-23-5
Single
SOT-23-6
Dual
IN LOGIC
EN
TTL/CMOS
Yes
TTL/CMOS
No
TTL/CMOS
Yes
TTL/CMOS
Yes
TTL/CMOS
No
OUTPUT
Split
Single
Single
Single
Split
Inverting/Non-
Inverting
INVERTING
MAX VDD
No
Yes
No
No
35 V
35 V
35 V
35 V
35 V
UCC27531
UCC27533
UCC27536
UCC27537
UCC27538
EN
IN
1
2
3
6
5
OUTH VDD
1
2
3
5
OUT EN
GND
1
2
3
5
VDD
EN
GND
IN+
1
2
3
5
1
2
3
6
5
OUTH
IN2
VDD VDD
PIN OUT
GND
IN+
OUTL
GND
IN1
VDD
OUT
OUT GND
4
4
IN-
IN-
4
4
4
OUTL
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SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
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TERMINAL FUNCTIONS
TERMINAL
I/O
FUNCTION
PIN NUMBER
NAME
UCC27531DBV
Enable (Pull EN to GND in order to disable output, pull it high or leave open to enable
output)
1
EN
I
2
IN
I
I
Driver non-inverting input
3
VDD
Bias supply input
4
GND
OUTL
OUTH
-
Ground (all signals are referenced to this node)
5-A sink current output of driver
2.5-A Source Current Output of driver
5
O
O
6
UCC27533DBV
1
VDD
GND
IN+
I
-
Bias supply input
2
Ground (All signals are referenced to this node)
Driver non-inverting input
3
I
4
IN-
I
Driver inverting input
5
OUT
O
2.5-A source and 5-A sink current output of driver
UCC27536DBV
Enable (pull EN to GND in order to disable output, pull it high or leave open to enable
output)
1
EN
I
2
GND
IN-
-
I
Ground (all signals are referenced to this node)
Driver inverting input
3
4
OUT
VDD
O
I
2.5-A source and 2.5-A sink current output of driver
Bias supply input
5
UCC27537DBV
Enable (Pull EN to GND in order to disable Output, Pull it high or leave open to
enable Output)
1
EN
I
2
GND
IN+
-
I
Ground (All signals are referenced to this node)
Driver non-inverting input
3
4
OUT
VDD
O
I
2.5-A source and 5-A sink current output of driver
Bias supply input
5
UCC27538DBV
1
2
3
4
5
6
VDD
IN1
I
I
Bias supply input
Driver non-inverting input
GND
OUTL
IN2
-
Ground (all signals are referenced to this node)
5-A sink current output of driver
Driver non-inverting input
O
I
OUTH
O
2.5-A source current output of driver
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INPUT/OUTPUT LOGIC TRUTH TABLE
(for single output driver)
UCC27531DBV
IN PIN
OUT
EN PIN
OUTH PIN
OUTL PIN
(OUTH and OUTL pins
tied together)
L
L
High-impedance
High-impedance
High-impedance
H
L
L
L
L
H
L
H
H
L
H
L
L
High-impedance
High-impedance
L
H
H
L
H
FLOAT
H
H
FLOAT
High-impedance
INPUT/OUTPUT LOGIC TRUTH TABLE
UCC27533DBV
UCC27536DBV
UCC27537DBV
IN+ PIN
IN- PIN
OUT PIN
L
L
L
L
H
L
L
L
L
H
H
H
L
H
FLOAT
X
X
FLOAT
IN- PIN
EN PIN
OUT PIN
L
L
L
H
L
L
H
H
L
H
H
FLOAT
L
L
X
L
FLOAT
H
IN+ PIN
EN PIN
OUT PIN
L
L
L
L
L
H
H
H
L
H
L
H
L
FLOAT
H
X
FLOAT
H
INPUT/OUTPUT LOGIC TRUTH TABLE
(for single output driver)
UCC27538DBV
IN1 PIN
OUT
IN2 PIN
OUTH PIN
OUTL PIN
(OUTH and OUTL pins
tied together)
L
L
High-Impedance
High-Impedance
High-Impedance
H
L
L
L
L
H
L
L
L
H
L
H
H
L
H
L
High-Impedance
X
FLOAT
X
High-Impedance
High-Impedance
L
L
FLOAT
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TYPICAL CHARACTERISTICS
If not specified, INPUT refers to non-inverting input
12
25
20
15
10
5
10
8
6
4
Cload = 1.8nF
Cload = 1.8nF
2
0
10
20
30
40
0
10
20
30
40
C002
Supply Voltage (V)
C001
Supply Voltage (V)
Figure 13. Rise Time vs. Supply Voltage
Figure 14. Fall Time vs. Supply Voltage
21
19
17
15
20
16
12
8
Turn-
On
Turn-
Off
Cload = 1.8nF
0
10
20
30
40
4
C003
Supply Voltage (V)
0
0
10
20
30
40
Supply Voltage (V)
C001
Figure 15. UCC27536 Fall Time vs. Supply Voltage
Figure 16. Propagation Delay vs. Supply Voltage
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TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
27
30
25
20
15
10
5
OUT RISING, IN- 5V to
0V
OUT FALLING, IN- 0V
VDD = 10V
VDD = 18V
VDD = 32V
to 5V
25
23
21
19
17
15
Cload = 1.8nF
0
0
10
20
30
40
0
100
200
300
400
500
Supply Voltage (V)
Frequency (kHz)
C001
C001
Figure 17. IN- Propagation Delay vs. Supply
Figure 18. Operating Supply Current vs. Frequency
300
250
200
150
100
300
250
200
150
100
EN=IN=Vdd
EN=IN=GND
IN- = VDD, IN+ = GND
IN+ = VDD, IN- = GND
Vdd = 7V
Vdd = 7V
-50
0
50
100
150
Temperature (˙C)
C002
-50
0
50
100
150
Temperature (˘C)
C005
Figure 19. UCC27533 Start-Up Current vs. Temperature
Figure 20. UCC27531 Start-Up Current vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
300
300
250
200
150
100
IN1 = IN2 = VDD
IN1 = IN2 = GND
IN- = GND, EN = VDD
IN- = VDD, EN = GND
250
200
Vdd = 7V
Vdd = 7V
150
100
-50
0
50
100
150
-50
0
50
Temperature (˙C)
100
150
Temperature (˙C)
C004
C005
Figure 21. UCC27536 Start-Up Current vs. Temperature
Figure 22. UCC27538 Start-Up Current vs. Temperature
4.5
300
IN+ = EN = Vdd
IN+ = EN = GND
4.3
4.1
3.9
3.7
3.5
250
200
150
100
Vdd = 7V
Vdd = 18V
Cload = 1.8nF
fsw = 100kHz
-50
0
50
Temperature (˙C)
100
150
C003
-50
0
50
100
150
Temperature (˘C)
C006
Figure 23. UCC27537 Start-Up Current vs. Temperature
Figure 24. Operating Supply Current vs. Temperature
(output switching)
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SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
9.6
2.4
2.2
2
Turn-On
Turn-Off
UVLO Rising
UVLO Falling
9.2
1.8
1.6
1.4
1.2
1
8.8
8.4
8
0.8
-50
0
50
100
150
-50
0
50
100
150
Temperature (˘C)
Temperature (˘C)
C007
C008
Figure 25. UVLO Threshold Voltage vs. Temperature
Figure 26. Input Threshold vs. Temperature
2.4
2.2
2
2.4
2.2
2
Enable
Disable
OUT FALL
OUT RISE
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
0.8
-50
0
50
100
150
Temperature (˙C)
0.8
C002
-50
0
50
100
150
Temperature (˘C)
C009
Figure 27. IN- Input Threshold vs. Temperature
Figure 28. Enable Threshold vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
25
1.2
ROH
ROL
1
20
0.8
0.6
0.4
0.2
15
10
Vdd = 18V
Vdd = 18V
5
-50
0
50
100
150
-50
0
50
100
150
Temperature (˘C)
Temperature (˘C)
C010
C011
Figure 29. Output Pull-Up Resistance vs. Temperature
0.6
Figure 30. Output Pull-Down Resistance vs. Temperature
30
IN=HIGH
IN=LOW
Turn-On
Turn-Off
0.5
0.4
0.3
0.2
25
20
15
Vdd = 18V
Vdd = 18V
100
10
-50
0
50
Temperature (˘C)
150
-50
0
50
100
150
Temperature (˘C)
C012
C013
Figure 31. Operating Supply Current vs. Temperature
(output in DC on/off condition)
Figure 32. Input-to-Output Propagation Delay vs.
Temperature
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TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
30
16
15
14
13
12
11
OUT RISING, IN- 5V to 0V
OUT FALLING, IN- 0V to 5V
26
22
18
Vdd = 18V
Cload = 1.8nF
Vdd = 18V
14
10
-50
0
50
100
150
Temperature (˙C)
C003
-50
0
50
100
150
Temperature (˘C)
C014
Figure 33. IN- Input-to-Output Propagation Delay vs.
Temperature
Figure 34. Rise Time vs. Temperature
9
20
8
7
6
5
4
15
10
5
Vdd = 18V
Cload = 1.8nF
Vdd = 18V
Cload = 1.8nF
0
-50
0
50
100
150
Temperature (˙C)
C003
-50
0
50
Temperature (˘C)
100
150
C015
Figure 35. Fall Time vs. Temperature
Figure 36. UCC27536 Fall Time vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
If not specified, INPUT refers to non-inverting input
10
140
120
100
80
8
6
4
Cload = 10nF
fsw = 20kHz
2
0
60
Cload = 10nF
30
40
0
10
20
30
40
0
10
20
Supply Voltage (V)
40
Supply Voltage (V)
C016
C017
Figure 37. Operating Supply Current vs. Supply Voltage
(output switching)
Figure 38. Rise Time vs. Supply Voltage
70
60
50
40
30
120
100
80
60
Cload = 10nF
40
20
20
Cload = 10nF
0
10
20
30
40
Supply Voltage (V)
10
C002
0
10
20
30
40
Supply Voltage (V)
C018
Figure 39. Fall Time vs. Supply Voltage
Figure 40. UCC27536 Fall Time vs. Supply Voltage
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SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
APPLICATION INFORMATION
High-current gate driver devices are required in switching power applications for a variety of reasons. In order to
enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can
be employed between the PWM output of controllers or signal isolation devices and the gates of the power
semiconductor devices. Further, gate drivers are indispensable when sometimes it is just not feasible to have the
PWM controller directly drive the gates of the switching devices. The situation will be often encountered since the
PWM signal from a digital controller or signal isolation device is often a 3.3-V or 5-V logic signal which is not
capable of effectively turning on a power switch. A level shifting circuitry is needed to boost the logic-level signal
to the gate-drive voltage in order to fully turn on the power device and minimize conduction losses. Traditional
buffer drive circuits based on NPN/PNP bipolar, (or p- n-channel MOSFET), transistors in totem-pole
arrangement, being emitter follower configurations, prove inadequate for this since they lack level-shifting
capability and low-drive voltage protection. Gate drivers effectively combine both the level-shifting, buffer drive
and UVLO functions. Gate drivers also find other needs such as minimizing the effect of switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses into itself.
The UCC2753x is very flexible in this role with a strong current drive capability and wide supply voltage range up
to 32 V. This allows the driver to be used in 12-V Si MOSFET applications, 20-V and -5-V (relative to Source)
SiC FET applications, 15-V and -15-V(relative to Emitter) IGBT applications and many others. As a single-
channel driver, the UCC2753x can be used as a low-side or high-side driver. To use as a low-side driver, the
switch ground is usually the system ground so it can be connected directly to the gate driver. To use as a high-
side driver with a floating return node however, signal isolation is needed from the controller as well as an
isolated bias to the UCC2753x. Alternatively, in a high-side drive configuration the UCC2753x can be tied directly
to the controller signal and biased with a non-isolated supply. However, in this configuration the outputs of the
UCC2753x need to drive a pulse transformer which then drives the power-switch to work properly with the
floating source and emitter of the power switch. Further, having the ability to control turn-on and turn-off speeds
independently with both the OUTH and OUTL pins ensures optimum efficiency while maintaining system
reliability. These requirements coupled with the need for low propagation delays and availability in compact, low-
inductance packages with good thermal capability makes gate driver devices such as the UCC2753x extremely
important components in switching power combining benefits of high-performance, low cost, component count
and board space reduction and simplified system design.
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Table 2. UCC2753x Features and Benefits
FEATURE
BENEFIT
High source and sink current capability, 2.5 A and
5 A (asymmetrical).
High current capability offers flexibility in employing UCC2753x device to drive a
variety of power switching devices at varying speeds.
Low 17 ns (typ) propagation delay.
Extremely low pulse transmission distortion.
Flexibility in system design.
Wide VDD operating range of 10 V to 32 V.
Can be used in split-rail systems such as driving IGBTs with both positive and
negative(relative to Emitter) supplies.
Optimal for many SiC FETs.
VDD UVLO protection.
Outputs are held Low in UVLO condition, which ensures predictable, glitch-free
operation at power-up and power-down.
High UVLO of 8.9V typical ensures that power switch is not on in high-impedance
state which could result in high power dissipation or even failures.
Outputs held low when input pin (INx) in floating
condition.
Safety feature, especially useful in passing abnormal condition tests during safety
certification
Split output structure option (OUTH, OUTL).
Allows independent optimization of turn-on and turn-off speeds using series gate
resistors.
Strong sink current (5 A) and low pull-down
High immunity to high dV/dt Miller turn-on events.
impedance (0.65 Ω).
CMOS and TTL compatible input threshold logic
with wide hysteresis.
Enhanced noise immunity, while retaining compatibility with microcontroller logic level
input signals (3.3 V, 5 V) optimized for digital power.
Input capable of withstanding -6.5 V.
Enhanced signal reliability in noisy environments that experience ground bounce on
the gate driver.
VDD Under Voltage Lockout
The UCC2753x device has internal under voltage lockout (UVLO) protection feature on the VDD pin supply
circuit blocks. To ensure acceptable power dissipation in the power switch, this UVLO prevents the operation of
the gate driver at low supply voltages. Whenever the driver is in UVLO condition (when VDD voltage less than
VON during power-up and when VDD voltage is less than VOFF during power down), this circuit holds all outputs
LOW, regardless of the status of the inputs. The UVLO is typically 8.9 V with 700-mV typical hysteresis. This
hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also
when there are droops in the VDD bias voltage when the system commences switching and there is a sudden
increase in IDD. The capability to operate at voltage levels such as 10 V to 32 V provides flexibility to drive Si
MOSFETs, IGBTs, and emerging SiC FETs.
VDD Threshold
VDD
IN
OUT
Figure 41. Power Up
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Input Stage
The input pins of UCC2753x device are based on a TTL and CMOS compatible input threshold logic that is
independent of the VDD supply voltage. With typical high threshold = 2 V and typical low threshold = 1 V, the
logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic. Wider
hysteresis (typically 1 V) offers enhanced noise immunity compared to traditional TTL logic implementations,
where the hysteresis is typically less than 0.5 V. This device also features tight control of the input pin threshold
voltage levels which eases system design considerations and guarantees stable operation across temperature.
The very low input capacitance , typically 20 pF, on these pins reduces loading and increases switching speed.
The device features an important safety function wherein, whenever the input pin is in a floating condition, the
output is held in the low state. This is achieved using pull-up or pull-down resistors on the input pins as shown in
the block diagrams.
The input stage of the driver should preferably be driven by a signal with a short rise or fall time. Caution must be
exercised whenever the driver is used with slowly varying input signals, especially in situations where the device
is located in a separate daughter board or PCB layout has long input connection traces:
•
High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. Since
the device features just one GND pin which may be referenced to the power ground, this may interfere with
the differential voltage between Input pins and GND and trigger an unintended change of output state.
Because of fast 17 ns propagation delay, this can ultimately result in high-frequency oscillations, which
increases power dissipation and poses risk of damage
•
1-V Input threshold hysteresis boosts noise immunity compared to most other industry standard drivers.
If limiting the rise or fall times to the power device to reduce EMI is necessary, then an external resistance is
highly recommended between the output of the driver and the power device instead of adding delays on the input
signal. This external resistor has the additional benefit of reducing part of the gate charge related power
dissipation in the gate driver device package and transferring it into the external resistor itself.
Finally, because of the unique input structure that allows negative voltage capability on the Input and Enable
pins, caution must be used in the following applications:
•
•
Input or Enable pins are switching to amplitude > 15 V
Input or Enable pins are switched at dV/dt > 2 V/ns
If both of these conditions occur, it is advised to add a series 150-Ω resistor for the pin(s) being switched to limit
the current through the input structure.
Enable Function
The Enable (EN) pin of the UCC2753x has an internal pull-up resistor to an internal reference voltage so leaving
Enable floating turns on the driver and allows it to send output signals properly. If desired, the Enable can also
be driven by low-voltage logic to enable and disable the driver.
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Output Stage
The output stage of the UCC2753x device is illustrated in Figure 42. The UCC2753x device features a unique
architecture on the output stage which delivers the highest peak source current when it is most needed during
the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector voltage
experiences dV/dt). The device output stage features a hybrid pull-up structure using a parallel arrangement of
N-Channel and P-Channel MOSFET devices. By turning on the N-Channel MOSFET during a narrow instant
when the output changes state from low to high, the gate driver device is able to deliver a brief boost in the peak
sourcing current enabling fast turn on.
VDD
ROH
RNMOS, Pull Up
OUTH
Anti Shoot-
Through
Circuitry
Input Signal
OUTL
Narrow Pulse at
each Turn On
ROL
Figure 42. UCC27531 Gate Driver Output Stage
Split output depicted in Figure 42. For devices with single OUT pin, OUTH and OUTL are connected internally
and then connected to OUT.
The ROH parameter (see Electrical Table) is a DC measurement and it is representative of the on-resistance of
the P-Channel device only, since the N-Channel device is turned-on only during output change of state from low
to high. Thus the effective resistance of the hybrid pull-up stage is much lower than what is represented by ROH
parameter. The pull-down structure is composed of a N-Channel MOSFET only. The ROL parameter (see
ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of true impedance of
the pull-down stage in the device. In UCC2753x, the effective resistance of the hybrid pull-up structure is
approximately 3 x ROL
.
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The UCC2753x is capable of delivering 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink capability
results in a very low pull-down impedance in the driver output stage which boosts immunity against the parasitic
Miller turn-on (high slew rate dV/dt turn on) effect that is seen in both IGBT and FET power switches .
An example of a situation where Miller turn on is a concern is synchronous rectification (SR). In SR application,
the dV/dt occurs on MOSFET drain when the MOSFET is already held in Off state by the gate driver. The current
charging the CGD Miller capacitance during this high dV/dt is shunted by the pull-down stage of the driver. If the
pull-down impedance is not low enough then a voltage spike can result in the VGS of the MOSFET, which can
result in spurious turn on. This phenomenon is illustrated in Figure 43.
VDS
VIN
Miller Turn -On Spike in V GS
CGD
Gate Driver
VTH
VGS of
MOSFET
RG
COSS
ISNK
ON OFF
VIN
CGS
ROL
VDS of
MOSFET
Figure 43. Low Pull-Down Impedance in UCC2753x
(output stage mitigates Miller turn-on effect)
The driver output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS
output stage which delivers very low dropout. The presence of the MOSFET body diodes also offers low
impedance to switching overshoots and undershoots. This means that in many cases, external Schottky diode
clamps may be eliminated.
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Power Dissipation
Power dissipation of the gate driver has two portions as shown in equation below:
P
= P + P
DC SW
DISS
(1)
The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver. The
quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference
voltage, logic circuits, protections etc and also any current associated with switching of internal devices when the
driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-
through). The UCC2753x features very low quiescent currents (less than 1 mA) and contains internal logic to
eliminate any shoot-through in the output driver stage. Thus the effect of the PDC on the total power dissipation
within the gate driver can be safely assumed to be negligible. In practice this is the power consumed by driver
when its output is disconnected from the gate of power switch.
The power dissipated in the gate driver package during switching (PSW) depends on the following factors:
•
Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to
input bias supply voltage VDD due to low VOH drop-out)
•
•
Switching frequency
Use of external gate resistors
When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power
that is required from the bias supply. The energy that must be transferred from the bias supply to charge the
capacitor is given by:
1
2
EG
=
CLOADVDD
2
where
•
CLOAD is load capacitor and VDD is bias voltage feeding the driver.
(2)
There is an equal amount of energy dissipated when the capacitor is discharged. During turn off the energy
stored in capacitor is fully dissipated in drive circuit. This leads to a total power loss during switching cycle given
by the following:
2
LOAD DD sw
P
= C
V
f
G
where
•
ƒSW is the switching frequency
(3)
The switching load presented by a power FET and IGBT can be converted to an equivalent capacitance by
examining the gate charge required to switch the device. This gate charge includes the effects of the input
capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between
the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC,
to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that
must be dissipated when charging a capacitor. This is done by using the equivalence, Qg = CLOADVDD, to provide
the following equation for power:
2
LOAD DD sw
P
= C
V
f
= Q V f
g DD sw
G
(4)
This power PG is dissipated in the resistive elements of the circuit when the MOSFET and IGBT is being turned
on or off. Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other
half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is
employed between the driver and MOSFET and IGBT, this power is completely dissipated inside the driver
package. With the use of external gate drive resistors, the power dissipation is shared between the internal
resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power
dissipated in the higher resistance component). Based on this simplified analysis, the driver power dissipation
during switching is calculated as follows:
æ
ö
÷
÷
ø
ROFF
+ RGATE
RON
PSW = 0.5´Qg ´ VDD ´ f
+
ç
sw ç
è
R
(
R
ON + RGATE
) (
)
OFF
where
•
ROFF = ROL and RON (effective resistance of pull-up structure) = 3 x ROL
(5)
26
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
www.ti.com
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the package. In order for a gate driver to be useful over a particular temperature range the
package must allow for the efficient removal of the heat produced while keeping the junction temperature within
rated limits. The thermal metrics for the driver package is summarized in the ‘Thermal Information’ section of the
datasheet. For detailed information regarding the thermal information table, please refer to Application Note from
Texas Instruments entitled “IC Package Thermal Metrics” (SPRA953A).
PCB Layout
Proper PCB layout is extremely important in a high current, fast switching circuit to provide appropriate device
operation and design robustness. The UCC2753x gate driver incorporates short propagation delays and powerful
output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power
switch to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current capability is even
higher (2.5-A and 5-A peak current is at VDD = 18 V). Very high di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. The following circuit layout guidelines are strongly recommended
when designing with these high-speed drivers.
•
Locate the driver device as close as possible to power device in order to minimize the length of high-current
traces between the driver Output pins and the gate of the power switch device.
•
Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal
trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD
during turn-on of power switch. The use of low inductance SMD components such as chip resistors and chip
capacitors is highly recommended.
•
•
The turn-on and turn-off current loop paths (driver device, power switch and VDD bypass capacitor) should be
minimized as much as possible in order to keep the stray inductance to a minimum. High di/dt is established
in these loops at two instances – during turn-on and turn-off transients, which induces significant voltage
transients on the output pins of the driver device and gate of the power switch.
Wherever possible, parallel the source and return traces of a current loop, taking advantage of flux
cancellation
•
•
Separate power traces and signal traces, such as output and input signals.
Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of
the driver should be connected to the other circuit nodes such as source of power switch, ground of PWM
controller etc at one, single point. The connected paths should be as short as possible to reduce inductance
and be as wide as possible to reduce resistance.
•
Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well.
Copyright © 2012–2013, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538
UCC27531
UCC27533, UCC27536
UCC27537, UCC27538
SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Original (December 2012) to Revision A
Page
•
Changed Block Diagram. ...................................................................................................................................................... 7
Changes from Revision A (December 2012) to Revision B
Page
•
Added UCC27533, UCC27536, UCC27537 and UCC27538 parts to the datasheet. .......................................................... 1
Changes from Revision B (April 2013) to Revision C
Page
•
Added additional DESCRIPTION information. ...................................................................................................................... 1
Changes from Revision C (April, 2013) to Revision D
Page
•
•
•
Added Startup Current UCC27537 Bias Current Parameters to the ELECTRICAL CHARACTERISTICS. ......................... 4
Added UCC27531 Start-Up Current vs. Temperature TYPICAL CHARACTERISTICS diagram. ...................................... 15
Added UCC27537 Start-Up Current vs. Temperature TYPICAL CHARACTERISTICS diagram. ...................................... 16
28
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Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: UCC27531 UCC27533, UCC27536 UCC27537, UCC27538
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2013
PACKAGING INFORMATION
Orderable Device
UCC27531DBVR
UCC27531DBVT
UCC27533DBVR
UCC27533DBVT
UCC27536DBVR
UCC27536DBVT
UCC27537DBVR
UCC27537DBVT
UCC27538DBVR
UCC27538DBVT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 140
-40 to 140
-40 to 140
-40 to 140
-40 to 140
-40 to 140
-40 to 140
-40 to 140
-40 to 140
-40 to 140
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
6
6
5
5
5
5
5
5
6
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
7531
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
250
3000
250
Green (RoHS
& no Sb/Br)
7531
7533
7533
7536
7536
7537
7537
7538
7538
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27531DBVR
UCC27531DBVT
UCC27533DBVR
UCC27533DBVT
UCC27536DBVR
UCC27536DBVT
UCC27537DBVR
UCC27537DBVT
UCC27538DBVR
UCC27538DBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
5
5
5
5
5
5
6
6
3000
250
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC27531DBVR
UCC27531DBVT
UCC27533DBVR
UCC27533DBVT
UCC27536DBVR
UCC27536DBVT
UCC27537DBVR
UCC27537DBVT
UCC27538DBVR
UCC27538DBVT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
6
6
5
5
5
5
5
5
6
6
3000
250
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
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