UCC27712-Q1 [TI]
具有互锁功能的汽车类 1.8A/2.8A、620V 半桥栅极驱动器;
| 型号： | UCC27712-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有互锁功能的汽车类 1.8A/2.8A、620V 半桥栅极驱动器 栅极驱动 驱动器 |
| 文件： | 总43页 (文件大小：1655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC27712-Q1
ZHCSGJ1 –AUGUST 2017
具有互锁功能的 UCC27712-Q1 汽车类 620V、1.8A、2.8A 高侧低侧
栅极驱动器
1 特性
3 说明
1
•
符合面向汽车应用的 AEC-Q100标准
UCC27712-Q1 是一款 620V 高侧和低侧栅极驱动器，
具有 1.8A 拉电流、2.8A 灌电流能力，专用于驱动功
率 MOSFET 或 IGBT。
–
–
器件 HBM 分类等级 1C
器件 CDM 分类等级 C4B
•
•
•
高侧和低侧配置
对于 IGBT，建议的 VDD 工作电压为 10V 至 20V，对
于功率 MOSFET，建议的 VDD 工作电压为 10V 至
17V。
双输入，带输出互锁和 150ns 死区时间
在高达 620V 的电压下完全可正常工作，HB 引脚
上的绝对最高电压为 700V
UCC27712-Q1 包含保护 功能， 在此情况下，当输入
保持开路状态时，或当未满足最低输入脉宽规范时，输
出保持低位。互锁和死区时间功能可防止两个输出同时
打开。此外，该器件可接受的偏置电源范围宽幅达
10V 至 22V，并且为 VDD 和 HB 偏置电源提供了
UVLO 保护。
•
•
•
•
•
•
•
•
•
•
•
•
•
VDD 建议范围为 10V 至 20V
峰值输出电流 2.8A 灌电流、1.8A 拉电流
50V/ns 的 dv/dt 抗扰度
HS 引脚上的逻辑运行电压高达 –11V
输入负电压容差为 –5V
大型负瞬态安全工作区
为两个通道提供 UVLO 保护
短传播延迟（典型值 100ns）
延迟匹配（典型值 12ns）
低静态电流
该器件采用 TI 先进的高压器件技术， 具有 强大的驱
动器，拥有卓越的噪声和瞬态抗扰度，包括较大的输入
负电压容差、高 dV/dt 容差、开关节点上较宽的负瞬态
安全工作区 (NTSOA)，以及互锁。
TTL 和 CMOS 兼容输入
该器件包含一个接地基准通道 (LO) 和一个悬空通道
(HO)，后者专用于自举电源或隔离式电源操作。该器
件 具有 快速传播延迟和两个通道之间卓越的延迟匹
配。在 UCC27712-Q1 上，每个通道均由其各自的输
入引脚 HI 和 LI 控制。
行业标准 SOIC-8 封装
所有参数额定温度范围：–40°C 至 +125°C
2 应用
•
•
•
汽车逆变器
车载充电器（PFC，移相全桥）
器件信息(1)
用于汽车应用的 电机驱动 （步进电机、风扇）
器件型号
封装
SOIC (8)
封装尺寸（标称值）
UCC27712-Q1
3.91mm × 8.65mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
简化原理图
Bias
Up to 600 V
UCC27712-Q1
3
2
VDD
HB
8
PWM
Controller
PWM1
HI
HO
HS
7
6
Load
LI
PWM2
GND
1
LO
5
4
COM
Copyright
© 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCW3
UCC27712-Q1
ZHCSGJ1 –AUGUST 2017
www.ti.com.cn
典型传播延迟比较
300
250
200
150
100
50
Competitor
TI
0
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Typi
2
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
目录
7.4 Device Functional Modes........................................ 21
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application ................................................. 27
Power Supply Recommendations...................... 36
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Dynamic Electrical Characteristics ........................... 6
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 36
11 器件和文档支持 ..................................................... 37
11.1 文档支持................................................................ 37
11.2 相关链接................................................................ 37
11.3 社区资源................................................................ 37
11.4 商标....................................................................... 37
11.5 静电放电警告......................................................... 37
11.6 Glossary................................................................ 37
12 机械、封装和可订购信息....................................... 37
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2017 年 8 月
*
初始发行版。
Copyright © 2017, Texas Instruments Incorporated
3
UCC27712-Q1
ZHCSGJ1 –AUGUST 2017
www.ti.com.cn
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
LI
HI
1
8
7
6
5
HB
HO
HS
LO
2
3
4
VDD
COM
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
COM
4
–
I
Ground
High-side floating supply. Bypass this pin to HS with a suitable capacitor to sustain boot-strap
circuit operation, typically 10 times bigger than the MOSFETs/IGBTs gate capacitance.
HB
8
HI
HO
HS
LI
2
7
6
1
5
I
Logic input for high-side driver. If HI is unbiased or floating, HO is held low
High-side driver output.
O
–
I
Return for high-side floating supply.
Logic input for low-side driver. If LI is unbiased or floating, LO is held low
Low-side driver output.
LO
O
Bias supply input. Power supply for the input logic side of the device and also low-side driver
output. Bypass this pin to COM with a 0.1-µF or larger value ceramic capacitor.
VDD
3
I
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to COM (unless otherwise
noted), currents are positive into and negative out of the specified terminal.(1)
PARAMETER
MIN
–5
MAX
22
UNIT
(2)
HI, LI
VDD supply voltage
–0.3
–0.3
–0.3
HS–0.3
HS–2
–0.3
–2
22
Input voltage
V
HB
700
HB–HS
22
DC
HB+0.3
HB+0.3
VDD+0.3
VDD+0.3
2.8/–1.8
0.15
HO
V
V
Transient, less than 100 ns(3)
Output voltage
Output current
DC
LO
Transient, less than 100 ns(3)
IOUT_PULSED (100 ns)
IOUT_DC
HO, LO
A
dVHS/dt
TJ
Allowable offset supply voltage transient
Junction temperature
–50
–40
–65
50
V/ns
°C
150
Tstg
Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The maximum voltage on the input pins is not restricted by the voltage on the VDD pin
(3) Values are verified by characterization on bench.
4
Copyright © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
±1500
±750
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
All voltages are with respect to COM, over operating free-air temperature range (unless otherwise noted)
MIN
10
NOM
MAX
20
UNIT
IGBT applications
VDD
Supply voltage
MOSFET applications
IGBT applications
10
17
10
20
HB–HS
Driver bootstrap voltage
V
MOSFET applications
10
17
HS
Source terminal voltage(1)
Input voltage with respect to COM
Ambient temperature
–11
–4
600
20
HI, LI
TA
–40
125
°C
(1) Logic operational for HS of –11 V to +600 V at HB–HS = 15 V
6.4 Thermal Information
UCC27712-Q1
(SOIC)
8 PINS
108.3
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
61.5
57.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
15.3
ψJB
57.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C
(unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY BLOCK
VVDD ON
VVDD OFF
VVDD HYS
Turn-on threshold voltage of VDD
Turn-off threshold voltage of VDD
Hysteresis of VDD
8.0
7.5
8.9
9.8
8.4
0.5
9.3
Turn-on threshold voltage of
VHB–VHS
V
VVHB ON
7.2
8.2
7.3
9.2
8.3
Turn-off threshold voltage of
VHB–VHS
VVHB OFF
6.4
0.5
VVHB HYS
IQ
Hysteresis of VHB–VHS
0.9
255
190
Total quiescent supply current
HI = LI = 0 V or 5 V, DC on/off state
180
420
320
IQVDD
Quiescent VDD-COM supply current HI = LI = 0 V or 5 V, DC on/off state
HI = 0 V or 5 V, HO in DC on/off
IQBS
IBL
Quiescent HB-HS supply current
state
65
100
20
µA
Bootstrap supply leakage current
HB = HS = 600 V
HI = LI = 0 V or 5 V, f = 100 kHz,
duty = 50%, CL= 1 nF
IOP
Dynamic operating current
3800(1)
4500
(1) Ensured by design, not tested in production
Copyright © 2017, Texas Instruments Incorporated
5
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ZHCSGJ1 –AUGUST 2017
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Electrical Characteristics (continued)
At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C
(unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BLOCK
VINH
VINL
Input Pin (HI, LI) high threshold
Input Pin (HI, LI) low threshold
1.6
0.8
2.0
2.4
1.2
0.8
0
1.5
V
Input Pin (HI, LI) threshold
hysteresis
VINHYS
IINL
IINH
HI, LI input low bias current
HI, LI input high bias current
HI, LI = 0 V
–5
5
µA
HI, LI = 5 V
1.7
70
OUTPUT BLOCK
VDD-VLOH LO output high voltage
VHB-VHOH HO output high voltage
LI = 5 V, ILO = –20 mA
HI = 5 V, IHO = –20 mA
LI = 0 V, ILO = 20 mA
HI = 0 V, IHO = 20 mA
60
60
30
30
136
136
80
mV
VLOL
VHOL
LO output low voltage
HO output low voltage
80
RLOL
RHOL
,
LO, HO output pull-down resistance ILO = IHO = 20 mA
1.5
3.0
4
Ω
RLOH
RHOH
,
LO, HO output pull-up resistance
ILO = IHO = –20 mA
6.8
HO, LO output low short circuit
pulsed current
HI = LI = 0 V, HO = LO = 15 V, PW
< 10 µs
(1)
IGPK-
2.8
A
HO, LO output high short circuit
pulsed current
HI = LI = 5 V, HO = LO = 0 V, PW <
10 µs
(1)
IGPK+
–1.8
6.6 Dynamic Electrical Characteristics
At VDD = VHB = 15 V, COM = VHS = 0, all voltages are with respect to COM, no load on LO and HO, –40°C < TJ < +125°C
(unless otherwise noted). Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DYNAMIC CHARACTERISTICS
Turn-on propagation delay (without
deadtime)
tPDLH
LI to LO, HI to HO, HS = COM = 0 V
LI to LO, HI to HO, HS = COM = 0 V
100
160
tPDHL
tPDRM
tPDFM
Turn-off propagation delay
Low-to-high delay matching
High-to-low delay matching
100
5
160
30
12
30
10% to 90%, HO/LO with 1000-pF
load
tRISE
tFALL
tON
Turn-on rise time
Turn-off fall time
16
10
25
50
30
45
ns
10% to 90%, HO/LO with 1000-pF
load
Minimum HI/LI ON pulse that
changes output state
0-V to 5-V input signal on HI and LI
pins
Minimum HI/LI OFF pulse that
changes output state
5-V to 0-V input signal on HI and LI
pins
tOFF
DT
35
45
Deadtime
Internal deadtime for Interlock
100
150
200
6
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
HI
50%
50%
50%
50%
LI
tFALL
10%
tPDLH tRISE
HO
90%
90%
tPDHL
10%
90%
90%
tRISE
10%
10%
LO
tPDHL tFALL
Deadtime
Interlock
(DT)
(set by controller if > DT)
图 1. Typical Test Timing Diagram
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7
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ZHCSGJ1 –AUGUST 2017
www.ti.com.cn
6.7 Typical Characteristics
130
120
110
100
90
130
120
110
100
90
VDD = 10V
VDD = 12V
VDD = 15V
VDD=10V
VDD=12V
VDD=15V
80
80
70
70
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D001
D002
图 2. Low-Side, Turn-On Propagation Delay vs Temperature
图 3. Low-Side, Turn-Off Propagation Delay vs Temperature
130
130
120
110
100
90
120
110
100
90
80
VDD=10V
VDD=12V
VDD=15V
VDD=10V
VDD=12V
VDD=15V
80
70
70
-40
60
-40
-20
0
20
40
60
80
100 120
-20
0
20
40
60
80
100 120
Temperature (oC)
Temperature (oC)
D004
D003
图 5. High-Side, Turn-Off Propagation Delay vs Temperature
图 4. High-Side, Turn-On Propagation Delay vs Temperature
30
30
VDD=10V
VDD=12V
VDD=10V
VDD=12V
27
27
VDD=15V
VDD=15V
24
24
21
18
15
12
9
21
18
15
12
9
6
6
3
3
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D005
D006
图 6. Turn-On Delay Matching vs Temperature
图 7. Turn-Off Delay Matching vs Temperature
8
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
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ZHCSGJ1 –AUGUST 2017
Typical Characteristics (接下页)
130
125
120
115
110
105
100
95
30
25
20
15
10
5
Turn On
Turn Off
VDD=10V
VDD=12V
VDD=15V
90
85
80
75
0
70
-40
-20
0
20
40
60
80
100
120
0
60 120 180 240 300 360 420 480 540 600
VHS (V)
Temperature (oC)
D008
D007
图 9. LO Rise Time with 1000-pF Load vs Temperature
图 8. High-Side Propagation Delay vs HS
20
15
10
5
30
VDD=10V
VDD=12V
VDD=15V
25
20
15
10
VDD=10V
VDD=12V
VDD=15V
5
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D009
D001
图 10. LO Fall Time with 1000-pF Load vs Temperature
图 11. HO Rise Time with 1000-pF Load vs Temperature
10
20
UVLO On
UVLO Off
VDD=10V
VDD=12V
VDD=15V
9.5
9
15
10
5
8.5
8
0
7.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D001
D001
图 12. HO Fall Time with 1000-pF Load vs Temperature
图 13. VDD UVLO Thresholds vs Temperature
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Typical Characteristics (接下页)
9
1.5
1.25
1
HB UVLO On
HB UVLO Off
VDD Hysteresis
VHB Hysteresis
8.5
8
0.75
0.5
0.25
0
7.5
7
6.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D001
D001
图 14. VHB-VHS UVLO Thresholds vs Temperature
图 15. VDD and VHB-VHS UVLO Hysteresis vs Temperature
2.4
1.5
HI High Thresh
HI Low Thresh
LI High Thresh
LI Low Thresh
2.3
2.2
2.1
2
1.4
1.3
1.2
1.1
1
1.9
1.8
1.7
1.6
0.9
0.8
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D001
D001
图 16. HI/LI Pin High Threshold vs Temperature
图 17. HI/LI Pin Low Threshold vs Temperature
1
4
HI Hysteresis
LI Hysteresis
VDD=10V
VDD=15V
3.5
3
0.9
0.8
0.7
0.6
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D001
D001
图 18. HI/LI Pin Hysteresis vs Temperature
图 19. LO Output Pull-Down Resistance vs Temperature
10
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UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
Typical Characteristics (接下页)
4
3.5
3
6
5.5
5
VDD=10V
VDD=15V
4.5
4
2.5
2
3.5
3
1.5
1
2.5
2
0.5
0
VDD=10V
VDD=15V
1.5
1
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D001
D002
图 20. HO Output Pull-Down Resistance vs Temperature
图 21. LO Output Pull-Up Resistance vs Temperature
6
400
VDD=10V
VDD=15V
HI, LI 0V
HI, LI 5V
5.5
350
5
4.5
4
300
250
200
150
3.5
3
2.5
2
1.5
1
VDD=VHB=15V
80 100 120
100
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
Temperature (oC)
Temperature (oC)
D002
D002
图 22. HO Output Pull-Up Resistance vs Temperature
图 23. Total Quiescent VDD plus HB Supply Current vs
Temperature
100
5
IQ HB to HS
VHB=VHS=400V
VHB=VHS=600V
90
80
70
60
50
4
3
2
1
0
40
VDD=VHB=15V
80 100 120
30
-40
-20
0
20
40
60
-40
-20
0
20
40
60
80
100
120
Temperature (oC)
Temperature (oC)
D002
D002
图 24. Quiescent HB to HS Supply Current vs Temperature
图 25. HB to COM Bootstrap Supply Leakage Current vs
Temperature
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Typical Characteristics (接下页)
4
3.5
3
10
9
8
7
6
5
4
3
2
1
0
IVDD 12V
IVHB 12V
IVDD 15V
IVHB 15V
2.5
2
1.5
1
IVDD 12V
IVHB 12V
IVDD 15V
IVHB 15V
0.5
0
0
50 100 150 200 250 300 350 400 450 500
Fsw (kHz)
0
50 100 150 200 250 300 350 400 450 500
Fsw kHz
D002
D002
图 26. VDD and HB Operating Current with No Load vs
图 27. VDD and HB Operating Current with 1000-pF Load vs
Switching Frequency
Switching Frequency
40
35
30
25
20
15
10
5
IVDD 12V
IVHB 12V
IVDD 15V
IVHB 15V
0
0
50 100 150 200 250 300 350 400 450 500
Fsw (kHz)
D002
图 28. VDD and HB Operating Current with 4700-pF Load vs Switching Frequency
12
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7 Detailed Description
7.1 Overview
The UCC27712-Q1 consists of one ground-referenced channel (LO) and one floating channel (HO) which is
designed for operating with bootstrap or isolated power supplies. The device features fast propagation delays
and excellent delay matching between both channels. On the UCC27712-Q1, each channel is controlled by its
respective input pins,
Developed with TI’s state of the art high-voltage technology, the device features robust drive with excellent noise
and transient immunity including large negative voltage tolerance on its inputs, high dv/dt tolerance, and wide
negative transient safe operating area (NTSOA) on the switch node (HS).
The UCC27712-Q1 includes protection features where the outputs are held low when the inputs are floating or
when the minimum input pulse width specification is not met. Interlock and deadtime functions prevent both
outputs from being turned on simultaneously. In addition, the device accepts a wide range bias supply range
from 10 V ~ 22 V, and offers UVLO protection for both the VDD and HB bias supply.
High-current, gate-driver devices are required in switching power applications for a variety of reasons. In order to
implement fast switching of power devices and reduce associated switching power losses, a powerful gate-driver
device is employed between the PWM output of control devices and the gates of the power semiconductor
devices. Further, gate-driver devices are indispensable when having the PWM controller device directly drive the
gates of the switching devices is sometimes not feasible. In the case of digital power supply controllers, this
situation is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal
which is not capable of effectively turning on a power switch.
In bridge topologies, like hard-switch half bridge, hard-switch full bridge, half-bridge and full-bridge LLC, and
phase-shift full bridge, the source and emitter pin of the top-side power MOSFET and IGBT switch is referenced
to a node whose voltage changes dynamically; that is, not referenced to a fixed potential, so floating-driver
devices are necessary in these topologies.
The UCC27712-Q1 is a high-side and low-side driver dedicated for offline AC-to-DC power supplies and
inverters. The high side is a floating driver that can be biased effectively using a bootstrap circuit, and can handle
up to 600-V. The driver can be used with 100% duty cycle as long as HB-HS can be above UVLO of the high
side.
The device features industry best-in-class propagation delay and delay matching between both channels aimed
at minimizing pulse width distortion in high-frequency switching applications. Each channel is controlled by its
respective input pins (HI and LI), allowing independent flexibility to control on and off state of the output but does
not allow the HO and LO outputs to be on at the same time. The UCC27712-Q1 includes an interlock feature
which guarantees a 150ns dead time between the HO and LO outputs if the HI and LI inputs are complimentary.
The UCC27712-Q1 includes protection features wherein the outputs are held low when inputs are floating or
when the minimum input pulse width specification is not met. The driver inputs are CMOS and TTL compatible
for easy interface to digital power controllers and analog controllers alike.
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7.2 Functional Block Diagram
HB
8
VHB UVLO
Level Shifter
R
HO
7
6
3
R
S
Q
Pulse
Filter
Deglitch
Filter
2
HI
Pulse
Generator
HS
Shoot Through
Prevention
VDD
VDD UVLO
LO
5
4
Delay
Deglitch
Filter
LI
1
COM
Copyright © 2017, Texas Instruments Incorporated
图 29. UCC27712-Q1 Block Diagram
14
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7.3 Feature Description
7.3.1 VDD and Under Voltage Lockout
The UCC27712-Q1 has an internal under voltage-lockout (UVLO) protection feature on the supply circuit blocks
between VDD and VSS pins, as well as between HB and HS pins. When VDD bias voltage is lower than the
VVDD(on) threshold at device start-up or lower than VVDD(off) after start-up, the VDD UVLO feature holds both the
LO and HO outputs low, regardless of the status of the HI and LI inputs. On the other hand, if HB-HS bias supply
voltage is lower than the VVHB(on) threshold at start-up or VVHB(off) after start-up, the HB-HS UVLO feature only
holds HO to low, regardless of the status of the HI. The LO output status is not affected by the HB-HS UVLO
feature (see 表 1 and 表 2). This allows the LO output to turn-on and re-charge the HB-HS capacitor using the
boot-strap circuit and thus allows HB-HS bias voltage to surpass the VVHB(on) threshold.
Both the VDD and VHB UVLO protection functions are provided with a hysteresis feature. This hysteresis
prevents chatter when there is ground noise from the power supply. Also this allows the device to accept a small
drop in the bias voltage which is bound to happen when the device starts switching and quiescent current
consumption increases instantaneously, as well as when the boot-strap circuit charges the HB-HS capacitor
during the first instance of LO turn-on causing a drop in VDD voltage.
The UVLO circuit of VDD-VSS and HB-HS in UCC27712-Q1 generate internal signals to enable/disable the
outputs after UVLO_ON/UVLO_OFF thresholds are crossed respectively (please refer to 图 30). Design
considerations indicate that the UVLO propagation delay before the outputs are enabled and disabled can vary
from 20 μs to 50 μs.
表 1. VDD UVLO Feature Logic Operation
CONDITION (VHB-VHS>VVHB, ON FOR ALL CASES
HI
LI
HO
LO
BELOW)
VDD-VSS < VVDD(on) during device start up
VDD-VSS < VVDD(on) during device start up
VDD-VSS < VVDD(on) during device start up
VDD-VSS < VVDD(on) during device start up
VDD-VSS < VVDD(off) after device start up
VDD-VSS < VVDD(off) after device start up
VDD-VSS < VVDD(off) after device start up
VDD-VSS < VVDD(off) after device start up
H
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
H
L
表 2. VHB UVLO Feature Logic Operation
CONDITION (VDD-VSS > VVDD,ON FOR ALL CASES
BELOW)
HI
LI
HO
LO
VHB-VHS < VVHB(on) during device start up
VHB-VHS < VVHB(on) during device start up
VHB-VHS < VVHB(on) during device start up
VHB-VHS < VVHB(on) during device start up
VHB-VHS < VVHB(off) after device start up
VHB-VHS < VVHB(off) after device start up
VHB-VHS < VVHB(off) after device start up
VHB-VHS < VVHB(off) after device start up
H
L
L
H
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
L
H
L
H
L
L
H
H
L
H
L
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VVDD(on)
VVDD(off)
4 V
VDD
LI
tDelay
tDelay
LO
VVHB(on)
HB-HS
HI
tDelay
HO
图 30. Power-Up Driver
7.3.2 Input and Output Logic Table
UCC27712-Q1 features separate inputs, HI and LI, for controlling the state of the outputs, HO and LO,
respectively. The device does include internal cross-conduction prevention logic and does not allow both HO and
LO outputs to be turned on simultaneously (refer to 表 3). This feature prevents cross conduction in bridge
topologies in the case of incorrect timing from the controller.
表 3. Input/Output Logic Table
(Assuming no UVLO fault condition exists for VDD and VHB)
HI
LI
HO
L
LO
L
Note
L
L
L
H
L
H
L
Output transitions occur after the
dead time expires
H
H
L
H
H
L
L
Left Open
Left Open
L
L
16
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7.3.3 Input Stage
The input pins of UCC27712-Q1 are based on a TTL and CMOS compatible input-threshold logic that is
independent of the VDD supply voltage. With typical high threshold (VINH) of 2.0 V and typical low threshold
(VINL) of 1.2 V, along with very little temperature variation as summarized in 图 16 and 图 17, the input pins are
conveniently driven with logic level PWM control signals derived from 3.3-V and 5-V digital power-controller
devices. Wider hysteresis (typically 0.8 V) offers enhanced noise immunity compared to traditional TTL logic
implementations, where the hysteresis is typically less than 0.5 V. UCC27712-Q1 also features tight control of
the input pin threshold voltage levels which eases system design considerations and ensures stable operation
across temperature.
The UCC27712-Q1 includes an important feature: wherein, whenever any of the input pins is in a floating
condition, the output of the respective channel is held in the low state. This is achieved using COM pull-down
resistors on all the input pins (HI, LI).
The UCC27712-Q1 input pins are capable of sustaining voltages higher than the bias voltage applied on the
VDD pin of the device, as long as the absolute magnitude is less than the recommended operating condition's
maximum ratings. This features offers the convenience of driving the PWM controller at a higher VDD bias
voltage than the UCC27712-Q1 helping to reduce gate charge related switching losses. This capability is
envisaged in UCC27712-Q1 by way of two ESD diodes tied back-to-front as shown in 图 31.
Additionally, the input pins are also capable of sustaining negative voltages below COM, as long as the
magnitude of the negative voltage is less than the recommended operating condition minimum ratings. A similar
diode arrangement exists between the input pins and COM as illustrated in 图 31.
The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied
in typical power supply applications, when the input signals are provided by a PWM controller or logic gates with
fast transition times. With a slow changing input voltage, the output of driver may switch repeatedly at a high
frequency. While the wide hysteresis offered in UCC27712-Q1 definitely alleviates this concern over most other
TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall times to
the power device is the primary goal, then an external resistance is highly recommended between the output of
the driver and the power device. This external resistor has the additional benefit of reducing part of the gate-
charge related power dissipation in the gate-driver device package and transferring it into the external resistor
itself. If an RC filter is to be added on the input pins for reducing the impact of system noise and ground bounce,
the time constant of the RC filter is recommended to be 20 ns or less, for example, 50 Ω with 220 pF is an
acceptable choice.
1
2
LI
22 V
HI
5 V
4
COM
图 31. Diode Structure of Input Stage
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7.3.4 Output Stage
The UCC27712-Q1 device output stage pull-up structure features a P-Channel MOSFET to provide source
current until the output is saturated to VDD or HB. The ROH parameter (see 图 21) is a DC measurement and it is
representative of the on-resistance of the P-Channel device.
The pull-down structure in UCC27712-Q1 is composed of a N-Channel MOSFET. The ROL parameter (see 图
19), which is also a DC measurement, is representative of the impedance of the pull-down stage in the device.
Each output stage in UCC27712-Q1 is capable of supplying 1.8-A peak source and 2.8-A peak sink current
pulses. The output voltage swings between (VDD and COM) / (HB and HS) providing rail-to-rail operation, thanks
to the MOSFET output stage which delivers very low drop-out.
VDD
3
Body
Diodes
ROH
Anti Shoot-
Through
Circuitry
Input
Voltage
5
LO
ROL
Body
Diodes
4
COM
图 32. Output Stage Structure
18
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7.3.5 Level Shift
The level shift circuit (refer to the Functional Block Diagram) is the interface from the high-side input to the high-
side driver stage which is referenced to the switch node (HS). It is a pulsed generated level shifter. With an input
signal the pulse generator generates "on" pulses based on the rising edge of the signal and "off" pulses based
on the falling edge. On pulses and off pulses turn on each branch of the level shifter so that current flows in each
branch to generate different voltages, which is transferred to the set and reset signal in the high side. The signal
is rebuilt by the RS latch in the high side domain. The level shift allows control of the HO output referenced to the
HS pin and provides excellent delay matching with the low-side driver. The delay matching of UCC27712-Q1 is
summarized in 图 6 and 图 7.
The level shifter in UCC27712-Q1 offers best-in-class capability while operating under negative voltage
conditions on HS pin. The level shifter is able to transfer signals from the HI input to HO output with only 4-V
headroom between HB and COM. Refer to Operation Under Negative HS Voltage Condition for detailed
explanations.
7.3.6 Low Propagation Delays and Tightly Matched Outputs
The UCC27712-Q1 features a best in class, 100-ns (typical) propagation delay (refer to 图 2, 图 3, 图 4 and 图
5 ) between input and output in high voltage 600-V driver, which goes to offer a low level of pulse width
distortion for high frequency switching applications.
图 33. Turn-On Propagation Delay
图 34. Turn-Off Propagation Delay
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7.3.7 Parasitic Diode Structure
图 35 illustrates the multiple parasitic diodes involved in the ESD protection components of UCC27712-Q1
device. This provides a pictorial representation of the absolute maximum rating for the device.
8
7
HB
HO
22V
700V
6
3
HS
1
2
LI
VDD
22V
HI
22V
5
4
LO
5V
COM
图 35. ESD Structure
20
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7.4 Device Functional Modes
7.4.1 Minimum Input Pulse Operation
The UCC27712-Q1 device has a minimum turn-on, turn-off pulse transfer function to the output pin from the input
pin. This function ensures UCC27712-Q1 is in the correct state when the input signal is very narrow. The
function is summarized in 图 36 and 图 37. The tON which is 25 ns typical is shown in 图 36 and tOFF which is
35ns typical is shown in 图 37
<25 ns
≥25 ns
HI, LI
HI, LI
tPDLH
Low State
HO, LO
HO, LO
图 36. Minimum Turn-On Pulse
HI, LI
HI, LI
<35 ns
≥35 ns
tPDHL
HO, LO
HO, LO
High State
图 37. Minimum Turn-Off Pulse
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Device Functional Modes (接下页)
7.4.2 Output Interlock and Dead Time
The UCC27712-Q1 has cross-conduction prevention logic, which is a feature that does not allow both the high-
side and low-side outputs to be in high state simultaneously. In bridge power supply topologies, such as half-
bridge or full-bridge, the UCC27712-Q1 interlock feature will prevent the high-side and low-side power switches
to be turned on simultaneously. The UCC27712-Q1 generates a fixed minimum dead time of tDT which is 150ns
nominal in the case of LI and HI overlap or no dead time. 图 38 illustrates the mode of operation where LI and HI
have no dead time and HO and LO outputs have the minimum dead time of tDT
.
图 38. HO and LO Minimum Dead Time with LI HI Complementary
22
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Device Functional Modes (接下页)
An input signal's falling edge activates the dead time for the other signal. The output signal's dead time is always
set to the longer of either the driver's minimum dead time, tDT, or the input signal's own dead time. If both inputs
are high simultaneously, both outputs will immediately be set low. This feature is used to prevent cross
conduction, and it does not affect the programmed dead time setting for normal operation. Various driver dead
time logic operating conditions are illustrated and explained in 图 39.
HI
LI
HO
LO
D
E
F
C
B
A
图 39. Input and Output Logic Relationship
Condition A: HI goes high, LI goes low. LI sets LO low immediately and assigns tDT to HO. HO is allowed to go
high after tDT
.
Condition B: LI goes high, HI goes low. HI sets HO low immediately and assigns tDT to HO. LO is allowed to go
high after tDT
.
Condition C: LI goes low, HI is still low. LI sets LO low immediately and assigns tDT to HO. In this case, the
input signal's own dead time is longer than tDT. Thus when HI goes high HO is set high immediately.
Condition D: HI goes low, LI is still low. HI sets HO low immediately and assigns tDT to LO. In this case, the
input signal's own dead time is longer than tDT. Thus when LI goes high LO is set high immediately.
Condition E: HI goes high, while LI and LO are still high. To avoid cross-conduction, HI immediately sets LO low
and keeps HO low. After some time LI goes low and assigns tDT to HO. LO is already low. After tDT HO is allowed
to go high.
Condition F: LI goes high, while HI and HO are still high. To avoid cross-conduction, LI immediately sets HO low
and keeps LO low. After some time HI goes low and assigns tDT to LO. HO is already low. After tDT LO is allowed
to go high.
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Device Functional Modes (接下页)
7.4.3 Operation Under 100% Duty Cycle Condition
The UCC27712-Q1 allows constant on or constant off operation (0% and/or 100% duty cycle) as long as the
VDD and VHB bias supplies are maintained above the UVLO thresholds. This is a challenge when boot-strap
supplies are used for VHB. However, when a dedicated bias supply is used, constant on or constant off
conditions can be supported. Also consider the HI and LI interlock function prevents both outputs from being
high.
7.4.4 Operation Under Negative HS Voltage Condition
A typical half-bridge configuration with UCC27712-Q1 is shown in 图 40. There are parasitic inductances in the
power circuit from die bonding and pinning in QT/QB and PCB tracks of power circuit, the parasitic inductances
are labeled LK1,2,3,4
.
During switching of HS caused by turning off HO, the current path of power circuit is changed to current path 2
from current path 1. This is known as current commutation. The current across LK3, LK4 and body diode of QB
pulls HS lower than COM. The negative voltage of HS with respect to COM causes a logic error of HO if the
driver cannot handle negative voltage of HS. However, the UCC27712-Q1 offers robust operation under these
conditions of negative voltage on HS.
VBUS+
LK1
QT
HO
HS
7
6
Current Path 1
LK2
LK3
QB
Load
Current
Path 2
LO
5
4
LK4
COM
图 40. HS Negative Voltage In Half-Bridge Configuration
24
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Device Functional Modes (接下页)
The level shifter circuit is with respect to COM (refer to Functional Block Diagram), the voltage from HB to COM
is the supply voltage of level shifter. Under the condition of HS is negative voltage with respect to COM, the
voltage of HB-COM is decreased, as shown in 图 41. There is a minimum operational supply voltage of level
shifter, if the supply voltage of level shifter is too low, the level shifter cannot pass through HI signal to HO. The
minimum supply voltage of level shifter of UCC27712-Q1 is 4 V, so the recommended HS specification is
dependent on HB-HS. The specification of recommended HS is –11 V at HB – HS = 15 V.
In general, HS can operate until -11 V when HB – HS = 15 V as the ESD structure in 图 35 allows a maximum
voltage difference of 22 V between both pins. If HB-HS voltage is different, the minimum HS voltage changes
accordingly.
HB
HS
HB-COM
COM
图 41. Level Shifter Supply Voltage with Negative HS
注
Logic operational for HS of –11 V to 600 V at HB – HS = 15 V
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Device Functional Modes (接下页)
The capability of a typical UCC27712-Q1 device to operate under a negative voltage condition in HS pin is
reported in 图 43. The test method is shown in 图 42.
Bias
RBIAS
15 V
CVDD
3
VDD
HB
8
CBOOT
+
15 V
Probe
œ
2
1
HI
LI
HO
HS
7
6
Single Phase
Negative
Voltage
Generator
LO
5
4
COM
图 42. Negative Voltage Test Method
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
NTSO
图 43. Negative Voltage Chart
Pulse Width vs Negative Voltage
26
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8 Application and Implementation
注
Information in the following Applications section is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers
are responsible for determining suitability of components for their purposes.
Customers should validate and test their design implementation to confirm system
functionality.
8.1 Application Information
To effect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability.
Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other
needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver
physically close to the power switch, driving gate-drive transformers and controlling floating power-device gates,
reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the
controller into the driver.
8.2 Typical Application
The circuit in 图 44 shows a reference design example with UCC27712-Q1 driving a typical half-bridge
configuration which could be used in several common power converter topologies such as synchronous buck,
synchronous boost, half-bridge/full bridge isolated topologies, and motor drive applications.
For more information, please refer to 图 44.
Bias
RBIAS
DBOOT
RBOOT
HV
CVDD
DGATE
RON
ROFF
3
2
HB
HO
HS
8
7
VDD
HI
RHI
Q1
Q2
PWM1
PWM2
GND
CBOOT
CHI
RGS
RLI
SW
6
LI
1
DGATE
RON
ROFF
CLI
5
4
LO
RGS
COM
Copyright © 2017, Texas Instruments Incorporated
图 44. Typical Application Schematic
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Typical Application (接下页)
8.2.1 Design Requirements
表 4 shows the reference design parameters for the example application: UCC27712-Q1 driving 650-V
MOSFETs in a high side-low side configuration.
表 4. UCC27712-Q1 Design Requirements
PARAMETER
Power transistor
VDD
VALUE
UNIT
IPB65R190CFD
-
V
12
Input signal amplitude
Switching frequency (fSW
3.3
V
)
100
400
kHz
V
DC link voltage (VHV
)
8.2.2 Detailed Design Procedure
This procedure outlines the steps to design a 600-V high-side, low-side gate driver with 1.8-A source and 2.8-A
sink current capability, targeted to drive power MOSFETs or IGBTs using the UCC27712-Q1. Refer to 图 44 for
component names and network locations. For additional design help see the UCC27712EVM-287 User Guide,
SLUUBO1.
8.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
It is recommended that users avoid shaping the input signals to the gate driver in an attempt to slow down (or
delay) the signal at the driver output. However it is good practice to have a small RC filter added between PWM
controller and input pin of UCC27712-Q1 to filter the high frequency noise, like RHI/CHI and RLI/CLI which is
shown in 图 44.
Such a filter should use a RHI/RLI in the range of 10 Ω to 100 Ω and a CHI/CLI between 10 pF and 220 pF. In the
example, a RHI/RLI = 49.9 Ω and a CHI/CLI = 33 pF are selected.
8.2.2.2 Selecting Bootstrap Capacitor (CBOOT
)
The bootstrap capacitor should be sized to have more than enough energy to drive the gate of FET Q1 high, and
maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with:
IQBS
fSW
65mA
fSW
QTotal = QG +
= 68nC +
= 68.65nC
(1)
This design example targets a boot capacitor ripple voltage of 0.5 V. Therefore, the absolute minimum CBOOT
requirement is:
QTOTAL
68.65nC
0.5V
CBOOT =
=
ö 137nF
DVBOOT
(2)
In practice, the value of CBOOT needs to be greater than the calculated value. This allows for capacitance shift
from DC bias and temperature, and also skipped cycles that occur during load transients. For this design
example 2x 220-nF capacitors were chosen for the bootstrap capacitor.
CBOOT = 440nF
(3)
28
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
8.2.2.3 Selecting VDD Bypass/Holdup Capacitor (CVDD) and Rbias
The VDD capacitor (CVDD) should be chosen to be at least 10 times larger than CBOOT so there is minimal voltage
drop on the VDD capacitor when charging the boot capacitor . For this design example a 4.7-µF capacitor was
selected.
CVDD í 10ìCBOOT = 4.7mF
(4)
A 10-Ω resistor RBIAS in series with bias supply and VDD pin is recommended to make the VDD ramp up time
larger than 20 µs to minimize LO and HO rising as shown in 图 45
LO
HO
图 45. VDD/HB-HS Fast Ramp Up
8.2.2.4 Selecting Bootstrap Resistor (RBOOT
)
Resistor RBOOT is selected to limit the current in DBOOT and limit the ramp up slew rate of voltage of HB-HS to
avoid the phenomenon shown in 图 45. It is recommended when using the UCC27712-Q1 that RBOOT is
between 2 Ω and 20 Ω. For this design we selected an RBOOT current limiting resistor of 2.2 Ω. The bootstrap
diode current (IDBOOT(pk)) was limited to roughly 5.0 A.
VDD - VDBOOT 12V -1V
IDBOOT(pk) =
=
= 5.0 A
RBOOT
2.2ꢀ
(5)
The power dissipation capability of the bootstrap resistor is important. The bootstrap resistor must be able to
withstand the short period of high power dissipation during the initial charging sequence of the boot-strap
capacitor. This energy is equivalent to 1/2 × CBOOT × V2. This energy is dissipated during the charging time of
the bootstrap capacitor (~3 × RBOOT × CBOOT). Special attention must be paid to use a bigger size RBOOT when a
bigger value of CBOOT is chosen.
版权 © 2017, Texas Instruments Incorporated
29
UCC27712-Q1
ZHCSGJ1 –AUGUST 2017
www.ti.com.cn
8.2.2.5 Selecting Gate Resistor RON/ROFF
Resistor RON and ROFF are sized to achieve the following:
•
•
•
•
Limit ringing caused by parasitic inductances and capacitances.
Limit ringing caused by high voltage/current switching dV/dt, dI/dt, and body diode reverse recovery.
Fine-tune gate drive strength to optimize switching loss.
Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC27712-Q1 has a pull up structure with a P-channel MOSFET providing a
peak source current of 1.8A.
For this example 3.3-Ω resistors for RON and 2.2-Ω resistors for ROFF were selected to provide damping for
ringing and ample gate drive current.
RON = 3.3ꢀ,ROFF = 2.2ꢀ
(6)
Therefore the peak source current can be predicted with:
VDD - VDBOOT
RHOH +RON +RGFET_Int
≈
’
IHO+ = MIN 1.8A,
∆
÷
◊
«
(7)
(8)
VDD
≈
’
ILO+ = MIN 1.8A,
∆
÷
◊
RLOH + RON + RGFET_Int
«
where
•
•
•
RON: External turn-on resistance
RGFET_Int: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current. The maximum values between 1.8 A, the UCC27712-Q1 peak source current, and
the calculated value based on the gate drive loop resistance.
In this example:
VDD - VDBOOT
RHOH + RON + RGFET_Int 3.0ꢀ + 3.3ꢀ +1.0ꢀ
12V
RLOH +RON +RGFET_Int 3.0ꢀ + 3.3ꢀ +1.0ꢀ
12V-0.6V
IHO+ =
=
ö 1.6A
ö 1.6A
(9)
VDD
ILO+ =
=
(10)
Therefore, the high-side and low side peak source current is 1.6 A. Similarly, the peak sink current can be
calculated with:
VDD - VDBOOT - VDGATE
RHOL + ROFF + RGFET_Int
≈
’
IHO- = MIN 2.8A,
∆
÷
◊
«
(11)
(12)
VDD - VDGATE
≈
’
ILO- = MIN 2.8 A,
∆
÷
RLOL + ROFF + RGFET_Int
«
◊
where
•
•
ROFF: External turn-off resistance
VDGATE: The diode forward voltage drop which is in series with ROFF. The diode in this example is an
MBRM130L.
•
IO- = Peak sink current. The maximum values between 2.8 A, the UCC27712-Q1 peak sink current, and the
calculated value based on the gate drive loop resistance.
In this example:
VDD - VDBOOT - VDGATE
12V-0.6 V-0.6 V
1.5ꢀ + 2.2ꢀ +1.0ꢀ
12V-0.6V
IHO- =
=
ö 2.3 A
RHOL + RON + RGFET_Int
VDD - VDGATE
(13)
(14)
ILO- =
=
ö 2.4A
RLOL +RON +RGFET_Int 1.5ꢀ + 2.2ꢀ +1.0ꢀ
30
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
8.2.2.6 Selecting Bootstrap Diode
A fast recovery diode should be chosen to avoid charge being taken away from the bootstrap capacitor. Thus, a
fast reverse recovery time tRR, low forward voltage VF and low junction capacitance is recommended.
Suggested parts include MURA160T3G and BYG20J.
8.2.2.7 Estimate the UCC27712-Q1 Power Losses (PUCC27712-Q1
)
The power losses of UCC27712-Q1 (PUCC27712-Q1) are estimated by calculating losses from several components.
The gate drive loss in the UCC27712-Q1 is typically dominated by gate drive losses associated with charging
and discharging the power device gate charge. There are other losses to consider especially if operating at high
switching frequencies outlined below.
To determine the UCC27712-Q1 operating with no driver load, refer to the Typical Characteristics 图 26 for IDD
and IHB to determine the operating current at the appropriate fSW. The operating current power losses with no
driver load are calculated in 公式 15:
PQ = VVDD ì IVDD,100kHz +IHB,100kHz = 12V ì 310 mA + 350 mA ö 8mW
(15)
Static losses due to leakage current (IBL) are calculated from the HB high-voltage node as shown in 公式 16:
PIBL = VHB ìIBL ìD = 400V ì20mA ì0.5 = 4mW
(16)
公式 17 calculates dynamic losses during the operation of the level shifter at HO turn-off edge. QP, typically 0.6
nC, is the charge absorbed by the level shifter during operation at each edge. Please note that if high-voltage
switching occurs during HO turn-on as well (as in the case of ZVS topologies), then the power loss due to this
component must be effectively doubled.
PLevelShift = VHV +(VHB - VHS) ìQP ìfSW = 411.4V ì0.6nCì100kHz = 24.7mW
»
ÿ
⁄
(17)
where
•
•
VHV: DC link high voltage input in V
fSW: Switching frequency of converter in Hz.
Dynamic losses incurred due to the gate charge while driving the FETs Q1 and Q2 are calculated 公式 18.
Please note that this component typically dominates over the dynamic losses related to the internal VDD and
VHB switching logic circuitry in UCC27712-Q1. The losses incurred driving the gate charge are not all dissipated
in the gate driver device, this includes losses in the external gate resistance and internal power switch gate
resistance.
PQG1,QG2 = 2ì VVDD ìQG ìfSW = 2ì12V ì68nCì100kHz = 163mW
(18)
The UCC27712-Q1 gate driver loss on the output stage ,PGDO, is part of PQG1,QG2. If the external gate resistances
are zero most of the PQG1,QG2 will be dissipated in the UCC27712-Q1. If there are external gate resistances, the
total loss will be distributed between the gate driver pull-up/down resistances and the external gate resistances.
The gate drive power dissipated within the UCC27712-Q1 driver can be determined by 公式 19:
PQG1,QG2
RHOH
RHOL
≈
’
PGDO =
ì
+
∆
«
÷
◊
2
RHOH +RON +RGFET_Int RHOL +ROFF +RGFET_Int
(19)
(20)
In this example the gate drive related losses are approximately 60mW as shown in 公式 20:
≈
∆
«
’
÷
◊
163mW
2
3W
1.5W
PGDO =
ì
+
ö 60mW
3W + 3.3W +1W 1.5W + 2.2W +1W
For the conditions, VDD=12V, VHB = 400V, HO On-state Duty cycle D = 50%, QG = 68nC, fSW = 100kHz, the
total power loss in UCC27712-Q1 driver for a half bridge power supply topology can be estimated as follows:
PUCC27712 = PQ +PIBL +PLevelShift +PGDO = 8mW + 4mW + 25mW + 60mW = 97mW
(21)
版权 © 2017, Texas Instruments Incorporated
31
UCC27712-Q1
ZHCSGJ1 –AUGUST 2017
www.ti.com.cn
8.2.2.8 Estimating Junction Temperature
The junction temperature can be estimated with:
TJ = TC + YJT ìPUCC27712
(22)
where
•
TC is the UCC27712-Q1 case-top temperature measured with a thermocouple or some other instrument.
and
•
ѰJT is the junction-to-top characterization parameter from the Thermal Information table. Importantly.
Using the junction-to-top characterization parameter (ѰJT) instead of the junction-to-case thermal resistance
(RθJC) can greatly improve the accuracy of estimating the junction temperature. The majority of the power
dissipation of most devices is released into the PCB through the package leads, whereas only a small
percentage of the total dissipation is released through the top of the case (where thermocouple measurements
are usually taken). RθJC can only be used effectively when most of the thermal energy is released through the
case, such as with metal packages or a heatsink is applied to the device package. In other cases RθJC will
inaccurately estimate the true junction temperature of the device. ѰJT is experimentally derived by assuming the
amount of thermal energy dissipated through the top of the device will be similar in both the testing environment
and the application environment. As long as the recommended layout guidelines are observed, junction
temperature can be estimated accurately to within a few degrees Celsius. For more information, see the
Semiconductor and IC Package Thermal Metrics application report.
Additional Considerations: In the application example schematic there are 10-kΩ resistors across the gate and
source terminals of FET Q1 and Q2. These resistors are placed across these nodes to ensure FETs Q1 and Q2
are not turned on if the UCC27712-Q1 is not in place or properly soldered to the circuit board or if UCC27712-Q1
is in an unbiased state.
8.2.2.9 Operation With IGBT's
The UCC27712-Q1 is well suited for driving IGBT's in various applications including motor drive and inverters.
The design procedure is as the previous MOSFET example but the VDD voltage is typically 15-V to drive IGBT
devices. Use the power transistor parameters and application specifications to determine the detail design and
component values. See 图 46 below for a typical IGBT application.
Bias
RBIAS
DBOOT
RBOOT
HV
CVDD
DGATE
ROFF
3
2
HB
HO
HS
8
7
VDD
HI
Q1
Q2
RON
RHI
PWM1
PWM2
GND
CBOOT
CHI
RGS
SW
RLI
6
LI
1
DGATE
RON
ROFF
CLI
5
4
LO
RGS
COM
Copyright © 2017, Texas Instruments Incorporated
图 46. Typical IGBT Application Schematic
32
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
Refer to 图 47 below for the UCC27712-Q1 driving 40-A, 650-V IGBT's in a high voltage sync buck configuration.
The input voltage is 400 V, output 100 V with a 150-W output load. Channel 1 is the inductor current, Channel 2
is high-side IGBT VGE, Channel 3 is low-side IGBT VGE, and Channel 4 is the switch node or HS voltage.
IL
HS
GH
GL
图 47. IGBT Sync-Buck Operating at 400 V and 150 W
版权 © 2017, Texas Instruments Incorporated
33
UCC27712-Q1
ZHCSGJ1 –AUGUST 2017
www.ti.com.cn
8.2.3 Application Curves
图 48 and 图 49 show the measured LI to LO turn-on and turn-off delay of one UCC27712-Q1 device. Channel 3
depicts LI and Channel 4 LO.
图 48. LI to LO Turn-On Propagation Delay
图 49. LI to LO Turn-Off Propagation Delay
图 50 and 图 51 show the measured HI to HO turn-on and turn-off delay of one UCC27712-Q1 device. Channel 1
depicts HI and Channel 2 HO.
图 50. HI to HO Turn-On Propagation Delay
图 51. HI to HO Turn-Off Propagation Delay
34
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
IL
HS
GH
GL
图 52. MOSFET Sync-Buck Operating at 400 V and 150 W
图 52 shows UCC27712-Q1 operating in a high voltage sync-buck. Channel 1 depicts inductor current, Channel
2 high side MOSFET VGS, Channel 3 low side MOSFET VGS, and Channel 4 high voltage switch node.
版权 © 2017, Texas Instruments Incorporated
35
UCC27712-Q1
ZHCSGJ1 –AUGUST 2017
www.ti.com.cn
9 Power Supply Recommendations
The VDD power terminal for the device requires the placement of an energy storage capacitor, because of
UCC27712-Q1 is 1.8-A, peak-current driver. And requires the placement of low-esr noise-decoupling capacitance
as directly as possible from the VDD terminal to the COM terminal, ceramic capacitors with stable dielectric
characteristics over temperature are recommended, such as X7R or better.
The recommended storage capacitor is an X7R, 50-V capacitor. The recommended decoupling capacitors
are a 1-µF 0805-sized 50-V X7R capacitor, ideally with (but not essential) a second smaller parallel 100-nF
0603-sized 50-V X7R capacitor.
Similarly, a low-esr X7R capacitance is recommended for the HB-HS power terminals which must be placed
as close as possible to device pins.
10 Layout
10.1 Layout Guidelines
•
Locate UCC27712-Q1 as close as possible to the MOSFETs in order to minimize the length of high-current
traces between the HO/LO and the Gate of MOSFETs, as well as the return current path to the driver HS and
COM.
•
•
A resistor in series with bias supply and VDD pin is recommended.
Locate the VDD capacitor (CVDD) and VHB capacitor (CBOOT) as close as possible to the pins of
UCC27712-Q1.
•
•
•
•
A 2-Ω to 20-Ω resistor series with bootstrap diode is recommended to limit bootstrap current.
A RC filter with 10 Ω to 100 Ω and 10 pF to 220 pF for HI/LI is recommended.
Separate power traces and signal traces, such as output and input signals.
Maintain as much separation as possible from the from the low voltage pins and floating drive HB, HO and
HS pins.
•
Ensure there is not high switching current flowing in the control ground (input signal reference) from the
power train ground.
10.2 Layout Example
图 53. UCC27712-Q1 Layout Example
36
版权 © 2017, Texas Instruments Incorporated
UCC27712-Q1
www.ti.com.cn
ZHCSGJ1 –AUGUST 2017
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
用户指南，使用 UCC27712EVM-287，(SLUUBO1)
11.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及申请样片或购买产品的快速访问
链接。
表 5. 相关链接
器件
产品文件夹
请单击此处
样片与购买
请单击此处
技术文档
工具和软件
请单击此处
支持和社区
请单击此处
UCC27712-Q1
请单击此处
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
37
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC27712QDQ1
UCC27712QDRQ1
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 140
-40 to 140
27712Q
27712Q
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
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所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
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