UCC28019AP [TI]
8-Pin Continuous Conduction Mode (CCM) PFC Controller; 8针连续传导模式（CCM ） PFC控制器
| 型号： | UCC28019AP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Pin Continuous Conduction Mode (CCM) PFC Controller |
| 文件： | 总47页 (文件大小：1110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC28019A
www.ti.com.................................................................................................................................................. SLUS828B–DECEMBER 2008–REVISED APRIL 2009
8-Pin Continuous Conduction Mode (CCM) PFC Controller
1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
8-pin Solution Reduces External Components
Wide-Range Universal AC Input Voltage
Fixed 65-kHz Operating Frequency
Maximum Duty Cycle of 98% (typ.)
Output Over/Under-Voltage Protection
Input Brown-Out Protection
The UCC28019A 8-pin active Power Factor
Correction (PFC) controller uses the boost topology
operating in Continuous Conduction Mode (CCM).
The controller is suitable for systems in the 100 W to
2 kW range over a wide-range universal ac line input.
Start-up current during under-voltage lockout is less
than 200 µA. The user can control low power standby
mode by pulling the VSENSE pin below 0.77 V.
Cycle-by-Cycle Peak Current Limiting
Open Loop Detection
Low-distortion wave shaping of the input current
using average current mode control is achieved
without input line sensing, reducing the external
component count. Simple external networks allow for
flexible compensation of the current and voltage
control loops. The switching frequency is internally
fixed and trimmed to better than 5% accuracy at
25°C. Fast 1.5-A peak gate current drives the
external switch.
Low-Power User Controlled Standby Mode
APPLICATIONS
•
CCM Boost Power Factor Correction Power
Converters in the 100 W to 2 kW Range
Digital TV
Home Electronics
White Goods and Industrial Electronics
Server and Desktop Power Supplies
•
•
•
•
Numerous system-level protection features include
peak current limit, soft over-current, open-loop
detection,
input
brown-out,
and
output
over/under-voltage. Soft start limits boost current
during start-up. A trimmed internal reference provides
accurate protection thresholds and regulation
set-point. An internal clamp limits the gate drive
voltage to 12.5 V.
Typical Application Diagram
VOUT
EMI Filter
LINE
INPUT
Bridge
–
+
Rectifier
GND
GATE
VCC
1
2
3
4
8
7
6
5
Auxilary
Supply
ICOMP
ISENSE VSENSE
VINS VCOMP
Rload
UCC28019A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UCC28019A
SLUS828B–DECEMBER 2008–REVISED APRIL 2009.................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
UCC28019ADG4
UCC28019APG4
PACKAGE
SOIC 8-Pin (D) Lead (Pb)-Free/Green(1)
OPERATING TEMPERATURE RANGE, TA
-40°C to 125°C
Plastic DIP 8-Pin (P) Lead (Pb)-Free/Green
(1) SOIC (D) package is available taped and reeled by adding “R” to the above part number. Reeled quantities are 2,500 devices per reel.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range unless otherwise noted. Unless noted, all voltages are with respect to GND.
Currents are positive into and negative out of the specified terminal.
PARAMETER
VCC, GATE
VALUE
-0.3 to 22
UNIT
Input voltage range
VINS, VSENSE, VCOMP, ICOMP
ISENSE
-0.3 to 7
-24 to 7
-1 to 1
V
Input current range
VSENSE, ISENSE
Operating
mA
°C
-55 to 150
-65 to 150
300
Junction temperature, TJ
Lead temperature, TSOL
Storage
Soldering, 10s
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
DISSIPATION RATINGS(1)
THERMAL IMPEDANCE,
JUNCTION TO AMBIENT (°C/W)
TA = 25°C,
POWER RATING (W)
TA = 85°C,
POWER RATING (W)
PACKAGE
SOIC-8 (D)
PDIP-8 (P)
160
110
0.65
1
0.25
0.36
(1) Tested per JEDEC EIA/JESD 51-1. Thermal resistance is a strong function of board construction and layout. Air flow will reduce thermal
resistance. This number is only a general guide. See TI document SPRA953 IC Thermal Metrics.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC input voltage from a low-impedance source
Operating junction temperature, TJ
MIN
VCCOFF + 1 V
-40
MAX
UNIT
V
21
125
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
PARAMETER
Human Body Model (HBM)
Charged Device Model (CDM)
RATING
UNIT
2
kV
V
500
2
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted, VCC=15 VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
VCC Bias Supply
ICCPRESTART
ICCSTBY
ICC pre-start current
ICC standby current
ICC operating current
VCC = VCCON – 0.1 V
25
1
100
200
µA
VSENSE = 0.5 V
2.2
7.5
2.9
10
mA
ICCON_load
VSENSE = 4.5 V, CGATE = 4.7 nF
4
Under Voltage Lockout (UVLO)
VCCON
VCC turn on threshold
10
9
10.5
9.5
1
11
10
VCCOFF
VCC turn off threshold
UVLO hysteresis
V
0.8
1.2
Oscillator
TA = 25°C
61.7
59
65
65
68.3
71
fSW
Switching frequency
-25°C ≤ TA ≤ 125°C
-40°C ≤ TA ≤ 125°C
kHz
57
71
PWM
VCOMP = 0 V, VSENSE = 5 V,
ICOMP = 6.4 V
DMIN
Minimum duty cycle
0%
DMAX
Maximum duty cycle
Minimum off time
VSENSE = 4.95 V
94%
100
98%
250
99.3%
600
tOFF(min)
VSENSE = 3 V, ICOMP = 1 V
ns
System Protection
ISENSE threshold, Soft Over Current
VSOC
VPCL
IISOP
VISOP
VOLP
-0.66
-1
-0.73
-1.08
-2.1
-0.79
-1.15
-4.0
(SOC)
V
µA
V
ISENSE threshold, Peak Current Limit
(PCL)
ISENSE bias current, ISENSE Open-Pin
Protection (ISOP)
ISENSE = 0 V
ISENSE threshold, ISENSE Open-Pin
Protection (ISOP)
ISENSE = open pin
0.082
0.82
100
VSENSE threshold, Open Loop
Protection (OLP)
ICOMP = 1 V, ISENSE = -0.1 V,
VCOMP = 1 V
0.77
0.86
250
Open Loop Protection (OLP) Internal
pull-down current
VSENSE = 0.5 V
ISENSE = -0.1 V
nA
VSENSE threshold, output
VUVD
VOVP
4.63
5.12
0.76
1.4
4.75
5.25
0.82
4.87
5.38
0.88
Under-Voltage Detection (UVD)(1)
VSENSE threshold, output Over-Voltage
Protection (OVP)
V
VINSBROWNOUT Input Brown-Out Detection (IBOP)
high-to-low threshold
_th
Input Brown-Out Detection (IBOP)
VINSENABLE_th
1.5
0
1.6
low-to-high threshold
IVINS_0V
VINS bias current
VINS = 0 V
±0.1
µA
ICOMP threshold, external overload
protection
0.6
V
(1) Not production tested. Characterized by design.
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, VCC=15 VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Current Loop
gmi
Transconductance gain
Output linear range(2)
TA = 25°C
0.75
0.95
1.15
mS
µA
V
±50
4
ICOMP voltage during OLP
VSENSE = 0.5 V
3.7
4.3
Voltage Loop
VREF
Reference voltage
-40°C ≤ TA ≤ 125°C
4.9
5
-42
5.1
V
gmv
Transconductance gain without EDR
Transconductance gain under EDR
-31.5
-52.5
µS
gmv-EDR
VSENSE = 4.65 V
-440
Maximum sink current under normal
operation
VSENSE = 6 V, VCOMP = 4 V
21
30
38
Source current under soft start
VSENSE = 4 V, VCOMP = 2.5 V
VSENSE = 4 V, VCOMP = 2.5 V
VSENSE = 4 V, VCOMP = 4 V
-21
-30
-300
-170
-38
µA
Maximum source current under EDR
operation
Enhanced dynamic response VSENSE
low threshold, falling(2)
4.63
4.75
4.87
V
VSENSE input bias current
VCOMP voltage during OLP
VCOMP rapid discharge current
VCOMP precharge voltage
VCOMP precharge current
VSENSE = 5 V
20
0
100
0.2
250
0.4
nA
V
VSENSE = 0.5 V, IVCOMP = 0.5 mA
VCOMP = 3 V, VCC = 0 V
IVCOMP = -100 µA, VSENSE = 5 V
VCOMP = 1.0 V
0.77
1.76
-1
mA
V
VPRECHARGE
IPRECHARGE
mA
V
VSENSE threshold, end of soft start
Initial start up
4.95
GATE Driver
GATE current, peak, sinking(2)
GATE current, peak, sourcing(2)
GATE rise time
CGATE = 4.7 nF
2
-1.5
40
A
CGATE = 4.7 nF
CGATE = 4.7 nF, GATE = 2 V to 8 V
CGATE = 4.7 nF, GATE = 8 V to 2 V
IGATE = 0 A
8
8
60
40
ns
GATE fall time
25
GATE low voltage, no load
GATE low voltage, sinking
GATE low voltage, sourcing
0
0.05
0.8
IGATE = 20 mA
0.3
-0.3
0.75
0.9
12.5
10.5
IGATE = -20 mA
-0.8
1.2
VCC = 5 V, IGATE = 5 mA
VCC = 5 V, IGATE = 20 mA
VCC = 20 V, CGATE = 4.7 nF
VCC = 11 V, CGATE = 4.7 nF
0.2
0.2
GATE low voltage, sinking, device OFF
V
1.5
11.0
9.5
14.0
11.0
GATE high voltage
VCC = VCCOFF + 0.2 V, CGATE
4.7 nF
=
8.0
9.4
10.2
(2) Not production tested. Characterized by design.
4
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DEVICE INFORMATION
SOIC PDIP Top View
GND
GATE
VCC
1
2
3
4
8
7
6
5
ICOMP
ISENSE VSENSE
VINS
VCOMP
TERMINAL FUNCTIONS
NAME
GATE
GND
PIN #
I/O
FUNCTION
Gate drive: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 2.0-A
sink and 1.5-A source capability. Output voltage is typically clamped at 12.5 V.
8
1
O
Ground: device ground reference.
Current loop compensation: Transconductance current amplifier output. A capacitor connected to
GND provides compensation and averaging of the current sense signal in the current control loop.
The controller is disabled if the voltage on ICOMP is less than 0.6 V.
ICOMP
2
O
I
Inductor current sense: Input for the voltage across the external current sense resistor, which
represents the instantaneous current through the PFC boost inductor. This voltage is averaged by the
current amplifier to eliminate the effects of ripple and noise. Soft Over Current (SOC) limits the
average inductor current. Cycle-by-cycle Peak Current Limit (PCL) immediately shuts off the GATE
drive if the peak-limit voltage is exceeded. An internal 1.5-µA current source pulls ISENSE above 0.1
V to shut down PFC operation if this pin becomes open-circuited. Use a 220-Ω resistor between this
pin and the current sense resistor to limit inrush-surge currents into this pin.
ISENSE
3
Device supply: External bias supply input. Under-Voltage Lockout (UVLO) disables the controller until
VCC exceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off
(UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 µF minimum value must be connected
from VCC to GND as close to the device as possible for high frequency filtering of the VCC voltage.
VCC
7
5
Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor
network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC,
VINS, and VSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP
is charged until the VSENSE voltage reaches 99% of its nominal regulation level. When Enhanced
Dynamic Response (EDR) is engaged, a higher transconductance is applied to VCOMP to reduce the
charge time for faster transient response. Soft Start is programmed by the capacitance on this pin.
The EDR higher transconductance is inhibited during Soft Start.
VCOMP
O
Input ac voltage sense: A filtered resistor-divider network connects from this pin to the rectified-mains
node. Input Brown-Out Protection (IBOP) detects when the system ac-input voltage is above a
user-defined normal operating level, or below a user-defined “brown-out” level. At startup the
controller is disabled until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft start. The
controller is also disabled if VINS drops below the brown-out threshold of 0.8 V. Operation will not
resume until both VINS and VSENSE voltages exceed their enable thresholds, initiating another soft
start.
VINS
4
6
I
Output voltage sense: An external resistor-divider network connected from this pin to the PFC output
voltage provides feedback sensing for regulation to the internal 5-V reference voltage. A small
capacitor from this pin to GND filters high-frequency noise. Standby mode disables the controller and
discharges VCOMP when the voltage at VSENSE drops below the enable threshold of 0.8 V. An
internal 100-nA current source pulls VSENSE to GND for Open-Loop Protection (OLP), including pin
disconnection. Output Over-Voltage Protection (OVP) disables the GATE output when VSENSE
exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR) rapidly returns the
output voltage to its normal regulation level when a system line or load step causes VSENSE to fall
below 95% of the reference voltage.
VSENSE
I
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Block Diagram
EMI Filter
LBST
DBST
VOUT
LINE
INPUT
Bridge
Rectifier
–
+
RVINS1
RFB1
QBST
RGATE
CIN
COUT
RLOAD
RVINS2
RFB2
10k
RSENSE
ICOMP Protection
0.6V
+
ISOP
UCC28019A Block Diagram
ICOMP
2
PWM
Comparator
KPC(s)
VCC
Current
Amplifier
+
FAULT
Gate Driver
gmi
CICOMP
S
R
Q
Q
+
Fault
4V
IBOP
PWM
RAMP
M2
Fault
Logic
UVLO
GAIN
M1, K1
GATE
Min Off Time
OLP
8
65kHz
Oscillator
PCL
OVP
S
R
Q
Q
Pre-Drive and
Clamp Circuit
Auxiliary
Supply
Clock
M2
M1
VCOMP
SOC
UVLO
RISENSEfilter
VCC
7
1
+
VCCON
10.5V
Q
Q
S
R
40k
40k
CVCC
GND
ISENSE
Peak Current Limit (PCL)
3
300ns
Leading Edge
Blanking
VPCL
1.08V
VCCOFF
9.5V
+
+
+
CISENSEfilter
UVLO
+
+
-1x
OVERVOLTAGE
5.25V
OVP
EDR
Soft Over Current (SOC)
UNDERVOLTAGE
4.75V
VSOC 0.73V
SOC
ISOP
+
OLP/STANDBY
0.82V
+
Input Brown-Out Protection
(IBOP)
OLP/STANDBY
20k
5V
VINS
100nA
Voltage Error
Amplifier
4
+
+
S
R
Q
Q
5V
+
CVINS
VINENABLE_th 1.5V
gmv
VSENSE
CVSENSE
IBOP
6
5
VINBROWNOUT_th 0.82V
gmv Enhancement
+
END OF
SOFT-START
4.95V
END OF SS
VCOMP
RCV
Rapid Discharge
when
VCC < VCCOFF
EDR
UVLO
SS
Q
Q
S
R
END OF SS
FAULT
CCV2
FAULT
CCV1
VPRECHARGE
FAULT
6
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TYPICAL CHARACTERISTICS
Unless otherwise noted, VCC = 15VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
SUPPLY CURRENT
vs
BIAS SUPPLY VOLTAGE
UVLO THRESHOLDS
vs
TEMPERATURE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
12.0
11.0
10.0
9.0
TJ = 25°C
VSENSE = VINS = 3V
No Gate Load
VCC Turn ON
ICC Turn OFF
ICC Turn ON
VCC Turn OFF
0
8.0
0
5
10
15
20
-60
-35
-10
15
40
65
90
115 140
VCC - Bias Supply Voltage - V
TJ - Temperature - °C
Figure 1.
Figure 2.
SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
TEMPERATURE
10
9
8
7
6
5
4
3
2
1
0
0.5
VCC = 15V
VCC = UVLO - 0.1 V
0.4
0.3
Operating, GATE Load = 4.7 nF
0.2
0.1
0
Pre-Start
Standby
-60
-35
-10
15
40
65
90
115 140
-60
-35
-10
15
40
65
90
115 140
TJ - Temperature - °C
TJ - Temperature - °C
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
Unless otherwise noted, VCC = 15VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
OSCILLATOR FREQUENCY
vs
TEMPERATURE
OSCILLATOR FREQUENCY
vs
BIAS SUPPLY VOLTAGE
75
73
75
73
VCC = 15V
TJ = 25°C
71
69
67
65
71
69
67
65
Switching Frequency
Switching Frequency
63
61
59
57
55
63
61
59
57
55
-60
-35
-10
15
40
65
90
115 140
10
12
14
16
18
20
TJ - Temperature - °C
VCC - Bias Supply Voltage - V
Figure 5.
Figure 6.
CURRENT AVERAGING
AMPLIFIER TRANSCONDUCTANCE
VOLTAGE ERROR AMPLIFIER
TRANSCONDUCTANCE
vs
vs
TEMPERATURE
TEMPERATURE
2.0
1.8
50
48
46
VCC = 15V
VCC = 15V
1.6
1.4
1.2
1.0
Gain, No EDR
44
42
40
Gain
0.8
0.6
0.4
0.2
0
38
36
34
32
30
-60
-35
-10
15
40
65
90
115 140
-60
-35
-10
15
40
65
90
115 140
TJ - Temperature - °C
TJ - Temperature - °C
Figure 7.
Figure 8.
8
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TYPICAL CHARACTERISTICS (continued)
Unless otherwise noted, VCC = 15VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
ISENSE THRESHOLD
vs
TEMPERATURE
REFERENCE VOLTAGE
vs
TEMPERATURE
0
5.50
5.25
5.00
VCC = 15V
VCC = 15V
-0.1
-0.2
-0.3
-0.4
Reference Voltage
-0.5
-0.6
Soft Over-Current Protection (SOC)
-0.7
-0.8
4.75
4.50
-0.9
-1.0
-60
-35
-10
15
40
65
90
115 140
-60
-35
-10
15
40
65
90
115 140
TJ - Temperature - °C
TJ - Temperature - °C
Figure 9.
Figure 10.
VSENSE THRESHOLD
vs
TEMPERATURE
VSENSE THRESHOLD
vs
TEMPERATURE
5.50
5.25
5.00
4.75
4.50
2.0
VCC = 15V
1.8
VCC = 15V
1.6
1.4
1.2
1.0
Over-Voltage Protection (VOVP
)
Open Loop Protection
0.8
0.6
0.4
0.2
0
Under-Voltage Protection (VUVD
)
-60
-35
-10
15
40
65
90
115 140
-60
-35
-10
15
40
65
TJ - Temperature - °C
90
115 140
TJ - Temperature - °C
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
Unless otherwise noted, VCC = 15VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
VINS THRESHOLD
vs
TEMPERATURE
MINIMUM OFF TIME
vs
TEMPERATURE
2.0
1.8
600
550
VSENSE = 3 V
ICOMP = 1 V
VCC = 15V
1.6
1.4
1.2
1.0
500
450
400
350
VINS Enable (VINSENABLE_TH
)
0.8
0.6
0.4
0.2
0
300
250
200
105
100
tOFF(min)
Input Brown-Out Protection (VINSBROWNOUT_TH
)
-60
-35
-10
15
40
65
90
115 140
-60
-35
-10
15
40
65
TJ - Temperature - °C
90
115 140
TJ - Temperature - °C
Figure 13.
Figure 14.
GATE DRIVE SWITCHING
vs
TEMPERATURE
GATE DRIVE SWITCHING
vs
BIAS SUPPLY VOLTAGE
50
45
50
45
TJ = 25°C,
CGATE = 4.7 nF
VGATE = 2V-8V
VCC = 15V
CGATE = 4.7 nF
VGATE = 2V-8V
40
35
30
25
40
35
30
25
Rise Time
Fall Time
20
15
10
5
20
15
10
5
Fall Time
Rise Time
0
0
-60
-35
-10
15
40
65
90
115 140
10
12
14
16
18
20
TJ - Temperature - °C
VCC - Bias Supply Voltage - V
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
Unless otherwise noted, VCC = 15VDC, 0.1 µF from VCC to GND, -40°C ≤ TJ = TA ≤ 125°C. All voltages are with respect to
GND. Currents are positive into and negative out of the specified terminal.
GATE LOW VOLTAGE
WITH DEVICE OFF
vs
TEMPERATURE
2.0
VCC = 5V
1.8
ICC = 20mA
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VGATE
-60
-35
-10
15
40
65
90
115 140
TJ - Temperature - °C
Figure 17.
APPLICATION INFORMATION
UCC28019A Operation
The UCC28019A is a switch-mode controller used in boost converters for power factor correction operating at a
fixed frequency in continuous conduction mode. The UCC28019A requires few external components to operate
as an active PFC pre-regulator. Its trimmed oscillator provides a nominal fixed switching frequency of 65 kHz,
ensuring that both the fundamental and second harmonic components of the conducted-EMI noise spectrum are
below the EN55022 conducted-band 150 kHz measurement limit.
Its tightly-trimmed internal 5-V reference voltage provides for accurate output voltage regulation over the typical
world-wide 85-265VAC mains input range from zero to full output load.
Regulation is accomplished in two loops. The inner current loop shapes the average input current to match the
sinusoidal input voltage under continuous inductor current conditions. Under light load conditions, depending on
the boost inductor value, the inductor current may go discontinuous but still meet Class-D requirements of
EN61000-3-2 despite the higher harmonics. The outer voltage loop regulates the PFC output voltage by
generating a voltage on VCOMP (dependent upon the line and load conditions) which determines the internal
gain parameters for maintaining a low-distortion steady-state input current wave-shape.
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Bias Supply
The UCC28019A operates from an external bias supply. It is recommended that the device be powered from a
regulated auxiliary supply.
NOTE:
This device is not intended to be used from a bootstrap bias supply. A bootstrap bias
supply is fed from the input high voltage through a resistor with sufficient capacitance
on VCC to hold up the voltage on VCC until current can be supplied from a bias
winding on the boost inductor. For that reason, the minimal hysteresis on VCC would
require an unreasonable value of hold-up capacitance.
During normal operation, when the output is regulated, current drawn by the device includes the nominal run
current plus the current supplied to the gate of the external boost switch. Decoupling of the bias supply must take
switching current into account in order to keep ripple voltage on VCC to a minimum. A ceramic capacitor of 0.1
µF minimum value from VCC to GND with short, wide traces is recommended.
VCC
VCC(ON) 10.5V
VCC(OFF) 9.5V
ICC
ICC(ON)
ICC(stby) <2.9mA
ICC(start) <200µA
Controller
State
Soft-
Start
UVLO
OFF
Soft-Start
Ramp
Run
Fault/Standby
OFF
Run
UVLO
OFF
PWM
State
Regulated
Ramp Regulated
Figure 18. Device Supply States
The device bias operates in several states. During startup, VCC Under-Voltage Lock-Out (UVLO) sets the
minimum operational dc input voltage of the controller. There are two UVLO thresholds. When the UVLO turn-on
threshold is exceeded, the PFC controller turns ON. If the VCC voltage falls below the UVLO turn-off threshold,
the PFC controller turns off. During UVLO, current drawn by the device is minimal. After the device turns on, Soft
Start (SS) is initiated and the boost inductor current is ramped up in a controlled manner to reduce the stress on
the external components and avoids output voltage overshoot. During Soft Start and after the output is in
regulation, the device draws its normal run current. If any of several fault conditions is encountered or if the
device is put in Standby with an external signal, the device draws a reduced standby current.
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Soft Start
Soft Start controls the rate of rise of VCOMP in order to obtain a linear control of the increasing duty cycle as a
function of time. VCOMP, the output of the voltage loop transconductance amplifier, is pulled low during UVLO,
IBOP, and OLP (Open-Loop Protection)/STANDBY. Once the fault condition is released, an initial pre-charge
source rapidly charges VCOMP to about 1.9 V. After that point, a constant 30 µA of current is sourced into the
compensation components causing the voltage on this pin to ramp linearly until the output voltage reaches 85%
of its final value. At this point, the sourcing current decreases until the output voltage reaches 99% of its final
rated voltage. The Soft-Start time is controlled by the voltage error amplifier compensation capacitor values
selected, and is user programmable based on desired loop crossover frequency. Once the output voltage
exceeds 99% of rated voltage, the pre-charge source is disconnected and EDR is no longer inhibited.
Soft-Start
5V
+
gmv
VCOMP
FAULT
VSENSE
VCOMP
ISS = -30uA
for VSENSE < 4.25V
during Soft-Start
FAULT
END OF SS
(LATCHED)
VPRECHARGE
source for
+
rapid pre-charge
of VCOMP prior
to Soft-Start
Figure 19. Soft Start
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System Protection
System-level protection features help keep the converter within safe operating limits:
VCC Under-Voltage Lockout (UVLO)
During startup, Under-Voltage Lockout (UVLO) keeps the device in the off state until VCC rises above the 10.5-V
enable threshold, VCCON. With a typical 1 V of hysteresis on UVLO to increase noise immunity, the device turns
off when VCC drops to the 9.5-V disable threshold, VCCOFF
.
UVLO
VCC
Auxilary Supply
+
S
R
Q
Q
VCCON 10.5V
VCCOFF 9.5V
CDECOUPLE
GND
UVLO
+
Figure 20. UVLO
If, during a brief ac-line dropout, the VCC voltage falls below the level necessary to bias the internal FAULT
circuitry, the UVLO condition enables a special rapid discharge circuit which continues to discharge the VCOMP
capacitors through a low impedance despite a complete lack of VCC. This helps to avoid an excessive current
surge should the ac-line return while there is still substantial voltage stored on the VCOMP capacitors. Typically,
these capacitors can be discharged to less than 1.2 V within 150 ms of loss of VCC.
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Input Brown-Out Protection (IBOP)
The sensed line-voltage input, VINS, provides a means for the designer to set the desired mains RMS voltage
level at which the PFC pre-regulator should start-up, VACturnon, as well as the desired mains RMS level at which it
should shut down, VACturnoff. This prevents unwanted sustained system operation at or below a brown-out
voltage, where excessive line current could overheat components. In addition, because VCC bias is not derived
directly from the line voltage, IBOP protects the circuit from low line conditions that may not trigger the VCC
UVLO turn-off.
Input Brown-Out Protection (IBOP)
RVINS1
20k
5V
VINS
CVINS
Rectified AC Line
+
S
R
Q
Q
VINENABLE_th 1.5V
RVINS2
CIN
IBOP
+
VINBROWNOUT_th 0.8V
Figure 21. Input Brown-Out Protection
Input line voltage is sensed directly from the rectified ac mains voltage through a resistor-divider filter network
providing a scaled and filtered value at the VINS input. IBOP will put the device into standby mode when VINS
falls (high to low) below 0.8 V, VINSBROWNOUT_th. The device comes out of standby when VINS rises (low to high)
above 1.5 V, VINSENABLE_th. Bias current sourced from VINS, IVINS_0V, is less than 0.1 µA. With a bias current this
low, there is little concern for any set-point error caused by this current flowing through the sensing network. The
highest praticable value resistance for this network should be chosen to minimize power dissipation, especially in
applications requiring low standby power. Be aware that higher resistance values are more susceptible to noise
pickup, but low-noise PCB layout techniques can help mitigate this. Also, depending on the resistor type used
and its voltage rating, RVINS1 should be implemented with multiple resistors in series to reduce voltage stresses.
First, select RVINS1 based on choosing the highest reasonable resistance value available for typical applications.
Then select RVINS2 based on this value:
VINSENABLE _th
RVINS 2 = RVINS1
2VACturnon -VINSENABLE _th
(1)
Power dissipated in the resistor network is:
2
VIN( RMS )
P
=
VINS
R
VINS1 + RVINS 2
(2)
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The filter capacitor, CVINS, has two functions. First, to attenuate the voltage ripple to levels between the enable
and brown-out threshold to prevent ripple on VINS from falsely triggering IBOP when the converter is operating
at low line. Second, CVINS delays the brown-out protection operation for a desired number of line-half-cycle
periods while still having a good response to an actual brown-out event.
The capacitor is chosen so that it will discharge to the VINSBROWNOUT_th level after a delay of N number of line
-cycles to accommodate ac-line dropout ride-through requirements.
-tdischrg
CVINS
=
æ
ç
ç
ö
÷
÷
VINSBROWNOUT _th
RVINS 2
VINS1 + RVINS 2
RVINS 2 ln
ç
ç
è
÷
÷
ø
0.9VAC min
R
(3)
(4)
Where,
1
tdischrg
=
N
2 fLINE
and VACmin is the lowest normal operating rms input voltage.
Output Over-Voltage Protection (OVP)
VOUT(OVP) is the output voltage exceeding 5% of the rated value, causing VSENSE to exceed a 5.25-V threshold
(5-V reference voltage + 5%), VOVP. The normal control loop is bypassed and the GATE output is disabled until
VSENSE falls below 5.25 V. VOUT(OVP) is 420 V in a system with a 400-V rated output, for example.
Open Loop Protection/Standby (OLP/Standby)
If the output voltage feedback components were to fail and disconnect (open loop) the signal from the VSENSE
input, then it is likely that the voltage error amp would increase the GATE output to maximum duty cycle. To
prevent this, an internal pull-down forces VSENSE low. If the output voltage falls below 16% of its rated voltage,
causing VSENSE to fall below 0.8 V, the device is put in standby, a state where the PWM switching is halted and
the device is still on but draws standby current below 2.9 mA. This shutdown feature also gives the designer the
option of pulling VSENSE low with an external switch.
ISENSE Open-Pin Protection (ISOP)
If the current feedback components were to fail and disconnect (open loop) the signal to the ISENSE input, then
it is likely that the PWM stage would increase the GATE output to maximum duty cycle. To prevent this, an
internal pull-up source drives ISENSE above 0.1 V so that a detector forces a state where the PWM switching is
halted and the device is still on but draws standby current below 2.9 mA. This shutdown feature avoids continual
operation in OVP and severely distorted input current.
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Output Under-Voltage Detection (UVD) and Enhanced Dynamic Response (EDR)
During normal operation, small perturbations on the PFC output voltage rarely exceed 5% deviation and the
normal voltage control loop gain drives the output back into regulation. For large changes in line or load, if the
output voltage drop exceeds -5%, an output under-voltage is detected (UVD) and Enhanced Dynamic Response
(EDR) acts to speed up the slow response of the low-bandwidth voltage loop. During EDR, the transconductance
of the voltage error amplifier is increased approximately 16 times to speed charging of the voltage-loop
compensation capacitors to the level required for regulation. EDR is removed when VSENSE > 4.75 V. The EDR
feature is not activated until soft start is completed.
Over and Under Voltage Protection
Open Loop Protection / Standby
Soft-Start Complete
Output Voltage
Standby
OVP
UVD
+
+
RFB1
VSENSE
OVERVOLTAGE
5.25V
UNDERVOLTAGE 4.75V
RFB2
Optional
SOFT-START COMPLETE 4.95V
OPEN LOOP
0.82V
PROTECTION/STANDBY
END OF SS
OLP/STANDBY
+
+
Figure 22. OVP, UVD, OLP/ Standby, Soft Start Complete
OVP 105% VREF
100% VREF
EDR 95% VREF
Feedback
Voltage
OLP/SS 16% VREF
Protection
State
Soft-Start
(No EDR
to 99% VREF
OVP
(No Gate Output)
UVD
(EDR on)
OLP
Run
Run
OLP
)
Figure 23. Soft Start and Protection States
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Over-Current Protection
Inductor current is sensed by RISENSE, a low value resistor in the return path of input rectifier. The other side of
the resistor is tied to the system ground. The voltage is sensed on the rectifier side of the sense resistor and is
always negative. The voltage at ISENSE is buffered by a fixed gain of -1.0 to provide a positive internal signal to
the current functions. There are two over-current protection features; Soft Over-Current (SOC) protects against
an overload on the output and Peak Current Limit (PCL) protects against inductor saturation.
Soft Over Current (SOC)
VSOC
0.73V
SOC
ISENSE Open-Pin
Protection (ISOP)
+
LINE
INPUT
–
+
IISOP
1.5µA
VOUT
VISOP
0.1V
ISOP
RISENSE
+
ISENSE
CISENSEfilter
RISENSEfilter
VPCL
1.08V
300 ns
Leading Edge
Blanking
(Optional)
PCL
+
+
-1x
Peak Current Limit (PCL)
Figure 24. Soft Over Current/ Peak Current Limit
Soft Over Current (SOC)
Soft Over-Current (SOC) limits the input current. SOC is activated when the current sense voltage on ISENSE
reaches -0.73 V, affecting the internal VCOMP level, and the control loop is adjusted to reduce the PWM duty
cycle.
Peak Current Limit (PCL)
Peak Current Limit (PCL) operates on a cycle-by-cycle basis. When the current sense voltage on ISENSE
reaches -1.08 V, PCL is activated, immediately terminating the active switch cycle. PCL is leading-edge blanked
to improve noise immunity against false triggering.
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Current Sense Resistor, RISENSE
The current sense resistor, RISENSE, is sized using the minimum threshold value of Soft Over Current (SOC),
VSOC(min) = 0.66 V. To avoid triggering this threshold during normal operation, resulting in a decreased duty-cycle,
the resistor is sized for an overload current of 10% more than the peak inductor current,
VSOC(min)
RISENSE
£
1.1IL_ PEAK(max)
(5)
Since RISENSE sees the average input current, worst-case power dissipation occurs at input low-line when input
current is at its maximum. Power dissipated by the sense resistor is given by:
P
= ( IIN _ RMS(max) )2 RISENSE
RISENSE
(6)
Peak Current Limit (PCL) protection turns off the output driver when the voltage across the sense resistor
reaches the PCL threshold, VPCL. The absolute maximum peak current, IPCL, is given by:
VPCL
=
IPCL
RISENSE
(7)
Gate Driver
The GATE output is designed with a current-optimized structure to directly drive large values of total MOSFET
gate capacitance at high turn-on and turn-off speeds. An internal clamp limits voltage on the MOSFET gate to
12.5 V (typical). When VCC voltage is below the UVLO level, the GATE output is held in the Off state. An
external gate drive resistor, RGATE, can be used to limit the rise and fall times and dampen ringing caused by
parasitic inductances and capacitances of the gate drive circuit and to reduce EMI. The final value of the resistor
depends upon the parasitic elements associated with the layout and other considerations. A 10-kΩ resistor close
to the gate of the MOSFET, between the gate and ground, discharges stray gate capacitance and helps protect
against inadvertent dv/dt-triggered turn-on.
VCC
Rectified
AC
Gate Driver
L BOOST
UVLO
OLP
FAULT
DBOOST
VOUT
VCC
From
PWM
Latch
Fault
Logic
QBOOST
IBOP
GATE
COUT
RGATE
PCL
OVP
10k
S
R
Q
Q
GND
Pre-Drive and
Clamp Circuit
CLOCK
Figure 25. Gate Driver
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Current Loop
The overall system current loop consists of the current averaging amplifier stage, the pulse width modulator
(PWM) stage, the external boost inductor stage and the external current sensing resistor.
ISENSE and ICOMP functions
The negative polarity signal from the current sense resistor is buffered and inverted at the ISENSE input. The
internal positive signal is then averaged by the current amplifier (gmi), whose output is the ICOMP pin. The
voltage on ICOMP is proportional to the average inductor current. An external capacitor to GND is applied to the
ICOMP pin for current loop compensation and current ripple filtering. The gain of the averaging amplifier is
determined by the internal VCOMP voltage. This gain is non-linear to accommodate the world-wide ac-line
voltage range.
ICOMP is connected to 4V internally whenever the device is in a Fault or Standby condition.
Pulse Width Modulator
The PWM stage compares the ICOMP signal with a periodic ramp to generate a leading-edge-modulated output
signal which is High whenever the ramp voltage exceeds the ICOMP voltage. The slope of the ramp is defined
by a non-linear function of the internal VCOMP voltage.
PWM cycle
VICOMP
VRAMP =
F(VVCOMP
)
tOFF
tON
PWM
t
Figure 26. PWM Generation
The PWM output signal always starts Low at the beginning of the cycle, triggered by the internal clock. The
output stays Low for a minimum off-time, tOFF_min, after which the ramp rises linearly to intersect the ICOMP
voltage. The ramp-ICOMP intersection determines tOFF, and hence DOFF. Since DOFF = VIN/VOUT by the
boost-topology equation, and since VIN is sinusoidal in wave-shape, and since ICOMP is proportional to the
inductor current, it follows that the control loop forces the inductor current to follow the input voltage wave-shape
to maintain boost regulation. Therefore, the average input current is also sinusoidal in wave-shape.
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Control Logic
The output of the PWM comparator stage is conveyed to the GATE drive stage, subject to control by various
protection functions incorporated into the device. The GATE output duty-cycle may be as high as 99%, but will
always have a minimum off-time tOFF_min. Normal duty-cycle operation can be interrupted directly by OVP and
PCL on a cycle-by-cycle basis. UVLO, IBOP and OLP/Standby also terminate the GATE output pulse, and
further inhibit output until the SS operation can begin.
Voltage Loop
The outer control loop of the PFC controller is the voltage loop. This loop consists of the PFC output sensing
stage, the voltage error amplifier stage, and the non-linear gain generation.
Output Sensing
A resistor-divider network from the PFC output voltage to GND forms the sensing block for the voltage control
loop. The resistor ratio is determined by the desired output voltage and the internal 5-V regulation reference
voltage.
Like the VINS input, the very low bias current at the VSENSE input allows the choice of the highest practicable
resistor values for lowest power dissipation and standby current. A small capacitor from VSENSE to GND serves
to filter the signal in a high-noise environment. This filter time constant should generally be less than 100 µs.
Voltage Error Amplifier
The transconductance error amplifier (gmv) generates an output current proportional to the difference between the
voltage feedback signal at VSENSE and the internal 5-V reference. This output current charges or discharges
the compensation network capacitors on the VCOMP pin to establish the proper VCOMP voltage for the system
operating conditions. Proper selection of the compensation network components leads to a stable PFC
pre-regulator over the entire ac-line range and 0-100% load range. The total capacitance also determines the
rate-of-rise of the VCOMP voltage at soft start, as discussed earlier.
The amplifier output VCOMP is pulled to GND during any Fault or Standby condition to discharge the
compensation capacitors to an initial zero state. Usually, the large capacitor has a series resistor which delays
complete discharge for their respective time constant (which may be several hundred milliseconds). If VCC bias
voltage is quickly removed after UVLO, the normal discharge transistor on VCOMP loses drive and the large
capacitor could be left with substantial voltage on it, negating the benefit of a subsequent soft start. The
UCC28019A incorporates a parallel discharge path which operates without VCC bias, to further discharge the
compensation network after VCC is removed.
When output voltage perturbations greater than 5% appear at the VSENSE input, the amplifier moves out of
linear operation. On an over-voltage, the OVP function acts directly to shut off the GATE output until VSENSE
returns within 5% of regulation. On an under-voltage, the UVD function invokes EDR which immediately
increases the voltage error amplifier transconductance to about 440 µS. This higher gain facilitates faster
charging of the compensation capacitors to the new operating level.
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Non-Linear Gain Generation
The voltage at VCOMP is used to set the current amplifier gain and the PWM ramp slope. This voltage is
buffered internally and is then subject to modification by the SOC function, as discussed earlier.
Together the current gain and the PWM slope adjust to the different system operating conditions (set by the
ac-line voltage and output load level) as VCOMP changes, to provide a low-distortion, high-power-factor input
current wave-shape following that of the input voltage.
Layout Guidelines
As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the
integrity of the ground return. The pin out of the UCC28019A is ideally suited for separating the high di/dt
induced noise on the power ground from the low current quiet signal ground required for adequate noise
immunity. A star point ground connection at the GND pin of the device can be achieved with a simple cut out in
the ground plane of the printed circuit board. As shown in Figure 27, the capacitors on ISENSE, VINS, VCOMP,
and VSENSE must all be returned directly to the quiet portion of the ground plane, indicated by Signal GND, and
not the high current return path of the converter, shown as the Power GND. Because the example circuit in
Figure 27 uses surface mount components, the ICOMP capacitor, C10, has its own dedicated return to the GND
pin.
Layout Components
LAYOUT COMPONENTS
Power
GND
REFERENCE
DESIGNATOR
FUNCTION
U1
UCC28019A
Q1
Main switch
R1
RGATE
Cut out in
ground plane
R5
Pull-down resistor on GATE
VCC bypass capacitors
ICOMP compensation, CICOMP
Inrush current limiting resistor, RISENSE
ISENSE filter, CISENSE
RFB1 on VSENSE
C13, C14
C10
GND
GATE
VCC
ICOMP
ISENSE
VSENSE
VCOMP
R6
VINS
C11
R12, R13, R14
R18
Signal
GND
RFB2 on VSENSE
C16
CVSENSE
R16, C17, C15
VCOMP compensation components,
RVCOMP, CVCOMP, CVCOMP_P
C12, R17
D2
CVINS, RVINS2 on VINS
Boost diode
Figure 27. Recommended Layout for the
UCC28019A
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DESIGN EXAMPLE
350-W, Universal Input, 390-VDC Output, PFC Converter
This example illustrates the design process and component selection for a continuous conduction mode power
factor correction boost converter utilizing the UCC28019A. The target design is a universal input, 350-W PFC
designed for an ATX supply application. This design process is directly tied to the UCC28019A Design Calculator
(TI Literature Number SLUC117) spreadsheet that can be found in the Tools section of the UCC28019A product
folder on the Texas Instruments website.
Table 1. Design Goal Parameters
PARAMETER
Input characteristics
Input voltage
TEST CONDITION
MIN
TYP
MAX
UNIT
VIN
85
47
115
265
VAC
Hz
fLINE
Input frequency
63
VAC(on), IOUT = 0.9 A
75
65
Brown out voltage
VAC
VAC(off), IOUT = 0.9 A
Output characteristics
85 VAC ≤ VIN ≤ 265 VAC, 47 Hz ≤ fLINE ≤ 63
VOUT Output voltage
Hz
380
390
402
VDC
0 A ≤ IOUT ≤ 0.9 A
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
VIN = 230 VAC , fLINE = 50 Hz, IOUT = 0.9 A
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
3.9
3.9
VRIPPL High frequency output voltage
ripple
E(SW)
Vpp
VRIPPL
E(f_LIN
19.5
Line frequency output voltage
ripple
VIN = 230 VAC, fLINE = 50 Hz, IOUT = 0.9 A
19.5
E)
85 VAC ≤ VIN ≤ 265 VAC, 47 Hz ≤ fLINE ≤ 63
Hz
IOUT
Output load current
0.9
A
POUT Output power
VOUT(
350
W
Output over voltage protection
410
370
OVP)
V
VOUT(
UVP)
Output under voltage protection
Control loop characteristics
Switching frequency
Control loop bandwidth
Phase margin
fSW
TJ = 25°C
61.7
0.98
0.95
65
14
70
68.3
kHz
Hz
f(CO)
VIN = 162 VDC, IOUT = 0.45 A
VIN = 162 VDC, IOUT = 0.45 A
VIN = 115 VAC, IOUT = 0.9 A
degrees
PF
THD
η
Power factor
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
VIN = 230 VAC, fLINE = 50 Hz, IOUT = 0.9 A
VIN = 115 VAC, fLINE = 60 Hz, IOUT = 0.9 A
4.3%
6.6%
10%
10%
Total harmonic distortion
Full load efficiency
TAMB Ambient temperature
50
°C
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The following procedure refers to the schematic shown in Figure 28.
Figure 28. Design Example Schematic
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Current Calculations
First, determine the maximum average output current, IOUT(max)
:
P
OUT(max)
IOUT(max)
=
VOUT
(8)
(9)
350W
390V
IOUT(max)
=
@ 0.9 A
The maximum input RMS line current, IIN_RMS(max), is calculated using the parameters from Table 1 and the
efficiency and power factor initial assumptions:
P
OUT(max)
I
=
IN _ RMS(max)
hVIN(min)PF
(10)
(11)
350W
I
=
= 4.52A
IN _ RMS(max)
0.92´85V ´0.99
Based upon the calculated RMS value, the maximum peak input current, IIN_PEAK(max), and the maximum average
input current, IIN_AVG(max), assuming the waveform is sinusoidal, can be determined.
IIN _ PEAK(max) = 2IIN _ RMS(max)
(12)
IIN _ PEAK(max) = 2 ´4.52A = 6.39A
(13)
2IIN _ PEAK(max)
IIN _ AVG(max)
=
p
(14)
(15)
2´6.39A
IIN _ AVG(max)
=
= 4.07A
p
Bridge Rectifier
Assuming a forward voltage drop, VF_BRIDGE, of 0.95 V across the rectifier diodes, BR1, the power loss in the
input bridge, PBRIDGE, can be calculated:
P
= 2VF _ BRIDGE IIN _ AVG(max)
BRIDGE
(16)
(17)
P
= 2´0.95V ´4.07A = 7.73W
BRIDGE
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Input Capacitor
Note that the UCC28019A is a continuous conduction mode controller and as such the inductor ripple current
should be sized accordingly. High inductor ripple current has an impact on the CCM/DCM boundary and results
in higher light-load THD, and also affects the choices for RSENSE and CICOMP values. Allowing an inductor ripple
current, IRIPPLE, of 20% and a high frequency ripple voltage factor, ΔVRIPPLE_IN, of 6%, the minimum input
capacitor value, CIN, is calculated by first determining the input ripple current, IRIPPLE, and the input ripple voltage,
VIN_RIPPLE(max)
:
I
RIPPLE = DIRIPPLE IIN _ PEAK(max)
DIRIPPLE = 0.2
RIPPLE = 0.2´6.39A =1.28A
VIN _ RIPPLE(max) = DVRIPPLE _ INVIN _ RECTIFIED(min)
DVRIPPLE _ IN = 0.06
(18)
(19)
(20)
(21)
(22)
I
VIN _ RECTIFIED = 2VIN
(23)
(24)
(25)
VIN _ RECTIFIED(min)
=
2 ´ 85V = 120.2V
VIN _ RIPPLE(max) = 0.06´120.2V = 7.21V
The value for the input x-capacitor can now be calculated:
I
RIPPLE
CIN =
8 fSWVIN _ RIPPLE(max)
(26)
(27)
1.28A
8´65kHz´7.21V
CIN =
= 0.341mF
A 0.33 µF, 275 VAC X2 film capacitor was selected for CIN.
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Boost Inductor
The boost inductor, LBST, is selected after determining the maximum inductor peak current, IL_PEAK(max)
:
IRIPPLE
+
IL_ PEAK(max) = IIN _ PEAK(max)
2
(28)
(29)
1.28A
IL_ PEAK(max) = 6.39A+
= 7.03A
2
The minimum value of the boost inductor is calculated based upon a worst case duty cycle of 0.5:
VOUT D(1- D )
LBST(min)
³
fSW ( typ )IRIPPLE
(30)
(31)
390V ´0.5(1- 0.5)
65kHz´1.28A
LBST(min)
³
³1.17mH
The actual value of the boost inductor that will be used is 1.25 mH.
The maximum duty cycle, DUTY(max), can be calculated and will occur at the minimum input voltage:
VOUT -VIN _ RECTIFIED(min)
=
DUTY
(max)
VOUT
VIN _ RECTIFIED(min) = 2 ´85V =120V
390V -120V
(32)
(33)
DUTY
=
= 0.692
(max)
390V
(34)
Boost Diode
The diode losses are estimated based upon the forward voltage drop, VF, at 125°C and the reverse recovery
charge, QRR, of the diode. This design uses a silicon-carbide diode. Although somewhat more expensive, it
essentially eliminates the reverse recovery losses because QRR is equal to 0nC.
P
=VF _125C IOUT(max) + 0.5 fSW ( typ )VOUT QRR
DIODE
(35)
(36)
(37)
(38)
VF _125C =1.5V
QRR = 0nC
P
=1.5V ´0.897A+ 0.5´65kHz´390V ´0nC =1.35W
DIODE
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Switching Element
The conduction losses of the switch are estimated using the RDS(on) of the FET at 125°C , found in the FET data
sheet, and the calculated drain to source RMS current, IDS_RMS
:
P
= ID2S _ RMS RDSon(125C )
COND
(39)
(40)
RDSon(125C ) = 0.35W
P
16VIN _ RECTIFIED(min)
OUT(max)
IDS _ RMS
=
2 -
VIN _ RECTIFIED(min)
3pVOUT
(41)
350W
120V
16´120V
3p ´390V
IDS _ RMS
=
2 -
= 3.54A
(42)
(43)
P
= 3.54A2 ´0.35W = 4.38W
COND
The switching losses are estimated using the rise time, (tr), and fall time, (tf), of the gate, and the output
capacitance losses.
For the selected device:
tr = 5.0 ns,t f = 4.5 ns
(44)
COSS = 780pF
(45)
P
= fSW ( typ )( 0.5VOUT IIN -PEAK (max) t + t + 0.5COSSVO2UT
)
( )
r f
SW
(46)
(47)
P
= 65kHz( 0.5´390V ´6.39A 5n + 4.5ns + 0.5´780pF ´390V 2 ) = 4.626W
(
)
SW
Total FET losses:
P
COND + P = 4.38W + 4.626W = 9.007W
SW
(48)
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Sense Resistor
To accommodate the gain of the internal non-linear power limit, RSENSE is sized such that it will trigger the soft
over-current at 25% higher than the maximum peak inductor current using the minimum SOC threshold, VSOC, of
ISENSE.
VSOC
RSENSE
=
I
L_ PEAK(max) ´1.25
(49)
(50)
0.66V
7.03A´1.25
RSENSE
=
= 0.075W
Using a parallel combination of available standard value resistors, the sense resistor is chosen.
RSENSE = 0.067W
(51)
The power dissipated across the sense resistor, PRsense, must be calculated:
PRsense = II2N _ RMS(max) RSENSE
(52)
(53)
P
= ( 4.52A)2 ´0.067W =1.37W
Rsense
The peak current limit, PCL, protection feature will be triggered when current through the sense resistor results in
the voltage across RSENSE to be equal to the VPCL threshold. For a worst case analysis, the maximum VPCL
threshold is used:
VPCL
IPCL
=
RSENSE
(54)
1.15V
IPCL
=
=17.16A
0.067W
(55)
To protect the device from inrush current, a standard 220-Ω resistor, RISENSE, is placed in series with the ISENSE
pin. A 1000-pF capacitor, CISENSE, is placed close to the device to improve noise immunity on the ISENSE pin.
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Output Capacitor
The output capacitor, COUT, is sized to meet holdup requirements of the converter. Assuming the downstream
converters require the output of the PFC stage to never fall below 300 V, VOUT_HOLDUP(min), during one line cycle,
tHOLDUP = 1/fLINE(min), the minimum calculated value for the capacitor is:
2POUT tHOLDUP
VO2UT -VO2UT _ HOLDUP(min)
COUT(min)
³
(56)
(57)
2´350W ´21.28ms
390V 2 -300V 2
COUT(min)
³
³ 240mF
It is advisable to de-rate this capacitor value by 20%; the actual capacitor used is 270 µF.
Setting the maximum peak-to-peak output ripple voltage to be less than 5% of the output voltage will ensure that
the ripple voltage will not trigger the output over-voltage or output under-voltage protection features of the
controller. The maximum peak-to-peak ripple voltage, occurring at twice the line frequency, and the ripple current
of the output capacitor are calculated:
V
OUT _ RIPPLE( pp ) < 0.05VOUT
(58)
(59)
V
OUT _ RIPPLE( pp ) < 0.05´390V <19.5VPP
IOUT
VOUT _ RIPPLE( pp )
=
p( 2 fLINE(min) )COUT
(60)
(61)
0.9A
VOUT _ RIPPLE( pp )
=
=11.26V
p( 2´47Hz )´270mF
The required ripple current rating at twice the line frequency is equal to:
IOUT(max)
ICout _2 fline
=
2
(62)
(63)
0.9A
ICout _2 fline
=
= 0.635A
2
There will also be a high frequency ripple current through the output capacitor:
16VOUT
ICout _ HF = IOUT(max)
-1.5
3pVIN _ RECTIFIED(min)
(64)
(65)
16´390V
ICout _ HF = 0.9A
-1.5 =1.8A
3p ´120V
The total ripple current in the output capacitor is the combination of both and the output capacitor must be
selected accordingly:
I
Cout _ RMS( total ) = IC2out _ 2 fline + IC2out _ HF
(66)
(67)
I
Cout _ RMS( total ) = 0.635A2 +1.8A2 =1.9A
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Output Voltage Set Point
For low power dissipation and minimal contribution to the voltage set point error, it is recommended to use 1 MΩ
for the top voltage feedback divider resistor, RFB1. Multiple resistors in series are used due to the maximum
allowable voltage across each. Using the internal 5-V reference, VREF, select the bottom divider resistor, RFB2, to
meet the output voltage design goals.
VREF RFB1
RFB2
=
VOUT -VREF
(68)
5V ´1MW
390V -5V
RFB2
=
=13.04kW
(69)
Using 13 kΩ for RFB2 results in a nominal output voltage set point of 391 V.
The over-voltage protection, OVD, will be triggered when the output voltage exceeds 5% of its nominal set-point:
æ
ç
è
ö
÷
ø
R
FB1 + RFB2
VOUT( OVP ) =VSENSEOVP
RFB2
(70)
(71)
1MW +13kW
13kW
æ
ö
VOUT( OVP ) = 5.25V ´
= 410.7V
ç
è
÷
ø
The under-voltage detection, UVD, will be triggered when the output voltage falls below 5% of its nominal
set-point:
æ
ç
è
ö
÷
ø
R
FB1 + RFB2
VOUT(UVD ) =VSENSEUVD
RFB2
(72)
(73)
1M W +13kW
13kW
æ
ö
VOUT ( UVD ) = 4.75V ´
= 371.6V
ç
è
÷
ø
A small capacitor on VSENSE must be added to filter out noise. Limit the value of the filter capacitor such that
the RC time constant is less than 0.1 ms so as not to significantly reduce the control response time to output
voltage deviations. With careful layout, the noise on this design is minimal, so an RC time constant of 0.01 ms
was all that was needed:
0.01ms
CVSENSE
=
RFB2
(74)
(75)
0.01ms
13kW
CVSENSE
=
= 769pF
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Loop Compensation
The selection of compensation components, for both the current loop and the voltage loop, is made easier by
using the UCC28019A Design Calculator spreadsheet that can be found in the Tools section of the UCC28019A
product folder on the Texas Instruments website. The current loop is compensated first by determining the
product of the internal loop variables, M1M2, using the internal controller constants K1 and KFQ
:
IOUT(max)VO2UT RSENSE
K
1
M M =
1
2
2
h VIN2 _ RMS KFQ
(76)
(77)
1
KFQ
=
fSW ( typ )
1
KFQ
=
=15.385ms
65kHz
(78)
(79)
K = 7
1
0.9A´391V 2 ´0.067W´7
0.922 ´115V 2 ´15.385ms
V
M M =
= 0.374
1
2
ms
(80)
The VCOMP operating point is found on Figure 29. The Design Calculator spreadsheet enables the user to
iteratively select the appropriate VCOMP value.
M1M2
vs
VCOMP
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
VCOMP - V
Figure 29. M1M2 vs. VCOMP
For the given M1M2 of 0.374 V/µs, the VCOMP is approximately equal to 4, as shown in Figure 29.
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The individual loop factors, M1 which is the current loop gain factor, and M2 which is the voltage loop PWM ramp
slope, are calculated using the following conditions:
The M1 current loop gain factor:
•
if : 0 < VCOMP < 2
then : M = 0.064
1
(81)
•
if : 2 ≤ VCOMP < 3
then : M = 0.139´VCOMP - 0.214
1
(82)
(83)
•
if : 3 ≤ VCOMP < 5.5
then : M = 0.279 ´VCOMP - 0.632
1
•
if : 5.5 ≤ VCOMP < 7
then : M = 0.903
1
(84)
(85)
In this example:
VCOMP = 4
M = 0.279´4 - 0.632 = 0.484
1
The M2 PWM ramp slope:
•
if : 0 < VCOMP < 1.5
V
then : M = 0
2
ms
(86)
(87)
(88)
•
if : 1.5 ≤ VCOMP < 5.6
V
then : M = 0.1223´(VCOMP -1.5)2
2
ms
•
if : 5.6 ≤ VCOMP < 7
V
then : M = 2.056
2
ms
In this example:
VCOMP = 4
V
V
M = 0.1223´( 4 -1.5)2
= 0.764
2
ms
ms
(89)
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Verify that the product of the individual gain factors is approximately equal to the M1M2 factor determined above,
if not, reselect VCOMP and recalculate M1M2.
V
V
M ´ M = 0.484´0.764
= 0.37
1
2
ms
ms
(90)
(91)
V
V
0.37
@ M M = 0.372
1 2
ms
ms
The non-linear gain variable, M3, can now be calculated:
if : 0 < VCOMP < 3
•
then : M = 0.0510´VCOMP2 - 0.1543´VCOMP - 0.1167
3
(92)
(93)
•
if : 3 ≤ VCOMP < 7
then : M = 0.1026´VCOMP2 - 0.3596´VCOMP + 0.3085
3
In this example:
VCOMP = 4
M = 0.1026´42 - 0.3596´4 + 0.3085 = 0.512
3
(94)
The frequency of the current averaging pole, fIAVG, is chosen to be at 9.5 kHz. The required capacitor on ICOMP,
CICOMP, for this is determined using the transconductance gain, gmi, of the internal current amplifier:
gmiM
1
CICOMP
=
K 2p fIAVG
1
(95)
(96)
0.95mS ´0.484
CICOMP
=
=1100pF
7´2´p ´9.5kHz
Using a 1200 pF capacitor for CICOMP results in a current averaging pole frequency of 8.7 kHz:
gmiM
1
fIAVG
=
K 2pCICOMP
1
(97)
(98)
0.95mS ´0.484
f
=
= 8.7kHz
IAVG
7´2´p ´1200pF
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The transfer function of the current loop can be plotted:
K RSENSEVOUT
1
1
GCL( f ) =
´
s( f )2 K CICOMP
KFQM M LBST
1
1
2
s( f )+
gmiM
1
(99)
GCLdB( f ) = 20log G ( f )
(
CL
)
(100)
CURRENT AVERAGING CIRCUIT
100
-80
80
60
40
20
0
-100
-120
Phase
Gain
-20
-40
-140
-160
-180
-60
-80
-100
10
100
1*103
f - Hz
1*104
1*105
1*106
Figure 30. Bode Plot of the Current Averaging Circuit.
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The open loop of the voltage transfer function, GVL(f) contains the product of the voltage feedback gain, GFB, and
the gain from the pulse width modulator to the power stage, GPWM_PS, which includes the pulse width modulator
to power stage pole, fPWM_PS. The plotted result is shown in Figure 31.
RFB2
GFB
=
R
FB1 + RFB2
(101)
(102)
13kW
1MW +13kW
GFB
=
= 0.013
1
fPWM _ PS
=
K RSENSEVO3UT COUT
1
2p
KFQM M VIN2 ( typ )
1
2
(103)
(104)
1
fPWM _ PS
=
=1.581Hz
7´0.067W´391V 3 ´270mF
2p
V
15.385ms´0.484´0.764 ´115V 2
ms
M VOUT
3
M M ´1ms
1
2
GPWM _ PS ( f ) =
s( f )
1+
2p fPWM _ PS
(105)
(106)
GVL( f ) = GFBGPWM _ PS ( f )
GVLdB( f ) = 20log G ( f )
(
VL
)
(107)
OPEN LOOP VOLTAGE TRANSFER
FUNCTION
20
0
-20
-40
0
Gain
Phase
-20
-40
-60
-60
-80
-100
0.01
0.1
1
10
100
1*103
1*104
f - Hz
Figure 31. Bode Plot of the Open Loop Voltage Transfer Function
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The voltage error amplifier is compensated with a zero, fZERO, at the fPWM_PS pole and a pole, fPOLE, placed at 20
Hz to reject high frequency noise and roll off the gain amplitude. The overall voltage loop crossover, fV, is desired
to be at 10 Hz. The compensation components of the voltage error amplifier are selected accordingly.
1
fZERO
=
2p RVCOMPCVCOMP
(108)
(109)
1
fPOLE
=
RVCOMPCVCOMPCVCOMP _ P
2p
C
VCOMP + CVCOMP _ P
é
ê
ê
ê
ê
ê
ë
ù
ú
ú
ú
ú
ú
û
1+ s( f )RVCOMPCVCOMP
G ( f ) = gmv
EA
é
ù
ú
æ
ö
RVCOMPCVCOMPCVCOMP _ P
C
(
VCOMP + CVCOMP _ P s( f ) 1+ s( f )
ê
)
ç
ç
÷
÷
CVCOMP + CVCOMP _ P
ê
ë
ú
û
è
ø
(110)
(111)
fV =10Hz
From Figure 31, and the Design Calculator spreadsheet, the open loop gain of the voltage transfer function at 10
Hz is approximately 0.667 dB. Estimating that the parallel capacitor, CVCOMP_P, is much smaller than the series
capacitor, CVCOMP, the unity gain will be at fV, and the zero will be at fPWM_PS, the series compensation capacitor
is determined:
fV
gmv
fPWM _ PS
( f )
CVCOMP
=
G
VLdB
20
10
´2p fV
(112)
(113)
10Hz
42mS ´
1.581Hz
CVCOMP
=
= 3.92mF
0.667dB
20
10
´2´p ´10Hz
A 3.3-µF capacitor is used for CVCOMP
.
1
RVCOMP
=
2p fZEROCVCOMP
(114)
(115)
1
RVCOMP
=
= 30.51kW
2´p ´1.581Hz´3.3mF
A 33.2-kΩ resistor is used for RVCOMP
.
CVCOMP
CVCOMP _ P
=
2p fPOLE RVCOMPCVCOMP -1
(116)
(117)
3.3mF
2´p ´ 20Hz ´ 33.2kW ´ 3.3mF -1
CVCOMP _ P
=
= 0.258mF
A 0.22-µF capacitor is used for CVCOMP_P
.
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The total closed loop transfer function, GVL_total, contains the combined stages and is plotted in Figure 32.
GVL_total ( f ) = GFB( f )GPWM _ PS ( f )GEA( f )
(118)
GVL_totaldB( f ) = 20log G
(
( f )
)
VL_total
(119)
CLOSED LOOP VOLTAGE TRANSFER
FUNCTION
100
100
50
0
80
60
Gain
-50
40
20
0
Phase
-100
-150
0.01
0.1
1
10
100
1*103
1*104
f - Hz
Figure 32. Closed Loop Voltage Bode Plot
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Brown Out Protection
Select the top divider resistor into the VINS pin so as not to contribute excessive power loss. The extremely low
bias current into VINS means the value of RVINS1 could be hundreds of megaOhms. For practical purposes, a
value less than 10 MΩ is usually chosen. Assuming approximately 150 times the input bias current through the
resistor dividers will result in an RVINS1 that is less than 10 MΩ , so as to not contribute excessive noise, and still
maintain minimal power loss. The brown out protection will turn off the gate drive when the input falls below the
user programmable minimum voltage, VAC(off), and turn on when the input rises above VAC(on)
.
IVINS =150´ IVINS _0V
(120)
(121)
IVINS =150´0.1mA =15mA
VAC( on ) = 75V
(122)
(123)
VAC ( off = 65V
)
2 ´VAC( on ) -VF _ BRIDGE -VINSENABLE _th(max)
RVINS1
=
IVINS
(124)
(125)
2 ´75V - 0.95V -1.6V
15mA
RVINS1
=
= 6.9MW
A 6.5-M resistance is chosen.
VINS ENABLE _th(max)´RVINS1
RVINS 2
=
2 ´VAC( on ) -VINSENABLE _th(max) -VF _ BRIDGE
(126)
(127)
1.6V ´6.5MW
=100kW
2 ´75V -1.6V - 0.95V
RVINS 2
=
Copyright © 2008–2009, Texas Instruments Incorporated
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Product Folder Link(s): UCC28019A
UCC28019A
SLUS828B–DECEMBER 2008–REVISED APRIL 2009.................................................................................................................................................. www.ti.com
The capacitor on VINS, CVINS, is selected so that it's discharge time is greater than the output capacitor hold up
time. COUT was chosen to meet one-cycle hold-up time so CVINS will be chosen to meet 2.5 half-line cycles.
NHALF _ CYCLES
tCVINS _ dischrg
=
2´ fLINE(min)
(128)
(129)
2.5
tCVINS _ dischrg
=
= 25.6ms
2´ 47Hz
-tCVINS _dischrg
CVINS
=
é
ê
ê
ù
ú
ú
ú
ú
VINSBROWNOUT _th(min)
RVINS 2 ´ln
ê
ê
æ
ö
÷
ø
RVINS 2
VINS1 + RVINS 2
0.9´V
´
ç
IN _ RMS(min)
R
ê
ë
ú
û
è
(130)
-25.6ms
C
=
= 0.63mF
VINS
é
ê
ê
ù
ú
ú
ú
0.76V
100kW´ln
100kW
æ
ö
ê
0.9´85V ´
ç
è
÷
ø
ê
ë
ú
û
6.5MW +100kW
(131)
40
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Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): UCC28019A
UCC28019A
www.ti.com.................................................................................................................................................. SLUS828B–DECEMBER 2008–REVISED APRIL 2009
Additional References
These references, additional design tools, and links to additional references, including design software and
models may be found on the web at www.power.ti.com under Technical Documents.
Design Spreadsheet, UCC28019A Design Calculator, Texas Instruments Literature Number SLUC117.
Related Products
The following parts have characteristics similar to the UCC28019A and may be of interest.
Related Products
DEVICE
UCC28019
UCC3817/18
UC2853A
DESCRIPTION
8-Pin CCM PFC Controller
Full-Feature PFC Controller
8-Pin CCM PFC Controller
Copyright © 2008–2009, Texas Instruments Incorporated
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41
Product Folder Link(s): UCC28019A
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2009
PACKAGING INFORMATION
Orderable Device
UCC28019AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
UCC28019ADR
UCC28019AP
SOIC
PDIP
D
P
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
UCC28019ADR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
340.5 338.1 20.6
UCC28019ADR
D
8
2500
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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相关型号：
UCC2801D
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