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UCC28065

SLUSDW0B –MAY 2020–REVISED MAY 2020

UCC28065 Natural Interleaving™ Transition-Mode PFC Controller

with High Light-Load Efficiency Supporting High-Frequency Switching up-to 800 kHz

1 Features

3 Description

The UCC28065 interleaved PFC controller enables

transition mode PFC at higher power ratings than

previously possible. The device uses a Natural

Interleaving™ technique to maintain a 180-degree

phase shift. Both channels operate as masters (there

is no slave channel) synchronized to the same

frequency. This approach enables faster response

time, accurate phase shift, and transition mode

operation for each channel. The device has a burst

mode function to get high light-load efficiency. Burst

mode eliminates the need to turn off the PFC during

light load operation to meet standby power targets,

eliminating the need for an auxiliary Flyback when

paired with UCC25640x LLC controller and the

UCC24612 or UCC24624 synchronous rectifier

controllers. The increased frequency clamping

doubles the switching frequency capability compared

with previous generation devices. The increased

switching frequency range also allows the design to

fully utilize the benefits of GaN MOSFETs such as

LMG3410 and SiC MOSFETs.

1

•

Input filter and output capacitor ripple-current

reduction

–

Reduced current ripple for higher system

reliability and smaller bulk capacitor

–

Reduced EMI filter size

•

Higher switching frequency support

–

Up-to 800-kHz switching frequency, reducing

boost inductor size to at least one-half in size

–

Improved input-current THD

High light-load efficiency

–

User adjustable phase management with input

voltage compensation

Burst mode operation with adjustable burst

threshold

Helps enable compliance to EUP Lot6 tier II,

CoC tier II and DOE Level VI standards

•

Sensorless current-shaping simplifies board layout

and improves efficiency

Device Information⁽¹⁾

Input line feed-forward for fast line transient

response

PART NUMBER

PACKAGE

BODY SIZE (NOM)

UCC28065

SOIC (16)

9.90 mm × 3.91 mm

Inrush-safe current limiting:

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

–

Prevents MOSFET conduction during inrush

Eliminates CCM operation and reverse

recovery events in output rectifier

5

P_OUT= 600 W

V_OUT= 40 V

1-phase TM

4

2 Applications

1-phase CCM

•

Slim AC/DC for LED and OLED TVs

All-in-one PC

3

2

High-density AC/DC and gaming adapters

Home audio systems

2-phase TM Interleaved

1

70

120

170

220

270

Input Voltage (V)

Server, telecom, and DIN rail power supplies

Simplified Application

UCC28065

ZCD_B

R_ZCDB

R_ZCDA

VRECT

ZCD_A

VREF

GDA

VOUT

L_B

L_A

VSENSE

TSET

+

L

PHB Threshold

PHB

PGND

VCC

VSENSE

N

CS

HVSEN

VCC

CS

COMP

GDB

VINAC

HVSEN

AGND

VRECT

œ

R_CS

CS

HVSEN

BRST

Burst Threshold

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC28065

SLUSDW0B –MAY 2020–REVISED MAY 2020

www.ti.com

Table of Contents

8.4 Device Functional Modes........................................ 36

Application and Implementation ........................ 37

9.1 Application Information............................................ 37

9.2 Typical Application .................................................. 37

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Description (Continued)........................................ 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 5

7.6 Typical Characteristics.............................................. 9

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 14

8.3 Feature Description................................................. 15

9

10 Power Supply Recommendations ..................... 45

11 Layout................................................................... 46

11.1 Layout Guidelines ................................................. 46

11.2 Layout Example .................................................... 47

12 Device and Documentation Support ................. 48

12.1 Documentation Support ........................................ 48

12.2 Receiving Notification of Documentation Updates 48

12.3 Community Resources.......................................... 48

12.4 Trademarks........................................................... 48

12.5 Electrostatic Discharge Caution............................ 48

12.6 Glossary................................................................ 48

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 49

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2020) to Revision B

Page

•

Changed from Advance Information to initial release............................................................................................................. 1

2

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5 Description (Continued)

Expanded system level protections features include input brownout and dropout recovery, output over-voltage,

open-loop, overload, soft-start, phase-fail detection, and thermal shutdown. The additional fail-safe over-voltage

protection (OVP) feature protects against shorts to an intermediate voltage that, if undetected, could lead to

catastrophic device failure. Advanced non-linear gain results in rapid, yet smooth response to line and load

transient events. Special line-dropout handling avoids significant current disruption. Strong reduction of bias

current when not switching during burst mode operation, improves stand-by performance.

6 Pin Configuration and Functions

D Package

16-Pin SOIC

Top View

ZCD_B

VSENSE

TSET

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

ZCD_A

VREF

GDA

PHB

PGND

VCC

COMP

AGND

VINAC

HVSEN

GDB

CS

BRST

Pin Functions

I/O

DESCRIPTION

NAME

AGND

BRST

COMP

CS

NO.

6

-

I

Analog ground

9

Burst mode threshold input

Error amplifier output

5

O

I

10

14

11

8

Current sense input

GDA

O

I

Phase A gate driver output

Phase B gate driver output

High voltage output sense

Power ground

GDB

HVSEN

PGND

PHB

13

4

-

I

Phase B enable disable threshold input

Timing set

TSET

VCC

3

I

12

7

-

Bias supply input

VINAC

VSENSE

VREF

ZCD_A

ZCD_B

I

Input AC voltage sense

Error amplifier input

2

I

15

16

1

O

I

Voltage reference output

Phase A zero current detection input

Phase B zero current detection input

I

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7 Specifications

7.1 Absolute Maximum Ratings

All voltages are with respect to GND, −40°C < T_J= T_A< 125°C, currents are positive into and negative out of the specified

terminal, unless otherwise noted.

MIN

−0.5

–0.5

MAX UNIT

VCC⁽¹⁾

21

7

COMP⁽²⁾, PHB, HVSEN⁽³⁾, VINAC⁽³⁾, VSENSE⁽³⁾, TSET, BRST

Continuous input voltage

Continuous input current

ZCD_A, ZCD_B

CS⁽⁴⁾

GDA, GDB⁽⁵⁾

4

V

3

VCC + 0.3

VCC

20

±5

25

ZCD_A, ZCD_B

GDA, GDB⁽⁵⁾

VREF

mA

–25

–2

Peak input current

CS

–30

–40

mA

°C

T_J

Operating junction temperature

Soldering 10 s

125

260

150

T_SOL

T_stg

Storage temperature

–65

(1) Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current

limited below the absolute maximum continuous VCC input current level.

(2) In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.

(3) In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing.

Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative

voltage sources, and input currents as high as +0.5mA from positive voltage sources.

(4) In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these

situations, negative voltage on CS may exceed the continuous absolute maximum rating.

(5) No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to

damp resonant ringing due to stray inductance.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

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7.3 Recommended Operating Conditions

All voltages are with respect to GND, −40°C < T_J= T_A< 125°C, currents are positive into and negative out of the specified

terminal, unless otherwise noted.

MIN

14

8

MAX

UNIT

V

VCC input voltage from a low-impedance source

VCC input current from a high-impedance source

VINAC input voltage

21

18

mA

V

0

6

VREF load current

0

–2

mA

kΩ

V

ZCD_A, ZCD_B series resistor

20

66.5

0.8

0

80

TSET resistor to program PWM on-time

HVSEN input voltage

400

4.5

2

PHB Phase management threshold voltage

BRST Burst mode threshold voltage

V

0

V_PHB- 0.6 V

V

7.4 Thermal Information

UCC28064

SOIC (D)

16 PINS

91.6

THERMAL METRIC

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance⁽¹⁾

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

Junction-to-top characterization parameter⁽⁴⁾

Junction-to-board characterization parameter⁽⁵⁾

°C/W

52.1

48.6

14.9

ψ_JB

48.3

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.5 Electrical Characteristics

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCC BIAS SUPPLY

VCC_SHUNT

I_VCC(UVLO)

I_VCC(stby)

I_VCC(on)

VCC shunt voltage⁽¹⁾

VCC current, UVLO

VCC current, disabled

VCC current, enabled

I_VCC= 10 mA

22

24

125

150

5

26

200

210

8

V

VCC = 9.3 V prior to turn on

VSENSE = 0 V

µA

mA

VSENSE = 2 V

VCC current burst mode no

switching

I_VCC(BURST)

V_COMP< V_BURST

650

850

µA

UNDERVOLTAGE LOCKOUT (UVLO)

VCC_ON

VCC turnon threshold

VCC turnoff threshold

UVLO Hysteresis

VCC rising

9.45

8.8

10.35

9.6

11.1

10.7

0.9

V

VCC_OFF

VCC falling

ΔVCC_UVLO

REFERENCE

V_REF

VCC_ON- VCC_OFF

0.68

0.8

VREF output voltage, no load

VREF change with load

I_VREF= 0 mA

5.82

-6

6.00

-1

6.18

V

ΔV_{REF_LOAD}

0 mA ≤ I_VREF≤ −2 mA

mV

(1) Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply.

If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended.

See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.

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Electrical Characteristics (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ΔV_{REF_VCC}

VREF change with VCC

12 V ≤ VCC ≤ 20 V

2

10

mV

ERROR AMPLIFIER

VSENSEreg25

VSENSEreg

I_VSENSE

VSENSE input regulation voltage

T_A= 25°C

5.85

5.82

50

6

6.15

6.18

150

V

VSENSE input regulation voltage

VSENSE input bias current

In regulation

100

1.25

0.07

4.95

0.03

nA

V

V_ENAB

VSENSE enable threshold, rising

VSENSE enable hysteresis

COMP high voltage, clamped

COMP low voltage, saturated

1.15

0.02

4.70

1.35

0.15

5.10

0.125

ΔV_ENAB

V

V_{COMP_CLMP}

V_{COMP_SAT}

VSENSE = VSENSEreg – 0.3 V

VSENSE = VSENSEreg + 0.3 V

V

VSENSE to COMP

transconductance, small signal

0.99(VSENSEreg) < VSENSE <

1.01(VSENSEreg), COMP = 3 V

g_M1

40

55

5

70

µS

%

VSENSE high-going threshold to

enable COMP large signal gain,

percent

V_{SENSE_gM2_SINK}

Relative to VSENSEreg, COMP = 3 V

3.25

6.75

VSENSE low-going threshold to

enable COMP large signal gain,

percent

V_{SENSE_gM2_SOUR}

–6.75

−5

−3.25

%

CE

VSENSE to COMP

transconductance, large signal

g_{M2_SOURCE}

g_{M2_SINK}

VSENSE = VSENSEreg – 0.4 V , COMP = 3 V

VSENSE = VSENSEreg + 0.4 V, COMP = 3 V

210

290

370

µS

VSENSE to COMP

transconductance, large signal

I_{COMP_SOURCE_MA}

COMP maximum source current

COMP discharge resistance

VSENSE = 5 V, COMP = 3 V

-170

1.6

-125

-80

2.4

4.8

µA

kΩ

µA

X

R_COMPDCHG

I_DODCHG

HVSEN = 5.2 V, COMP = 3 V

2

4

COMP discharge current during

Dropout

VSENSE = 5 V, VINAC = 0.3 V, COMP = 1V

3.2

VSENSE overvoltage threshold,

rising

V_{LOW_OV}

Relative to VSENSEreg

Relative to V_{LOW_OV}

6.5

-3

8

-2

9.5

-1.5

12.7

%

ΔV_{LOW_OV_HYST}

V_{HIGH_OV}

VSENSE overvoltage hysteresis

VSENSE 2nd overvoltage threshold,

rising

Relative to VSENSEreg

9.3

11

SOFT START

V_SSTHR

COMP Soft-Start threshold, falling

COMP Soft-Start current, fast

COMP Soft-Start current, slow

VSENSE = 1.5 V

10

-170

-20

23

-125

-16

35

-80

mV

µA

I_SS,FAST

SS-state, V_ENAB< VSENSE < VREF/2

SS-state, VREF/2 < VSENSE < 0.88VREF

I_SS,SLOW

-11.5

VSENSE End-of-Soft-Start threshold

factor

K_EOSS

Percent of VSENSEreg

96.5%

98.3%

99.8%

OUTPUT MONITORING

HVSEN threshold to overvoltage

V_{HV_OV_FLT}

HVSEN rising

HVSEN falling

4.64

4.45

4.87

4.67

5.1

4.8

V

fault

HVSEN threshold to overvoltage

clear

V_{HV_OV_CLR}

GATE DRIVE

V_{GDx_H}

GDA, GDB output voltage, high

GDA, GDB on-resistance, high

GDA, GDB output voltage, low

GDA, GDB on-resistance, low

I_GDA, I_GDB= −100 mA

I_GDA, I_GDB= 100 mA

10.7

12.4

8.8

0.18

2

15

16.7

0.32

3.2

V

Ω

V

Ω

R_{GDx_H}

V_{GDx_L}

R_{GDx_L}

GDA, GDB output voltage high,

clamped

V_{GDx_H_VCCH}

V_{GDx_H_VCCL}

VCC = 20 V, I_GDA, I_GDB= −5 mA

VCC = 12 V, I_GDA, I_GDB= −5 mA

11.8

10

13.5

10.5

15

V

GDA, GDB output voltage high, low

VCC

11.5

V_{GDx_L_UVLO}

t_{GDx_RISE}

GDA, GDB output voltage, UVLO

VCC = 3.0 V, I_GDA, I_GDB= 2.5 mA

1 V to 9 V, C_LOAD= 1 nF

100

18

200

30

mV

ns

Rise time

Fall time

t_{GDx_FALL}

9 V to 1 V, C_LOAD= 1 nF

12

25

ns

6

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Electrical Characteristics (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ZERO CURRENT DETECTOR

ZCD_A, ZCD_B voltage threshold,

falling

V_{ZCDx_TRIG}

V_{ZCDx_ARM}

0.8

1.5

1

1.2

1.9

V

ZCD_A, ZCD_B voltage threshold,

rising

1.7

V_{ZCDx_CLMP_H}

V_{ZCDx_CLMP_L}

I_ZCDx

ZCD_A, ZCD_B clamp, high

ZCD_A, ZCD_B clamp, low

ZCD_A, ZCD_B input bias current

I_{ZCD_A}= +2 mA, I_{ZCD_B}= +2 mA

I_{ZCD_A}= −2 mA, I_{ZCD_B}= −2 mA

ZCD_A = 1.4 V, ZCD_B = 1.4 V

2.6

-0.40

-0.5

3

−0.2

0

3.4

0

V

0.5

µA

ZCD_A, ZCD_B delay to GDA, GDB From ZCD_x input falling to 1 V to respective

t_{ZCDx_DEL}

50

100

ns

outputs

gate drive output rising 10%

t_{ZCDx_BLNK}

CURRENT SENSE

I_CS

ZCD_A, ZCD_B blanking time

From GDx rising and GDx falling⁽²⁾

100

CS input bias current, dual-phase

At rising threshold

PHB = 6 V

-200

-166

-0.2

-120

µA

V

CS current-limit rising threshold,

dual-phase

V_{CS_DPh}

V_{CS_SPh}

V_{CS_RST}

t_{CS_DEL}

-0.22

-0.18

CS current-limit rising threshold,

single-phase

-0.183

-0.025

-0.166

–0.015

-0.149

-0.002

100

V

CS current-limit reset falling

threshold

From CS exceeding threshold−0.05 V to GDx

dropping 10%

CS current-limit response time

CS blanking time

60

ns

t_{CS_BLNK}

From GDx rising and falling edges

100

VINAC INPUT

VINAC input bias current, above

brownout

I_VINAC

VINAC = 2 V

-0.5

1.33

500

0

1.45

640

0.5

1.6

µA

V

V_BOTHR

t_BODLY

VINAC brownout threshold

VINAC brownout filter time

VINAC below the brownout detection threshold

for the brownout filter time

810

ms

VINAC above the brownout threshold for the

brownout reset time after Brown out event

t_BORST

VINAC brownout reset time

300

450

600

ms

I_BOHYS

VINAC brownout hysteresis current

VINAC dropout detection threshold

VINAC = 1 V for > t_BODLY

VINAC falling

1.6

1.95

0.35

2.25

0.38

µA

V

V_DODET

0.310

VINAC below the dropout detection threshold for

the dropout filter time

t_DODLY

VINAC dropout filter time

3.5

5

7

ms

V

V_DOCLR

VINAC dropout clear threshold

VINAC rising

0.67

0.71

0.75

PULSE-WIDTH MODULATOR

On-time factor, two phases

operating, low VINAC_PK

K_TL

VINAC=1.6V, VCOMP=4V⁽³⁾

3.0

0.36

6.1

4.15

0.43

8.3

5.3

0.5

µs/V

On-time factor, two phases

operating, high VINAC_PK

K_TH

VINAC= 5V, VCOMP = 4V⁽³⁾

On-time factor, single-phase

operating, low VINAC_PK

K_TSL

K_TSH

VINAC=1.6V, VCOMP = 1.5V, PHB = 2V⁽³⁾

VINAC= 5V, VCOMP = 1.5V, PHB=2V⁽³⁾

10.5

1.01

On-time factor, single-phase

operating, high VINAC_PK

0.73

0.87

R_TSET= 133 kΩ, VCOMP = 0.3, VINAC = 3 V⁽³⁾

R_TSET= 266 kΩ, VCOMP = 0.3, VINAC = 3 V⁽³⁾

ZCD_A = ZCD_B = 2 V⁽⁴⁾

1.05

1.0

1.5

1.18

210

1.95

1.35

265

t_MIN

Minimum Switching period

PWM restart time

µs

t_START

160

15.1

µs

t_{ONMAX_L}

Maximum FET on time at low VINAC VSENSE = 5.8 V, VINAC=1.6V

20.4

26.2

Maximum FET on time at

VSENSE = 5.8 V, VINAC= 5V

HighVINAC

t_{ONMAX_H}

1.5

2

2.4

µs

(2) ZCD blanking times are ensured by design.

(3) Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET

and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.

(4) An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart

time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.

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Electrical Characteristics (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET= 133 kΩ,

all voltages are with respect to GND, all outputs unloaded, −40°C < T_J= T_A< 125°C, and currents are positive into and

negative out of the specified terminal, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Maximum FET on time at low

VINAC, Single Phase operation.

t_{ONMAX_SL}

VSENSE = 5.8V, VINAC=1.6V, PHB = 6V

11.8

16

20.2

µs

Maximum FET on time at low

VINAC, single phase operation

t_{ONMAX_SH}

VSENSE = 5.8V, VINAC=5 V, PHB = 6V

VSENSE = 5.8 V, VINAC=1.6V

VSENSE = 5.8 V, VINAC= 5V

BRST = 1V, VINAC = 1.5 V

1.37

–6

-6

1.66

1.95

6

µs

%

Phase B to phase A on-time

matching error

Δt_{ONMAX_AB_L}

Δt_{ONMAX_AB_H}

ΔV_{BRST_HYST}

ΔV_{PHB_HYST}

I_{PHB_RANGE}

I_{BRST_RANGE}

Phase B to phase A on-time

matching error

6

%

BRST Hysteresis, COMP voltage

rising

30

80

2

50

150

3

70

210

4.1

mV

µA

PHB Hysteresis COMP voltage

rising

PHB = 3V, VINAC = 2.5 V

PHB pin sourced current when high

input voltage

VINAC = 3.75V, PHB = 2V

BRST pin sourced current when

high input voltage

VINAC = 3.75V, BRST = 2V

PHB = 2V, BRST = 2V

PHB = 2V, BRST=2V

2

2.95

300

3

3.15

350

4.1

3.3

µA

V

V_{VINAC_RANGE_THF}VINAC range falling threshold

VINAC range Hysteresis at rising

edge

ΔV_{INAC_RANGE}

400

mV

THERMAL SHUTDOWN

T_{J_SD}

Thermal shutdown temperature

Thermal restart temperature

Temperature rising⁽⁵⁾

Temperature falling⁽⁵⁾

160

140

°C

T_{J_RST}

(5) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating

temperature is not specified or assured.

8

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7.6 Typical Characteristics

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

2.6

2.4

2.2

2

1.5

1.49

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.41

1.4

1.8

1.6

1.4

1.2

1

1.39

50

100

150

200

250

300

350

400

-40

-20

0

20

40

T_j-Temperature (°C)

60

80

100 120 140

R_TSETvalue (kW)

D001

D101

Figure 1. Minimum Period vs. R_TSETResistance

Figure 2. VINAC Brownout Detection Threshold

6.05

6.04

6.03

6.02

6.01

6

1.9475

1.9425

1.9375

1.9325

1.9275

1.9225

1.9175

1.9125

1.9075

1.9025

1.8975

VREF (V)

VREF_LOAD (V)

5.99

5.98

5.97

5.96

5.95

-40

-20

0

20

40

60

T_j-Temperature (°C)

80

100 120 140

-40

-20

0

20

40

60

T_j-Temperature (°C)

80

100 120 140

D102

D103

Figure 3. VINAC Brownout Hysteresis Current

Figure 4. VREF Output Voltage

11

10.8

10.6

10.4

10.2

10

0.85

0.84

0.83

0.82

0.81

0.8

VCCON (V)

VCCOFF (V)

9.8

0.79

0.78

0.77

0.76

0.75

9.6

9.4

9.2

9

-40

-20

0

20

40

T_j-Temperature (°C)

60

80

100 120 140

-40

-20

0

20

40

T_j-Temperature (°C)

60

80

100 120 140

D104

D105

Figure 5. UVLO On Off Thresholds

Figure 6. UVLO Hysteresis

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Typical Characteristics (continued)

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

10

150

Low OV

Clear

100

50

0

1

Low OV

Trigger

Transconduction

55 ꢀS

0.1

œ50

œ100

œ150

I_VCC(ON)

I_VCC(BURST)

I_VCC(UVLO)

0.01

5.0 5.2 5.4 5.6 6.8 6.0 6.2 6.4 6.6 6.8 7.0

-40

-20

0

20

40

60

T_j-Temperature(°C)

80

100 120 140

VSENSE Input Voltage (V)

D106

Soft-start period completed

Figure 7. VCC Bias Supply Current

Figure 8. Error Amplifier Output Current vs Input Voltage

300

250

200

150

100

50

60

5.9 V < V_VSENSE< 6.1 V

58

56

54

52

50

48

46

44

42

40

0

5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0

−40

−20

0

20

40

60

80

100

120

V_VSENSE− Input Voltage (V)

T_J− Temperature (°C)

G005

G006

Figure 9. Error Amplifier Transconductance vs VSENSE

Figure 10. Error Amplifier Transconductance vs

Temperature

10

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Typical Characteristics (continued)

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

20

14

12

10

8

3.0

2.5

2.0

1.5

1.0

0.5

0

15

10

V_VSENSE= 6.2 V

GD Voltage:

V_CC= 20 V

V_VSENSE= 6.1 V

5

GD Source Current:

V_CC= 20 V

V_CC= 12 V

0

6

V_CC= 12 V

V_VSENSE= 5.9 V

−5

4

V_VSENSE= 5.8 V

−10

−15

−20

2

0

-0.5

-1.0

-2

0

1

2

3

4

5

0

50

100

150

200

250

300

350

V_COMP− Output Voltage (V)

Time (ns)

G007

C_LOAD= 4.7 nF

Figure 11. Error Amplifier Output Current vs Output Voltage

Figure 12. Gate Drive Rising vs Time

14

12

10

8

3.0

2.5

2.0

1.5

1.0

0.5

0

7

6

14

12

10

8

5

GD Output:

T_J= –40°C

GD Sink Current:

V_CC= 20 V

4

T_J= +25°C

V_CC= 12 V

T_J= +125°C

6

3

6

4

2

4

2

1

2

GD Voltage:

V_CC= 20 V

0

-0.5

-1.0

0

ZCD Input Voltage

V_CC= 12 V

-2

-1

-2

0

20

40

60

80

100

120 140

-25

0

50

100

150

200

250

300

Time (ns)

C_LOAD= 4.7 nF

Figure 13. Gate Drive Falling vs Time

C_LOAD= 4.7 nF

Figure 14. Gate Drive Rising and Delay From ZCD Input vs

Time

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Typical Characteristics (continued)

V_VCC= 16 V, V_AGND= V_PGND= 0 V, V_VINAC= 3 V, V_VSENSE= 6 V, V_HVSEN= 3 V, V_PHB= 0 V, R_TSET= 133 kΩ; all voltages are

with respect to GND, all outputs unloaded, T_J= 25°C, and currents are positive into and negative out of the specified terminal,

unless otherwise noted.

500

400

300

200

100

0

14

12

10

8

CS Input

Voltage

6

GD Output:

T_J= -40°C

4

T_J= +25°C

T_J= +125°C

-100

-200

-300

2

0

-2

-25

0

50

100

150

200

250

300

Time (ns)

C_LOAD= 4.7 nF

Figure 15. Gate Drive Falling and Delay From CS Input vs Time

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8 Detailed Description

8.1 Overview

Transition mode (TM) control is a popular choice for the boost power factor correction topology at lower power

levels. Some advantages of this control method are its lower complexity in achieving high power factor and

because lower cost boost diode with higher reverse recovery current specification may be used. In TM control

MOSFET is turned on always when no current is flowing into diode. Interleaved Transition Mode Control retains

this benefit and generally extends the applicability up to much higher power levels while simultaneously

conferring the interleaving benefits of reduced input and output ripple current and system thermal optimization.

To reduce the overall power supply size and improve the power density, the switching frequency needs to be

increased to shrink the inductor size. With higher switching frequency, further EMI fitler size reduction is possible.

The UCC28065 is designed to provide higher switching frequency capability comparing with its earlier

generations, with up to 800-kHz maximum switching frequency.

In UCC28065, burst mode was introduced respect its predecessor (UCC28063) to achieve higher efficiency in

light load conditions. Input voltage feed-forward and threshold adjustment is also available to ensure the user can

optimize performance across line and load conditions. When operating single phase on time of the switching

phase is doubled with the purpose of compensating the missing power from the not switching phase. In this way

for the same COMP value the converter should provide the same output power regardless if operating single

phase mode or dual phase mode. Unfortunately this is not always the case. Component variations and

MOSFETs turn-off delay can lead to big differences (for the same COMP voltage) in the output power delivery.

The Phase Management and Light-Load Operation section will discuss some ways to deal with the variations.

Line voltage feed-forward compensation provides several benefits: it maintains constant bandwidth of the control

loop versus line voltage variation, avoids high current in the MOSFETs, inductors, and line filter when line

transitions from low to high happens, and helps to keep simple Phase Management control because the COMP

pin voltage is almost proportional to Load. Burst Mode enables high efficiency at light load and soft-on and soft-

off in burst mode reduces risk of audible noise. The optimal load current at which the converter should enter

burst mode can be different for different input voltages. These thresholds can be customized by the user.

Interleaving control and phase management facilitates high efficiency 80+ and Energy Star designs with reduced

input and output ripple. The Natural Interleaving method allows TM operation and achieves 180 degrees between

the phases by On-time management. Moreover Natural interleaving method does not rely on tight tolerance

requirements on the inductors. Negative current sensing is implemented on the total input current instead of just

the MOSFET current which prevents MOSFET switching during inrush surges or in any mode where the inductor

current may enter in continuous conduction mode (CCM). This prevents reverse recovery conduction events

between the MOSFET and output rectifier.

Independent output voltage sense circuits with their separate fault management behaviors provide a high degree

of redundancy against PFC stage over-voltage. Brownout, over voltage protection on HVSEN pin (HVSENSE

OV), under voltage lockout (UVLO), and device over-temperature faults will all cause a complete Soft-Start cycle.

Other faults such as short duration AC Drop-Out, minor over-voltage or cycle-by-cycle over-current cause a live

recovery process to initiate by pulling down the COMP pin or by terminating the pulses early.

The error amplifier transconductance is designed to allow smaller compensation components and optimum

transient response for large changes in line or load. The Soft-Start process is carefully optimized. A complete

Soft-Start is implemented. It is dependent on the output voltage sense to speed up start-up from low AC line and

to minimize the effect of excessive capacitance on the COMP pin during start-up into no-load. If some faults

events are triggered COMP pin is fast pulled down to zero. This complete discharge of COMP aids with

preventing excessive currents on recovery from an AC Brown-Out event.

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8.2 Functional Block Diagram

CS_OPEN

Overcurrent

VCC_ON

VCC_OFF

/

CS

OPEN

10

CS

UVLO

100ns

Blanking

OC

12

VCC

167mV

Hyst. 15mV

200mV

Hyst. 15mV

24V

TSD

CS_OPEN

TSET_FAULT

EN

UVLO

HVSEN_OV

BROWNOUT

PHB_OFF

S

R

Q

COMP_DSCHG

7

VINAC

DISCH_RST

2ꢀA

Brownout Detection

1.45V

Hyst. 20mV

5ms

Delay

DROPOUT

640ms

Delay

0.7V /

0.35V

BROWNOUT

VAC_PK

PHB_OFF

PEAK

DETECT

COMP_DSCHG

STOP_GDB

15

6V

VREF

HIGH_OV

OC

VAC_PK

STOP_G

DA

3

TSET

VFF

VFF_ITSET

PHB_OFF

TSET

12.4V Max

STOP_GDA

SW_EN

TSET_FAULT

Phase A

On Time Control

VFF_ITSET

V_{COMP_II}

1.7V /

1V

14

GDA

100ns

Blanking

ZCA

TRIGGER

t_ONModulation

16

ZCD_A

ZCD_B

PGND

Interleave

Control

1.7V /

1V

12.4V Max

100ns

Blanking

ZCB

TRIGGER

t_ONModulation

1

11

13

GDB

Phase B

On Time Control

V_{COMP_II}

SW_EN

VFF_ITSET

STOP_GDB

PGND

VAC_PK

3ꢀA

20mV /

40mV

HLN

3.5V

3.15V

DISCH_RST

HLN

BRST

9

8

DROPOUT

V_{COMP_II}

Burst Mode

Managment

V_COMP

HIGH_OV

PHB_OFF_F

SW_EN

6.67V

V_COMP

HVSEN

2kꢁ

HVSEN_OV

20mV

LOW_OV

4ꢀA

4.87V /

4.67V

6.48V

1.25V

LOW_OV

COMP_DISCH

50mV

EN

DIS_HIGH_GAIN

DIS_EA

EA gain control for

Soft Start

And Dropout

VREF

3ꢀA

2

VSENSE

PHB_OFF_F

HLN

100nA

V_COMP

Phase

Managment

PHB_OFF

4

6

5

AGND

COMP

PHB

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8.3 Feature Description

8.3.1 Principles of Operation

The UCC28065 device contains the control circuits for two parallel-connected boost pulse-width modulated

(PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period

proportional to the voltage on the error amplifier output (COMP pin). Each power converter then turns off the

power MOSFET until current in the boost inductor decays to zero (as sensed on the zero current detection

inputs, ZCD_A and ZCD_B). After the inductor demagnetizes, the power converter starts another cycle. This

cycle process produces a triangular waveform of current, with peak current set by the on-time and the

instantaneous power mains input voltage, V_IN(t) value, as shown in Equation 1.

V (t)´ T_ON

IN

I_PEAK(t) =

L

(1)

The average line current is exactly equal to half of the peak line current, as shown in Equation 2.

V (t)´ T_ON

IN

I_AVG(t) =

2´L

(2)

When the t_ONand L values are essentially constant during an AC-line period, the resulting triangular current

waveform during each switching cycle has an average value proportional to the instantaneous value of the

rectified AC-line voltage. This architecture results in a resistive input impedance characteristic at the line

frequency and a near-unity power factor.

8.3.2 Natural Interleaving

Under normal operating conditions, the UCC28065 device regulates the relative phasing of the channel A and

channel B inductor currents to be approximately 180°. This greatly reduces the switching-frequency ripple

currents seen at the line-filter and output capacitors, compared to the ripple current of each individual converter.

This design allows a reduction in the size and cost of input and output filtering. The phase-control function

differentially modulates the on-times of the A and B channels based on their phase and frequency relationship.

The Natural Interleaving method allows the converter to achieve 180° phase-shift and transition-mode operation

for both phases without tight requirements on boost inductor tolerance.

Ideally, the best current-sharing is achieved when both inductors are exactly the same value. Typically the

inductances are not the same, so the current-sharing of the A and B channels is proportional to the inductor

tolerance. Also, switching delays and resonances of each channel typically differ slightly, and the controller

allows some necessary phase-error deviation from 180° to maintain equal switching frequencies. Optimal phase

balance occurs if the individual power stages and the on-times are well matched. Mismatches in inductor values

do not affect the phase relationship.

Interleaving may not be ideal under all conditions. In particular a loss of interleaving may be experienced at light

loads near the zero crossings. In some cases there may be insufficient current to trigger a large enough signal to

trip the zero crossing detectors. In addition the turn off delay in the MOSFET may dominate the overall on-time at

very light loads. This creates a very limited ability for the controller to correct for phase errors in the system.

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Feature Description (continued)

8.3.3 On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward

compensation

Gate-drive on-time varies proportionately with the error-amplifier output voltage (V_COMP) and inversely

proportional to the squared value of the peak of the rectified input voltage sensed through VINAC pin as stated

by Equation 3. In Equation 3 it is shown that the on-time is inversely proportionally to the value of resistor R_TSET

connected between pin TSET and pin AGND. In order to calculate on-time, Equation 4 can be used. Parameter

K_Tis function of the rectified peak input voltage sensed by pin VINAC as reported in graph of Figure 16. In this

graph three curves are reported for three different values of R_TSET. Two values of parameter K_Tare reported in

Electrical Characteristics the electrical specs table for two values of VINAC: K_TLand K_THcorresponding at the

VINAC = 1.6V and VINAC = 5V and R_TSET= 133kΩ. Because voltage on VINAC is proportional to the line

rectified voltage, for t_ONcalculation purposes we refer to the peak value of this voltage that is obtained through

an internal peak detect. K_Tis inversely proportional to the squared value of VINAC peak value so it is the t_ON

time realizing the so called voltage feed-forward compensation. The Voltage Feed-forward function modifies the

MOSFET on time according to line voltage so, ideally output power delivered does not change if line voltage

changes. When operating in single phase mode K_Tis called K_TSand its value is doubled.

V_COMP-125mV

t_ON

î

V

²ìR_TSET

INAC_PK

(3)

(4)

The COMP pin voltage value is clamped at 4.95 V, so the maximum on time can be calculated by Equation 4.

t_ON= (V_COMP-125mV)ìK_T

Figure 16 shows the values of K_Tversus the peak voltage value on VINAC pin.

K_Tvs V_{INAC, PK}

10

R_TSET

7

66 kW

5

133 kW

266 kW

3

2

1

0.7

0.5

0.3

0.2

0.1

1.5

2

2.5

3

3.5 4

V_INAC,PK(V)

4.5

5

5.5

6

D012

Figure 16. K_Tvs Peak Voltage

The maximum switching frequency of each phase is limited by minimum-period timers. If the inductor current

decays to zero before the minimum-period timer elapses, the next turn on will be delayed, resulting in

discontinuous phase current. As illustrated in Figure 17, when the ZCD signal arrives before the minimum period

expires, the ZCD signal is ignored and the controller waits for the next ZCD signal after the minimum period

expires to turn on the switch. The minimum switching period, t_MIN, is inversely proportional to the time-setting

resistor R_TSET(the resistor from the TSET pin to ground). The typical t_MINas a function of TSET pin resistor value

is shown in Figure 1. The UCC28065 device doubles the clamping frequency compared with UCC28064A. For

more detailed comparison between UCC28065 and UCC28064A, refer to the application note "Convert

UCC28064A EVM to Higher Switching Frequency Using UCC28065".

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Feature Description (continued)

Boost Switch

Vds

V_IN

Boost Switch

Vgs

ZCD

Tmin Clock

Tmin

ZCD after Tmin clock

Frequency is not clamped

TM operation

ZCD before Tmin clock

Frequency is clamped

DCM operation

Figure 17. UCC28065 Frequency Clamp

A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either

phase has not transitioned from high-to-low within approximately 210 µs.

8.3.4 Zero-Current Detection and Valley Switching

In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current reaches zero. Because of

the resonance between the boost inductor and the parasitic capacitance at the MOSFET drain node, part of the

energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore,

when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET

junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate

delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley-switching). In this way,

the energy recovery can be maximized and switching loss is minimized.

The optimal time delay is generally derived empirically, but a good starting point is a value equal to 25% of the

resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 18, but

the delay time increases slightly as the input voltage nears the output voltage. Because the ZCD pin is internally

clamped, a more accurate delay can also be realized by using the circuit shown in Figure 19.

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Feature Description (continued)

ZCD

R

CT

C

Figure 18. Simple RC Delay Circuit

ZCD

R

C

CT

R2

Figure 19. More Accurate Time Delay Circuit

18

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Feature Description (continued)

8.3.5 Phase Management and Light-Load Operation

It is challenging to maintain high efficiency under all loading conditions. When operating in light-load, switching

losses may dominate over conduction losses and the efficiency may be improved if one phase is turned off.

Turning off a phase at light load is especially valuable for meeting light-load efficiency standards. This is a major

benefit of interleaved PFC and it is especially valuable for meeting 80+ design requirements.

In order to ensure smooth operation when removing or adding a phase, some additional considerations are

required. When the number of phases operating is changed from 2 to 1 the overall switching frequency is

reduced by a factor of 2. If everything else is held constant this will also reduce the energy delivered to the load

by a factor of 2. In order to maintain the same power delivery to the output, it is necessary to increase the on-

time when performing such a transition. A similar situation exists when a phase is added. In other words, when

going from 1 phase to 2 phases, the on-time should decrease in order to have smooth continuous power

delivery. If everything is ideal, the amount by which the system has to increase/decrease the on-time is a factor

of 2. Since 1 phase needs to deliver twice the energy as each phase when both phases are operating, doubling

the on-time would seem to make the most sense (or cutting it in half if going from 1 phase to 2 phases). While

this works well in many cases there are real world examples where this fails to provide a sufficiently smooth

phase shedding/adding operation. In order to resolve this conflict the circuit in Figure 20 can be utilized to

program a custom on-time for both 1 phase and 2 phase operation. The circuit operates by monitoring the gate

drive of phase 2 (GDB). When this signal is active the resistor R_TSETconfigures the on-time. When the gate drive

is absent the on-time is configured by the parallel combination of R_TSETand R_{TSET_II}. The capacitors C_FILand

C_HOLDcan be adjusted to set up custom delays in the phase shedding/adding process.

TSET

VREF

GDB

R_{TSET_II}

900 lQ

R_{PULL_UP}

100 lQ

330 Q

M1

D1

1N4148

R_TSET

160 lQ

M2

C_FIL

1 nF

R_DISCH

120 lQ

C_HOLD

4.7 nF

Figure 20. External circuit for Enhanced Phase Shedding

In the case where the 2x factor is sufficient, the UCC28065 can manage this phase shedding/adding process

without the need of the circuit in Figure 20.The PHB input can be used to set the load value when the UCC28065

has to operate in single-phase mode. The UCC28065 internally compares the voltage fed to PHB pin with the

COMP pin voltage. If COMP is below PHB channel B will stop switching and the channel A on-time will

automatically double to compensate the missing power from channel B. When operating in single phase mode in

order to avoid risk of inductor saturation an internal clamp ensures the on time never can exceed the maximum

on-time you will have when operating in dual phase mode. The device will resume dual-phase mode when the

COMP pin voltage exceeds PHB voltage plus the PHB hysteresis. In order to avoid voltage ripple on the COMP

pin causing the system to oscillate between one and two phases a time delay filter is present. In order to change

from normal operation to single phase mode the COMP voltage should stay below PHB pin voltage for 14 line

half cycles. The filter does not apply for the opposite transition. When the COMP pin voltage exceeds PHB pin

voltage plus the hysteresis, channel B is immediately turned on and the channel A on-time is halved.

At start up, the output voltage can be very close to the peak line voltage. The inductor current value during the

off time will decrease very slowly and it is possible systems will operate in CCM for a few switching cycles. In

order to avoid high current, during soft start, the system is forced to work with both phases on even if the COMP

pin voltage is below PHB pin voltage. In two phase mode the on-time of each phase is one half of the on time of

phase A when Phase B is off so this mitigates the risk of high CCM currents.

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Feature Description (continued)

VCC

VREF

6V REG

Error Amplifier

R_U

VSENSE

6MegW

COMP

2pF

4bit Up Counter

D3

clk

6MegW

D2

D1

D0

Phase B off

PHB

2pF

DV = 150mV

Hysteresis

RST

Phase B off

LINE_HR

R_D

V_RECT

I_{PHB_RANGE}

@ 3µA

3.15 V

3.50 V

V_{INAC_PK}

PEAK

DETECT

VINAC

RST_PLS

AGND

Figure 21. Phase Management Block Diagram

Figure 22. Phase Management Time Diagram

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Feature Description (continued)

The voltage on the PHB pin can be set using a simple resistor divider connected to the V_REFpin. Another

important feature, that allows optimization of phase management is that it is possible to set different thresholds

wether the PFC input voltage is in the range of 90 to 132 V_RMS(US mains) or in the range of 180 to 265 V_RMS

(European mains). If the peak voltage sensed by the V_INACpin exceeds 3.5V the converter assumes that the

input voltage is in the range of 180 to 265 V_RMSand starts sourcing from PHB a small current (3µA typically) that

increases the voltage on PHB pin.

Figure 23. Change Phase Management Thresholds

Use Equation 5 and Equation 6 to calculate PHB thresholds.

R_D

V_{PHB _LR}

=

ì V_REF

R_U+ R_D

(5)

(6)

R_D

R_DìR_U

R_D+R_U

V_{PHB_HR}

=

ì V_REF

+

ìI_{PHB_RANGE}

R_U+R_D

The load value at which the system moves between single phase and dual phase modes of operation is part of

the system specification. The formulas to calculate resistor divider resistance values that allows us to get the

desired thresholds are reported below.

DV_PHBì V_REF

V_{PHB _LR}ìI_{PHB _RANGE}

R_U=

(7)

DV_PHBì V_REF

R_D=

V

_REF- V_{PHB_LR}ìI

(

)

PHB_RANGE

where

•

R_Dis the lower resistor of the resistor divider that provides voltage to PHB pin that is supplied by V_REF

R_Uis the upper resistor of the resistor divider.

(8)

(9)

DV_PHB= V_{PHB_HR}- V_{PHB_LR}

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Feature Description (continued)

PHB thresholds are selected by the user according to the load value where they want to turn off Phase B. So

assuming we want to turn off Phase B when the load goes below P_{OUT_PHB}we can calculate the threshold using

Equation 10. We can use the same equation in order to calculate the two thresholds V_{PHB_HR}and V_{PHB_LR}once

provided the two different load values, for US range and EU range where Phase B has to be turned off. Of

course main EU range PHB_OFF load value has to be greater than main US range PHB_OFF load value. A

reasonable range of load values is from 20% to 30% of converter rated power.

P_OUT(PHB)

4.825V

V_REF

V_PHB

=

ì

+125mV

P_OUT(MAX)

(10)

When the COMP voltage goes below the burst mode threshold the device is forced to work in single phase mode

so if the COMP pin voltage drops below the burst threshold it is possible that the time delay filtering is not

respected. Moreover it is recommended that PHB pin voltage is at least 600mV higher than BRST pin voltage.

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Feature Description (continued)

8.3.6 Burst Mode Operation

To further improve light load efficiency burst mode operation can be used. In this case the burst mode threshold

is fed to BRST pin by an external source that could be a simple resistor divider connected to the V_REFpin. If

COMP pin voltage goes below the BRST pin voltage the converter stops switching. When the COMP voltage

exceeds BRST pin voltage plus hysteresis, the converter restarts switching.

In order to have a smooth transition between switching and not switching and vice-versa burst soft-on and burst

soft-off features are added. So when the COMP voltage goes below BRST voltage switching is not stopped

immediately, but there will be eight additional switching cycles where FET on time is decreased gradually. In

similar way when COMP voltage exceeds BRST voltage plus hysteresis a soft-on period occurs where the on

time is increased gradually to a value that corresponds to the present COMP voltage in eight switching cycles.

When the load decreases the device is intended to operate in single phase mode starting from 35% to 15% of

rated load and goes to burst mode at lower load values when single phase operation is activated. If the PHB

threshold is lower than the Burst mode threshold, single phase operation is forced during soft-on and soft-off

periods of burst mode.

Similar to the PHB feature the burst mode threshold has two different levels depending if the PFC input voltage is

in the range of 90 to 132 V_RMS(US main) or in the range of 180 to 265 V_RMS(European main). If the peak

voltage on VINAC pin peak voltage exceeds 3.5 V (typ.) a small current (3 µA typically) is provided from BRST

pin. If a resistor divider is used to set the BRST pin voltage this current will raise the voltage.

Use Equation 11 and Equation 12 to calculate the resistor divider that sets the Burst Mode thresholds. These

equations are identical to the equations used to calculate the PHB resistor divider.

R_Uand R_Dare the upper and the lower resistence of the resistor divider connected to VREF pin.

DV_BRSTì V_REF

V_{BRST _LR}ìI_{BRST _RANGE}

R_U=

(11)

DV_BRSTì V_REF

R_D

=

V

_REF- V_{BRST _LR}ìI

(

)

BRST _RANGE

(12)

8.3.7 External Disable

The UCC28065 can be externally disabled by pulling the VSENSE pin to ground with an open-drain or open-

collector driver. When disabled, the device supply current drops significantly and COMP is actively pulled low.

This disable method forces the device into standby mode and minimizes its power consumption. When VSENSE

is released, the device enters soft-start mode.

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Feature Description (continued)

8.3.8 Improved Error Amplifier

The voltage error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the

error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is

shown in Figure 24. For loop-stability purposes, the compensation network values are calculated based on small-

signal perturbations of the output voltage using the nominal transconductance (gain) of 55 µS.

VREF

COMP

+

g_M

VSENSE

C_Z

C_P

4.95V

R_Z

Figure 24. Transconductance Error Amplifier With Typical Compensation Network

To improve the transient response to large perturbations, the error amplifier gain increases by a factor of around

5X when the error amplifier input deviates more than ±5% from the nominal regulation voltage, VSENSEreg. This

increase allows faster charging and discharging of the compensation components following sudden load-current

increases or decreases.

I_EA

V_SENSE

V_REF

Basic voltage error amplifier transconductance curve showing small-signal and large-signal gain sections, with

maximum current limitations.

Figure 25. Basic Voltage-Error Amplifier Transconductance Curve

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Feature Description (continued)

8.3.9 Soft Start

Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input

voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the

UCC28065 uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by

way of increasing the COMP voltage. To avoid excessive start-up time-delay when the ac-line voltage is low, a

higher current is applied until VSENSE exceeds 3 V at which point the current is reduced to minimize the

tendency for excess COMP voltage at no-load start-up.

The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to

AGND charges from zero to near its final value. This process implements a soft-start, with timing set by the

output current of the error amplifier and the value of the compensation capacitors. Soft-start ends when VSENSE

pin voltage exceeds 95% of VSENSEreg. During soft-start the device will operate with both phases on and even

if the COMP voltage is below the BRST pin voltage the device will not stop switching. In the event of a HVSEN

failsafe OVP, brownout, external-disable, UVLO fault, or other protection faults, COMP is actively discharged and

the UCC28065 will soft-start after the triggering event is cleared. Even if a fault event happens very briefly, the

fault is latched into the soft-start state and soft-start is delayed until COMP is fully discharged to 20 mV and the

fault is cleared. See Figure 26 for details on the COMP current. See Figure 27 which illustrates an example of

typical system behavior during soft-start.

I_COMP

OVP1 trigger. 2k pull-down

applied to COMP.

+63μA

OVP1 reset. 2k pull-down

removed from COMP .

+15μA

-15μA

1.0

2.0

3.0

4.0

5.0

6.0

7.0

VSENSE

COMP current limit

during Soft-Start only

(high-gain disabled )

-111 μA

Expanded COMP output current curve including voltage error amplifier transconductance and modifications applicable

to soft-start and overvoltage conditions.

Figure 26. Expanded COMP pin Output Current Curve

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Feature Description (continued)

OVERSHOOT

V

VSENSE_REG

V_ENDofSS

VSENSE

V_COMPCLMP

COMP

V_SSTHR

t

I_AC-LINE

I_COMP

I_SS,SLOW

I_SS,FAST

HIGH GAIN ENABLED

SOFTSTART

Figure 27. Soft-Start Timing with System Behavior

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Feature Description (continued)

8.3.10 Brownout Protection

As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output

voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher

RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC pin. When the

VINAC fails to exceed the brownout threshold for the brownout filter time (t_BODLY), a brownout condition is

detected and both gate drive outputs are turned off. During brownout, COMP is actively pulled low and soft-start

condition is initiated. When VINAC rises above the brownout threshold, the power stage soft-starts as COMP

rises with controlled current.

The brownout threshold and its hysteresis are set by the voltage-divider ratio and resistor values. Brownout

protection is based on VINAC peak voltage; the threshold and hysteresis are also based on the line peak

voltage. Hysteresis is provided by a 2-μA current-sink (I_BOHYS) enabled whenever Brownout protection is

activated. As soon as the Brownout protection is activated an additional timer is started that counts the t_BORST

time. During this time the device is forced to stay in a Brownout condition. So, during t_BORSTtime, the device is

not allowed to switch, COMP is pulled low and the 2-μA current sink (I_BOHYS) is active regardless of the voltage

on VINAC pin. After t_BORSTis elapsed the device can exit from Brownout condition only if VINAC pin exceeds

V_BOTHRthreshold. When the device operates in burst mode, several blocks inside the IC are turned off to reduce

IC current consumption. The Brownout management block is also turned off. Each time the system stops

switching, because of burst mode, the Brownout filter timer is reset. So if the system is operating in burst mode,

the Brownout protection, generally is not triggered. The main purpose of Brownout is to avoid excess system

thermal stress. When the system is operating in burst-mode the load is low enough to avoid thermal stress. The

peak VINAC voltage can be easily translated into an RMS value. Example resistor values for the voltage divider

are 8.61 MΩ ±1% from the rectified input voltage to VINAC and 133 kΩ ±1% from VINAC to ground. These

resistors set the typical thresholds for RMS line voltages, as shown in Table 1.

Table 1. Brownout Thresholds (For Conditions Stated in the Text)

THRESHOLD

Falling

AC-LINE VOLTAGE (RMS)

67 V

81 V

Rising

Equation 13 and Equation 14 can be used to calculate the VINAC divider-resistors values based on desired

brownout and brown-in voltage levels. V_{AC_OK}is the desired RMS turnon voltage, V_{AC_BO}is the desired RMS

turnoff brownout voltage, and V_LOSSis total series voltage drop due to wiring, EMI-filter, and bridge-rectifier

impedances at V_{AC_BO}. V_BOTHR, and I_BOHYSare found in Electrical Characteristics.

2 ì V

- V_AC

(

)

AC_OK

BO

R_A

=

I_BOHYS

(13)

R_A

R_B=

2V

- V_LOSS

AC_BO

-1

V_BOTHR

(14)

When standard values for the VINAC divider-resistors R_Aand R_Bare selected, the actual turn-on and brownout

threshold RMS voltages for the ac-line can be back-calculated with Equation 15 and Equation 16:

»

…

ÿ

Ÿ

≈

∆

«

’

÷

◊

R_A

R_B

1

V

=

ì

1+

ì V

+ V

AC_BO

BOTHR

^LOSSŸ

2

⁄

(15)

(16)

»

…

ÿ

Ÿ

≈

∆

«

’

÷

◊

R_A

R_B

1

V

=

ì

ì V

+ R_AìI

^BOHYSŸ

AC_OK

BOTHR

2

⁄

An example of the timing for the brownout function is illustrated in Figure 28.

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8.3.11 Line Dropout Detection

It is often the case that the AC-line voltage momentarily drops to zero or nearly zero, due to transient abnormal

events affecting the local AC-power distribution network. Referred to as AC-line dropouts (or sometimes as line-

dips) the duration of such events usually extends to only 1 or 2 line cycles. During a dropout, the down-stream

power conversion stages depend on sufficient energy storage in the PFC output capacitance, which is sized to

provide the ride-through energy for a specified hold-up time. Typically while the PFC output voltage is falling, the

voltage-loop error amplifier output rises in an attempt to maintain regulation. As a consequence, excess duty-

cycle is commanded when the AC-line voltage returns and high peak current surges may saturate the boost

inductors with possible overstress and audible noise.

The UCC28065 incorporates a dropout detection feature which suspends the action of the error amplifier for the

duration of the dropout. If the VINAC voltage falls below 0.35 V for longer than 5 ms, a dropout condition is

detected and the error amplifier output is turned off. In addition, a 4-μA pull down current is applied to COMP to

gently discharge the compensation network capacitors. In this way, when the AC-line voltage returns, the COMP

voltage (and corresponding duty-cycle setting) remains very near or even slightly below the level it was before

the dropout occurred. Current surges due to excess duty-cycle, and their undesired attendant effects, are

avoided. The dropout condition is cancelled and the error amplifier resumes normal operation when VINAC rises

above 0.71 V.

Based on the VINAC divider-resistor values calculated for Brownout in the previous section, the input RMS

voltage thresholds for dropout detection V_{AC_DO}and dropout clearing V_{DO_CLR}can be determined using

Equation 17 and Equation 18, below.

æ

ç

è

ö

R

A

B

V

+1 + V

÷

DODET

LOSS

ø

V

=

AC _DO

2

(17)

(18)

æ

ç

è

ö

R

A

V

+1 + V

÷

DOCLR

LOSS

B

ø

V

=

DO _CLR

2

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Avoid excessive filtering of the VINAC signal, or dropout detection may be delayed or defeated. An RC time-

constant of ≤ 100 s. should provide good performance. Figure 29 shows an example of the timing for the dropout

function.

6 V

VSENSE

3 V

COMP

switching

no switching

switching

Brownout

Detect

VINAC_PK

V_BOTHR

VINAC

t_BODLY

t_BORST

Figure 28. AC-Line Brownout Timing and System Behavior

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V_SENSE

VINAC

COMP

V_DOCLR

V_DODET

0V

t

DROPOUT

t_DODLY

Figure 29. AC-Line Dropout Timing With Illustrative System Behavior

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8.3.12 VREF

VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as

serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance 0.1-

μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external circuits

should not exceed 2mA and should not be pulsing.

The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below

the Enable threshold. This output can only source current and is unable to accept current into the pin.

8.3.13 VCC

VCC is usually connected to a bias supply of between 14 V and 21 V. To minimize switching ripple voltage on

VCC, it should be bypassed with a low-impedance capacitor as close to the VCC and GND pins as possible. The

capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the highest

operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener diode is

recommended to prevent excessive current into VCC.

The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or

has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and

most circuits within the device are disabled and VCC current falls significantly below the normal operating level.

The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during

pre-power up and standby conditions.

8.3.14 System Level Protections

8.3.14.1 Failsafe OVP - Output Over-voltage Protection

Failsafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths

for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is

implemented through two independent paths: VSENSE and HVSEN.

VSENSE pin voltage is compared with two levels of over-voltage. If the lower one, V_{LOW_OV},is exceeded the

COMP pin is discharged by an internal 2-kΩ resistance until the output voltage falls below V_{LOW_OV}reduced of

2% to provide hysteresis (ΔV_{LOW_OV_HYST}). If also the higher over-voltage threshold is exceeded in addition to

activate the 2-kΩ pull down switching is soon disabled. In order to re-enable the switching the sensed voltage

has to fall below V_{LOW_OV}reduced of 2%. Additional over-voltage protection can be implemented on HVSEN pin

through a separate resistor divider to monitor output voltage. An over-voltage is detected if HVSEN pin voltage

exceeds V_{HV_OV_FLT}an as consequence device stops switching and the 2-kΩ pull down is activated. The pull

down 2-kΩ pull down is removed only if HVSEN pin goes below V_{HV_OV_CLR}threshold and the COMP pin is fully

discharged to 20 mV. Both conditions needs to be true before the soft-start can begin.

The converter shuts down if either input senses a severe over-voltage condition. The output voltage can still

remain below a safe limit if either sense path fails. The device is re-enabled when both sense inputs fall back into

their normal ranges. At that time, the gate drive outputs will resume switching under PWM control. A low-level

over-voltage on VSENSE does not trigger soft-start, an higher-level over voltage on VSENSE additionally shuts

off the gate-drive outputs until the OV clears, but still does not trigger a soft-start. However, an over-voltage

detected on HVSEN does trigger a full soft-start and the COMP pin is fully discharged to 20 mV before the soft-

start can begin.

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8.3.14.2 Overcurrent Protection

Under certain conditions (such as inrush, brownout-recovery, and output over-load) the PFC power stage sees

large currents. It is critical that the power devices be protected from switching during these conditions.

The conventional current-sensing method uses a shunt resistor in series with each MOSFET source leg to sense

the converter currents, resulting in multiple ground points and high power dissipation. Furthermore, since no

current information is available when the MOSFETs are off, the source-resistor current-sensing method results in

repeated turn-on of the MOSFETs during overcurrent (OC) conditions. Consequently, the converter may

temporarily operate in continuous conduction mode (CCM) and may experience failures induced by excessive

reverse-recovery currents in the boost diodes or other abnormal stresses.

The UCC28065 uses a single resistor to continuously sense the combined total inductor (input) current. This

way, turn-on of the MOSFETs is completely avoided when the inductor currents are excessive. The gate drive to

the MOSFETs is inhibited until total inductor current drops to near zero, precluding reverse-recovery-induced

failures (these failures are most likely to occur when the AC-line recovers from a brownout condition).

The nominal OC threshold voltage during two-phase operation is -200 mV, which helps minimize losses. This

threshold is automatically reduced to -166 mV during single-phase operation, either by detection of a phase

failure or because COMP is below PHB.

An OC condition immediately turns off both gate-drive outputs, but does not trigger a soft-start and does not

modify the error amplifier operation. The overcurrent condition is cleared when the total inductor current-sense

voltage falls below the OC-clear threshold (–15 mV).

Following an overcurrent condition, both MOSFETs are turned on simultaneously once the input current drops to

near zero. Because the two phase currents are temporarily operating in-phase, the current-sense resistance

should be chosen so that OC protection is not triggered with twice the maximum current peak value of either

phase to allow quick return to normal operation after an overcurrent event. Automatic phase-shift control will re-

establish interleaving within a few switching cycles.

8.3.14.3 Open-Loop Protection

If the feedback loop is disconnected from the device, a 100-nA current source internal to the UCC28065 pulls the

VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device becomes disabled. When

disabled, the bias supply current decreases, both gate-drive outputs and COMP are actively pulled low, and a

soft-start condition is initiated. The device is re-enabled when VSENSE rises above 1.25 V. At that time, the gate

drive outputs will begin switching under soft-start PWM control.

If the resistor connected from AGND pin and VSENSE pin (Low resistor of the resistor divider used to sense

output voltage from VSENSE pin) opens, the VSENSE voltage will be pulled high. When VSENSE rises above

the 2nd-level over-voltage protection threshold, both gate drive outputs are shut off and COMP is actively pulled

low. The device is re-enabled when VSENSE falls below the OV-clear threshold. The VSENSE input can tolerate

a limited amount of current into the device under abnormally high input voltage conditions. Refer to the Absolute

Maximum Ratings table near the beginning of this datasheet for details.

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8.3.14.4 VCC Undervoltage Lock-Out (UVLO) Protection

VCC must rise above the turn-on threshold for the controller to begin functioning. If VCC drops below the UVLO

threshold during operation, both gate-drive outputs are actively pulled low, COMP is actively pulled low, and a

soft-start condition is triggered. VCC must again rise above the turn-on threshold for the PWM function to restart

in soft-start mode.

8.3.14.5 Phase-Fail Protection

The UCC28065 detects failure of either of the phases by monitoring the sequence of ZCD pulses. During normal

two-phase operation, if one ZCD input remains idle for longer than approximately 400 µs while the other ZCD

input switches normally, the over-current threshold is reduced to the value used for single phase operation

(V_{CS_SPh}). During normal single-phase operation, phase failure is not monitored. Phase failure is also not

monitored when COMP is below approximately 250 mV.

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8.3.14.6 CS - Open, TSET - Open and Short Protection

In the event that CS input becomes open-circuited, the UCC28065 detects this condition and will shutdown the

outputs and trigger a full soft start condition. In the event that TSET input becomes either open-circuited or short-

circuited to GND, the UCC28065 detects these conditions and will shutdown the outputs and trigger a full-soft-

start condition. Normal operation will resume (with a soft start) when the fault clears.

8.3.14.7 Thermal Shutdown Protection

Overloading of the gate-drive outputs, VREF, or both can dissipate excess power within the device which may

raise the internal temperature of the circuits beyond a safe level. Even normal power dissipation can generate

excess heat if the thermal impedance is too high or the ambient temperature is too high. When the UCC28065

detects an internal over-temperature condition it will shutdown the outputs and trigger a full soft-start condition.

When the internal device junction temperature has cooled below the thermal hysteresis temperature, operation

will resume under soft-start control.

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8.3.14.8 Fault Logic Diagram

Figure 30 depicts the fault-handling logic involving VSENSE, COMP, and several internal states. It should be

noted that recovery from any fault except OC if the soft start is not triggered, will result in single phase soft-on

operation (8 switching cycles).

PHASE_B_OFF

STOP GDB

OC

STOP GDA

HIGH_OV

HIGH_OV Latch

BROWNOUT

6.67 V

S

Q

HVSEN_OV

UVLO

COMP Discharge Latch

+

S

Q

EN

Q

R

TSET_FLT

R

Q

CS_OPEN

TSD

LOW_ OV Latch

6.38 V

6.36 V

S

Q

+

20 mV

R

Q

OV-Clear

COMP

4 µA

2 kΩ

EN

1.25 V

+

LOW_OV

DIS_EA

DROPOUT

Gain-Disable Latch

S

Q

V_CC

DIS_High_Gain

+

R

Q

5.9 V

3.0 V

V_SENSE

Figure 30. Fault Logic With VSENSE Detections and Error Amplifier Control

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8.4 Device Functional Modes

The controller is primarily intended for set up as a dual phase interleaved PFC which utilizes inductor

demagnetization information based on inductor sense winding voltages which are routed to ZCD_A and ZCD_B

to trigger the start of a switching cycle.

The functionality may be extended in a couple of ways:

Phase-B Enable and Disable: When the voltage on COMP is below the voltage on the PHB pin, Phase B and

the Phase Fail Detector will be disabled. The on-time for Phase-A will be doubled to compensate

the Phase-B missing power. When the voltage on COMP is greater than the PHB pin voltage, two

phase mode is enabled. Connect PHB to a resistor divider sourced by VREF to set a threshold for

COMP pin and obtain an automatic light load efficiency management feature. Because when PHB

voltage is higher then COMP voltage, the on-time is doubled, in order to avoid risk of inductor

saturation an internal clamp ensures the on-time never can exceed dual phase mode maximum on-

time.

PFC Stage Enable and Disable Control: Controller operation is enabled when VSENSE voltage exceeds the

1.25-V enable threshold. The primary disable method should be by pulling VSENSE low by an open

drain or open collector logic output. This will disable the outputs and significantly reduce VCC

current. Releasing VSENSE will initiate a soft-start. Avoid any PCB traces which would couple any

noise into this node.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

This control device is generally applicable to the control of AC-DC power supplies which require Active Power

Factor Correction off Universal AC line. Applications using this device generally meet the Class-D equipment

input current harmonics standards per EN61000-3-2. This standard applies to equipment with rated Powers

higher than 75W. The device brings two phase interleaved control capability to the Transition Mode Boost and

hence will be generally a very good choice for cost optimized applications in the 150W to 800W space, or to

even lower powers that wish to leverage on the interleaving benefits of reduced filtering component size, lower

profile solutions and distributed thermal management.

9.2 Typical Application

Figure 31 shows an example of the UCC28065 PFC controller in a two-phase interleaved, transition-mode PFC

pre-regulator. For more detailed comparison between UCC28065 and UCC28064A, refer to the application note

"Convert UCC28064A EVM to Higher Switching Frequency Using UCC28065".

D1

L_A

L

R_ZA

D2

L_B

C_ZA

N

+

R_ZB

C_B

220nF

PHB THRESHOLD

R_E

C_ZB

C_OUT

ZCD_B

VSENSE

TSET

ZCD_A

VREF

GDA

VSENSE

R_C

R_T

Q1

HVSEN

PHB THRESHOLD

PHB

PGND

VCC

VSENSE

R_D

C_Z

R_Z

COMP

AGND

VINAC

HVSEN

C_P

Q2

R_F

GDB

CS

R_A

HVSEN

BRST

R_B

-

R_S

Figure 31. Typical Interleaved Transition-Mode PFC Preregulator

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Typical Application (continued)

9.2.1 Design Requirements

The specifications for this design were chosen based on the power requirements of a typical 300-W LCD TV.

Table 2 lists these specifications.

Table 2. Design Specifications

DESIGN PARAMETER

RMS input voltage

MIN

TYP

MAX

UNIT

V_IN

85

265

(VIN_MAX)

VRMS

(VIN_MIN)

V_OUT

f_LINE

PF

Output voltage

390

V

AC-line frequency

47

63

Hz

Power factor at maximum load

0.90

P_OUT

η

300

W

Full-load efficiency

92%

f_MIN

Minimum switching frequency

45

kHz

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

The boost inductor is selected based on the minimum switching requirements. Operating at the boundary

between DCM and CCM the minimum switching frequency will be at maximum power and at the peak of the line.

It is possible that the minimum switching frequency can occur at minimum line or at maximum line. Equation 20.

hì V

²ì V_OUT- 2 ì V

0.92ì 264V ²ì 390V - 2 ì264V

(

)

(

)

(

)

IN_MAX

L_H=

L_L=

=

= 338mH

f_MINì V_OUTìP_{OUT _MAX}

27kHzì390V ì300W

(19)

hì V

²ì V

- 2 ì V

IN_MIN

0.92ì 85V ²ì 390V - 2 ì85V

(

)

(

)

(

)

IN_MIN

OUT

=

= 568mH

f_MINì V_OUTìP_{OUT _MAX}

27kHzì390V ì300W

(20)

In order to be sure that converters operates always above the desired (f_MIN) we will select the minimum value

between L_Hthat would be the value we have if we consider the minimum occurs at maximum input voltage and

L_Lthat would be the value we have if we consider that minimum switching frequency occurs at minimum Line

voltage. For this design example, f_MINis set to 27 kHz in order to be always above the audible range. For a 2-

phase interleaved design, L_Aand L_Bare determined by minimum between L_Hand L_Las stated in formula (19)

here belowEquation 21.

L_A= L_B= min(L_H,L_L) @ 340mH

(21)

The inductor for this design would have a peak current (I_LPEAK) of 5.4 A, as shown in Equation 22, and an RMS

current (I_LRMS) of 2.2 A, as shown in Equation 23.

P_OUT

2

300W 2

I_LPEAK

=

» 5.4Apk

V_{IN_MIN}´ h 85V ´ 0.92

(22)

(23)

I

5.4A

6

LPEAK

I

=

» 2.2Arms

LRMS

6

This converter uses constant on time (T_ON) and zero-current detection (ZCD) to set up the converter timing.

Auxiliary windings on L₁and L_Bdetect when the inductor currents are zero. Selecting the turns ratio using

Equation 24 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after

every switching cycle.

The turns-ratio of each auxiliary winding is:

V_OUT- V

2

N_P

N_s

390V - 265V 2

2V

IN_MAX

=

» 8

2V

(24)

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9.2.2.2 ZCD Resistor Selection R_ZA, R_ZB

The minimum value of the ZCD resistors is selected based on the internal clamps maximum current ratings of 3

mA, as shown in Equation 25.

V

N

390V

OUT

S

R

= R

³

ZB

=

N ´ 3mA 8´3mA

» 16.3kW

ZA

P

(25)

(26)

In this design the ZCD resistors are set to 20 kΩ, as shown in Equation 26.

= R = 20kW

R

ZA

ZB

9.2.2.3 HVSEN

According to R_Eand R_Fresistor values, the Failsafe OVP threshold will be set according to Equation 27

4.87V R + R

(

4.87V 8.22MW + 82.5kW

(

82.5kW

)

E

F

V

=

» 490V

OV _FAILSAFE

R

F

(27)

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9.2.2.4 Output Capacitor Selection

The output capacitor ( C_OUT) is selected based on holdup requirements, as shown in Equation 28.

P_OUT

1

300W

1

2

h

f_LINE

0.92 47Hz

390V²- (252V)²

C_OUT

³

=

» 156mF

V_OUT²- (V_{OUT _MIN}

2

)

(28)

(29)

Two 100-μF capacitors were used in parallel for the output capacitor.

= 200mF

C

OUT

For this size capacitor, the low-frequency peak-to-peak output voltage ripple (V_RIPPLE) is approximately 14 V, as

shown in Equation 30:

2´P

1

2´300W

OUT

V

=

» 14Vppk

RIPPLE

h

V

´ 4p´ f

´ C

OUT

0.92´ 390V ´ 4p´ 47Hz ´ 200mF

OUT

LINE

(30)

In addition to holdup requirements, a capacitor must be selected so that it can withstand the low-frequency RMS

current (I_{COUT_100Hz}) and the high-frequency RMS current (I_{COUT_HF}); see Equation 31 to Equation 33. High-

voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current ratings on the

product data sheets.

P_OUT

300W

I_{COUT _100Hz}

=

= 0.591 Arms

V

_OUT´ h´ 2 390V ´ 0.92´ 2

(31)

æ

ç

ö²

÷

4 2V

2

P_OUT2 2

2´ h´ V

IN_MIN

I_{COUT _HF}

=

- I

(

COUT _100Hz

)

ç

÷

9pV_OUT

IN_MIN

è

ø

(32)

(33)

2

æ

ç

ö

÷

300W ´ 2 2 4 2 ´85V

2´ 0.92´85V 9p´390V

2

)

I

=

- 0.591A » 0.966Arms

(

COUT _HF

ç

è

÷

ø

40

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9.2.2.5 Selecting R_SFor Peak Current Limiting

The UCC28065 peak limit comparator senses the total input current and is used to protect the MOSFETs during

inrush and over-load conditions. For reliability, the peak current limit (I_PEAK) threshold in this design is set for

120% of the nominal maximum current that will be observed during power up, as shown in Equation 34.

2P_OUT2(1.2)

2´300W 2 ´1.2

0.92´85V

I_PEAK

=

» 13A

h´ V

IN_MIN

(34)

A standard 15-mΩ metal-film current-sense resistor will be used for current sensing, as shown in Equation 35.

The estimated power loss of the current-sense resistor (P_RS) is less than 0.25 W during normal operation, as

shown in Equation 36.

200mV 200mV

R_S=

=

» 15mΩ

I_PEAK

13A

(35)

(36)

ö²

÷

ø

æ

ö²

÷

P_OUT

_{IN_MIN}´ h

æ

300W

85V ´0.92

P

=

R_S=

´15mW » 0.22 W

ç

÷

RS

ç

V

è

ø

The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to

withstand a short-circuit current larger than the current required to open the fuse (F1). I²t (ampere-squared-

seconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I²t is equal

to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I²t of 14 A²s was

chosen to protect the design from a short-circuit condition. To ensure the current-sense resistor has high-enough

surge protection, a 15-mΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-W

surge rating for 5 seconds. This result translates into 833 A²s and has a high-enough I²t rating to survive a short-

circuit before the fuse opens, as described in Equation 37.

2.5W

2

I t =

2

´ 5s = 833A s

0.015W

(37)

9.2.2.6 Power Semiconductor Selection (Q1, Q2, D1, D2)

The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. For an explanation of

how to select power semiconductor components for transition-mode PFC preregulators, refer to UCC38050 100-

W Critical Conduction Power Factor Corrected (PFC) Pre-regulator.

The MOSFET (Q1, Q2) pulsed-drain maximum current is shown in Equation 38:

I_DM³ I_PEAK= 13A

(38)

The MOSFET (Q1, Q2) RMS current calculation is shown in Equation 39:

4 2 V

I_PEAK

1

6

13A

2

1

6

4 2 ´85V

9p´390V

IN_MIN

I_DS

=

-

=

-

» 2.3A

2

9p´ V_OUT

(39)

(40)

To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.

The boost diode (D1, D2) RMS current is shown in Equation 40:

4 2 ´ V

I

13A 4 2 ´85V

IN_MIN

PEAK

I

=

» 1.4A

D

2

9p´ V

2

9p´ 390V

OUT

To meet the power requirements of the design, MURS360T3, 600-V diodes were chosen for D1 and D2.

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9.2.2.7 Brownout Protection

Resistor R_Aand R_Bare selected to activate brownout protection at ~75% of the specified minimum-operating

input voltage. Resistor R_Aprograms the brownout hysteresis comparator, which is selected to provide 17 V (~12

V_RMS) of hysteresis. Calculations for R_Aand R_Bare shown in Equation 41 through Equation 44.

Hysteresis 17V

=

R

=

= 8.5MW

A

2mA

(41)

(42)

(43)

(44)

To meet voltage requirements, three 2.87-MΩ resistors were used in series for R_A.

R

= 3´ 2.87MW = 8.61MW

A

1.4V ´R

1.4V ´8.61MW

A

R

=

´ 0.75 2 -1.4V 85V ´0.75 2 -1.4V

= 135.8kW

B

V

IN_MIN

Select a standard value for R_B.

= 133kW

R

B

In this design example, brownout becomes active (shuts down PFC) when the input drops below 67 V_RMSfor

longer than 680 ms and deactivates (restarts with a full soft start) if, after that the t_BORSTtime is elapsed, the input

reaches 81 V_RMS

.

9.2.2.8 Converter Timing

The MOSFET on-time T_ONdepends on value of the selected inductance on load value, represented by COMP

pin voltage and by the converter AC input voltage Equation 45. To ensure proper operation, the timing must be

set based on the highest boost inductance (L_{A_MAX}) and output power (P_OUT) at minimum operating AC input

Voltage. Because the input voltage is sensed by VINAC pin the on time setting needs to take into account of the

selected resistor divider that provide voltage at VINAC pin. In this design example, the boost inductor could be as

high as 390 µH.

Let's call K_BOthe voltage divider ratio on VINAC pin:

R_A+ R_B

R_B

9.61MW +133kW

133kW

K_BO

=

= 65.74

(45)

the Maximum on time at full load (P_OUT= 300W) and minimum input voltage (85V_AC) is given by formula;

P_OUTìL

300W ì340mH

t_{ON_MAX}

=

= 15.34ms

2

0.92ì 85V

(

)

hì V

(

)

IN_MIN

(46)

The value of the resistor R_Tconnected to TSET pin to set the on time timers is the minimum of R_THand R_TL

provided by Equation 48 and Equation 49

R = min R_TL,R_TH

(

)

T

(47)

(48)

(49)

K_{TH_MIN}ì 5V ²ì133kW ì 4.825V

(

)

R_TH

=

2

≈

’

2 ì V

IN_MIN

∆

«

÷

◊

ì t_{ON_MAX}

K_BO

K_{TL _MIN}ì 1.6V ²ì133kW ì 4.825V

(

)

R_TL

=

2

≈

’

2 ì V

IN_MIN

∆

«

÷

◊

ì t_{ON_MAX}

K_BO

Where the values of K_{TL_min}and K_{TH_min}are the minimum values of K_TLand K_THparameters reported in Electrical

Characteristics.

The selected value for R_Tis 115 kΩ.

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9.2.2.9 Programming V_OUT

Resistor R_Cis selected to minimize loading on the power line when the PFC is disabled. Construct resistor R_C

from two or more resistors in series to meet high-voltage requirements. Resistor R_Dis then calculated based on

R_C, the reference voltage, V_REF, and the required output voltage, V_OUT. Based on the values shown in

Equation 50 to Equation 53, the primary output overvoltage protection threshold should be as shown in

Equation 54:

R

= 2.74MW + 2.74MW + 3.01MW = 8.49MW

C

(50)

(51)

V

= 6 V

REF

V

´R

C

6V ´ 8.49MW

390V - 6V

REF

R

=

= 132.7kW

D

V

- V

REF

OUT

(52)

Select a standard value for R_D.

R

= 133kW

D

(53)

(54)

R

+ R

D

8.49MW +133kW

133kW

C

V

= 6.48V

= 420.1V

OVP

R

D

9.2.2.10 Voltage Loop Compensation

Resistor R_Zis sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This

value ensures good power factor and low harmonic distortion on the input current. The voltage on the COMP pin

needs to stay above 250 mV to maintain normal operation. If COMP falls below this threshold switching will stop.

The transconductance amplifier small-signal gain is shown in Equation 55:

g

= 50mS

m

(55)

(56)

(57)

The voltage-divider feedback gain is shown in Equation 56:

V

6V

REF

H =

=

» 0.015

V

390V

OUT

The value of R_Zis calculated as shown in Equation 57:

100mV

R

=

= 9.52 kW

Z

V

´H´ g

14V ´0.015´50mS

RIPPLE

m

C_Zis then set to add 45° phase margin at 1/5th of the line frequency, as shown in Equation 58:

1

f_LINE

5

1

C_Z

=

= 1.78mF

47Hz

2p´

´ 9.52kW

2p´

´R_Z

5

(58)

(59)

C_Pis sized to attenuate high-frequency switching noise, as shown in Equation 59:

1

f_MIN

2

1

45kHz

2

C_p=

=

= 770pF

2p´

´ 9.52kW

2p´

´R_Z

Standard values should be chosen for R_Z, C_Zand C_P, as shown in Equation 60 to Equation 62.

R

= 9.53kW

= 2.2mF

= 820pF

Z

(60)

(61)

(62)

C

Z

C

P

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9.2.3 Application Curves

9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving

Figure 32 through Figure 34 show the input current (CH2), Inductor Ripple Currents (CH3, CH4) versus rectified

line voltage. From these graphs, it can be observed that natural interleaving reduces the overall magnitude of

input (and output) ripple current caused by the individual inductor current ripples.

CH3 = Phase A Inductor

Current

CH3 = Phase A Inductor

Current

CH2 = Input Current

CH4 = Phase B Inductor

Current

CH4 = Phase B Inductor

Current

Figure 32. Inductor and Input Ripple Current at 85 V_RMSat

Peak of Line Voltage

Figure 33. Inductor and Input Ripple Current at 265 V_RMS

Input at Peak Line Voltage

CH2 = Input Current

CH3 = Phase A Inductor Current

CH4 = Phase B Inductor Current

Figure 34. Inductor and Input Ripple Current at V_IN= 85 V_RMS, P_OUT= 300 W

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9.2.3.2 Brownout Protection

The UCC28065 has a brownout protection that shuts down both gate drives (GDA and GDB) when the VINAC

pin detects that the RMS input voltage is too low. Figure 35.

CH1 = V_GDA

CH3 = V_OUT

CH2 = V_GDB

CH3 = V_IN

Figure 35. UCC28065 Response to a Line Brownout Event at 115 V_RMS

10 Power Supply Recommendations

The device receives all of its power through the VCC pin. This voltage should be as well regulated as possible

through all of the operating conditions of the PFC stage. Consider creating the steady state bias for this stage

from a downstream DC:DC stage which will in general be able to provide a bias winding with very well regulated

voltage. This strategy will enhance the overall efficiency of the bias generation. A lower efficiency alternative will

be to consider a series-connected fixed positive-voltage regulator such as the UA78L15A.

For all normal and abnormal operating conditions it is critically important that VCC remains within the

recommended operating range for both Voltage and Input Current. VCC overvoltage may cause excessive power

dissipation in the internal voltage clamp and undervoltage may cause inadequate drive levels for power

MOSFETs, UVLO events (causing interrupted PFC operation) or inadequate headroom for the various on-chip

linear regulators and references.

Note also that the high RMS and peak currents required for the MOSFET gate drives are provided through the

device 13.5-V linear regulator, which does not have provision for the addition of external decoupling capacitance.

For higher Powers, very high Q_Gpower MOSFETs or high switching frequencies, consider using external driver

transistors, local to the power MOSFETs. These will reduce the device operating temperature and ensure that

the VCC maximum input current rating is not exceeded.

Use decoupling capacitances between VREF and AGND and between VCC and PGND which are as local as

possible to the device. These should have some ceramic capacitance which will provide very low ESR. PGND

and AGND should ideally be star connected at the control device so that there is negligible DC or high frequency

AC voltage difference between PGND and AGND. Use values for decoupling capacitors similar to or a little larger

than those used in the EVM.

Pay close attention to start-up and shutdown VCC bias bootstrap arrangements so that these provide adequate

regulated bias power as early as possible during power application and as late as possible during power

removal. Ensure that these start-up bias bootstrap circuits do not cause unnecessary steady-state power drain.

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11 Layout

11.1 Layout Guidelines

Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,

allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input

and output filter capacitors should be located after the two phase currents are combined together. Similar to

other power management devices, when laying out the printed circuit board (PCB) it is important to use star

grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the

interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in

(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath

magnetic elements. Because of the precise timing requirement, timing-setting resistor R_Tshould be placed as

close as possible to the TSET pin and returned to the analog ground pin with the shortest possible path.

Figure 36 shows a recommended component placement and layout.

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11.2 Layout Example

Dotted line could be or a wire mounted on the top of the board or Top layer traces, assuming device and other traces

are in the bottom layer.

Figure 36. Recommended PCB Layout

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

UCC28064AEVM 300W Interleaved PFC Pre-regulator

UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

E2E is a trademark of Texas Instruments.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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型号：	UCC28065DT
厂家：	TEXAS INSTRUMENTS
描述：	具有高频开关功能的 Natural Interleaving™ 转换模式 PFC 控制器 \| D \| 16 \| -40 to 125 开关控制器功率因数校正光电二极管
文件：	总55页 (文件大小：4340K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC28065DT [TI]

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