UCC2809PTR-1 [TI]
Economy Primary Side Controller; 经济型初级侧控制器
| 型号： | UCC2809PTR-1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Economy Primary Side Controller |
| 文件： | 总11页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
available
Economy Primary Side Controller
FEATURES
DESCRIPTION
• User Programmable Soft Start With
Active Low Shutdown
The UCC3809 family of BCDMOS economy low power integrated circuits
contains all the control and drive circuitry required for off-line and isolated
DC-to-DC fixed frequency current mode switching power supplies with
minimal external parts count. Internally implemented circuits include
undervoltage lockout featuring startup current less than 100µA, a user ac-
cessible voltage reference, logic to ensure latched operation, a PWM com-
parator, and a totem pole output stage to sink or source peak current. The
output stage, suitable for driving N-Channel MOSFETs, is low in the off
state.
• User Programmable Maximum Duty
Cycle
• Accessible 5V Reference
• Undervoltage Lockout
• Operation to 1MHz
• 0.4A Source/0.8A Sink FET Driver
• Low 100µA Startup Current
Oscillator frequency and maximum duty cycle are programmed with two
resistors and a capacitor. The UCC3809 family also features full cycle soft
start.
The family has UVLO thresholds and hysteresis levels for off-line and
DC-to-DC systems as shown in the table to the left.
PART
TURN ON
TURN OFF
The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP
(N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and
MSOP packages make the device ideal for applications where board
space and height are at a premium.
NUMBER THRESHOLD THRESHOLD
UCCX809-1
UCCX809-2
10V
15V
8V
8V
TYPICAL APPLICATION DIAGRAM
R
START
V
IN
FB
1
1V
–
+
1V
REF
NOISE
FILTER
+5V
+
–
5V
REF
8
FEEDBACK
C
6µA
SS
REF
2
–
+
V
SLOPE
COMP
OUT
CURRENT
SENSE
0.5V
VDD
C
SS
7
–
+
15/8V
10/8V
DISABLE
UVLO
17.5V
C
VDD
RT1
RT2
PWM
LATCH
3
4
OUT
GND
R
Q
S
CLK
OSC
6
5
–
+
V
REF
C
T
UDG-99036
SLUS166B - NOVEMBER 1999 - REVISED NOVEMBER 2004
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS*
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V
SOIC-8, DIL-8 (Top View)
D, N and J Packages
I
I
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
OUT (tpw < 1µs and Duty Cycle < 10%). . . . . . . . –0.4A to 0.8A
RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . –0.3V to REF + 0.3V
REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15mA
I
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
* Values beyond which damage may occur.
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
TSSOP-8 (Top View)
PW Package
MSOP-8 (Top View)
P Package
REF
1
8
7
6
5
FB
FB
REF
1
2
3
4
8
7
6
5
2
3
4
SS
VDD
OUT
GND
SS
VDD
RT1
RT1
OUT
GND
RT2
RT2
ORDERING INFORMATION
Temperature Range Available Packages
UCC 809
–
UCC1809-X
UCC2809-X
UCC3809-X
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
J
UVLO OPTION
N, D, P, PW
N, D, P, PW
PACKAGE
TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, CVREF = 0.47 mF, VDD = 12V. TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Supply Section
VDD Clamp
IVDD
IVDD = 10mA
No Load
16
17.5
600
110
110
130
19
V
900
µA
µA
µA
µA
IVDD Starting
IVDD Standby
(Note 1)
UCCx809-1, VDD = Start Threshold - 300mV
UCCx809-2, VDD = Start Threshold - 300mV
125
170
Undervoltage Lockout Section
Start Threshold (UCCx809-1)
UVLO Hysteresis (UCCx809-1)
Start Threshold (UCCx809-2)
UVLO Hysteresis (UCCx809-2)
Voltage Reference Section
Output Voltage
9.4
1.65
14.0
6.2
10.4
15.6
V
V
V
V
IREF = 0mA
4.75
5
2
2
5.25
V
Line Regulation
VDD = 10V to 15V
IREF = 0mA to 5mA
mV
mV
Load Regulation
Comparator Section
IFB
Output Off
–100
0.95
50
nA
V
Comparator Threshold
OUT Propagation Delay (No Load)
0.9
1
VFB = 0.8V to 1.2V at TR = 10ns
2
100
ns
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, CVREF = 0.47 mF, VDD = 12V. TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Soft Start Section
ISS
VDD = 16V, VSS = 0V; –40°C to +85°C
VDD = 16V, VSS = 0V; < –40°C; >+85°C
VDD = 7.5V, ISS = 200mA
–4.9
–4.0
–7.0
–9.1
mA
mA
V
–7.0 –10.0
0.2
VSS Low
Shutdown Threshold
Oscillator Section
Frequency
0.44
90
0.48
0.52
V
RT1 = 10k, RT2 = 4.32k, CT = 820pF
VDD = 10V to 15V
100
0.1
110
kHz
%/V
V
Frequency Change with Voltage
CT Peak Voltage
3.33
1.67
1.67
CT Valley Voltage
CT Peak to Peak Voltage
Output Section
V
1.54
1.80
V
Output VSAT Low
IOUT = 80mA (dc)
IOUT = –40mA (dc), VDD – OUT
IOUT = 20mA (dc)
VFB = 2V
0.8
0.8
1.5
1.5
1.5
V
V
Output VSAT High
Output Low Voltage During UVLO
Minimum Duty Cycle
Maximum Duty Cycle
Rise Time
V
0
%
%
ns
ns
70
35
18
COUT = 1nF
COUT = 1nF
Fall Time
Note 1. Ensured by design. Not 100% production tested.
PIN DESCRIPTIONS
FB: This pin is the summing node for current sense RT2: This pin connects to timing resistor RT2 and
feedback, voltage sense feedback (by optocoupler) and controls the negative ramp time of the internal oscillator
slope compensation. Slope compensation is derived (Tf = 0.74 · (CT + 27pF) · RT2). The negative threshold
from the rising voltage at the timing capacitor and can be of the internal oscillator is sensed through inactive timing
buffered with an external small signal NPN transistor. resistor RT1 which connects to pin RT1 and timing
External high frequency filter capacitance applied from capacitor CT.
this node to GND is discharged by an internal 250W on
SS: This pin serves two functions. The soft start timing
resistance NMOS FET during PWM off time and offers
capacitor connects to SS and is charged by an internal
effective leading edge blanking set by the RC time
6µA current source. Under normal soft start SS is
constant of the feedback resistance from current sense
discharged to at least 0.4V and then ramps positive to 1V
resistor to FB input and the high frequency filter capacitor
during which time the output driver is held low. As SS
capacitance at this node to GND.
charges from 1V to 2V soft start is implemented by an
GND: Reference ground and power ground for all
functions.
increasing output duty cycle. If SS is taken below 0.5V,
the output driver is inhibited and held low. The user
accessible 5V voltage reference also goes low and IVDD
< 100mA.
OUT: This pin is the high current power driver output. A
minimum series gate resistor of 3.9W is recommended to
limit the gate drive current when operating with high bias
voltages.
VDD: The power input connection for this device. This
pin is shunt regulated at 17.5V which is sufficiently below
the voltage rating of the DMOS output driver stage. VDD
should be bypassed with a 1mF ceramic capacitor.
REF: The internal 5V reference output. This reference is
buffered and is available on the REF pin. REF should be
bypassed with a 0.47mF ceramic capacitor.
RT1: This pin connects to timing resistor RT1 and
controls the positive ramp time of the internal oscillator
(Tr = 0.74 · (CT + 27pF) · RT1). The positive threshold of
the internal oscillator is sensed through inactive timing
resistor RT2 which connects to pin RT2 and timing
capacitor CT.
3
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION
UDG-99179
Figure 1. Isolated 50W flyback converter utilizing the UCC3809. The switching frequency is 70kHz, Vin = -32V to
-72V, Vout = +5V, Iout = 0A to 10A
4
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION (cont.)
The Typical Application Diagram shows an isolated reference) sensed through RT1. The R input to the oscil-
flyback converter utilizing the UCC3809. Note that the lator latch, R(OSC), is also level sensitive and resets the
capacitors CREF and CVDD are local decoupling capaci- CLK signal low when CT crosses the 1.67V threshold,
tors for the reference and IC input voltage, respectively. turning off Q2 and turning on Q1, initiating another charg-
Both capacitors should be low ESR and ESL ceramic, ing cycle.
placed as close to the IC pins as possible, and returned
Figure 3 shows the waveforms associated with the oscil-
directly to the ground pin of the chip for best stability.
lator latch and the PWM latch (shown in the Typical Ap-
REF provides the internal bias to many of the IC func-
plication Diagram). A high CLK signal not only initiates a
discharge cycle for CT, it also turns on the internal NMOS
FET on the FB pin causing any external capacitance
tions and CREF should be at least 0.47µF to prevent REF
from drooping.
used for leading edge blanking connected to this pin to
be discharged to ground. By discharging any external
capacitor completely to ground during the external
switch’s off-time, the noise immunity of the converter is
enhanced allowing the user to design in smaller RC com-
ponents for leading edge blanking. A high CLK signal
also sets the level sensitive S input of the PWM latch,
S(PWM), high, resulting in a high output, Q(PWM), as
shown in Figure 3. This Q(PWM) signal will remain high
until a reset signal, R(PWM) is received. A high R(PWM)
signal results from the FB signal crossing the 1V thresh-
old, or during soft start or if the SS pin is disabled.
FB Pin
The basic premise of the UCC3809 is that the voltage
sense feedback signal originates from an optocoupler
that is modulated by an external error amplifier located
on the secondary side. This signal is summed with the
current sense signal and any slope compensation at the
FB pin and compared to a 1V threshold, as shown in the
Typical Application Diagram. Crossing this 1V threshold
resets the PWM latch and modulates the output driver
on-time much like the current sense comparator used in
the UC3842. In the absence of a FB signal, the output
will follow the programmed maximum on-time of the os-
cillator.
Assuming the UVLO threshold is satisfied, the OUT sig-
nal of the IC will be high as long as Q(PWM) is high and
S(PWM), also referred to as CLK, is low. The OUT sig-
nal will be dominated by the FB signal as long as the FB
signal trips the 1V threshold while CLK is low. If the FB
signal does not cross the 1V threshold while CLK is low,
the OUT signal will be dominated by the maximum duty
cycle programmed by the user. Figure 3 illustrates the
various waveforms for a design set up for a maximum
duty cycle of 70%.
When adding slope compensation, it is important to use
a small capacitor to AC couple the oscillator waveform
before summing this signal into the FB pin. By correctly
selecting the emitter resistor of the optocoupler, the volt-
age sense signal can force the FB node to exceed the
1V threshold when the output that is being compared ex-
ceeds a desired level. Doing so drives the UCC3809 to
zero percent duty cycle.
Oscillator
The following equation sets the oscillator frequency:
V
−1
REF
(
)
(
)
FOS C =[0.74 • CT + 27pF • RT1+RT 2 ]
(
)
DMAX = 0.74 • RT1• CT + 27pF • FOS C
Q1
Referring to Figure 2 and the waveforms in Figure 3,
when Q1is on, CT charges via the RDS(on) of Q1 and
RT1. During this charging process, the voltage of CT is
sensed through RT2. The S input of the oscillator latch,
S(OSC), is level sensitive, so crossing the upper thresh-
old (set at 2/3 VREF or 3.33V for a typical 5.0V refer-
ence) sets the Q output (CLK signal) of the oscillator
latch high. A high CLK signal results in turning off Q1 and
turning on Q2. CT now discharges through RT2 and the
RDS(on) of Q2. CT discharges from 3.33V to the lower
threshold (set at 1/3 VREF or 1.67V for a typical 5.0V
3
+
CLK
S
Q
–
3.33V
1.67V
RT1
+
–
4
R
RT2
OS CILLATOR
LATCH
Q2
CT
OSC
UDG-97195
Figure 2. UCC3809 oscillator.
5
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION (cont.)
CT CT
CHARGING DISCHARGING
3.33V
1.67V
CT
S(OSC)
R(OSC)
Q(OSC)=CLK
=S(PWM)
1V
FB
R(PWM)
Q(PWM)
70%
ON
30%
OFF
OUT
FB S IGNAL DOMINANT
MAX. DUTY CYCLE DOMINANT
UDG-99037
Figure 3. Waveforms associated with the oscillator latch and the PWM latch.
The recommended value for CT is 1nF for frequencies in
1000
the 100 kHz or less range and smaller CT for higher fre-
quencies. The minimum recommended values of RT1
and RT2 are 10kΩ and 4.32kΩ, respectively. Using these
values maintains a ratio of at least 20:1 between the
RDS(on) of the internal FETs and the external timing resis-
tors, resulting in minimal change in frequency over tem-
100
perature. Because of the oscillator's susceptibility to
capacitive coupling, examine the oscillator frequency by
looking at the common RT1-RT2-CT node on the circuit
board as opposed to looking at pins 3 and 4 directly. For
good noise immunity, RT1 and RT2 should be placed as
close to pins 3 and 4 of the IC as possible. CT should be
10
returned directly to the ground pin of the IC with minimal
100
1000
CT [pF]
10000
stray inductance and capacitance.
Figure 4. Oscillator frequency vs. CT (RT1 = 10k,
RT2 = 4.32k)
6
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION (cont.)
Synchronization
changed.
Both of the synchronization schemes shown in Figure 5 Option II uses the synchronization pulse to superimpose
can be successfully implemented with the internal oscilla- the sync voltage onto the peak of the CT waveform. This
tor of the UCC3809. Both schemes allow access to the triggers the internal 3.33V comparator, initiating a dis-
timing ramp needed for slope compensation and have charge cycle. The sync pulse is summed with the free
minimal impact on the programmed maximum duty cycle. running oscillator waveform at the CT node, resulting in a
In the absence of a sync pulse, the PWM controller will spike on top of the CT peak voltage.
run independently at the frequency set by RT1, RT2, and
CT. This free running frequency must be approximately
ADDITIONAL INFORMATION
Please refer to the following Unitrode application topics
for additional information.
15 to 20% lower than the sync pulse frequency to insure
the free running oscillator does not cross the comparator
threshold before the desired sync pulse.
[1] Application Note U-165, Design Review: Isolated 50W
Flyback Converter with the UCC3809 Primary Side Con-
troller by Lisa Dinwoodie.
Option I uses the synchronization pulse to pull pin 3 low,
triggering the internal 1.67V comparator to reset the RS
latch and initiate a charging cycle. The valley voltage of
the CT waveform is higher when synchronized using this
configuration, decreasing the ramp charge and discharge
times, thereby increasing the operating frequency; other-
wise the overall shape of the CT voltage waveform is un-
[2] Design Note DN-89, Comparing the UC3842,
UCC3802, and UCC3809 Primary Side PWM Controllers
by Lisa Dinwoodie.
1k
3
+5V
3
4
UCC3809
OS CILLATOR
UCC3809
OS CILLATOR
2N2222A
SYNC
PULSE
RT1
4
RT1
SYNC
PULSE
2N2222A
RT2
RT2
424
CT
CT
24
0.1µF
424
OPTION I
OPTION II
UDG-99006
Figure 5. UCC3809 synchronization options.
7
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
TYPICAL CHARACTERISTICS CURVES
16
14
12
10
8
180
160
UCC2809-2
UCC2809-1
140
120
100
80
6
60
2809-2 UVLO on
2809-1UVLO on
UVLO off
4
40
20
2
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (deg C)
Temperature (deg C)
Figure 6. IDD (standby) vs. temperature.
Figure 7. UVLO vs. temperature.
110
105
100
95
90
-50
-25
0
25
50
75
100
125
temperature (deg C)
Figure 8. Oscillator frequency vs. temperature.
REVISION HISTORY
REV. B 11/04
Added Ivdd Stand-by Current specifications in the Electrical Characteristics table.
Modified Ivdd Starting specifications in the Electrical Characteristics table.
Added Typical Characteristics Curves for Idd(Standby), UVLO thresholds, and Oscillator Frequency.
8
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
UCC2809D-1
UCC2809D-2
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
75
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
SOIC
D
UCC2809DTR-1
UCC2809DTR-2
UCC2809P-1
SOIC
D
2500
2500
80
SOIC
D
MSOP
MSOP
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
DGK
DGK
DGK
DGK
DGK
PW
PW
PW
PW
D
UCC2809P-2
80
UCC2809PTR-1
UCC2809PTR-1G4
UCC2809PTR-2
UCC2809PW-1
UCC2809PW-2
UCC2809PWTR-1
UCC2809PWTR-2
UCC3809D-1
2500
2500
2500
150
150
2000
2000
75
Call TI
Call TI
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-NC-NC-NC
UCC3809D-2
SOIC
D
75
UCC3809DTR-1
UCC3809DTR-2
UCC3809N-1
SOIC
D
2500
2500
50
SOIC
D
PDIP
P
Pb-Free
(RoHS)
UCC3809N-2
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
UCC3809P-1
UCC3809P-2
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP
MSOP
MSOP
TSSOP
TSSOP
TSSOP
DGK
DGK
DGK
PW
8
8
8
8
8
8
80
80
None
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
UCC3809PTR-1
UCC3809PW-1
UCC3809PW-2
UCC3809PWTR-1
2000
150
150
2000
PW
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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Addendum-Page 2
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