UCC2810DWG4 [TI]
温度范围为 -40°C 至 85°C 的双通道同步电流模式 PWM | DW | 16 | -40 to 85;
| 型号： | UCC2810DWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 温度范围为 -40°C 至 85°C 的双通道同步电流模式 PWM | DW | 16 | -40 to 85 开关 控制器 信息通信管理 开关式稳压器 开关式控制器 光电二极管 电源电路 开关式稳压器或控制器 |
| 文件： | 总14页 (文件大小：519K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
ꢈꢀ ꢉꢊ ꢁ ꢋꢉꢌꢌꢍ ꢊ ꢎꢏ ꢌꢁꢋꢐꢑ ꢌꢒ ꢓ ꢍꢈ
ꢁꢀꢐ ꢐꢍꢌꢔ ꢕꢖ ꢑ ꢈꢍ ꢗꢘ ꢖ
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
Single Oscillator Synchronizes Two PWMs
150-µA Startup Supply Current
2-mA Operating Supply Current
Operation to 1 MHz
The UCC3810 is a high-speed BiCMOS controller
integrating two synchronized pulse width
modulators for use in off-line and dc-to-dc power
supplies. The UCC3810 family provides perfect
synchronization between two PWMs by usin g the
same oscillator. The oscillator’s sawtooth
waveform can be used for slope compensation if
required.
Internal Soft-Start
Full-Cycle Fault Restart
Internal Leading-Edge Blanking of the
Current Sense Signal
Using a toggle flip-flop to alternate between
modulators, the UCC3810 ensures that one PWM
does not slave, interfere, or otherwise affect the
other PWM. This toggle flip- flop also ensures that
each PWM is limited to 50% maximum duty cycle,
insuring adequate off-time to reset magnetic
elements. This device contains many of the same
elements of the UC3842 current mode controller
family, combined with the enhancements of the
UCC3802. This minimizes power supply parts
count. Enhancements include leading edge
blanking of the current sense signals, full cycle
fault restart, CMOS output drivers, and outputs
which remain low even when the supply voltage is
removed.
D
1-A Totem Pole Outputs
D
75-ns Typical Response from Current Sense
to Output
D
1.5% Tolerance Voltage Reference
N PACKAGE
(TOP VIEW)
SYNC
CT
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
REF
RT
ENABLE2
FB2
FB1
COMP1
CS1
COMP2
11 CS2
OUT1
GND
10 OUT2
ERROR AMPLIFIER GAIN AND PHASE
9
PWRGND
vs
FREQUENCY
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
CT
RT
FB1
COMP1
CS1
OUT1
GND
VCC
REF
ENABLE2
FB2
COMP2
CS2
OUT2
PWRGND
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Copyright 2004, Texas Instruments Incorporated
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1
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
ORDERING INFORMATION
(1)
PACKAGED DEVICES
T
J
PDIP (N)
SOP (DW)
−40_C to 85_C
0_C to 70_C
UCC2810DW (16)
UCC3810DW (16)
UCC2810N (16)
UCC3810N (16)
(1) All packages are available taped and reeled (indicated by the R suffix on the device type e.g., UCC2810JR)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)(3)
UNIT
V
(2)
Supply voltage , V
CC
11
Supply current, I
CC
20
1
mA
A
Output peak current, OUT1, OUT2, 5% duty cycle
Output energy, OUT1, OUT2, capacitive load
Analog inputs, FB1, FB2, CS1, CS2, SYNC
20
µJ
V
−0.3 to 6.3
150
Operating junction temperature, T
J
_C
_C
_C
Storage temperature range, T
stg
−65 to 150
300
Lead temperature (soldering, 10 sec)
(1) Currents are positive into, negative out of the specified terminal. All voltages are with respect to GND.
(2) In normal operation, V
is powered through a current-limiting resistor. Absolute maximum of 11 V applies when driven from a low impedance
CC
current does not exceed 20 mA.
such that the V
CC
(3) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
BLOCK DIAGRAM
UDG−92062−2
2
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
All parameters are the same for both channels, −40_C ≤ T ≤ 85_C for the UCC2810, 0_C ≤ T ≤ 70_C for the
A
A
(1)
UCC3810, V
= 10 V ; R = 150 kΩ, C = 120 pF; no load; T = T ; (unless otherwise specified)
CC
T T A J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
T = 25_C
J
4.925 5.000 5.075
J
V
CC
Output voltage
V
T = full range,
0 mA ≤ I
REF
≤ 5 mA
4.85
5.00
5
5.10
30
Load regulation
Line regulation
0 mA ≤ I ≤ 5 mA
REF
mV
UVLO stop threshold voltage,
0.5 V ≤ V ≤ V
12
CC SHUNT
(7)
Output noise voltage
10 Hz < f < 10 kHz,
T = 25_C
235
5
µV
mV
mA
J
(7)
Long term stability
T
= 125_C,
1000 hours
A
I
Output short circuit current
−8
−25
O(SC)
OSCILLATOR
R
R
= 30 kΩ
C
C
= 120 pF
= 120 pF
760
190
880
220
2.5%
2.5
1000
250
T
T
T
(2)
Oscillator frequency
f
kHz
OSC
= 150 kΩ
T
(7)
Temperature stability
Peak voltage
Valley voltage
0.05
2.45
1.65
30
V
Peak-to-peak amplitude
SYNC threshold voltage
SYNC input current
2.25
0.80
2.65
2.20
SYNC = 5 V
µA
ERROR AMPLIFIER
V
FB input voltage
COMP = 2.5 V
2.44
60
2.50
2.56
1
V
µA
FB
I
FB input bias current
Open loop voltage gain
FB
73
2
dB
(7)
f
I
I
Unity gain bandwidth
MHz
GAIN
SINK
SRCE
Sink current, COMP
FB = 2.7 V,
FB = 1.8 V,
COMP = 0 V
FB = 1.8 V,
COMP = 1 V
COMP = 4 V
0.3
1.4
−0.5
3.5
−0.8
0%
mA
ms
Source current, COMP
Minimum duty cycle
−0.2
Soft-start rise time, COMP
(1) For UCC3810, adjust V
5
rise from 0.5 V to (REF − 1.5 V)
above the start threshold before setting at 10 V.
4
CC
(2) Oscillator frequency is twice the output frequency. fOSC
+
RT CT
DVCOMP
(3) Current sense gain A is defined by: A +
,
0 V ≤ V ≤ 0.8 V.
CS
DVCS
(4) Parameter measured at trip point of latch with FB = 0 V.
(5) CS blank time is measured as the difference between the minimum non-zero on-time and the CS-to-OUT delay.
(6) Start threshold voltage and V internal zener voltage track each other.
CC
(7) Ensured by design. Not production tested.
3
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
All parameters are the same for both channels,−40_C ≤ T ≤ 85_C for the UCC2810, 0_C ≤ T ≤ 70_C for the
A
A
(1)
UCC3810, V
= 10 V ; R = 150 kΩ, C = 120 pF; no load; T = T ; (unless otherwise specified)
CC
T T A J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE
(3)
Gain
1.20
0.9
1.55
1.0
1.80
1.1
V/V
V
(4)
Maximum input signal
Input bias current, CS
COMP = 5 V
I
200
nA
CS
CS steps from 0 V to 1.2 V,
COMP = 2.5 V
Propagation delay time (CS to OUT)
75
ns
V
(5)
Blank time, CS
55
1.55
0.90
Overcurrent threshold voltage, CS
COMP-to-CS offset voltage
1.35
0.45
1.85
1.35
CS = 0 V
PWM
R
R
= 150 kΩ,
= 30 kΩ,
C
C
= 120 pF
= 120 pF
45%
40%
49%
45%
130
50%
48%
T
T
T
(7)
Maximum duty cycle
T
Minimum on-time
CS = 1.2 V,
COMP = 5 V
ns
OUTPUT
I
I
I
I
I
= 20 mA
0.12
0.48
0.7
0.42
1.10
1.2
OUT
OUT
OUT
OUT
OUT
= 200 mA
= 20 mA,
= −20 mA
= −200 mA
V
Low-level output voltage
OL
V
= 0 V
V
ns
V
CC
0.15
1.2
0.42
2.3
V
OH
High-level output voltage (V
− OUT)
CC
t
t
Rise time, OUT
Fall time, OUT
C
C
= 1 nF
= 1 nF
20
50
R
OUT
OUT
30
60
F
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage
9.6
7.1
11.3
8.3
13.2
9.5
Stop threshold voltage
Start-to-stop hysteresis
1.7
3.0
4.7
ENABLE2 input bias current
ENABLE2 input threshold voltage
ENABLE2 = 0 V
−20
0.80
−35
1.53
−55
2.00
µA
V
(1) For UCC3810, adjust V
CC
above the start threshold before setting at 10 V.
4
(2) Oscillator frequency is twice the output frequency. fOSC
+
RT CT
0 V ≤ V ≤ 0.8 V.
CS
DVCOMP
(3) Current sense gain A, is defined by: A +
,
DVCS
(4) Parameter measured at trip point of latch with FB = 0 V.
(5) CS blank time is measured as the difference between the minimum non-zero on-time and the CS-to-OUT delay.
(6) Start threshold voltage and V internal zener voltage track each other.
CC
(7) Ensured by design. Not production tested.
4
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
All parameters are the same for both channels, −40_C ≤ T ≤ 85_C for the UCC2810, 0_C ≤ T ≤ 70_C for the
A
A
(1)
UCC3810, V
= 10 V ; R = 150 kΩ, C = 120 pF; no load; T = T ; (unless otherwise specified)
CC
T T A J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
Startup current
V
V
V
< Start threshold voltage
0.15
2
0.25
3
CC
CC
CC
Operating supply current, outputs off
Operating supply current, outputs on
= 10 V,
FB = 2.75 V
= 10 V,
FB = 0 V,
mA
3.2
5.1
CS = 0 V,
R = 150 kΩ
T
V
= 10 V,
FB = 0 V,
= 30 kΩ
CC
CS = 0 V,
8.5
12.9
1.2
14.5
14.0
R
T
(6)
VCC internal zener voltage
I
= 10 mA
11.0
0.4
CC
V
VCC internal zener voltage minus start
threshold voltage
(6) Start threshold voltage and V
internal zener voltage track each other.
CC
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5
COMP1
COMP2
O
O
Low impedance output of the error amplifiers.
12
Current sense inputs to the PWM comparators. These inputs have leading edge blanking. For most
applications, no input filtering is required. Leading edge blanking disconnects the CS inputs from all
internal circuits for the first 55 ns of each PWM cycle. When used with very slow diodes or in other
applications where the current sense signal is unusually noisy, a small current-sense R-C filter may
be required.
CS1
6
I
CS2
CT
11
2
I
The timing capacitor of the oscillator. Recommended values of CT are between 100 pF and 1 nF.
Connect the timing capacitor directly across CT and GND.
O
A logic input which disables PWM 2 when low. This input has no effect on PWM 1. This input is inter-
nally pulled high. In most applications it can be left floating. In unusually noisy applications, the input
should be bypassed with a 1-nF ceramic capacitor. This input has TTL compatible thresholds.
ENABLE2
14
I
FB1
FB2
4
I
I
The high impedance inverting inputs of the error amplifiers.
13
To separate noise from the critical control circuits, this part has two different ground connections:
GND and PWRGND. GND and PWRGND must be electrically connected together. However, use
care to avoid coupling noise into GND.
GND
8
−
The high-current push-pull outputs of the PWM are intended to drive power MOSFET gates through
a small resistor. This resistor acts as both a current limiting resistor and as a damping impedance to
minimize ringing and overshoot.
OUT1
OUT2
7
O
O
10
To separate noise from the critical control circuits, this part has two different ground connections:
GND and PWRGND. GND and PWRGND must be electrically connected together.
PWRGND
REF
9
−
The output of the 5-V reference. Bypass REF to GND with a ceramic capacitor ≥ 0.01-µF for best
performance.
15
O
The oscillator charging current is set by the value of the resistor connected from RT to GND. This pin
is regulated to 1 V, but the actual charging current is 10 V/R . Recommended values of R are be-
tween 10 kΩ and 470 kΩ. For a given frequency, higher timing resistors give higher maximum duty
cycle and slightly lower overall power consumption.
T
T
RT
3
O
This logic input can be used to synchronize the oscillator to a free running oscillator in another part.
This pin is edge triggered with TTL thresholds, and requires at least a 10-ns-wide pulse. If unused,
this pin can be grounded, open circuited, or connected to REF.
SYNC
VCC
1
I
I
The power input to the device. This pin supplies current to all functions including the high current
output stages and the precision reference. Therefore, it is critical that VCC be directly bypassed to
PWRGND with an 0.1-µF ceramic capacitor.
16
5
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
timing resistor
Supply current decreases with increased R by the relationship:
T
11 V
DI
+
CC
R
T
(1)
For more information, see the detailed oscillator block diagram.
leading edge blanking and current sense
Figure 1 shows how an external power stage is connected to the UCC3810. The gate of an external power
N-channel MOSFET is connected to OUT through a small current-limiting resistor. For most applications, a 10-Ω
resistor is adequate to limit peak current and also practical at damping resonances between the gate driver and
the MOSFET input reactance. Long gate lead length increases gate capacitance and mandates a higher series
gate resistor to damp the R-L-C tank formed by the lead, the MOSFET input reactance, and the device’s driver
output resistance.
The UCC3810 features internal leading edge blanking of the current-sense signal on both current sense inputs.
The blank time starts when OUT rises and continues for 55 ns. During that 55 ns period, the signal on CS is
ignored. For most PWM applications, this means that the CS input can be connected to the current-sense
resistor as shown in Figure 1. However, high speed grounding practices and short lead lengths are still required
for good performance.
Figure 1. Detailed Block Diagram
oscillator
The UCC3810 oscillator generates a sawtooth wave at CT. The sawtooth rise time is set by the resistor from
RT to GND. Since R is biased at 1 V, the current through R is 1 V/R . The actual charging current is 10 times
T
T
T
higher. The fall time is set by an internal transistor on-resistance of approximately 100 Ω. During the fall time,
all outputs are off and the maximum duty cycle is reduced to below 50%. Larger timing capacitors increase the
discharge time and reduce frequency. However, the percentage maximum duty cycle is only a function of the
timing resistor R , and the internal 100-Ω discharge resistance.
T
6
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
APPLICATION INFORMATION
error amplifier output stage
The UCC3810 error amplifiers are operational amplifiers with low-output resistance and high-input resistance.
The output stage of one error amplifier is shown in Figure 3. This output stage allows the error amplifier output
to swing close to GND and as high as one diode drop below 5 V with little loss in amplifier performance.
Figure 2. Oscillator
Figure 3. Error Amplifier Output Stage
7
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
ERROR AMPLIFIER GAIN AND PHASE
vs
TIMING RESISTANCE
FREQUENCY
Figure 4
Figure 5
MAXIMUM DUTY CYCLE
vs
TIMING RESISTANCE
OSCILLATOR FREQUENCY
vs
TEMPERATURE
Figure 6
Figure 7
8
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
MAXIMUM DUTY CYCLE
vs
OSCILLATOR FREQUENCY
FREQUENCY
Figure 8
Figure 9
9
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
UDG−94022
Figure 10. Typical Application
10
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°−ā8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
28
0.710
DIM
0.410
0.462
0.510
0.610
A MAX
A MIN
(10,41) (11,73) (12,95) (15,49) (18,03)
0.400
0.453
0.500
0.600
0.700
(10,16) (11,51) (12,70) (15,24) (17,78)
4040000/E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
11
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SLUS162C − FEBRUARY 1999 − REVISED NOVEMBER 2004
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.035 (0,89) MAX
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
M
14/18 PIN ONLY
4040049/D 02/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
12
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
8-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
Drawing
UCC2810DW
UCC2810DWTR
UCC2810N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
16
16
16
16
16
16
40
2000
25
None
None
None
None
None
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-NA-NA-NA
DW
N
UCC3810DW
DW
40
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
UCC3810DWTR
UCC3810DWTRG4
DW
2000
DW
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3810N
ACTIVE
PDIP
N
16
25
None
CU NIPDAU Level-NA-NA-NA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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Copyright 2005, Texas Instruments Incorporated
相关型号：
UCC2810N
1A DUAL SWITCHING CONTROLLER, 1100kHz SWITCHING FREQ-MAX, PDIP16, PLASTIC, DIP-16
ROCHESTER
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