UCC28250PWR [TI]
Advanced PWM Controller With Pre-Bias Operation; 先进的PWM控制器，带有预偏置操作
| 型号： | UCC28250PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Advanced PWM Controller With Pre-Bias Operation |
| 文件： | 总50页 (文件大小：760K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Advanced PWM Controller With Pre-Bias Operation
Check for Samples: UCC28250
1
FEATURES
DESCRIPTION
•
Pre-biased Startup
The UCC28250 PWM controller is designed for high
power density applications that may have stringent
pre-biased startup requirements. The UCC28250’s
integrated synchronous rectifier control outputs target
high efficiency and high performance topologies such
as half-bridge, full-bridge, interleaved forward, and
push-pull. The UCC27200 half bridge drivers and
UCC2732X MOSFET drivers used in conjunction with
the UCC28250 provide a complete power converter
solution.
•
Synchronous Rectifier Control Outputs with
Programmable Delays (Including Zero Delay
Support)
•
Voltage Mode Control with Input Voltage
Feed-Forward or Current Mode Control
•
•
•
•
Primary or Secondary-Side Control
3.3-V, 1.5% Accurate Reference Output
1-MHz Capable Switching Frequency
Externally
programmable
soft-start,
used
in
1% Accurate Cycle-by-Cycle Over Current
Protection with Matched Duty Cycle Outputs
conjunction with an internal pre-biased startup circuit,
allows the controller to gradually reach a steady-state
operating point under all output conditions. The
UCC28250 can be configured for primary or
secondary-side control and either voltage or current
mode control can be implemented.
•
•
Programmable Soft-Start and Hiccup Restart
Timer
Thermally Enhanced 4-mm x 4-mm QFN-20
Package and 20-pin TSSOP Package
The oscillator operates at frequencies up to 2 MHz,
and can be synchronized to an external clock. Input
voltage feedforward, cycle-by-cycle current limit, and
a programmable hiccup timer allow the system to
stay within a safe operation range. Input voltage,
output voltage and temperature protection can be
implemented. Dead time between primary-side switch
and secondary-side synchronous rectifiers can be
independently programmed.
APPLICATIONS
•
Half-Bridge, Full-Bridge, Interleaved Forward,
and Push-Pull Isolated Converters
•
•
•
•
Telecom and Data-com Power
Wireless Base Station Power
Server Power
Industrial Power Systems
Simplified Application Diagram
VIN (36 V ~ 75 V)
VIN (36 V ~ 75 V)
UCC27200
UCC28250
VOUT
OVP
OUTA
OUTB
SRA
HI
HI
RAMP
RT
LO
LO
Isolation
UCC2732x
SS
SRB
COMP
Feedback and Isolation
GND
Not Shown: PS, SP, HICC, VDD, EA+, EA-, VREF, EN, ILIM, AND VSENSE
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
ORDERING INFORMATION
TEMPERATURE RANGE
TA = TJ
PACKAGE
TAPE AND REEL QTY
PART NUMBER
250
3000
250
UCC28250RGPT
UCC28250RGPR
UCC28250PWT
UCC28250PWR
Plastic 20-pin QFN (RGP)
Plastic 20-pin TSSOP (PW)
-40°C to 125°C
3000
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range(1)(2) (unless otherwise noted)
PARAMETER
VALUE
UNIT
VDD(3)
Input supply voltage
OUTA, OUTB, SRA and SRB
COMP
-0.3 to 20.0
-0.3 to VDD + 0.3
-0.3 to VREF + 0.3
-0.3 to 5.5
-0.3 to 3.6
-0.3 to 4.3
-0.3 to 3.6
3 k
Input voltages on SS and EN
Input voltages on RT, PS, SP, ILIM, OVP, HICC, VSENSE, EA+ and EA-
Input voltage on RAMP/CS
V
Output voltage on VREF
HBM
CDM
ESD rating
2 k
Lead temperature (soldering 10 sec) PW package
300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See
Packaging Section of the datasheet for thermal limitations and considerations of packages.
THERMAL INFORMATION
UCC28250
RGP
UCC28250
PW(1)
THERMAL METRIC
UNITS
20 PINS
20 PINS
qJA
126 with hot spot,
104 without hot spot
60.3 with hot spot,
39.3 without hot spot
Junction-to-ambient thermal resistance(2)
Junction-to-case(top) thermal resistance
(3)
qJC(top)
qJB
31.5
55.8
°C/W
(4)
Junction-to-board thermal resistance
(5)
qJC(bottom) Junction-to-case(bottom) thermal resistance
0.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
2
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
Supply voltage range, VDD
4.7
1
12
17
V
Supply bypass capacitor, CVDD
VREF bypass capacitor
µF
V
0.5
0
2
3.0
Error amplifier input common mode range (REF/EA+, FB/EA-)
VSENSE input voltage range
RT resistor range
0
3.3
12.5
5
200
250
2.7
kΩ
PS, SP resistor range
RAMP/CS voltage range
0
V
Operating junction temperature range
-40
125
°C
ELECTRICAL CHARACTERISTICS(1)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = -40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted).
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Supply Currents
IDD(off)
IDD
Startup current
VDD = 3.6 V
150
275
µA
mA
µA
Operating supply current
Standby current
100-pF capacitor on OUTA, OUTB, SRA and SRB
EN = 0 V
2.0
2.7
3.4
IDD(dis)
250
425
600
Under Voltage Lockout
VUVLOR Start threshold
4.0
3.8
4.3
4.1
4.6
4.4
Minimum operating voltage
after start
VUVLOF
V
Hysteresis
0.15
0.20
0.25
Soft Start
ISS
Soft-start charge current
Clamp voltage
VSS = 0 V
25
27
29
µA
V
VSS(max)
Enable(2)
3.3
3.6
4.0
Trigger threshold
2.25
V
Minimum pulse width for
pulse enable
3
µs
Error Amplifier
High-level COMP voltage
Low-level COMP voltage
Input offset
2.8
3
V
0.3
0.4
12
-12
70
mV
dB
Open loop gain
100
6.5
4.5
ICOMP(snk)
ICOMP(src)
COMP sink current
COMP source current
3.0
2.0
9.0
8.0
mA
(1) Typical values for TA = 25°C.
(2) Refer to EN pin description.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS(1) (continued)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = -40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted).
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Oscillator
Nominal switching frequency
FSW(nom)
at OUTA or OUTB set by RT RT/SYNC = 75 kΩ, RSP = 20 kΩ
185
200
215
resistor
kHz
Minimum switching frequency
FSW(min_sync)
at OUTA or OUTB set by
external sync frequency
fRT/SYNC = 100 kHz
fRT/SYNC = 2.5 MHz
85
Maximum switching
frequency at OUTA or OUTB
set by external sync
frequency
FSW(max_sync)
1.15
MHz
V
External synchronization
signal high
1
External synchronization
signal low
0.2
Voltage Reference
VVREF Output voltage
Short circuit current
VDD = from 7 V to 17 V, IVREF = 2 mA
0 < IREF < 10 mA
3.22
3.22
12
3.30
3.30
25
3.38
3.38
40
V
VREF = 3 V, TJ = 25°C
mA
Current Sense, Cycle-by-Cycle Current Limit With Hiccup
VILIM
ILIM cycle-by-cycle threshold
0.495
15
0.502
25
0.509
36
V
Propagation delay from ILIM
to OUTA and OUTB outputs
TPDILIM
TBLANK
Exclude leading edge blanking
ns
ns
leading edge blanking
40
60
90
Current limit shutdown delay
timing program current
Measured at HICC pin
Measured at HICC pin
55
75
95
µA
Hiccup timing program
current
2
2.7
3.5
Current limit shutdown delay
timer threshold at HICC
VHICC_SD
0.55
0.60
0.65
VHICC_PU
HICC pull-up threshold
Hiccup restart threshold
2.3
2.4
2.5
V
VHICC_RST
0.25
0.30
0.35
10-V ramp charging voltage source with 40-kΩ
current limiting resistor
VCS(max)
RAMP/CS clamp voltage
3.5
4.0
4.5
4
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
ELECTRICAL CHARACTERISTICS(1) (continued)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = -40°C to 125°C, RT = 75 kΩ connected to ground to set
FSW = 200 kHz (unless otherwise noted).
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
OVP/OTP Comparator
VOVP
IOVP
Primary Outputs
Rise/fall time
Internal reference
0.66
0.70
0.74
V
Internal current
8.5
11.0
13.5
µA
CLOAD = 100 pF
IOUT = 20 mA
IOUT = 20 mA
8
20
12
ns
RSRC
RSNK
Output source resistance
Output sink resistance
12
4
35
30
Ω
Synchronous Rectifier Outputs
Rise/fall time
CLOAD = 100 pF
8
20
25
12
0
ns
IOUT = 20 mA, VDD = 12 V
IOUT = 20 mA, VDD = 5 V
IOUT = 20 mA, VDD = 12 V
PS = VREF
12
15
35
45
30
7.5
50
43
7.5
50
43
RSRC
RSNK
Output source resistance
Ω
Output sink resistance
4
-5.0
27
Primary off to secondary on
dead time
TDPS
TDSP
PS = 27 kΩ
40
40
0
ns
ns
PS = 27 kΩ, 25°C
SP = VREF
37
-5.0
30
Secondary off to primary on
dead time
SP = 20 kΩ
40
40
SP = 20 kΩ, 25°C
37
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
9
8
7
6
Over
temperature
OTP
4.1V/4.3V
3
+
COMP
UVLO
5
VDD
Vref OK
EN_INT
OCP
2
1
FB/EA-
LDO
Switching Logic
OP
+
+
REF/EA+
Vref ready
20
18
VREF
EN
13
16
SS
+
350mV
RAMP/CS
Enable detection
Level&pulse
Enable
+
BLANK
Cycle by cycle
current limit
& duty cycle match
17
10
+
ILIM
OCP delay
timer
0.5V
+
+
550mV
SR_RAMP
generator
gm
HICC
14
4
VSENSE
GND
11uA
Hiccup
timer
19
+
OVP/OTP
OVP
0.7V
15
12
11
RT
SP
PS
CLK
Oscillator
Deadtime
70ns
leading edge blanking
BLANK
NOTE
Pin numbers are used for RGP package. PW package has different pin numbers.
6
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Typical Application Diagram
Figure 1. Primary-Side Half-Bridge Controller with Synchronous Rectification
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
Figure 2. Secondary-Side Half-Bridge Controller with Synchronous Rectification
8
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
DEVICE INFORMATION
Pinout Drawings
TSSOP-20
TOP VIEW
QFN-20
TOP VIEW
RT VSENSE SS
15 14 13
SP
12
PS
11
VSENSE
RT
1
2
3
4
5
6
7
8
9
20 SS
RAMP/CS 16
10 HICC
19 SP
RAMP/CS
ILIM
18 PS
ILIM 17
9
8
7
6
OUTA
OUTB
SRA
17 HICC
16 OUTA
15 OUTB
14 SRA
13 SRB
12 VDD
11 GND
EN 18
EN
OVP/OTP 19
VREF 20
OVP/OTP
VREF
SRB
REF/EA+
FB/EA-
1
2
3
4
5
REF/EA+ FB/EA- COMP GND VDD
COMP 10
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
TERMINAL FUNCTIONS
QFN-20
PW-20
NAME
VDD
VREF
EN
I/O
FUNCTION
5
12
7
I
O
I
Bias supply input.
20
18
15
12
11
3.3-V reference output.
Device enable and disable.
5
2
RT
I
Oscillator frequency set or synchronous clock input.
Synchronous rectifier off to primary on dead-time set .
Primary off to synchronous rectifier on dead-time set .
19
18
SP
I
PS
I
PWM ramp input (for voltage mode control) or current sense input (for current
mode control).
16
3
RAMP/CS
I
1
2
8
REF/EA+
FB/EA-
COMP
VSENSE
SS
I
I
Error amplifier non-inverting input.
9
Error amplifier inverting input.
3
10
1
I/O
I
Error amplifier output.
14
13
17
10
19
9
Output voltage sensing for pre-bias control.
Soft-start programming.
20
4
I/O
I
ILIM
Current sense for cycle-by-cycle over-current protection.
Cycle-by-cycle current limit time delay and Hiccup time setting.
Over voltage and over temperature protection pin.
0.2-A sink/source primary switching output.
0.2-A sink/source primary switching output.
0.2-A sink/source synchronous rectifier output.
0.2-A sink/source synchronous rectifier output.
Ground.
17
6
HICC
I
OVP/OTP
OUTA
OUTB
SRA
I
16
15
14
13
11
O
O
O
O
I
8
7
6
SRB
4
GND
10
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
DETAILED PIN DESCRIPTIONS
VDD (5/12)
The UCC28250 can be powered up by a wide supply range from 4.3 V (UVLO rising typical) to 20 V (absolute
maximum), making it suitable for primary-side control or secondary-side control. When the voltage at the VDD
pin is lower than 4.1 V (typical), the controller is in stand-by mode and consumes 150 µA (typical) at 3.6 V VDD.
In stand-by mode, VREF continues to be regulated to 3.3 V or follows VDD if VDD is lower than 3.3 V. Please
refer to the VREF description for more detailed information. A minimum 1-µF bypass capacitor is required from
VDD to ground. Keep the bypass capacitor as close to the device as possible.
VREF (Reference Generator) (20/7)
The VREF pin is regulated at 3.3 V. An external ceramic capacitor must be placed as close as possible to the
VREF and GND pins for noise filtering and to provide compensation to the regulator. The capacitance range
must be limited between 0.5 µF to 2 µF for stability. This reference is used to power the controller’s internal
circuits, and can also be used to bias an opto-coupler transistor, an external house-keeping microcontroller, or
other peripheral circuits. This reference can also be used to generate the reference for an external error
amplifier. This regulator output is internally current limited to 25 mA (typical).
EN (Enable Pin) (18/5)
The following conditions must be met before the controller allows start up:
1. VDD voltage is above the rising UVLO threshold 4.3 V (typical);
2. The 3.3-V reference voltage output at the VREF pin is available and above 2.4 V (typical);
3. Junction temperature is below the thermal shutdown threshold 130°C (minimum);
4. The voltage at OVP is below 0.7 V (typical).
If all these conditions are met, the signal driving the EN pin is able to initiate the soft start process. Once the
device is enabled, the 27-µA internal charging current at the SS pin is turned on and begins to charge the
soft-start capacitor. The EN pin can accept both level-enable and pulse-enable signals.
For level-enable, the voltage level on the EN pin needs to be continuously higher than 2.25 V to allow continuous
operation. Once the EN pin falls below 2.25 V, the device is disabled (see Figure 3).
UVLO
EN
0.3V
SS
CLK
Figure 3. Level Enable at EN pin
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
A pulse signal may also be applied to the EN pin. Pulse-enable operation is shown on Figure 4. If the EN falling
edge happens before the SS voltage reaches 0.3 V, the enable signal at EN pin is considered as a pulse. In this
case, the next rising edge at EN pin disables the controller. If the falling edge of the first pulse at EN pin happens
after SS rises to 0.3 V, the UCC28250 interprets the pulse enable as a level enable, and an external solution as
shown on Figure 5 (a) can be used to reduce the pulse width. In this circuit, R2 is used to limit the current
(especially the negative current) through the internal ESD cell. Figure 5 (b) illustrates the waveforms based on
this solution. To prevent false trigger by noises, the pulse at the EN pin must be at least 2.25 V (minimum) high
and 3 µs wide to be considered valid.
Choose the R1, R2, and C values based on the following equations:
Choose R2 based on the current limit requirement from the device.
R2 > 10kW
(1)
Choose R1 arbitrarily but much smaller than R2 and choose C1 according to the time constant requirement to
generate longer than 3-µs pulse.
6ms
C1 =
R1
(2)
If enable function is not used, pull EN pin to VREF.
UVLO
EN
0.3V
SS
CLK
Figure 4. Pulse Enable at EN Pin
(a)
(b)
UCC28250
C1
R2
Enable
Signal
Enable
Signal
EN
R1
EN
Figure 5. An External Solution to Generate Enable Pulses for Pulse Enable
12
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
RT (Oscillator Frequency Set and Synchronization) (15/2)
The UCC28250 oscillator frequency is set by an external resistor connected between the RT pin and ground.
Switching frequency selection is a trade-off between efficiency and component size. Based on the selected
switching frequency, the programming resistor value can be calculated as:
1
- T
d SP
(
)
2´ fSW
RT =
33.2pF
(3)
In this equation, fSW is the switching frequency and TD(sp) is the dead time between synchronous rectifier turn-off
to primary switch turn-on. TD(sp) is set by an external resistor between the SP pin and ground (refer to the SP pin
description).
Each output (OUTA, OUTB, SRA, SRB) switches at half the oscillator frequency (fSW = ½ x fOSC). Figure 6 shows
the relationship between RT and fOSC at certain TD(sp) and can be used to program oscillator frequency
accordingly.
OSCILLATOR FREQUENCY
vs
RT RESISTOR
2000
T
= 40 ns
D(ps)
1800
1600
1400
1200
1000
800
600
400
T
= 100 ns
D(ps)
200
0
0
20 40 60 80 100 120 140 160 180 200
RT Resistor - kW
Figure 6. Oscillator Frequency FOSC vs External Resistance of RT at TD(ps) = 40 ns and 100 ns
The UCC28250 can be synchronized to an external clock by applying an external clock source to the RT pin.
Synchronization helps with parallel operation and/or preventing beat frequency noise. The UCC28250
synchronizes its internal oscillator to an external frequency source ranging from 170 kHz to 2.3 MHz, which is
equivalent to an 85-kHz to 1.15-MHz switching frequency. The internal oscillator frequency is clamped to 170
kHz during synchronization if the external source frequency drops below 170 kHz.
The UCC28250 aligns the turn-on of primary outputs OUTA and OUTB to the falling edge of the synchronizing
signal, as shown in Figure 7. If the frequency source is from the gate outputs of another half bridge controller,
interleaving can be achieved. The interleaving angle is determined by the frequency source’s duty cycle. When a
50% duty cycle is applied, optimal interleaving is achieved, and EMI filters can be minimized.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
13
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
Frequency
Source
OUTA
OUTB
Figure 7. Timing Diagram for Synchronization
CLK
OUTA
SRA
Td(SP)
Td(PS)
OUTB
SRB
Td(SP)
Td(PS)
Figure 8. UCC28250 Outputs Timing Waveforms
14
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
SP (Synchronous Rectifier Turn-Off to Primary Output Turn-On Dead Time Programming) (13/19)
The dead time TD(sp) between synchronous rectifier turn-off to primary output turn-on is programmed by an
external resistor, RSP, connected between the SP pin and ground. The value of RSP can be determined by
Figure 9. Zero dead time can be achieved by tying the SP pin to VREF. The falling edge of synchronous rectifier
SRA/SRB is aligned with the raising edge of the primary output OUTA/OUTB.
NOTE
The minimum value for RPS/RSP is 5 kΩ and the maximum value is 250 kΩ.
SP DEAD TIME
vs
SP RESISTOR
400
350
300
250
200
150
100
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
- SP Resistor - kW
R
SP
Figure 9. Dead Time TD(sp) vs. External Resistor RSP at SP Pin
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
PS (Primary Output Turn-Off to Synchronous Rectifier Turn-On Dead Time Programming) (11/18)
The dead time TD(ps) between primary output turn-off to synchronous rectifier turn-on is set by external resistor,
RPS, connected between PS pin and ground. The value of is RPS is defined by Figure 10. Zero dead time can be
achieved by tying the SP pin to VREF.
NOTE
The minimum value for RPS/RSP is 5 kΩ and the maximum value is 250 kΩ.
PS DEAD TIME
vs
PS RESISTOR
400
350
300
250
200
150
100
50
0
0
20 40 60 80 100 120 140 160 180 200 220 240
- PS Resistor - kW
R
PS
Figure 10. Dead Time TD(ps) vs. External Resistor RPS at PS Pin
16
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3)
The UCC28250 can be controlled using either voltage mode or current mode. RAMP/CS is a multi-function pin
used either to generate the ramp signal for voltage mode control or to sense current for current mode control.The
following sections describe the RAMP/CS functionality for voltage mode and current mode control.
RAMP: Voltage Mode Control with Feed-Forward Operation
For voltage mode control, a resistor RCS and a capacitor CCS must be connected to the RAMP/CS pin as shown
in Figure 11. The internal pull-down switch has approximately 40-Ω on-resistance. The RAMP/CS pin is clamped
internally to 4 V for internal device protection. The CCS value must be small enough to discharge the RAMP/CS
pin from its peak voltage to ground within the pulse width of the BLANK signal (TD(sp) + 70 ns). The following
formula derives a CCS value.
T
d(SP) + 70ns
æ
ç
è
ö
÷
ø
4V / 2
CCS
<
´
40W
4V
(4)
A CCS value less than 650 pF works for most applications. In order to minimize the impacts of parasitic
capacitance caused by the PCB layout and routing, a minimum of 100 pF is recommended for CCS. Once CCS is
determined, RCS can be calculated according to the desired ramp peak amplitude.
1
RCS
=
æ
ç
è
ö
÷
ø
VCHARGE
2´ln
´CCS ´ fSW
VCHARGE - VPK
(5)
In this equation, the VCHARGE is the voltage used to generate the ramp, VPK is the desired ramp amplitude and
the fSW is the switching frequency.
Choose the ramp amplitude to accommodate the voltage range of the COMP pin and the maximum duty cycle
required by the power stage. Use the following equation to select VPK, in the equation, DMAX is the maximum duty
cycle for primary outputs.
1.4V
VPK
=
DMAX
(6)
UCC28250
VREF
UCC28250
VIN 36 V to 75 V
RCS
RCS
RAMP/CS
GND
RAMP/CS
CCS
CCS
BLANK
BLANK
GND
Figure 11. Fixed Ramp Generation/Ramp Generation With Input Voltage Feedforward
Voltage feed-forward can be achieved by driving RCS from line input VIN. The peak of RAMP/CS is proportional
to VIN and output has have much faster line transient response. When the UCC28250 is used for the
primary-side control, RAMP parameters are critical for the optimal pre-biased start up performance. Refer to the
‘Voltage Mode Control and Input Voltage Feed-Forward’ section of the Functional Description section for a
detailed design procedure of choosing RCS
.
If the line input cannot be easily accessed due to limited board area or other limitation, a RAMP signal with fixed
peak voltage can be implemented by simply driving RCS from 3.3 V VREF (Figure 11).
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
CS: Current Mode Control
For current mode control, the RAMP/CS pin is driven by a signal representative of the transformer primary-side
current. The current signal has to have compatible input range of the COMP pin. As shown in Figure 12, the
COMP pin voltage is used as the reference for peak current. The primary-side signals OUTA and OUTB are
turned on by the internal clock signal and turned off when sensed peak current reaches the COMP pin voltage.
Choose the current sense transformer turns ratio (1:n) and the burden resistor value (RB) based on the peak
current at maximum load IMAX. Refer to the Functional Description section for more details on the current mode
control.
3V
RB =
IMAX /n
(7)
COMP
CS
OUTA
OUTB
Figure 12. Peak Current Mode Control and PWM Generation
REF/EA+ (1/8)
REF/EA+ is the non-inverting input of the UCC28250’s internal error amplifier.
When the UCC28250 is configured for secondary-side control, the internal error amplifier is used as the control
loop error amplifier. Connect REF/EA+ directly to the VREF pin to provide the reference voltage for the feedback
loop.
When the UCC28250 is configured for primary-side control, the error amplifier is connected as a voltage follower.
Connect REF/EA+ to the opto-coupler output.
The voltage range on REF/EA+ pin is 0 V to 3.7 V.
18
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
FB/EA- (2/9)
FB/EA- is the inverting input of the UCC28250’s internal error amplifier.
When the UCC28250 is configured for secondary-side control, connect the output voltage sensing divider to this
pin. The voltage divider can be selected according to the voltage on REF/EA+ pin. Referring to Figure 13, pick
the lower resistor RO1 value arbitrarily, and choose the upper resistor RO2 value as:
æ
ç
è
ö
VO
RO2
=
-1 ´R
÷
O1
VREF /EA+
ø
(8)
Because the control loop gain is affected by voltage divider resistor values, choose an appropriate RO1 value so
that the voltage loop DC gain is larger than 40 dB to prevent interference between the primary-side control loop
and the SR control loop during start up.
When the UCC28250 is sitting on the primary side, the error amplifier is connected as a voltage follower.
Connect FB/EA- directly with COMP pin.
The maximum voltage allowed on FB/EA- pin is 3.7 V.
COMP (3/10)
The COMP pin is the internal error amplifier’s output. The voltage range of COMP pin is 0 V to 3 V. Both the
primary-side switches’ duty cycle and secondary-side SRs’ duty cycle is controlled by the COMP pin voltage. At
steady state, a higher COMP pin voltage results in a larger duty cycle for the primary-side switches and a smaller
duty cycle on the SRs.
When the UCC28250 controller is set up for secondary-side control, connect the compensation network from the
FB/EA- pin to the COMP pin.
For primary-side control, the error amplifier is connected as a voltage follower. Directly connect the COMP pin to
the FB/EA- pin.
VSENSE (14/1)
The VSENSE pin is used to directly sense the output voltage and to feed it into a transconductance error
amplifier. The measured voltage allows the UCC28250 to achieve optimal pre-biased start up performance.
When configured as a secondary-side controller, the output voltage is sensed and fed into the FB/EA- pin. The
UCC28250 uses a conventional error amplifier approach to allow type III compensation. Therefore, the FB/EA-
pin voltage always follows the REF/EA+ voltage. The FB/EA- pin does not reflect the true output voltage and
therefore this dedicated VSENSE pin is required. The voltage divider connected to VSENSE is discussed in the
Pre-Biased Start-Up Section.
When UCC28250 is set up as primary-side control, connect VSENSE pin to VREF.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
SS (Soft Start Programming Pin) (13/20)
The soft-start circuit gradually increases the converter’s output voltage until steady state operation is reached.
This reduces start-up stresses and current surge.
When the UCC28250 reaches its valid operating threshold, the SS pin capacitor is charged with a 27-µA current
source. The UCC28250’s internal error amplifier non-inverting terminal follows the SS pin voltage on REF/EA+
pin voltage depending on which one is lower. Hence, during soft start, the SS pin voltage is lower than REF/EA+.
The internal error amplifier then uses the SS pin as its reference voltage, until the SS pin voltage rises above the
REF/EA+ level. Once the SS pin voltage is above REF/EA+ voltage, soft-start time is considered finished.
The soft-start implementation scheme and timing is different, depending on the location of the UCC28250 with
respect to the isolation barrier.
For secondary-side control, the internal error amplifier is used to achieve the voltage regulation. The REF/EA+ is
connected to an external reference voltage, FB/EA- is connected to the voltage sensing divider, and the error
amplifier’s output pin (COMP) is connected through a compensation filter back to the FB/EA- pin (Figure 13). In
this case, the primary output’s start-up is a closed loop soft start (soft-start input reference of error amplifier). The
output soft-start time is determined by the external capacitor connected at SS pin based on the internal 27-µA
charging current and the voltage set at REF/EA+ pin.
Based on the soft-start time TSS, choose soft start capacitor CSS value as:
27mA ´ TSS
CSS
=
VREF /EA+
(9)
VOUT
UCC28250
VSENSE
C
P1
R
O2
VREF
R
Z3
R
C
Z2
S2
R
Z2
COMP
C
Z3
FB/EA-
REF/EA+
SS
+
+
R
R
O1
S1
C
SS
Figure 13. Error Amplifier EAMP Connections for secondary-side Control
20
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
For primary-side control, the internal error amplifier is connected as a buffer stage. In other words, the COMP pin
is shorted to the FB/EA- pin, and the output of an external error amplifier is connected to the REF/EA+ pin
through an optical coupler (Figure 14). In this case, the output start-up is an open loop soft start because the
COMP follows the soft-start voltage instead of the voltage loop output. The soft-start time is still determined by
external capacitor CSS and the 27-µA internal charge current. The voltage depends on the value of final COMP
voltage which corresponds to the regulated primary output duty cycle. According to the desired soft start time and
COMP pin voltage level at steady state, the SS pin capacitor can be calculated as:
27mA ´ TSS
CSS
=
VCOMP_ final
(10)
After soft start, the voltage at SS pin is eventually clamped at around 4 V. Under fault conditions (UVLO, internal
thermal shut down, OVP/OTP, hiccup mode), or when externally disabled, SS pin is pulled down to ground
quickly by an internal switch with 2 kΩ on resistance to prepare for re-start. Pulling SS pin to ground externally
shuts down the controller as well.
VOUT
UCC28250
R
C
VSENSE
O2
P1
R
Z3
C
VREF
Z2
R
Z2
COMP
C
Z3
FB/EA-
REF/EA+
SS
+
R
+
+
O1
External
Reference
C
SS
Figure 14. Error Amplifier EAMP Connections for primary-side Control
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
21
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
ILIM (Current Limit for Cycle-By-Cycle Over-Current Protection) (17/4)
Cycle-by-cycle current limit is accomplished using the ILIM pin for current mode control or for voltage mode
control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin
exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current
condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the
current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch at the
rising edge of every clock cycle. This internal switch remains on for an additional 70 ns after OUTA or OUTB
goes high to blank leading edge transient noise in the current sensing loop. This reduces the filtering
requirements at the ILIM pin and improves the current sense response time.
Transformer Primary
UCC28250
ILIM
Side Current
CT
R
HICC
S
C
S
1:n
C
HICC
Figure 15. Current Limit Circuit
Once the over current protection level IPK is selected, the current transformer turns ratio and the burden resistor
value can be decided as:
0.5V ´n
RS =
IPK
(11)
In this equation, current transformer turns ratio is 1:n and RS is the burden resistor value.
Some filtering capacitance is required to reduce the sensing noise. Choose the RC constant at about 100 ns,
and calculate the capacitor value as:
100ns
CS =
RS
(12)
The cycle-by-cycle current limit operation time before all four outputs shut down can be programmed by external
capacitor CHICC at HICC pin. (See HICC pin description)
22
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
HICC (10/17)
The cycle-by-cycle current limit operation time before all four outputs shut down can be programmed by an
external capacitor CHICC from HICC pin to ground, as shown in Figure 15. Once all four outputs are shutdown,
controller goes into hiccup cycle which is about 100 times of the cycle-by-cycle current limit shut-down delay
time. A 1-mA internal current source charges HICC pin up to 2.4 V, then the HICC pin is discharged by a 2.7-µA
internal current source to generate long hiccup restart time until HICC reaches 0.3 V. Based on the system
requirement, once the cycle-by-cycle current limit delay time TOC(delay) is selected, the HICC pin capacitor CHICC
can be selected based on the equation
T
OC(delay) ´75mA
CHICC
=
0.6V
(13)
TOCdealy
THICC
HICC
2.4V
0.6V
0.3V
t
t
SS
4V
OUTA
OUTB
Normal
OC
Normal
OC
Hiccup
Soft Start
Figure 16. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
As shown in Figure 16, cycle-by-cycle current limiting shut-down delay time is:
0.6V
TOC(delay) = CHICC
´
75mA
(14)
(15)
And hiccup-restart-time THICC is equal to:
2.4V - 0.3V
THICC = CHICC
´
2.7mA
As soon as the outputs are shut-down, the SS pin is pulled to ground internally until the hiccup restart timer is
reset after time duration THICC
.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
OVP/OTP (19/6)
The OVP/OTP pin provides multiple fault protection functions. If the voltage on the OVP/OTP pin exceeds 0.7 V,
a fault shutdown occurs. All outputs stop switching and stay off (low) during the shutdown, and the SS pin is
pulled to ground internally. Once the fault condition is cleared (i.e. OVP/OTP voltage drops below 0.7 V), the
UCC28250 enters hiccup mode. A soft-start cycle begins after the hiccup cycle is finished. An internal 11-µA
switched current source is used to create hysteresis.
If the external resistor divider runs from line voltage VIN, a line over voltage protection is implemented.
If the external resistor divider runs from the output voltage, output over voltage fault protection is achieved.
Figure 17 shows the over-voltage protection external configuration at the OVP/OTP pin.
According to the protection threshold VR and recovery threshold VF, choose an arbitrary R2 value. To ensure a
realistic solution, R2 needs to meet the following:
0.7V ´ V - V
(
)
R
F
R2 <
11mA ´ V - 0.7V
(
)
R
(16)
The other two resistors, R1 and R3 can be calculated.
VR - 0.7V
R1 =
R3 =
´R2
0.7V
0.7V ´ V - V -11mA ´R ´ V - 0.7V
)
(17)
(18)
(
)
(
R
R
F
2
11mA ´ VR
If the external resistor divider runs from 3.3-V VREF, and replaces R2 with a positive temperature coefficient
(PTC) thermistor, an over temperature fault protection with programmable hysteresis is accomplished
(Figure 18). Choose an arbitrary PTC value, which has a resistance as RPTC1 at protection temperature and
resistance as RPTC2 at recovery temperature. Because of its positive temperature coefficient, RPTC1 is larger than
RPTC2. To ensure an available solution, RPTC1 and RPTC2 need to meet the criteria.
0.7V ´ RPTC1 -RPTC2 -11mA ´RPTC1 ´RPTC2 ³ 0
( )
(19)
And resistors R1 and R3 can be calculated as:
R1 = 3.7´RPTC1
(20)
é
PTC2 ù
û
2.6V ´ 0.7V ´ RPTC1 -RPTC2 -11mA ´RPTC1 ´R
( )
ë
R3 =
11mA ´ 2.6V ´RPTC1 + 0.7V ´RPTC2
(
)
(21)
UCC28250
VREF
VIN or VOUT
11 mA
R1
R2
R3
OVP
+
0.7 V
Figure 17. Over Voltage Protection
24
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
UCC28250
VREF
R1
11 mA
R3
OVP
+
0.7 V
PTC
Figure 18. Over Temperature Protection
Figure 19 shows an external configuration using the OVP/OTP pin to achieve both over-voltage and over
temperature protection. Follow the same design procedure for the OVP setting to choose R1, R2, and R3. Choose
an NTC value at protection temperature much smaller than R1 and with the resistance at protection temperature
as RNTC1, and recover temperature as RNTC2. The R4 value can be calculated as:
0.7V
R4 =
´RNTC1
3.3V - 0.7V
(22)
Because of the interaction between the two voltage dividers, over temperature protection thresholds move
slightly with the different input voltages.
UCC28250
VREF
VIN or VOUT
NTC
R1
11 mA
R3
OVP
+
R4
R2
0.7 V
Figure 19. Over Voltage and Over Temperature Protection With Single OVP Pin
OUTA (9/16) and OUTB (8/15)
OUTA and OUTB are the primary-side switch control signals. With the 0.2-A peak current capability, an external
gate driver is required.
SRA (7/14) and SRB (6/13)
SRA and SRB are the synchronous rectifier control signals. With the 0.2A peak current capability, an external
gate driver is required.
GND (4/11)
GND pin is the ground reference for the whole device. Tie all the signal returns to this pin.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
TYPICAL CHARACTERISTICS
START-UP CURRENT
vs
STAND-BY CURRENT
vs
TEMPERATURE
TEMPERATURE
240
465
V
= 3.6 V
V
= 12 V
DD
DD
220
200
180
450
435
420
405
160
140
120
100
390
375
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
T - Temperature - °C
J
J
Figure 20.
Figure 21.
UVLO THRESHOLDS
vs
UVLO VOLTAGE LOCKOUT HYSTERESIS
vs
TEMPERATURE
TEMPERATURE
4.41
4.33
4.25
0.225
0.220
Turn On
0.215
0.210
4.17
0.205
0.200
Turn Off
4.09
4.01
3.93
0.195
0.190
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
T - Temperature - °C
J
J
Figure 22.
Figure 23.
26
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS (continued)
OPERATING SUPPLY CURRENT
SOFT-START CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
2.85
27.4
27.3
F
= 200 kHz
SW
2.80
2.75
27.2
27.1
27.0
2.70
2.65
2.60
26.9
26.8
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
T - Temperature - °C
J
J
Figure 24.
Figure 25.
RAMP/CS CLAMP VOLTAGE AND HICCUP PULL-UP
CYCLE-BY-CYCLE CURRENT LIMIT
THRESHOLD
vs
vs
TEMPERATURE
TEMPERATURE
5.0
500.6
500.4
500.2
500.0
499.8
4.5
4.0
V
CS(max)
3.5
3.0
2.5
V
HICC_PU
2.0
1.5
499.6
499.4
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
J
T - Temperature - °C
J
Figure 26.
Figure 27.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
27
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CURRENT LIMIT SHUTDOWN DELAY TIMER AND HICCUP
RESTART
PROPAGATION DELAY/LEADING EDGE BLANKING
vs
vs
TEMPERATURE
TEMPERATURE
0.7
0.6
90
T
BLANK
70
V
HICC_SD
0.5
50
0.4
V
HICC_RST
T
PD_ILIM
30
0.3
0.2
10
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
J
T - Temperature - °C
J
Figure 28.
Figure 29.
REFERENCE VOLTAGE
vs
REFERENCE VOLTAGE
vs
TEMPERATURE
TEMPERATURE
3.306
V
= 12 V
DD
I
= 1 mA
LOAD
3.305
I
= 10 mA
LOAD
3.302
V
= 7 V
DD
3.295
I
= 1 mA
LOAD
3.298
V
= 17 V
DD
I
= 10 mA
LOAD
3.285
3.294
V
= 12 V
DD
3.275
3.290
-55 -35 -15
5
25 45
65
85 105 125
-55 -35 -15
5
25 45
65
85 105 125
T - Temperature - °C
J
T - Temperature - °C
J
Figure 30.
Figure 31.
28
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS (continued)
OVP INTERNAL REFERENCE
OVP INTERNAL CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
0.7015
11.20
11.15
0.7010
0.7005
11.10
11.05
11.00
10.95
0.7000
0.6995
0.6990
10.90
10.85
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
T - Temperature - °C
J
J
Figure 32.
Figure 33.
MINIMUM SYNCHRONIZATION FREQUENCY
MAXIMUM SYNCHRONIZATION FREQUENCY
vs
vs
TEMPERATURE
TEMPERATURE
85.4
85.2
1.153
1.151
1.149
1.147
85.0
84.8
84.6
84.4
1.145
1.143
84.2
84.0
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
T - Temperature - °C
J
J
Figure 34.
Figure 35.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
29
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
NOMINAL SWITCHING FREQUENCY
DEAD TIME
vs
vs
TEMPERATURE
TEMPERATURE
201.0
200.6
42.5
42.0
TD at R = 27 kW
PS
PS
41.5
41.0
200.2
199.8
40.5
40.0
TD at R = 20 kW
SP
SP
39.5
39.0
199.4
199.0
38.5
38.0
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
T - Temperature - °C
J
J
Figure 36.
Figure 37.
OUTPUT RISE/FALL TIME
OUTPUT SOURCE RESISTANCE/SINK RESISTANCE
vs
vs
TEMPERATURE
TEMPERATURE
35
12
V
= 12 V
DD
11
10
T
R
30
25
20
R
SRC
9
T
F
R
SNK
8
7
6
15
10
-45
-15
15
45
75
105
135
-45
-15
15
45
75
105
135
T - Temperature - °C
J
T - Temperature - °C
J
Figure 38.
Figure 39.
30
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
APPLICATION INFORMATION
The UCC28250 is a high performance PWM controller with advanced synchronous rectifier outputs and is ideally
suited for regulated half-bridge, full-bridge and push-pull converters. A dedicated internal pre-biased start up
control loop working in conjunction with a primary-side voltage loop achieves monotonic pre-biased start up for
either primary-side or secondary-side control applications. The UCC28250 architecture allows either voltage
mode or current mode control.
Input voltage feedforward can be implemented, allowing PWM ramp generator to improve the converter line
transient response. Advanced cycle-by-cycle current limit achieves volt-second balancing even during fault
conditions. The hiccup timer helps the system to stay within a safe operation range under over load conditions.
With a multifunction OVP/OTP pin, combinations of input voltage protection, output voltage protection and over
temperature protection can be implemented. The UCC28250 allows individual programming of dead time
between primary-side switch and secondary-side SRs, in order to allow optimal power stage design. Dead time
can also be reduced to zero, and this allows optimal system configuration considering the delays on the gate
driver stage. The UCC28250 also provides complete system level protection functions, including UVLO, thermal
shut down and over voltage, over current protection.
Error Amplifier and PWM Generation
The UCC28250 includes a high performance internal error amplifier with low input offset, high source/sink current
capability and high gain bandwidth (typical 3.5 MHz). The reference of the error amplifier (REF/EA+ pin) is set
externally to support flexible trimming of the voltage loop, and to make the controller flexible for both primary
side, as well as secondary-side control. The extra positive input for the error amplifier is the SS pin which is used
to externally program the soft-start time of the converter’s output.
During steady state operation, the primary switch duty cycle, D, is generated based on the external ramp on
RAMP/CS pin and the COMP pin voltage. A higher COMP pin voltage results in a larger duty cycle. The
secondary-side SR duty cycle is SR_D = (1-D), complementary to the primary-side duty cycle, without
considering the dead time between primary-side switch and secondary-side SR. The primary outputs begin to
switch when COMP pin voltage is above the 350 mV internal offset. The synchronous rectifier outputs only switch
after COMP pin voltage is above 550 mV internal offset. According to the internal logic, the minimum pulse width
for the primary-side OUTA and OUTB is typically 100 ns.
During soft start, the primary-side switch duty cycle is generated based on the external ramp on RAMP/CS pin
and the COMP pin voltage. However, the duty cycle of secondary-side SR is generated based on an internal
ramp and the COMP pin voltage. When the converter is controlled on the primary side, an internal ramp is a
fixed ramp with 3-V peak voltage. When the converter is controlled on secondary side, an internal ramp is
generated based on the internal pre-biased start-up loop. An internal pre-biased start-up loop modifies the SR
duty cycle during soft start to achieve the optimal pre-biased start-up performance.
After the SS pin reaches 2.9 V, the pre-biased start-up control loop is disabled. The secondary-side SR
instantaneously changes into its steady state value as complementary to the primary-side duty cycle.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
31
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
Pre-Biased Start Up
With the internal error amplifier, UCC28250 supports both primary-side control and secondary-side control. For
different control methods, the controller is configured accordingly and so is the pre-biased start-up control. During
soft start, both the primary-side switches’ duty cycle and secondary-side SRs’ duty cycle are increased. This
gradually increases the output voltage until steady state operation is reached, thereby reducing surge current.
Secondary-Side Control
For secondary-side control, the UCC28250 implements close-loop control of both the primary-side switches and
secondary-side synchronous rectifiers’ duty cycles. This makes it easy to achieve optimal start up performance.
The internal error amplifier is set up as the control loop error amplifier. Connect REF/EA+, FB/EA-, COMP and
VSENSE as shown in Figure 40. To achieve optimal pre-biased start up performance, the output voltage needs
to be directly measured. The UCC28250 uses the VSENSE pin to directly sense this output voltage. Choose the
voltage dividers on VSENSE slightly different to the FB/EA- voltage divider so that the voltage on VSENSE pin is
roughly 10% to 15% more than FB/EA- pin voltages. Select RO1 equal to RS1, and RS2 about 10% to 15% smaller
than RO2
.
VOUT
UCC28250
VSENSE
C
P1
R
O2
VREF
R
Z3
R
C
Z2
S2
R
Z2
COMP
C
Z3
FB/EA-
REF/EA+
SS
+
+
R
R
O1
S1
C
SS
Figure 40. Error Amplifier Set Up for Secondary-Side Control
The error amplifier uses the lower voltage between the SS pin and the REF/EA+ pin to be the reference voltage
for the feedback loop. In this method, the control loop is said to be ‘closed’ during the entire start up process, as
it is always based on the true output voltage.
During soft start, the primary-side switch duty cycle is controlled by the COMP pin voltage and ramp voltage
generated on the RAMP/CS pin. A higher COMP pin voltage results in larger duty cycle. However, to improve
start up performance, the secondary-side synchronous rectifier duty cycle is controlled by a separate, internal
ramp signal (generated by a dedicated pre-biased start up loop) and by the COMP pin voltage. This dedicated
pre-biased loop is much faster than the regular voltage loop in order to avoid interaction between the two loops.
The start up loop reads the output voltage via a transconductance error amplifier connected to the VSENSE pin.
When the output voltage is higher than the reference, the pre-biased start up loop increases the SR duty cycle to
reduce the output voltage. Conversely, when the output voltage is lower than the reference, the SR duty cycle is
decreased to help maintain higher output voltage. To speed up the start up time, the minimum duty cycle of the
synchronous rectifier is 50%.
Once the soft start is finished, the pre-biased loop is disabled and the duty cycle of the synchronous rectifiers
becomes the complimentary of primary switches’ duty cycle, with some dead time inserted in between.
32
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Primary-Side Control
When the UCC28250 is sitting on the primary side, the internal error amplifier is connected as a voltage follower
and an extra error amplifier is needed on the secondary side for closed loop control. The error amplifier
implementation is shown in Figure 41.
VOUT
UCC28250
R
C
VSENSE
O2
P1
R
Z3
C
VREF
Z2
R
Z2
COMP
C
Z3
FB/EA-
REF/EA+
SS
+
R
+
+
O1
External
Reference
C
SS
Figure 41. Error Amplifier Setup for Primary-Side Control
In the above configuration, the UCC28250 can only see the control loop feedback voltage, and cannot directly
access the output voltage. The design of the soft-start time is critical to achieve optimal pre-biased start up
performance. Some trial and error approaches are needed to achieve optimal performance. It is also important to
choose the appropriate ramp amplitude. Refer to the ramp section discussion on the detailed design procedure
for choosing ramp generation components.
During soft start, regardless of the pre-biased condition, the output voltage is always lower than the regulation
voltage, so that the feedback loop is always saturated. When the internal error amplifier is connected as a
voltage follower, the COMP voltage follows the lower of the voltage on the RER/EA+ pin and the SS pin. Since
the feedback loop is saturated, the COMP pin always follows the SS pin voltage, until the output voltage
becomes regulated and the feedback voltage takes over. In this control method, the output voltage control loop is
always saturated, and the controller soft starts the COMP pin voltage. Therefore, it is called open loop soft start.
The primary-side switch duty cycle is controlled by the COMP pin voltage and by the RAMP/CS pin voltage.
During soft start, the COMP pin voltage follows the SS pin as it is rising, so the primary-side switch duty cycle
keeps increasing. When the output voltage becomes regulated, the feedback voltage becomes less than the SS
pin voltage and the primary-side switch comes controlled by the control loop.
For the primary-side control setup, because output voltage is not directly accessible, the internal pre-biased start
up loop is disabled by connecting VSENSE to VREF. Instead, the internal ramp used to generate the
synchronous rectifier duty cycle is fixed, with the peak voltage of 3 V. The duty cycle of the synchronous rectifier
increases as the SS pin voltage increases. When the SS pin voltage reaches 2.9 V, the soft start is considered
finished and the synchronous rectifier duty cycle becomes the complementary of the primary-side switch duty
cycle, minus the programmed dead time. Because of different COMP pin voltages at different line voltages, the
SR duty cycle generated by the internal ramp might be different than the complementary of the primary-side
switch duty cycle (1-D). If the duty cycle is too large, the internal logic is able to limit the duty cycle to (1-D).
However, if the duty cycle is too small, when the soft start is finished, the SR duty cycle has a sudden change,
which will cause output voltage disturbance. To optimize the pre-biased start up performance, it is recommended
that the duty cycle change at the end of soft start be as small as possible.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
33
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
Voltage Mode Control and Input Voltage Feed-Forward
For voltage mode control, a resistor RCS and a capacitor CCS are connected externally at RAMP/CS pin as
shown in Figure 42. A ramp signal is generated on the RAMP/CS pin, at a rate of two times that of the switching
frequency. The generated ramp signal is used to control the duty cycle for both the primary-side switches and
secondary-side synchronous rectifiers. The ramp amplitude can be fixed or variable with the input voltage (input
voltage feedforward).
To realize a fixed amplitude ramp, connect RCS to the VREF pin, so that the ramp capacitor charging voltage is
fixed regardless of line and load condition. The RAMP/CS pin is clamped internally to 4 V for internal device
protection. Because the internal pull-down switch has about 40-Ω on-resistance, the CCS value must be small
enough to discharge RAMP/CS from the peak to ground within TD(sp) + 70 ns (i.e. the pulse width of BLANK
signal).
To achieve the input voltage feedforward, the slope of the ramp needs to be proportional to the input voltage. Tie
RCS to the input line voltage. Because the ramp voltage is much lower than the input voltage, the ramp capacitor
charging current is considered to be proportional to the input voltage. With input voltage feedforward, the COMP
pin voltage should only move slightly even with large input voltage variation. This will provide much better line
transient response for the converter.
UCC28250
UCC28250
V
36 V to 75 V
IN
VREF
R
R
CS
CS
RAMP/CS
RAMP/CS
C
C
CS
CS
BLANK
BLANK
GND
GND
Figure 42. External Configuration of RAMP/CS Pin With/Without Feed-Forward Operation
34
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
The input voltage feedforward also helps on pre-biased start up. When doing primary-side control to pre-biased
start up, three conditions need to be considered:
Condition 1
At initial start up the primary side needs to provide enough energy to prevent output voltage dip;
Condition 2
At the end of soft start, it is required to keep the SR duty cycle change to be as small as possible. With input
voltage feedforward, the COMP pin voltage is virtually fixed for different input voltages. Therefore, before the end
of soft start, the duty cycle is the same for different input voltages. Choose the RCS and CCS following the
procedure below.
Considering initial start up, the RAMP peak voltage should be:
V
IN
- VPRE-BIAS
2´n
VRAMP
=
´ VSR(ramp)
2´ VPRE-BIAS
(23)
In this equation, VIN is the input voltage because of the feedforward any input voltage should be fine; VPRE-BIAS is
the highest pre-bias start-up voltage required by the system; n is the tranformer primary to secondary turns ratio
and VSR(ramp) is the internal SR ramp peak voltage 3 V.
Another consideration is at the end of soft start, the SR duty cycle changes from controlled by the soft start, to
complimentary to the primary-side duty cycle. The design should keep the transition as smooth as possible.
Considering this, based on the output voltage and input voltage range, as well as the transformer turns ratio,
calculate the SR duty cycle at different line voltages.
Next, based on the maximum duty cycle on the SR_DMAX, and the internal fixed ramp amplitude 3 V, the COMP
voltage at regulation can be chosen as:
VCOMP(final) = SR _D
(
- 0.5 ´3V ´ 2
)
MAX
(24)
Condition 3
Use the calculated COMP pin voltage to derive the external ramp amplitude
VCOMP(final)
VRAMP
=
1- SR _D
´ 2
)
(
MAX
(25)
According to the calculated ramp voltage from Equation 23 and Equation 25 some trade off is required to pick up
the appropriate ramp voltage. Based on the selected ramp capacitor CCS value, choose the ramp resistor RCS
value:
VIN(max) ´ 2
RCS
=
VRAMP ´CCS ´ fsw
(26)
In this equation, VIN(max) is the maximum input voltage, fSW is the switching frequency.
Because these calculations ignore the dead time and the non-linearity of the ramp, slight modification is expected
to achieve the optimal design. When the input voltage feed forward is not used, refer to the RAMP pin discussion
for RC calculation.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
35
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
Peak Current Mode Control
For peak current mode control, RAMP/CS pin is connected directly with the current signal generated from a
current transformer. The current signal must be compatible with the input range of the COMP pin. External slope
compensation is required to prevent sub-harmonic oscillation and to maintain flux-balance. The slope
compensation can be implemented by using OUTA and OUTB to charge external capacitors and use the voltage
follower to add into the sensed the current signal, as shown in Figure 43. Follow the peak current mode control
theory to select compensation slope or refer to “Modeling, Analysis and Compensation of the Current-Mode
Converter”, (TI Literature Number SLUA101).
OUTA
OUTB
UCC28250
VREF
Transformer Primary
Side Current
RAMP/CS
CT
BLANK
R
S
C
S
1:n
Figure 43. UCC28250 Set Up for Peak Current Mode Control
36
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Cycle-by-Cycle Current Limit and Hiccup Mode Protection
Cycle-by-cycle current limit is accomplished using the ILIM pin for both current mode control and voltage mode
control. The input to the ILIM pin represents the primary current information. If the voltage sensed at ILIM pin
exceeds 0.5 V, the current sense comparator terminates the pulse of output OUTA or OUTB. If the high current
condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the
current sense comparator instead of the PWM comparator. ILIM pin is pulled down by an internal switch at the
rising edge of each clock cycle. This internal switch remains on for an additional 70 ns after OUTA or OUTB
goes high to blank leading edge transient noise in the current sensing loop. This reduces the filtering
requirements at the ILIM pin and improves the current sense response time.
UCC28250 makes it possible to maintain flux balance during cycle-by-cycle current limit operation. The duty
cycles of primary switches are always matched. If one switch duty cycle is terminated earlier because of current
limiting, a matched duty cycle is applied to the other switch for the next half switching cycle, regardless of the
current condition, as shown in Figure 44. This matched duty cycle helps to maintain volt-second balancing on the
transformer and prevents the transformer saturation.
CLK
70ns
0.5V
ILIM
OUTA
OUTB
Figure 44. Cycle-by-Cycle Current Limit Duty Cycle Matching
Once the current limit is triggered, the 75-µA internal current source begins to charge the capacitor on HICC pin.
If the current limit condition went away before HICC pin reaches 0.6 V, the device stops charge HICC capacitor
and begins to discharge it with 2.7-µA current source. If the cycle-by-cycle current limit condition continues, HICC
pin reachs 0.6 V, and all four outputs are shut down. The UCC28250 then enters hiccup mode. During hiccup
mode, all four outputs keep low; SS pin is pulled to ground internally; a 2.7-µA current source continuously
discharge HICC pin capacitor; until HICC pin voltage reaches 0.3 V. After that, HICC pin is discharged internally
to get ready for the next HICC event. The whole converter starts with soft start after hiccup mode.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
37
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
The cycle-by-cycle current limit operation time before all four outputs shut down is programmed by external
capacitor CHICC at HICC pin. The delay time can be calculated as:
0.6V
TOC(delay) = CHICC
´
75mA
(27)
The hiccup timer keeps all outputs being zero until the timer expires. The hiccup time THICC is calculated as:
2.4V - 0.3V
THICC = CHICC
´
2.7mA
(28)
As soon as the outputs are shut-down, SS pin is pulled down internally until the hiccup restart timer is reset after
time duration THICC. The detailed illustration of HICCUP mode is shown in Figure 45.
TOCdealy
THICC
HICC
2.4V
0.6V
0.3V
t
t
SS
4V
OUTA
OUTB
Normal
OC
Normal
OC
Hiccup
Soft Start
Figure 45. Cycle-by-Cycle Current Limit Delay Timer and Hiccup Restart Timer
Thermal Protection
Internal thermal shutdown circuitry protects the UCC28250 in the event the maximum rated junction temperature
is exceeded. When activated, typically at 160°C, with the maximum threshold at 170°C and minimum threshold at
150°C the controller is forced into a low power standby mode. The outputs (OUTA, OUTB, SRA, SRB) are
disabled. This helps to prevent accidental device overheating. A 20°C hysteresis is added to prevent comparator
oscillation. During thermal shutdown, the UCC28250 follows a normal start up sequence after the junction
temperature falls below 140°C (typical value, with 130°C minimum threshold and 150°C maximum threshold).
38
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Design Example
The example provided here is to show how to design a symmetrical half bridge converter of voltage mode control
with UCC28250 on primary side.
Figure 46 is the circuit diagram to be used in this design example. This design example is to show how to
determine the values in the circuit associated to UCC28250 programming.
Figure 46. Circuit Diagram in Design Example.
Table 1 shows the specifications for the design example.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
39
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Design Steps
www.ti.com
Step 1, Power Stage Design
The power stage design in this example is standard and the same as that for symmetrical half bridge converter of
voltage mode control. From the standard design, these components are determined. This includes Q1 through
Q4, C1, C2, CT1, D1 and D2, D3, T1, T2 and T3, and U6. Their design is standard. Also, design associated to
current sensing and protection is also standard. This includes CT1, D1, D2, R5 and C5.
Step 2, Feedback Loop Design
D3 (TLV431) with U6, R6, R9, R10, R12, R13, C11 and C12 are composed of standard type 3 feedback loop
compensation network and output voltage set point. Their design is also standard.
Table 1. Specifications for the Design Example
PARAMETER
MIN
TYP
MAX
UNITS
VIN
Input voltage
36
48
72
VDC
VOUT
POUT
IOUT
COUT
fSW
Output voltage
Outpu power
3.3
75
23
W
A
Output load current
Load capacitance
Switching frequency
Over-power limit
Efficiancy at full load
Isolation
5000
µF
kHz
150
PLIMIT
h
150%
90%
1500
V
40
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Step 3, Programming the Device
Step 3-1
Equation 3 is used to determine RT based on switching frequency, 300 kHz and assumes the dead time of 150
ns.
1
1
- Td SP
-150ns
(
)
2´ fSW
2´150kHz
RT =
=
= 94.9kW Þ R4 = 100kW
33.2pF
33.2pF
(29)
Step 3-2, Determine RAMP Resistance and Capacitance
There are two-fold considerations to determine RAMP resistance and capacitance. Equation 23 provides RAMP
consideration for SR initial start up with prebias. The corresponding RAMP peak voltage is determined with input
voltage low line and maximum prebias output voltage. In the below T1 turns ratio n = 4.
V
36V
IN
- Vpre-bias
- 3.0V
2´n
2´ Vpre-bias
2´ 4
2´3.0V
VRAMP
=
´ VSR _RAMP
=
´3.0V = 0.750V
(30)
Equation 24 and Equation 25 provides RAMP consideration for soft start completion to make duty cycle match
(1-D) = SR_D.
1. Calculate OUTA or OUTB duty cycle at 75-V input voltage, 3.3-V output.
n´ VO
1
2
4´3.3V
1
2
D =
´
=
´
= 0.176
V
75V / 2
IN
2
(31)
(32)
(33)
2. Calculate SRA or SRB duty cycle.
SR _D = 1-D = 1- 0.176 = 0.82
3. Calculate the COMP voltage value in steady state (Equation 24).
VCOMP = (SR _D - 0.5)´3.0V ´2 = (0.824 - 0.5)´3.0V ´2 = 1.944V
4. Calculate the RAMP peak value (Equation 25).
VCOMP
=
(D´ 2) (0.176´ 2)
1.944V
VRAMP
=
= 5.523V
(34)
5. Arbitrary select CRAMP 470 pF, then C3 = 470 pF.
6. Calculate RRAMP
.
1
1
RRAMP _1
=
=
= 336.9kW
36V
æ
ç
è
ö
÷
ø
VCHARGE
2´ln(
)´ 470pF´150kHz
2´ln
´CRAMP ´ fsw
36V - 0.750V
VCHARGE - VRAMP
(35)
1
VCHARGE
1
RRAMP _ 2
=
=
= 92.7kW
75V
æ
ç
è
ö
÷
ø
2´ln(
)´ 470pF´150kHz
2´ln
´CRAMP ´ fsw
75V - 5.523V
VCHARGE - VRAMP
(36)
As different RAMP resistor values are obtained, at this stage, we may take their average value for initial design.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
41
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
Step 3-3, Determine Soft-Start Capacitance
Determine soft-start capacitance with soft-start time 15 ms.
27mA ´ TSS
27mA ´15ms
CSS
=
=
= 0.101mF Þ C8 = 0.1mF
VCOMP(final)
4.0V
(37)
Step 3-4, Determine Dead-Time Resistance
Assuming the dead time is 150 ns, Select R7 = R8 = 121 kΩ based on Figure 9 and Figure 10.
Step 3-5, Determine OCP Hiccup Off-Time Capacitance
Assuming off time is 0.8 s (Equation 15).
2.7mA
2.7mA
CHICC = THICC
´
= 0.8s´
= 1.03mF Þ C7 = 1.0mF
2.4V - 0.3V
2.4V - 0.3V
(38)
Step 3-6, Determine Primary-Side OVP Resistance
Assuming OV_OFF = 73 V, OV_ON = 72 V (Equation 16 to Equation 18).
0.7V ´ V - V
0.7V ´ 73V - 72V
(
11mA ´ 73V - 0.7V
(
(
11mA ´ V - 0.7V
)
)
)
r
f
R2 £
=
= 880W Þ R2 = 866W
(
)
r
(39)
(40)
VR - 0.7V
´R2 =
0.7V
73V - 0.7V
R1 =
R3 =
´866W = 89.4kW Þ R1= 88.7kW
0.7V
0.7V ´ V - V -11mA ´R ´ V - 0.7V
(
(
)
)
R
F
2
R
=
11mA ´ V
r
0.7V ´ 73V - 72V -11mA ´866W´ 73V - 0.7V
(
(
)
11mA ´73V
)
=
= 14W Þ R14 = 14W
(41)
Step 3-7, Select Capacitance for VDD and VREF
As recommended by the datasheet, select C6 = C4 = 1.0 µF. The final design is shown in Figure 47.
42
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
UCC28250
www.ti.com
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
Figure 47. Schematics of Primary-Side Control Design Example
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
43
Product Folder Link(s): UCC28250
UCC28250
SLUSA29B –APRIL 2010–REVISED OCTOBER 2010
www.ti.com
REVISION HISTORY
Changes from Revision A (April, 2010) to Revision B
Page
•
Added note, "The minimum value for RPS/RSP is 5 kΩ and the maximum value is 250 kΩ." in two places. ...................... 15
44
Submit Documentation Feedback
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): UCC28250
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
UCC28250PW
UCC28250PWR
UCC28250RGPR
UCC28250RGPT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
QFN
PW
PW
20
20
20
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
2000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Purchase Samples
RGP
RGP
Green (RoHS
& no Sb/Br)
QFN
Green (RoHS
& no Sb/Br)
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
Automotive
www.ti.com/automotive
www.ti.com/communications
Communications and
Telecom
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Consumer Electronics
Energy
www.ti.com/consumer-apps
www.ti.com/energy
Logic
Industrial
www.ti.com/industrial
Power Mgmt
Microcontrollers
RFID
power.ti.com
Medical
www.ti.com/medical
microcontroller.ti.com
www.ti-rfid.com
Security
www.ti.com/security
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明