UCC284-5_技术文档

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

DP PACKAGE

(FRONT VIEW)

D

Precision Negative Series Pass Voltage

Regulation

D

0.2 V Dropout at 0.5 A

VOUTS 1

8

SD/CT

VIN

Wide Input Voltage Range –3.2 V to –15 V

Low Quiescent Current Irrespective of Load

Simple Logic Shutdown Interfacing

–5 V, –12 V, and Adjustable Output

2.5% Duty Cycle Short Circuit Protection

2

3

4

7

6

5

VIN

VOUT

GND

description

The UCC384-x family of negative linear-series pass regulators is tailored for low-dropout applications where

low-quiescent power is important. Fabricated with a BCDMOS technology ideally suited for low input-to-output

differential applications, the UCC384-x passes 0.5 A while requiring only 0.2 V of input-voltage headroom.

Dropout voltage decreases linearly with output current, so that dropout at 50 mA is less than 20 mV.

Quiescent current consumption for the device under normal (non-dropout) conditions is typically 200 µA. An

integrated charge pump is internally enabled only when the device is operating near dropout with low VIN. This

ensured that the device meets the dropout specifications even for maximum load current and a VIN of –3.2 V

with only a modest increase in quiescent current. Quiescent current is always less than 350 µA, with the charge

pump enabled. The quiescent current of the UCC384 does not increase with load current.

Short-circuit current is internally limited. The device responds to a sustained overcurrent condition by turning

off after a t

beginspulsingonandoffatthet /t

delay. The device then stays off for a period, t

, that is 40 times the t

delay. The device then

ON

OFF

ON

dutycycleof2.5%.Thisdrasticallyreducesthepowerdissipationduring

ON OFF

short circuit such that heat sinking, if at all required, must only accommodate normal operation. An external

capacitor sets the on time. The off time is always 40 times t

.

ON

The UCCx84-x can be shutdown to 45 µA (maximum) by pulling the SD/CT pin more positive than –0.7 V. To

allow for simpler interfacing, the SD/CT pin may be pulled up to 6 V above the ground pin without turning on

clamping diodes.

Internal power dissipation is further controlled with thermal-overload protection circuitry. Thermal shutdown

occurs if the junction temperature exceeds 140°C. The chip remains off until the temperature has dropped 20°C

(T = 120°C).

J

AVAILABLE OPTIONS

OUTPUT VOLTAGE (V)

PACKAGE DEVICES

(SOIC) DP

T

A

TYP

–5

UCC284DP–5

–12

ADJ

–5

UCC284DP–12

UCC284DP–ADJ

UCC384DP–5

–40°C to 85°C

0°C to 70°C

–12

ADJ

UCC384DP–12

UCC384DP–ADJ

†

All package types are available taped and reeled. Add TR suffix to device type

(e.g. UCC284DP–5TR) to order quantities of 3000 devices per reel.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

functional block diagram

(+)

4

GND

1–

A

µ

R1

0

R2

DISCHARGE

UCC384–ADJ

UCC384–5

OPEN

+

–2.2 V

SHUTDOWN

375K 125K

375K 43.6K

–0.7 V

1.25 V

R2

UCC384–12

50 k

+

–1.6 V

–2.6 V

TON

TOFF

S

Q

SD/CT

8

VPUMP

R

R1

+

GM

µ

40

A

CHARGE

1

VOUTS

OVERCURRENT

700 mA

+

VIN

2

3

6

7

THERMAL

SHUTDOWN

VIN

(–)

UVLO

5

VOUT

(–)

UDG–99030

Ĕ}

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

‡

Input voltage range , V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –16 V

IN

Shutdown voltage range, SD/CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 6 V

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

J

Storage temperature range T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

electrical characteristics T = 0°C to 70°C for the UCC384 and –40°C to 85°C for the UCC284,

A

VIN = VOUT – 1.5 V, I

= 0 mA, C

= 4.7 µF, and CT = 0.015 µF. For UCC384–ADJ, VOUT is set

OUT

to –3.3V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UCC384–5 Fixed –5-V 0.5-A Regulation Section

T

= 25°C

–5.075

–5.100

–5 –4.925

–4.850

V

A

Output voltage

Over all conditions

Line regulation

VIN = –5.2 V to –15 V

1.5

0.1

10

mV

%

Load regulation

Output noise voltage

I

= 0 mA to 0.5 A

0.25

OUT

= 25°C,

T

BW = 10 Hz to 10 kHz

200

0.20

20

µVRMS

V

A

I

0.5 A,

VOUT = –4.8 V

0.50

50

OUT

Dropout voltage, VOUT – VIN

50 mA,

mV

OUT

UCC384–5 Fixed –5-V 0.5-A Power Supply Section

Input voltage range

–15

–5.2

350

250

V

Quiescent current charge pump on

Quiescent current

VIN = –4.85 V,

VIN = –15 V

VIN = –13 V,

See Note 1

280

200

µA

SD/CT = 0 V

15

45

µA

T

A

= 0°C to 85°C, See Note 2

Quiescent current in shutdown

VIN = –13 V,

SD/CT = 0 V

100

T

A

= –40°C to 0°C, See Note 2

Shutdown threshold

At shutdown pin (SD/CT)

SD/CT = 0 V

–1.0

–0.7

–0.4

V

Shutdown input current

5

10

25

µA

VIN = –15 V,

See Note 3

VOUT = 0 V,

Output leakage in shutdown

1

50

µA

Overtemperature shutdown

Overtemperature hysteresis

140

20

°C

UCC384–5 Fixed –5-V 0.5-A Current Limit Section

Peak current limit

VOUT = 0 V

0.7

1.1

0.7

2.5

500

1.5

0.9

4

A

Overcurrent threshold

Current limit duty cycle

0.55

VOUT = 0 V

%

µs

Overcurrent time out, t

ON

300

700

UCC384–12 Fixed 12-V 0.5-A Regulation Section

T

= 25°C

–12.18

–12.24

–12 –11.82

–11.64

V

A

Output voltage

Over all conditions

Line regulation

VIN = –12.5 V to –15 V

5

0.1

15

mV

%

Load regulation

Output noise voltage

I = 0 mA to 0.5 A

OUT

0.3

T

= 25°C

BW = 10 Hz to 10 kHz

VOUT = –11.6 V

200

0.15

15

µVRMS

V

A

I

0.5 A,

0.5

50

OUT

Dropout voltage, VOUT – VIN

50 mA,

VOUT = –11.6 V

mV

OUT

UCC384–12 Fixed –12 V-0.5-A Power Supply Section

Input voltage range

–15

–12.5

V

Quiescent current

VIN = –15 V

VIN = –13 V,

220

15

350

µA

SD/CT = 0 V

45

µA

T

A

= 0°C to 85°C, See Note 2

Quiescent current in shutdown

VIN = –13 V,

SD/CT = 0 V

100

T

A

= –40°C to 0°C, See Note 2

NOTES: 1. The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to

provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required,

it is disabled, which lowers overall device power consumption.

2. Ensured by design. Not production tested.

3. In the application during shutdown mode, output leakage current adds to quiescent current.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

electrical characteristics T = 0°C to 70°C for the UCC384 and –40°C to 85°C for the UCC284,

A

VIN = VOUT – 1.5 V, I

= 0 mA, C

= 4.7 µF, and CT = 0.015 µF. For UCC384–ADJ, VOUT is set

OUT

to –3.3V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

–1.0

TYP

–0.7

MAX

–0.4

UNIT

UCC384–12 Fixed –12 V-0.5-A Power Supply Section (continued)

Shutdown threshold

At shutdown pin (SD/CT)

V

Shutdown input current

SD/CT = 0 V

5

10

25

µA

VIN = –15 V,

See Note 3

VOUT = 0 V,

Output leakage in shutdown

1

50

µA

Overtemperature shutdown

Overtemperature hysteresis

140

20

°C

UCC384–12 Fixed –12-V 0.5-A Current Limit Section

Peak current limit

VOUT = 0 V

0.7

1.1

0.7

2.5

500

1.5

0.9

4

A

Overcurrent threshold

Current limit duty cycle

0.55

VOUT = 0 V

%

µs

Overcurrent time out, t

ON

300

700

UCC384–ADJ Adjustable 0.5-A Regulation Section

T

= 25°C

–1.27

–1.25

–1.23

–1.215

3

V

A

Reference voltage

Over temperature

VIN = –3.5 V to –15 V,

= 0 mA to 0.5 A

–1.275

Line regulation

VOUT = VOUTS

0.5

0.1

mV

%

Load regulation

Output noise voltage

I

0.18

OUT

BW = 10 Hz to 10 kHz,

T

A

= 25°C

200

0.25

25

µVRMS

V

I

0.5 A,

VOUT = –3.15 V

0.5

50

OUT

Dropout voltage, VOUT – VIN

50 mA,

mV

nA

Sense pin input current

100

250

UCC384–ADJ Adjustable 0.5-A Power Supply Section

Input voltage range

–15

–3.5

–2.7

350

250

V

Undervoltage lockout

–3.2

–2.95

200

Quiescent current charge pump on

Quiescent current

VIN = –3.15 V,

VIN = –15 V

VIN = –13 V,

See Note 1

µA

200

SD/CT = 0 V

15

45

µA

T

= 0°C to 85°C, See Note 2

A

Quiescent current in shutdown

VIN = –13 V,

SD/CT = 0 V

100

T

A

= –40°C to 0°C, See Note 2

Shutdown threshold

At shutdown pin (SD/CT)

SD/CT = 0V

–1.0

–0.7

–0.4

V

Shutdown input current

5

10

25

µA

VIN = –15V,

See Note 3

VOUT = 0 V,

Output leakage in shutdown

1

50

µA

Overtemperature shutdown

Overtemperature hysteresis

140

20

°C

UCC384–ADJ Adjustable 0.5-A Current Limit Section

Peak current limit

VOUT = 0 V

0.7

1.1

0.7

2.5

500

1.5

0.9

4

A

Overcurrent threshold

Current limit duty cycle

0.55

VOUT = 0 V

%

µs

Overcurrent time out, t

ON

300

700

NOTES: 1. The internal charge pump is enabled only for dropout condition with low VIN. Only in this condition is the charge pump required to

provide additional output FET fate drive to maintain dropout specifications. For conditions where the charge pump is not required,

it is disabled, which lowers overall device power consumption.

2. Ensured by design. Not production tested.

3. In the application during shutdown mode, output leakage current adds to quiescent current.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

pin descriptions

GND: This is the low noise ground reference input. All voltages are measured with respect to the GND pin.

SD/CT: This is the shutdown pin and also the short-circuit timing pin. Pulling this pin more positive than –0.7 V

puts the circuit in a low-current shutdown mode. Placing a timing capacitor between this pin and GND sets the

short-circuit charging time, t

pulses at approximately a 2.5% duty cycle.

during an overcurrent condition. During an overcurrent condition, the output

ON

NOTE:The CT capacitor must be connected between this pin and GND, not VIN, to assure that the

SD/CT pin is not pulled significantly negative during power-up. This pin should not be externally

driven more negative than –5 V or the device will be damaged.

VIN: This is the negative input supply. Bypass this pin to GND with at least 1 µF of low ESR or ESL capacitance.

VOUT: Regulated negative-output voltage. A single 4.7-µF capacitor should be connected between this pin and

GND. Smaller value capacitors can be used for light loads, but this degrades the load-step performance of the

regulator.

VOUTS: This is the feedback pin for sensing the output of the regulator. For the UCC384-5 and UCC384-12

versions, VOUTS can be connected directly to VOUT. If the load is placed at a considerable distance from the

regulator, the VOUTS lead can be used as a Kelvin connection to minimize errors due to lead resistance.

Connecting VOUTS at the load moves the resistance of the VOUT wire into the control loop of the regulator,

thereby effectively canceling the IR drop associated with the load path.

APPLICATION INFORMATION

overview

The UCCx84-x family of negative low-dropout linear (LDO) regulators provides a regulated-output voltage for

applications with up to 0.5 A of load current. The regulators feature a low-dropout voltage and short-circuit

protection, making their use ideal for demanding applications requiring fault protection.

programming the output voltage on the UCC384

The UCC384-5 and UCC384-12 have output voltages that are fixed at –5 V and –12 V respectively. Connecting

VOUTS to VOUT gives the proper output voltage with respect to ground.

The UCC384-ADJ can be programmed for any output voltage between –1.25 V and –15 V. This is easily

accomplished with the addition of an external resistor divider connected between GND and VOUT with VOUTS

connected to the center tap of the divider. For an output of –1.25 V, no resistors are needed and VOUTS is

connected directly to VOUT. The regulator-input voltage cannot be more positive than the UVLO threshold, or

approximately –3 V. Thus, low dropout cannot be achieved when programming the output voltage more positive

than approximately –3.3 V. A typical application circuit is shown in Figure 1.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

programming the output voltage on the UCC384 (continued)

(+)

CT

0.015 F

µ

4

R2

VOUT

GND

+

8

SD/CT

VOUTS

1

5

COUT

4.7 F

CIN

1 F

µ

+

C1

R1

VIN

UCC384–ADJ

VOUT

(–)

VIN VIN VIN VIN

2

3

6

7

(–)

UDG–99029

Figure 1. Typical Application Circuit

For the UCC384–ADJ, the output voltage is programmed by the following equation:

R1

R2

_{VOUT + * 1.25}ǒ_{1 )}

Ǔ

(1)

When R1 or R2 are selected to be greater than about 100 kΩ, a small ceramic capacitor should be placed across

R1 to cancel the input pole created by R1 and the parasitic capacitance appearing on VOUTS. Values of

approximately 20 pF should be adequate.

dropout performance

The UCC384 is tailored for low-dropout applications where low-quiescent power is important. Fabricated with

a BCDMOS technology ideally suited for low input-to-output differential applications, the UCC384 passes 0.5A

while requiring only 0.2 V of headroom. The dropout voltage is dependent on operating conditions such as load

current, input and load voltages, and temperature. The UCC384 achieves a low R (on) through the use of an

DS

internal charge-pump that drives the MOSFET gate.

Figure 2 shows typical dropout voltages versus output voltage for the UCC384-5 V and -12 V versions as well

as the UCC384–ADJ version programmed between –3.3 V and –15 V. Since the dropout voltage is also affected

by output current, Figure 3 shows typical dropout voltages versus load current for different values of VOUT.

Operating temperatures also affect the R (on) and the dropout voltage of the UCC384. Figure 4 shows typical

DS

dropout voltages for the UCC384 over temperature under a full load of 0.5 A.

short-circuit protection

The UCC384 provides unique short-circuit protection circuitry that reduces power dissipation during a fault.

When an overcurrent condition is detected, the device enters a pulsed mode of operation, limiting the output

toa2.5%dutycycle. Thisreducestheheatsinkrequirementsduringafault. TheoperationoftheUCC384during

an overcurrent condition is shown in Figure 5.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

short-circuit protection (continued)

DROPOUT VOLTAGE

vs

LOAD CURRENT

DROPOUT VOLTAGE

vs

OUTPUT VOLTAGE

0.25

0.20

0.15

0.30

V_OUT= –5 V

I_OUT= 0.3 A

0.25

0.20

V

= –3.3 V

OUT

I_OUT= 0.4 A

I_OUT= 0.5 A

0.15

0.10

0.05

0.00

0.10

0.05

V_OUT= –12 V

V_OUT= –15 V

I_OUT= 0.2 A

I_OUT= 0.1 A

6

0.05

0.15

0.25

0.35

0.45

3

9

12

15

I_OUT– Load Current – A

V

_OUT– Output Voltage – V

Figure 2

Figure 3

DROPOUT VOLTAGE

vs

TEMPERATURE

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

V_OUT= –3.3 V

V_OUT= –5 V

V_OUT= –12 V

V_OUT= –15 V

–50

–25

0

25

50

75

100

T

– Free-Air Temperature – _C

A

Figure 4

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

t

OFF

t

ON

IOUT=0A

~40 x t

ON

~40 x t

ON

IOUT (NOM)

IOVER

IPEAK

NOTE: CURRENT FLOW IS INTO THE DEVICE

VOUT = 0V

VOUT

=(IPEAK)(RL)

VOUT NOM. (–V)

CT = 0V

CT (NOM) = – 1.6V

CT = – 2.6V

UDG–99031

Figure 5. Short Circuit Timing

UCC384 short circuit timing

During normal operation the output voltage is in regulation and the SD/CT pin is held to –1.5 V via a 50-kΩ

internal-source impedance. If the output-current rises above the overcurrent threshold, the CT capacitor is

charged by a 40-µA current sink. The voltage on the SD/CT pin moves in a negative direction with respect to

GND.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

UCC384 short-circuit timing (continued)

During an overcurrent condition, the regulator actively limits the maximum output current to the peak-current

limit. This limits the output voltage of the regulator to:

(1)

V

+ I

R

OUT

PEAK

L

If the output current stays above the overcurrent threshold, the voltage on the SD/CT pin reaches –2.6 V with

respect to GND and the output turns off. The CT capacitor is then discharged by a 1-µA current source. When

thevoltageontheSD/CTpinreaches–1.6VwithrespecttoGND, theoutputturnsbackon. Thisprocessrepeats

until the output current falls below the overcurrent threshold.

t

, the time the output is on during an overcurrent condition is determined by the following equation:

1 V

ON

t

(2)

(3)

(

)

+ CT mF

seconds

ON

40 mA

t

, the time the output is off during an overcurrent condition is determined by the following equation:

OFF

t

1 V

(

)

+ CT mF

seconds

OFF

1 mA

capacitive loads

A capacitive load on the regulator’s output appears as a short-circuit during start-up. If the capacitance is too

large, the output voltage does not begin to regulate during the initial t period and the UCC384 enters a pulsed

ON

mode operation. For a constant current load the maximum allowed output capacitance is calculated as follows:

t

(sec)

(V)

ON

₊ƪ_IPEAK

_(A)ƫ

LOAD

(4)

C

(A) * I

Farads

OUT(max)

V

OUT

For worst case calculations, the minimum value for t

capacitor selected. For a resistive load the maximum output capacitor can be estimated as follows:

should be used, which is based on the value of CT

ON

t

(sec)

ON

(5)

C

+

Farads

OUT(max)

ȡ

ȣ

_{(W) ȏn}ȧ

1

R

ȧ

LOAD

V

(V)

OUT

(A) R

Ȣ^1*

ꢀ

ǒ

Ǔ^ȧ

I

(W)

MAX

LOAD

Figure 6 and Figure 7 are oscilloscope photos of the UCC384–ADJ operating during an overcurrent condition.

Figure 6 shows operation of the circuit as the output current initially rises above the overcurrent threshold. This

is shown on a 1ms/div. scale. Figure 7 shows operation of the same circuit on a 25 ms/div. scale showing one

complete cycle of operation during an overcurrent condition.

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

UCC384–ADJ

OVERCURRENT CONDITION OPERATION

25 ms/div

1 ms/div

Figure 6

Figure 7

shutdown feature of the UCC384

The shutdown feature of the UCC384 allows the device to be placed in a low quiescent current mode. The

UCC384 is shut down by pulling the SD/CT pin more positive than –0.7 V with respect to GND. Figure 8 shows

how a shutdown circuit can be configured for the UCC384 using a standard transistor-transistor logic signal to

control it.

TTL SHUTDOWN CIRCUIT

+5 V

470 k

+5 V

LOGIC

INPUT

GND

(+)

0.015 F

µ

CT

4

R2

GND

VOUT

+

8

SD/CT

1

5

COUT

4.7 F

VOUTS

UCC384–ADJ

VOUT

VIN VIN VIN VIN

µ

+

CIN

1 F

C1 R1

VIN

µ

(–)

2

3

6

7

(–)

UDG–99032

Figure 8. TTL Controlled Shutdown Circuit for the UCC384

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

controlling the SD/CT pin

Forcing the SD/CT pin to any fixed voltage affects the operation of the circuit. As mentioned before, pulling the

SD/CT pin more positive than –0.7 V puts the circuit in a shutdown mode, limiting the quiescent current to less

than 45 µA. Pulling this pin more positive than 6 V with respect to GND damages the device.

Forcing the SD/CT pin to any fixed voltage between –0.7 V and –1.6 V with respect to GND enables the output.

However, in an overcurrent condition, the output does not pulse at a 2.5% duty cycle, but the output current is

still limited to the peak current limit. This circuit may be used where a fixed current limit is needed, where a 2.5%

duty cycle is undesirable. The UCC384 supplies a maximum current in this configuration as long as the

temperature of the device does not exceed the overtemperature shutdown. This is determined by the peak

current being supplied, the input and output voltages, and the type of heat sink being used. Thermal design

is discussed later on in this data sheet.

Forcing the SD/CT pin to a voltage level between approximately –1.6 V and –2.6 V with respect to GND is not

recommended as the output may or may not be enabled.

Forcing the SD/CT pin to a voltage level between approximately –2.6 V and –5 V with respect to GND turns the

output off completely. The output remains off as long as the voltage is applied. Pulling this pin more negative

than –5 V with respect to GND damages the device (see Table 1).

Table 1 SD/CT Voltage Levels

STATE

SD/CT

6 V to –0.7 V

Output disabled and device in low quiescent shutdown mode.

–0.7 V to –1.6 V Output enabled

–1.6 V to –2.6 V Output enabled or disabled depending on the previous state.

–2.6 V to –5 V

Output disabled

VIN TO VOUT DELAY TIME

DURING POWER-UP WITH CT = 0.22 µF

Figure 9

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

VIN to VOUT Delay

During power-up there is a delay between VIN and VOUT. The majority of this delay time is due to the charging

time of the CT capacitor. When VIN moves more negative than the UVLO of the device with respect to GND,

the CT capacitor begins to charge. A 17-µA current sink is used only during power up to charge the CT capacitor.

When the voltage on the SD/CT pin reaches approximately –1.6 V with respect to GND, the output turns on and

regulates. The larger the value of the CT capacitor, the greater the delay time between VIN and VOUT. Figure 9

shows the VIN to VOUT start-up delay, approximately 16 ms for a circuit with CT = 0.22 µF.

Shorter delay times can be achieved with a smaller CT capacitor. The problem with a smaller CT capacitor is

that with a very large load, the circuit may stay in overcurrent mode and never turn on. A circuit with a large

capacitive load needs a large CT capacitor to operate properly.

One way to shorten the delay from VIN to VOUT during powerup, is with the use of the quick start-up circuit

shown in Figure 10.

(+)

R2

R1

4

CT

0.22 F

µ

GND

+

8

SD/CT

VOUTS 1

COUT VOUT

4.7 F

µ

VIN

+

CIN

1 F

C1

R4

18 k

UCC384–ADJ

VOUT 5

C2

0.1 F

µ

(–)

Q1

VIN VIN VIN VIN

2N7000

R3

12 k

2

3

6

7

(–)

QUICK START CURRENT

UDG–99033

Figure 10. Quick Start-Up Circuit for UCC384

With the quick start-up circuit, the delay time between VIN and VOUT during start-up can be reduced

dramatically. Figure 11 shows that with the quick start-up circuit, the VIN to VOUT delay time has been reduced

to approximately 1 ms.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

VIN to VOUT Delay

VIN TO VOUT DELAY TIME

WITH QUICK START-UP CIRCUIT

WITH CT CAPACITOR REMOVED

Figure 11

Figure 12

operation of the quick start-up circuit

During normal start-up, the UCC384 does not turn on until the voltage on the SD/CT pin reaches approximately

–1.6 V with respect to ground. It takes a certain amount of time for the CT capacitor to charge to this point. For

a circuit that has a very large load, the CT capacitor needs to be large in order for the overcurrent timing to work

properly. A large value of capacitance on the SD/CT pin increases the VIN to VOUT delay time.

The quick start-up circuit uses Q1 to quickly pull the SD/CT pin in a negative direction during start-up, thus

decreasing the VIN-to-VOUT delay time. When VIN is applied to the circuit, Q1 turns on and starts to charge

the CT capacitor. The current pulled through R4 determines the rate at which CT is charged. R4 can be

calculated as follows:

V

(V) T seconds

IN

D

(6)

R4 +

ohms

1.6 CT (F)

t is the approximate VIN-to-VOUT delay time desired.

D

Q1 needs to be turned off after a fixed time to prevent the SD/CT pin from going too far negative with respect

to GND. If the SD/CT pin is allowed to go too far negative with respect to GND, the output turns off again or

possibly even damages the SD/CT pin. The maximum amount of time that Q1 should be allowed to be on is

referred to as t and can be calculated as follows:

M

2.6

1.6

(7)

t

+

t seconds

M

D

R3alongwithC2setthetimethatQ1isallowedtobeon. Sincet isthemaximumamountoftimethatQ1should

M

be allowed to stay on, an added safety margin may be to use 0.9 × t instead. This ensures that Q1 is turned

M

off in the proper amount of time. With a chosen value for C2, R3 can be calculated as follows:

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UCC284–5, UCC284–12, UCC284–ADJ, UCC384–5, UCC384–12, UCC384–ADJ

LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR

SLUS234D – JANUARY 2000 – REVISED FEBRUARY 2002

APPLICATION INFORMATION

operation of the quick start-up circuit (continued)

0.9 t seconds

M

(8)

R3 +

Ohms

V

(V)*1.6

IN

C2(F) ȏn

ǒ

1 *

Ǔ

V

(V)

IN

After the CT capacitor has charged up for a time equal to 0.9 × t , Q1 turns off and allows the SD/CT pin to

be pulled back to –1.5 V with respect to GND through a 50-kΩ resistor. At this point , the SD/CT pin can be used

M

by the UCC384 overcurrent timing control.

minimum V to V

delay time

OUT

IN

Although it may desirable to have as short a delay time as possible, a small portion of this delay time is fixed

by the UCC384 and cannot be shortened. This is shown in Figure 12, where the CT capacitor has been removed

from the circuit completely, giving a fixed VIN to VOUT delay of approximately 150µs for a circuit with VIN = –6 V

and VOUT = –5 V.

thermal design

The Packaging Information section of the Power Supply Control Products Data Book (TI Literature

No. SLUD003) contains reference material for the thermal ratings of various packages. The section also

includes an excellent article entitled Thermal Characteristics of Surface Mount Packages, which is the basis

for the following discussion.

ThermaldesignfortheUCC384includestwomodesofoperation, normalandpulsed. Innormalmode, thelinear

regulator and heat sink must dissipate power equal to the maximum forward voltage drop multiplied by the

maximum load current. Assuming a constant current load, the expected heat rise at the regulator’s junction can

be calculated as follows:

(9)

( )

qjc ) qca

t

+ P

RISE

DISS

Theta (θ) is the thermal resistance and P

is the power dissipated. The junction-to-case thermal resistance

DISS

(θjc) of the SOIC–8 DP package is 22°C/W. In order to prevent the regulator from going into thermal shutdown,

the case-to-ambient thermal resistance (θca) must keep the junction temperature below 150°C. If the UCC384

is mounted on a 5 square inch pad of 1-ounce copper, for example, the thermal resistance (θja) becomes

40–70°C/W. If a lower thermal resistance is required for the application, the device heat sinking needs to be

improved.

When the UCC384 is in a pulsed mode, due to an overcurrent condition, the maximum average power

dissipation is calculated as follows:

t

(seconds)

ON

₊ƪ_V

_(V)ƫ_I

(10)

P

(V) * V

IN

(A)

PEAK

ǒ

Ǔ

Watts

avg

OUT

40 t

(seconds)

ON

As seen in equation (10), the average power during a fault is reduced dramatically by the duty cycle, allowing

the heat sink to be sized for normal operation. Although the peak power in the regulator during the t period

ON

can be significant, the thermal mass of the package normally keeps the junction temperature from rising unless

the t period is increased to several milliseconds.

ON

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2005

PACKAGING INFORMATION

Orderable Device

UCC284DP-12

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

8

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC284DP-5

SOIC

D

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC284DP-5G4

UCC284DP-ADJ

UCC284DP-ADJG4

UCC284DPTR-5

UCC284DPTR-5G4

UCC284DPTR-ADJ

UCC284DPTR-ADJG4

UCC384DP-12

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC384DP-5

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC384DP-5G4

UCC384DP-ADJ

UCC384DP-ADJG4

UCC384DPTR-12

UCC384DPTR-5

UCC384DPTR-ADJ

UCC384DPTR-ADJG4

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Sep-2005

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	UCC284-5
厂家：	TEXAS INSTRUMENTS
描述：	LOW-DROPOUT 0.5-A NEGATIVE LINEAR REGULATOR 低压降0.5负线性稳压器稳压器
文件：	总17页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC284-5 [TI]

相关型号：

UCC284-ADJ

UCC284-EP

UCC284DP-12

UCC284DP-12G4

UCC284DP-12TR

UCC284DP-5

UCC284DP-5G4

UCC284DP-5TR

UCC284DP-ADJ

UCC284DP-ADJG4

UCC284DP-ADJTR

UCC284DPTR-12