UCC28502 [TI]
BiCMOS PFC/PWM Combination Controller; 的BiCMOS PFC / PWM组合控制器
| 型号： | UCC28502 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BiCMOS PFC/PWM Combination Controller |
| 文件： | 总8页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
PRELIMINARY
BiCMOS PFC/PWM Combination Controller
FEATURES
• Combines PFC and 2nd Stage Down
DESCRIPTION
The UCC18500 family provides all of the functions necessary for an ac-
tive power factor corrected preregulator and a second stage DC-to-DC
converter. The controller achieves near-unity power factor by shaping
the AC input line current waveform to correspond to the AC input line
voltage using average current mode control. The DC-to-DC converter
uses peak current mode control to perform the step down power con-
version.
Converter Function
• Controls Boost PWM to Near-unity Power
Factor
• Accurate Power Limiting
• Average Current Mode Control in PFC
Stage
The PFC stage is leading edge modulated while the second stage is
trailing edge synchronized to allow for minimum overlap between the
boost and PWM switches. This reduces ripple current in the bulk output
capacitor.
• Peak Current Mode Control in Second
Stage
• Programmable Oscillator
In order to operate with a three to one range of input line voltages, a
line feedforward (VFF) in used to keep input power constant with vary-
ing input voltage. Generation of VFF is done using IAC in conjunction
with an external single pole filter. This not only reduces external parts
count, but avoids the use of high voltage components offering a lower
cost solution. The multiplier then divides the line current by the square
• Leading Edge/Trailing Edge Modulation
for Reduced Output Ripple Using
SmartSync™
• Low Startup Supply Current
• Synchronized Second Stage Start-up,
with Programmable Soft-start
of VFF
.
(continued)
• Programmable Second Stage Shut-down
BLOCK DIAGRAM
ISENSE2
8
SS2
13
VCC
9
GND
6
VERR
7
7.5V
REFERENCE
SECOND STAGE
SOFT START
20 VREF
6.75V
UVLO2
1.5V
UVLO
16V/10
VCC
OVP/ENBL
4
ENABLE
–
+
I
LIMIT
10
GT2
R
R
S
1.5V
1.3V
8.0V
+
–
PFCOVP
Q
ZERO
VAOUT
1
3
PWM
CLK2
POWER
VOLTAGE
ERROR AMP
0.25V
–
+
VSENSE
–
+
X
VCC
MULT
CURRENT AMP
÷
–
+
–
X
Q
S
PWM
PWM
+
7.5V
12 GT1
2
VFF 19
OSC
LATCH
(V
)
FF
R
R
CLK1
CLK2
MIRROR
2:1
11 PWRGND
CLK1
CLK2
I
LIMIT
OSCILLATOR
IAC 18
14 PKLMT
–
+
MOUT 17
16
15
2
5
ISENSE1 CAOUT
RT
CT
UDG-98189
SLUS419 - AUGUST 1999
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
DESCRIPTION (cont.)
The UCC18500 PFC section incorporates a low offset ating range with selectable options, and 50% maximum
voltage amplifier with 7.5V reference, a highly linear mul- duty cycle.
tiplier capable of a wide current range, a high bandwidth,
The UCC38500 and UCC38502 have a wide PFC-UVLO
low offset current amplifier, with a novel noise attenuation
threshold (16.5V/10V) for bootstrap bias supply opera-
configuration, PWM comparator and latch and a high cur-
tion. The UCC38501 and UCC38503 are designed with a
rent output driver. Additional PFC features include
narrow UVLO range (10.5V/10V) more suitable for fixed
over-voltage protection, zero power detection to turn-off
bias operation. The UCC38500 and UCC38501 have a
the output when VAOUT is below 0.25V and peak current
narrow UVLO threshold for PWM stage (to allow opera-
tion down to 75% of nominal bulk voltage), while the
and power limiting.
The DC-to-DC section relies on an error signal generated UCC38502 and UCC38503 are configured for a much
on secondary-side and processes it by performing peak wider operation range for the PWM stage (down to 50%
current mode control. The DC-to-DC section also fea- of bulk nominal voltage).
tures current limiting, a controlled soft-start, preset oper-
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Gate Drive Current
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2A
50% Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
Input Voltage
DIL-20, SOIC-20 (TOP VIEW)
N, DW and J Packages
VAOUT
RT
1
2
3
4
5
6
7
8
9
20 VREF
19 VFF
I
SENSE1, ISENSE2 MOUT,VSENSE, OVP, ENBL, . . . . . . . . 11V
PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Input Current, RSET, IAC, PKLMT, ENA . . . . . . . . . . . . . . 10mA
Maximum Negative Voltage, GT1, GT2,
PKLMT, MOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
VSENSE
OVP/ENA
CT
18 IAC
17 MOUT
16 ISENSE1
15 CAOUT
14 PKLMT
13 SS2
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages. All voltages are
referenced to GND.
GND
VERR
ISENSE2
VCC
ORDERING INFORMATION
UCC 850
12 GT1
GT2 10
11 PWRGND
PACKAGE INFORMATION
PRODUCT OPTION
TEMPERATURE RANGE
PACKAGE
UVLO
16
UVLO2 HYSTERESIS
UCC18500
UCC18501
UCC18502
UCC18503
UCC28500
UCC28501
UCC28502
UCC28503
UCC38500
UCC38501
UCC38502
UCC38503
1.2
1.2
3.0
3.0
1.2
1.2
3.0
3.0
1.2
1.2
3.0
3.0
–55°C to +125°C
10.5
16
J-CDIP
N-PDIP
10.5
16
DW-SOIC
–40°C to +85°C
0°C to +70°C
10.5
16
N-PDIP
DW-SOIC
10.5
16
10.5
16
10.5
2
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications hold for TA=0°C to 70°C for the
UCC3850X, –40°C to +85°C for the UCC2850X, and –55°C to +125°C for the UCC1850X, TA = TJ. VCC = 12V, RT = 22k, CT =
330pF.
PARAMETER
Supply Current Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Supply Current, Off
VCC = 12V (VCC Turn-on Threshold –300mV)
VCC = 12V
150
4
300
6
A
Supply Current, On
mA
UVLO Section
VCC Turn-On Threshold (UCCX8500/502)
UVLO Hysteresis (UCCX8500/502)
Shunt Voltage (UCCX8500/502)
VCC Turn-On Threshold (UCCX8501/503)
UVLO Hysteresis (UCCX8501/503)
Voltage Amplifier Section
Input Voltage
15.4
5.4
16
6
16.6
6.2
V
V
V
V
V
IVCC = 10mA
17
17.5
10.8
0.6
10.2
0.4
10.5
0.5
TA = 0°C to 70°C
7.388 7.500 7.613
V
V
TA = –40°C to 85°C
TA = –55°C to125°C
7.369 7.500 7.631
7.313 7.500 7.687
V
VSENSE Bias Current
Open Loop Gain
50
80
nA
dB
V
VAOUT = 2V to 5V
ILOAD = –150 A
ILOAD = 150µA
VOUT High
5.4
5.5
5.6
VOUT Low
0.05
0.10
V
Over Voltage Protection and Enable Section
Over Voltage Reference
Hysteresis
7.8
400
1
8.0
500
1.5
8.2
600
2
V
mV
V
Enable Threshold
Current Amplifier Section
Input Offset Voltage
Input Bias Current
Input Offset Current
Open Loop Gain
VCM = 0V, VCAOUT = 3V
VCM = 0V, VCAOUT = 3V
VCM = 0V, VCAOUT = 3V
VCM = 0V, VCAOUT = 2V to 5V
VCM = 0V to 1.5V, VCAOUT = 3V
ILOAD = –120 A
–5
0
5
mV
nA
nA
dB
dB
V
–50
25
90
CMRR
80
VOUT High
6.3
0.2
2.5
VOUT Low
ILOAD = 1mA
V
Gain Bandwidth Product
Voltage Reference Section
Input Voltage
(Note 1)
MHz
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –55°C to 125°C
IREF = 1mA to 2mA
VCC = 12V to 16V
VREF = 0V
7.388 7.500 7.613
7.369 7.500 7.631
7.313 7.500 7.687
V
V
V
Load Regulation
Line Regulation
5
10
20
mV
mV
mA
10
Short Circuit Current
Oscillator Section
Initial Accuracy
–25
TA = 25°C
85
100
1
115
kHz
%
Voltage Stability
VCC = 10.8V to 15V
Line, Temp
Total Variation
80
120
5.5
kHz
V
Ramp Peak Voltage
Ramp Amplitude Voltage (peak to peak)
4.5
5
4
V
3
UCC18500/1/2/3
UCC28500/1/2/3
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications hold for TA=0°C to 70°C for the
UCC3850X, –40°C to +85°C for the UCC2850X, and –55°C to +125°C for the UCC1850X, TA = TJ. VCC = 12V, RT = 22k, CT =
330pF.
PARAMETER
Peak Current Limit Section
PKLMT Reference Voltage
PKLMT Propogation Delay
Multiplier Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
–15
0
15
mV
ns
300
High Line, Low Power
High Line, High Power
Low Line, Low Power
Low Line, High Power
IAC Limited
I
AC = 500 A, VFF = 4.7V, VAOUT = 1.25V
–6
–90
–19
–300
–300
1
A
A
IAC = 500 A, VFF = 4.7V, VAOUT = 5V
IAC = 150 A, VFF = 1.4V, VAOUT = 1.25V
IAC = 150 A, VFF = 1.4V, VAOUT = 5V
IAC = 150 A, VFF = 1.3V, VAOUT = 5V
IAC = 300 A, VFF = 2.8V, VAOUT = 2.5V
IAC = 150 A, VFF = 1.4V, VAOUT = 0.25V
IAC = 500 A, VFF = 4.7V, VAOUT = 0.25V
IAC = 500 A, VFF = 4.7V, VAOUT = 0.5V
IAC = 150 A, VFF = 1.4V, VAOUT = 5V
A
A
A
Gain Constant (K)
1/V
A
Zero Current
0
–2
–2
–3
0
A
µA
W
Power Limit
–420
0.25
Zero Power Section
Zero Power Comparator Threshold
PFC Gate Driver Section
GT1 Pull Up Resistance
Measured on VAOUT
0.10
0.40
V
I
OUT = –100mA
7
GT1 Pull Down Resistance
GT1 Output Rise Time
IOUT = 100mA
3
CLOAD = 1nF, RLOAD = 10
CLOAD = 1nF, RLOAD = 10
25
10
94
ns
ns
%
GT1 Output Fall Time
Maximum Duty Cycle
Second Stage UVLO (UVLO2)
PWM Turn-on Reference (UCCX8500/501)
Hysteresis (UCCX8500/501)
PWM Turn-on Reference (UCCX8502/503)
Hysteresis (UCCX8502/503)
Second Stage Soft Start Section
SS2 Charge Current
6.30
6.30
6.75
1.2
6.75
3
7.30
7.30
V
V
V
V
–7.5
3
–10
–12.5
300
10
µA
mV
mA
VERR
IVERR = 2mA, UVLO = Low
SS2 Discharge Current
ENA = High, UVLO = Low, SS2 = 2.5V
Second Stage Duty Cycle Clamp Section
Maximum Duty Cycle
44
50
%
V
Second Stage Pulse by Pulse Current Sense Section
Current Sense Comparator Threshold
Second Stage Over Current Limit Section
Peak Current Comparator Threshold
Input Bias Current
VERR = 2.5V, Measured on ISENSE2
.95
1.15
1.05
1.15
1.45
1.30
50
V
nA
Second Stage Gate Driver Section
GT2 Pull Up Resistance
IOUT = –200mA
7
3
GT2 Pull Down Resistance
IOUT = 100mA
GT2 Output Rise Time
CLOAD = 1nF, RLOAD = 10
CLOAD = 1nF, RLOAD = 10
25
25
ns
ns
GT2 Output Fall Time
Note 1: Guaranteed by design, not 100% tested in production.
4
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
PIN DESCRIPTIONS
CAOUT: (current amplifier output) This is the output of a
wide bandwidth op amp that senses line current and
commands the PFC pulse width modulator (PWM) to
VAOUT −1.0 • I
(
)
AC
IMO
=
2
K • VFF
force the correct current. This output can swing close to Connect current loop compensation components be-
GND, allowing the PWM to force zero duty cycle when tween MOUT and CAOUT.
necessary.
OVP/ENBL: (over-voltage/enable) A window comparator
CT: (Oscillator timing capacitor) A capacitor from CT to input which will disable the PFC output driver if the boost
GND will set the oscillator frequency according to:
output is 6.67% above nominal or will disable both the
PFC and second stage output drivers and reset SS2 if
pulled below 1.5V. This input is also used to determine
the active range of the second stage PWM.
0.725
f =
(
)
RT • CT
GND: (ground) All voltages measured with respect to
ground. VCC and VREF should be bypassed directly to
GND with a 0.1µF or larger ceramic capacitor. The timing
capacitor discharge current also returns to this pin, so
the lead from the oscillator timing capacitor to GND
should be as short and direct as possible.
PKLMT: (PFC peak current limit) The threshold for peak
limit is 0V. Use a resistor divider from the negative side of
the current sense resistor to VREF to level-shift this sig-
nal to a voltage corresponding to the desired overcurrent
threshold across the current sense resistor.
PWRGND: Ground for totem pole output drivers.
GT1: (gate drive) The output drive for the PFC stage is a
totem pole MOSFET gate driver on GT1. Use a series
gate resistor of at least 5 ohms to prevent interaction be-
tween the gate impedance and the GT1 output driver that
might cause the GT1 to overshoot excessively. Some
overshoot of the GT1 output is always expected when
driving a capacitive load.
RT: (oscillator charging current) A resistor from RT to
GND is used to program oscillator charging current. A re-
sistor between 10kΩ and 100kΩ is recommended.
SS2: (soft start for PWM) SS2 is at ground for either en-
able low or OVP/ENBL below the UVLO2 threshold
conditions. When enabled, SS2 will charge an external
capacitor with a current source. This voltage will be used
as the voltage error signal during start-up, enabling the
PWM duty cycle to increase slowly. In the event of a dis-
able command or a UVLO2 dropout, SS2 will quickly
discharge to disable the PWM.
GT2: (gate drive) Same as output GT1 for the second
stage output drive. Limited to 50% maximum duty cycle.
IAC: (input ac current) This input to the analog multiplier
is a current. The multiplier is tailored for very low distor-
tion from this current input (IAC) to MOUT, so this is the
only multiplier input which should be used for sensing in-
stantaneous line voltage. Recommended maximum IAC is
500µA.
VAOUT: (voltage amplifier output) This is the output of
the opamp that regulates output voltage. The voltage am-
plifier output is internally limited to approximately 5.5V to
prevent overshoot.
ISENSE1: (current sense) This is the non-inverting input
to the current amplifier. This input and the inverting input
MOUT remain functional down to and below GND.
VCC: (positive supply voltage) Connect to a stable
source of at least 20mA between 12V and 17V for nor-
mal operation. Bypass VCC directly to GND to absorb
supply current spikes required to charge external
MOSFET gate capacitances. To prevent inadequate Gate
Drive signals, the output devices will be inhibited unless
VCC exceeds the upper under-voltage lockout threshold
and remains above the lower threshold.
ISENSE2: (current sense) A resistor from the source of
the lower FET to ground generates the input signal for
the peak limit control of the second stage. The oscillator
ramp can also be summed into this pin, for slope com-
pensation.
MOUT: (multiplier output and current sense amplifier in-
verting input) The output of the analog multiplier and the
inverting input of the current amplifier are connected to-
gether at MOUT. As the multiplier output is a current, this
is a high impedance input so the amplifier can be config-
ured as a differential amplifier to reject ground noise.
Multiplier output current is given by:
VERR: Voltage amp error signal for the second stage.
The error signal is generated by an external amplifier
which drives this pin.
VFF: (RMS feed forward signal) VFF signal generated at
this pin by mirroring Iac into a single pole external filter.
5
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
PIN DESCRIPTIONS
VFFMAX
VREF: (voltage reference output) VREF is the output of
an accurate 7.5V voltage reference. This output is capa-
ble of delivering 10mA to peripheral circuitry and is inter-
nally short circuit current limited. VREF is disabled and
will remain at 0V when VCC is below the UVLO thresh-
old. Bypass VREF to GND with a 0.1µF or larger ceramic
capacitor for best stability.
RVFF
=
IACMAX
2
2 •
• 0.9
VSENSE: (voltage amplifier inverting input) This is nor-
mally connected to a compensation network and to the
boost converter output through a divider network.
APPLICATION INFORMATION
The UCC38500 is designed to incorporate all the control One of the main system challenges in designing systems
functions required for a power factor correction circuit with a PFC front end is coordinating the turn-on and
and a second stage dc-dc converter. The PFC function turn-off on the dc-dc converter. If the dc-dc converter is
is implemented as a full feature, average current mode allowed to turn on before the boost converter is opera-
controller Integrated Circuit for excellent performance. In tional, it must operate at a much-reduced voltage and
addition, the input voltage feedforward function is imple- therefore can represent a large current draw to the boost
mented in a simplified manner. Current from IAC is mir- converter. This start-up sequencing is handled internally
rored over to the VFF pin. By simply adding a resistor by the UCC38500. The UCC38500 monitors the output
and capacitor (to attenuate 120Hz ripple) a voltage is de- voltage of the PFC converter and holds the dc-dc con-
veloped which is proportional to line voltage. This elimi- verter off until the output is within 10% of its regulation
nates several components normally connected to the point. Once the trip point is reached the dc-dc section
line.
goes through a soft start sequence for a controlled, low
stress start-up. Similarly if the output voltage drops too
low (2 voltage options are available) the dc-dc converter
shuts down thereby preventing overstress of the con-
verter.
The UCC38500 uses leading edge modulation for the
PFC stage and trailing edge modulation for the dc-dc
stage. This reduces ripple current in the output capacitor
by reducing the overlap in conduction time of the PFC
and dc-dc switches. In addition to the reduced ripple cur- Design details of the PFC section can be found in several
rent, noise immunity is improved through the current er- references shown below.
ror amplifier implementation.
• UCC3817 data sheet
The UCC38500 is optimized to control a boost PFC
• High Power Factor Preregulator for Off-Line Power
stage operating in continuous conduction mode, followed
Supplies, SEM-800
by a dc-dc converter (typically a forward topology). It is
• Optimizing the Design of a High Power Factor
Switching Regulator, SEM-800
usual that the dc-dc converter is transformer isolated and
therefore its error amplifier will be located on the second-
ary side. The UCC38500 is configured without an inter-
nal error amplifier. The externally generated error signal
is fed into the VERR pin.
A design example for a 2 switch forward converter can be
found in:
• 250W Off-Line Forward Converter Design Review,
The UCC38500 can be configured for voltage mode or
current mode control of the second stage. The applica-
tion figure shows a typical current mode configuration.
For voltage mode control the ramp generated by CT is
simply fed into the ISENSE2 pin.
SEM-500
6
UCC18500/1/2/3
UCC28500/1/2/3
UCC38500/1/2/3
TYPICAL APPLICATION CIRCUIT
UDG-99138
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
7
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Copyright 1999, Texas Instruments Incorporated
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