UCC28704 [TI]
具有初级侧调节 (PSR) 功能的高效离线 CV 和 CC 反激控制器;
| 型号： | UCC28704 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有初级侧调节 (PSR) 功能的高效离线 CV 和 CC 反激控制器 反激控制 控制器 |
| 文件： | 总45页 (文件大小：1459K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
UCC28704 具有一次侧稳压 (PSR) 功能的高效离线 CV 和 CC 反激控制器
1 特性
3 说明
1
•
效率超过 DoE VI 级和 EU CoC V5 Tier-2 外部电
源标准
UCC28704 离线反激控制器是一款高度集成的 6 引脚
一次侧稳压脉宽调制 (PWM) 控制器，旨在设计符合全
球效率标准的高效 AC 转 DC 电源。此控制器启动时
的电流消耗超低，可使设计获得低于 30mW 的无负载
输入功率，并且节省待机模式能耗。凭借智能一次侧感
应和控制功能，无需使用光电耦合器或二次侧反馈电路
即可将输出电压和电流控制在 5% 的变化范围内。
•
一次侧稳压功能免除了对光电耦合器和二次侧反馈
组件的需求
•
•
•
•
•
•
•
•
•
与同步整流器兼容
无负载输入功率 <30mW
±5% 输出电压 (CV) 和电流 (CC) 调节
增强型动态负载响应
UCC28704 应用了增强型负载瞬态响应技术，有助于
最大限度减小输出电容，从而减小系统整体尺寸并降低
成本。此外，该控制器还免除了对环路补偿组件的需
求，为电源设计人员简化了设计及调试过程。转换器的
输出电压和电流会得到稳定性处理，以防出现可能损坏
负载或连接器的过载状况。同样，恒流输出欠压保护
(CCUV) 关断特性会监控输出欠压故障以防止由于软短
路问题而造成连接器过热或烧毁，从而大幅度提升系统
整体可靠性。NTC 接口引脚有助于为电路板或组件施
加过热保护。
具有自动重启响应的恒流输出欠压保护 (CCUV)
电缆补偿（5V 满载时为 300mV）
85kHz 最大开关频率
断续导通模式 (DCM) 谷值开关运行
针对金属氧化物半导体场效应晶体管 (MOSFET) 的
已钳位栅极驱动输出
•
•
负温度系数 (NTC) 电阻接口
电阻或外部高压 (HV) 耗尽型场效应晶体管 (FET)
启动
•
•
故障保护：输入欠压、输出过压、过流和短路保护
小外形尺寸晶体管 (SOT) 23-6 封装
UCC28704 在 2A 或更高输出电流下可轻松与 TI 的二
次侧同步整流器 (SR) 控制器搭配使用，从而提高转换
效率或实现更为紧凑的设计。
2 应用
•
•
•
•
手机和平板电脑的适配器和充电器
器件信息 (1)
消费类电子产品的 USB Type-C 交流适配器
低功率 AC 至 DC 开关模式电源 (SMPS)
工业用和医疗用开关模式电源 (SMPS)
部件号
封装
SOT23-6
封装尺寸（标称值）
UCC28704
2.90mm x 1.60mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
LP38690 的
5V/2A 适配器效率
VBLK
D1
VREG
COUT
T1
CB1
NP
NS
VOUT
wt[
+
88
85
RSTR
VAC
82
UCC28704
VDD
CoC V5 Tier-2 Average
D2
VAUX
2
6
79
CDD
NA
Q1
w{1
DRV
3
4
76
DOE Level VI Average
VS
CS
w[/
115 VAC (with SR)
w{2
73
1
NTC/SU
GND
5
230 VAC (with SR)
CoC 10% Load
w/{
wbÇ/
115 VAC (without SR)
70
67
230 VAC (without SR)
-t°
0
25
50
75 100
Load (%)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLUSCA8
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 24
8
9
Applications and Implementation ...................... 25
8.1 Application Information............................................ 25
8.2 Typical Application .................................................. 25
8.3 Do's and Don'ts....................................................... 33
Power Supply Recommendations...................... 34
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 35
11 器件和文档支持 ..................................................... 36
11.1 器件支持................................................................ 36
11.2 文档支持................................................................ 39
11.3 社区资源................................................................ 39
11.4 商标....................................................................... 39
11.5 静电放电警告......................................................... 39
11.6 Glossary................................................................ 39
12 机械、封装和可订购信息....................................... 39
7
4 修订历史记录
日期
修订版本
注释
2016 年2 月
A
首次发布。
2
Copyright © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
5 Pin Configuration and Functions
SOT23-6 Package
6-Pin DBV
Top View
NTC
/SU
VS
1
2
3
6
5
4
VDD
GND
CS
DRV
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
NTC/SU is a multi-function pin. First, it provides an interface to an external NTC
(negative temperature coefficient) resistor for remote temperature sensing. Pulling
this pin low shuts down PWM action. Additionally, when used with an external
depletion-mode FET and a low-voltage NPN transistor this pin provides high-voltage
start up control. A maximum 100-pF noise filter capacitance may be added to this
pin. The pin should be left floating if not used.
NTC/SU
1
I/O
VDD
DRV
2
3
P
VDD is the bias supply input pin to the device.
DRV is an output pin used to drive the gate of an external high voltage MOSFET
switching transistor.
O
CS input connects to a ground referenced current sense resistor in series with the
power switch. The resulting voltage is used to monitor and control the peak-primary
current. A series resistor is added to this pin to compensate the peak-primary current
levels as the AC mains input varies. A small capacitance, up to 30 pF, can be added
to this pin to filter the current sense signal.
CS
GND
VS
4
5
6
I
G
I
GND pin is both the reference pin for the controller and the low-side return for the
drive output. Special care should be taken to return all AC decoupling capacitors as
close as possible to this pin and avoid any common-mode signal trace length with
analog signal return paths.
VS is an input used to provide voltage and timing feedback to the controller. This pin
is connected to a voltage divider between an auxiliary winding and GND. The value
of the upper resistor of this divider is used to program the AC-mains run-and-stop
thresholds and line compensation at the CS pin. Avoid placing a filter capacitor on
this input which would interfere with accurate sensing of this waveform.
(1)
P = Power, G = Ground, I = Input, O = Output, I/O = Input/Output
Copyright © 2016, Texas Instruments Incorporated
3
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
V
VVDD
VS
Bias supply voltage
38
Voltage range
–0.75
–0.5
–0.5
7
V
CS, NTC
VDRV
IDRV
IDRV
IDRV
IVS
Voltage range
5
Self-limiting
50
V
Gate-drive voltage at DRV
V
DRV continuous sink current
mA
mA
mA
mA
°C
°C
°C
DRV peak sourcing current, VDRV = 10 V to 0 V
DRV peak sink current, VDRV = 0 V to 10 V
VS, peak, 1% duty-cycle, when detecting line voltage
Operating junction temperature range
Storage temperature
Self-limiting
Self-limiting
1.2
TJ
–55
–65
150
TSTG
TLEAD
150
Lead temperature 0.6 mm from case for 10 seconds
260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM) ESD stress voltage(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
35
UNIT
VDD
CDD
IVS
Bias supply operating voltage
8.5
V
VDD bypass capacitor
0.047
no limit
1.0
µF
mA
°C
VS pin sourcing current when detecting line voltage
Operating junction temperature
TJ
–40
125
4
Copyright © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
6.4 Thermal Information
UCC28704
THERMAL METRIC
DBV
6 PINS
150
55
UNIT
(1)
θJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
(2)
θJCtop
θJB
Junction-to-case (top) thermal resistance
(3)
Junction-to-board thermal resistance
60
(4)
ψJT
ψJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3
(5)
55
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
6.5 Electrical Characteristics
Over operating free-air temperature range, VVDD = 25 V, RNTC = open, –40°C ≤ TA ≤ 125°C, TJ = TA (unless otherwise noted)
PARAMETER
BIAS SUPPLY INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IRUN
Supply current, run
Supply current, wait
Supply current, start
Supply current, fault
IDRV = 0, run state
1.65
40
2.3
70
2.65
100
2.5
mA
µA
IWAIT
ISTART
IFAULT
IDRV = 0, VVDD = 20 V, wait state
IDRV = 0, VVDD = 17 V, start state
IDRV = 0, fault state
1.5
2.2
µA
1.7
2.8
mA
UNDER-VOLTAGE LOCKOUT
VVDD(on)
VVDD(off)
VS INPUT
VVSR
VDD turn-on threshold
VDD turn-off threshold
VVDD low to high
VVDD high to low
17.5
7.3
21
23
V
V
7.7
8.15
(1)
Regulating level
Measured at no-load condition, TJ =
25°C
4.02
4.06
4.1
V
VVSNC
IVSB
Negative clamp level
Input bias current
IVS = –300 µA
VVS = 4 V
190
250
0
325
mV
µA
–0.25
0.25
CS INPUT
VCST(max)
VCST(min)
KAM
(2)
Max CS threshold voltage
Min CS threshold voltage
AM control ratio
VVS = 3.70 V
720
170
3.55
345
750
187.5
4
784
210
4.4
mV
mV
V/V
mV
(2)
VVS = 4.35 V
VCST(max) / VCST(min)
VCCR
Constant-current regulating level
Line compensating current
356
369
KLC
ratio, IVSLS
(current out of CS pin)
/
IVSLS = –300 µA
23
25
29
A/A
ns
TCSLEB
Leading-edge blanking time
DRV output duration, VCS = 1 V
170
255
340
(1) The regulation level and OV threshold at VS decrease with increasing temperature by 1 mV/℃. This compensation over temperature is
included to reduce the variances in power supply output regulation over-voltage detection with respect to the external output rectifier.
(2) These threshold voltages represent average levels. This device automatically varies the current sense threshold to improve EMI
performance.
Copyright © 2016, Texas Instruments Incorporated
5
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
Electrical Characteristics (continued)
Over operating free-air temperature range, VVDD = 25 V, RNTC = open, –40°C ≤ TA ≤ 125°C, TJ = TA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRV
IDRS
DRV source current
VDRV = 5 V, VVDD = 9 V
25
32
6.5
38
12
mA
Ω
RDRVLS
VDRCL
RDRVSS
TIMING
fSW(max)
fSW(min)
tZTO
DRV low-side drive resistance
DRV clamp voltage
IDRV = 10 mA
VVDD = 35 V
9.5
10.6
205
13
V
DRV pull-down in start state
165
250
kΩ
(3)
Maximum switching frequency
Minimum switching frequency
Zero-crossing timeout delay
VVS = 3.7 V
VVS = 4.6 V
78
0.88
1.7
85
1.03
2.39
94
1.18
3
kHz
kHz
µs
tCCUV_BLAN Blanking delay time before CCUV
VVS step from 3.5 V to 2.4 V to DRV
stop switching
90
120
150
ms
shutdown
K
PROTECTION
KOVP
Over-voltage threshold ratio to VVSR VOVP/VVSR
1.13
2.41
1.35
190
70
1.15
2.48
1.51
220
80
1.18
2.55
1.6
V/V
V
VCCUV
VOCP
CCUV VO = 3.0 V
TJ = 25℃, auto restart after fault
At CS input
Over-current threshold
VS line-sense run current
VS line-sense stop current
V
IVSL(run)
IVSL(stop)
KVSL
Current out of VS pin – increasing
Current out of VS pin – decreasing
265
100
µA
µA
VS line-sense ratio IVSL(run)
IVSL(stop)
/
2.55
2.8
2.95
260
A/A
°C
(4)
TJ(stop)
Thermal shut-down temperature
Internal junction temperature
150
CABLE COMPENSATION
VCVS(max)
Maximum compensation at VS
Change in VS regulating level at full-
load
180
220
mV
NTC INPUT
VNTCTH
NTC shut-down threshold
VDD UVLO cycle when below this
threshold
0.9
90
0.95
100
1
V
INTC
NTC pull-up current, out of pin
VNTC = 1.1 V
120
µA
(3) These frequency limits represent average levels. This device automatically varies the switching frequency to improve EMI performance.
(4) Not tested in production.
6
版权 © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
6.6 Typical Characteristics
VDD = 25 V, unless otherwise noted.
5x101
1x101
1x105
1x104
1x103
1x102
1x101
1x100
1x10-1
Run State
IRUN, VDD = 25V
IWAIT, VDD = 20V
1x100
Wait State
1x10-1
1x10-2
éVDD Turn-Off
åVDD Turn-On
1x10-3
1x10-4
ISTART, VDD = 17V
Start State
1x10-5
1x10-6
0
5
10
15
20
25
30
35
40
-50
-25
0
25
50
75
100
125
150
VDD - Bias Supply Voltage (V)
TJ - Temperature (èC)
D001
D002
图 1. Bias Supply Current vs. Bias Supply Voltage
图 2. Bias Supply Current vs. Temperature
300
275
250
225
200
175
150
125
100
75
4.12
4.10
4.08
4.05
4.03
4.00
3.98
3.95
IVSL, Run
IVSL, Stop
50
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature (èC)
TJ - Temperature (èC)
D003
D004
图 3. VS Regulation Voltage vs. Temperature
图 4. Line-Sense Current vs. Temperature
365
360
355
350
345
192.9
192.7
192.5
192.3
192.1
191.9
191.7
191.5
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature (èC)
TJ - Temperature (èC)
D006
D005
图 6. Constant-Current Regulation Level vs. Temperature
图 5. Minimum CS Threshold Voltage vs. Temperature
版权 © 2016, Texas Instruments Incorporated
7
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
Typical Characteristics (接下页)
VDD = 25 V, unless otherwise noted.
1.05
33.5
33.0
32.5
32.0
31.5
31.0
30.5
30.0
1.04
1.03
1.02
1.01
1.00
0.99
0.98
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature (èC)
TJ - Temperature (èC)
D007
D008
图 7. Minimum Switching Frequency vs. Temperature
图 8. DRV Source Current vs. Temperature
108
107
106
105
104
103
0.952
0.951
0.95
0.949
0.948
0.947
0.946
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
TJ - Temperature (èC)
TJ - Temperature (èC)
D010
D009
图 10. NTC Pullup Current vs. Temperature
图 9. NTC Shutdown Threshold Voltage vs. Temperature
2.6
2.55
2.5
2.45
2.4
2.35
-50
-25
0
25
50
75
100
125
150
TJ - Temperature (èC)
D011
图 11. Constant-Current Under-Voltage Threshold vs. Temperature
8
版权 © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
7 Detailed Description
7.1 Overview
The UCC28704 flyback power supply controller provides accurate constant voltage and constant current
regulation with primary-side feedback control. It also eliminates the need for opto-coupler feedback circuits. The
controller optimizes the modulation scheme and the device's power management to boost power conversion
efficiency, lower power dissipation at no-load and light load. Frequency dithering reduces the EMI peak energy at
the fundamental switching frequency and harmonics. Features include fixed cable compensation and constant
current output under-voltage shutdown, or CCUV, to protect USB terminals from getting over-heated or burn-out
condition during soft-short circuit fault.
The controller operates in discontinuous conduction mode with valley switching to minimize switching losses. A
combination of frequency modulation and primary peak current modulation to provide high power conversion
efficiency across the load range. Accurate voltage and constant current regulation, fast dynamic response, and
fault protection are achieved with primary-side control. A complete charger solution can be realized with a
straightforward design process, low cost and low component count.
In UCC28704, as compared to UCC28700/1/2/3, features such as constant current under voltage protection and
enhanced load transient schemes have been added. Also, in UCC28704, the demagnetizing ratio has been
extended to 0.475 along with an increased AM ratio of 4:1. The maximum frequency of the controller is set at 85
kHz and the AM region switching frequency is optimally set at 25 kHz to have better trade-offs between no-load
standby power consumption and load transient response. UCC28704 also incorporates schemes to have better
noise rejection at the output voltage sense (VS pin) allowing for improved output voltage ripple reduction.
7.2 Functional Block Diagram
VDD
INTC
UVLO
21 V/7.7 V
VDD
GND
OC FAULT
Line FAULT
2
5
Power and Fault
Managment
CCUV FAULT
OV FAULT
VNTCTH
VSS /1.15
4.06 V
OTP FAULT
NTC/SU
1
Minimum fSW
Bias
VSS /1.10
4.06 V
1 kHz
4 kHz
S
Q
VDD
R
Q
4.06 V + VCVS
VSS
30 mA
+
VCL
E/A
Control Law
6
Sampler
VS
CCUV FAULT
3
200 kW
DRV
120 ms
Delay
10 V
VCST
1/fSW
2.48 V
Zero Crossing
S
R
Q
Q
Detect
VCVS
CS
4
Secondary
Timing Detect
Current Regulation and
Cable compensation
VCST
LEB
IVSLS
IVSLS
Line Sense
IVSLS / KLC
Line
Fault
OC
Fault
10 kW
1.5 V
2.2 V / 0.8 V
版权 © 2016, Texas Instruments Incorporated
9
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
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7.3 Feature Description
7.3.1 Detailed Pin Description
7.3.1.1 VDD (Device Bias Voltage Supply)
The VDD pin is typically powered from a rectified auxiliary transformer winding, the same winding that is used to
capture the output voltage level. A bypass capacitor, with minimum value 0.047 μF, on the VDD pin is used for
initially biasing the device to start-up along with a resistive or active source of start-up charging current. UVLO
start / stop levels of 21 V / 7.7 V accommodate lower values of VDD capacitance that in turns keeps the start-up
current low, which for resistive start-up has an impact on both stand-by power and power-on delay. A high, 35-V,
maximum operating level on VDD alleviates concerns with leakage energy charging of VDD and gives added
flexibility to when varying power supply output voltage must be supported.
7.3.1.2 GND (Ground)
This is an external return pin, and provides the reference point for both external signal and the gate drive of the
device. The VDD bypass capacitor should be placed close to this pin. Critical component GND connections from
the VS, CS and NTC pins should have dedicated and short paths to this pin.
7.3.1.3 VS (Voltage-Sense)
The VS pin is connected to a resistor divider from the auxiliary winding to ground. The output-voltage feedback
information is sampled at the end of the transformer secondary current demagnetization time to provide an
accurate representation of the output voltage. Timing information to achieve valley-switching and to control the
duty cycle of the secondary transformer current is determined by the waveform on the VS pin. The VS input is a
critical signal and will generally be with relatively high impedance. To avoid unpredictable behavior avoid placing
a filter capacitor on this pin and keep the total PCB area tied to VS at a minimum.
The VS pin also senses the bulk capacitor input voltage to provide for ac-input run and stop thresholds, and to
compensate the current-sense threshold across the AC-input range. This information is sensed by monitoring the
current pulled out of the VS pin during the MOSFET on-time. During this time the voltage on the VS pin is
clamped to about 250mV below GND. As a result, the current out of the pin is determined by the upper VS
divider resistor, the auxiliary to primary turns-ratio and the bulk input voltage level. For the AC-input run/stop
function, the run threshold on VS is IVSL(run) (typical 220 µA) and the stop threshold is IVSL(stop) (typical 80 µA).
The values for the auxiliary voltage divider upper-resistor RS1 and lower-resistor RS2 can be determined by the
equations below.
2 ì V
VBULK(run)
IN(run)
RS1
=
ö
NPA ìIVSL(run) NPA ìIVSL(run)
where
•
•
•
•
NPA is the transformer primary-to-auxiliary turns ratio,
VIN(run) is the AC rms voltage to enable turn-on of the flyback converter (run),
VBULK(run) is the DC bulk voltage to enable turn-on of the flyback converter (run),
IVSL(run) is the run-threshold for the current pulled out of the VS pin during the primary MOSFET on-time. (see
the Electrical Characteristics table).
(1)
RS1 ì VVSR
NAS ì(VOCV + VF) - VVSR
RS2
=
where
•
•
•
•
•
VOCV is the converter regulated output voltage,
VF is the output rectifier forward voltage drop at near-zero current,
NAS is the transformer auxiliary to secondary turns ratio,
RS1 is the VS divider high-side resistance,
VVSR is the CV regulating level at the VS input (see the Electrical Characteristics table).
(2)
This pin is also used to sense the output constant current under voltage (CCUV) level, used to shut down the
converter in the case of a soft-short circuit at its output. Refer to Constant Current Under-Voltage Protection for
further information.
10
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Feature Description (接下页)
7.3.1.4 DRV (Gate Drive)
The DRV pin is connected to the MOSFET gate pin, usually through a series resistor. The DRV provides a gate
drive signal which is clamped to 10.5-V internally. During turn-on the driver applies a typical 30-mA current
source out of the DRV pin. When the DRV voltage rises to above 9 V the output current is reduced to about 100
µA. This current brings the DRV voltage to the 10.5-V clamp level, or to VDD, whichever is less. The 30-mA
current provides adequate turn-on speed while automatically limiting noise generated at turn-on by the MOSFET
drain dv/dt and by the leading edge turn-on current spike. The gate drive turn-off current is internally limited to
about 400 mA when DRV is above about 4 V. At lower DRV voltages the current will reduce, eventually being
limited by the low-side on resistance, RDS(on). The drain turn-on and turn-off dv/dt can be further impacted by
adding external resistor in series with DRV pin. The drain current resonances can be damped with a small series
gate resistor, generally less than a 1 Ω.
7.3.1.5 CS (Current Sense)
The current sense pin is connected through a series resistor (RLC) to the current-sense resistor (RCS). The
controller varies the internal current sense threshold between 0.188 V and 0.75 V, setting a corresponding
control range for the peak-primary winding current to a 4-to-1 range. The series resistor RLC provides an input
voltage feed-forward function. The voltage drop across this resistor reduces primary-side peak current as the line
voltage increases, compensating for the increased di/dt and delays in the MOSFET turn-off. There is an internal
leading-edge blanking time of 255 ns to eliminate sensitivity to the MOSFET turn-on leading edge current spike.
If additional blanking time is needed, a small bypass capacitor, up to 30 pF, can be placed on between CS pin
and GND pin. The value of RCS is determined by the target output current in constant current (CC) regulation.
The values of RCS and RLC can be determined by the equations below. The term ηXFMR is intended to account for
the energy stored in the transformer but not delivered to the secondary. This includes transformer core and
copper losses, bias power, and primary leakage inductance losses.
Example: With a transformer core and copper losses of 3%, leakage inductance caused power losses 2%, and
bias power to output power ratio of 0.5%. The transformer power transfer efficiency is estimated as ηXFMR
=
100% - 3% - 2% - 0.5% = 94.5%
VCCR ìNPS
2 ìIOCC
RCS
=
ì hXFMR
where
•
•
VCCR is a current regulation constant (see the Electrical Characteristics table),
NPS is the transformer primary-to-secondary turns ratio (a typical turns-ratio of 12 to 15 is recommended for 5-
V output),
•
•
IOCC is the target output current in constant-current regulation,
ηXFMR is the transformer efficiency.
(3)
KLC ì RS1 ìRCS ì(tD + tGATE_ OFF)ìNPA
RLC
=
LP
where
•
•
•
•
•
•
•
RS1 is the VS pin high-side resistor value,
RCS is the current-sense resistor value,
tD is the current-sense delay (typical 50 ns) plus MOSFET turn-off delay,
tGATE_OFF is the primary-side main MOSFET turn-off time,
NPA is the transformer primary-to-auxiliary turns-ratio,
LP is the transformer primary inductance,
KLC is a current-scaling constant (see the Electrical Characteristics table).
(4)
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Feature Description (接下页)
7.3.1.6 NTC/SU (NTC Thermistor Shutdown and External Start Up Control)
The UCC28704 uses an external NTC resistor tied to the NTC/SU pin to program a thermal shutdown
temperature for the power supply. The NTC/SU shutdown threshold is 0.95 V with an internal 105-µA current
source which results in a 9.05-kΩ thermistor shutdown threshold. A small capacitor with value not greater than
100 pF can be used on this pin for any noise reduction purposes. The capacitor with its value greater than 100
pF can cause a false over-temperature protection response. The NTC/SU pin should be left floating if not used.
The NTC/SU pin can be used to control an external depletion-mode FET to enable active high-voltage start up,
Refer to Initial Power-On with A Depletion-Mode FET for more detail.
7.3.2 Primary-Side Regulation (PSR)
图 12 illustrates a simplified flyback convertor with the main voltage regulation blocks of the device shown. The
power train operation is the same as any DCM flyback circuit but accurate output voltage and current sensing is
the key to primary-side control.
+ VF -
IS
Timing
VCL
Bulk Voltage -VBLK
Primary Winding
(VOUT + VF + ISRS) x NA / NS
COUT
RLOAD
Secondary
Winding
VOUT
RS1
Aux
Winding
Control
Law
Q1
Discriminator and
Sampler
VS
RS2
D5
DRV
-
Minimum
Period
And Peak
Primary
Current
CS
Zero Crossings
RCS
图 12. Simplified Flyback Convertor
(with the Main Voltage Regulation Blocks)
In primary-side control, the output voltage is sensed on the auxiliary winding during the transfer of transformer
energy to the secondary. As shown in 图 13 during this time, the auxiliary winding voltage has a down slope
representing a decreasing total rectifier forward voltage drop VF and resistance voltage drop (ISRS) as the
secondary current decreases to zero. To achieve an accurate representation of the secondary output voltage on
the auxiliary winding, the discriminator reliably blocks the leakage inductance reset and ringing, continuously
samples the auxiliary voltage during the down slope after the ringing is diminished, and captures the error signal
at the time the secondary winding reaches zero current. The internal reference on VS is 4.06 V; the resistor
divider is selected as outlined in the VS pin description.
VS Sample
(VOUT + VF + ISRS) NA / NS
0 V
- (VBLK) NA / NP
图 13. Auxiliary Winding Voltage
12
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Feature Description (接下页)
The UCC28704 VS signal sampler includes signal discrimination methods to ensure an accurate sample of the
output voltage from the auxiliary winding. There are however critical details of the auxiliary winding signal to
ensure reliable operation, specifically the reset time of the leakage inductance and the duration of any
subsequent leakage inductance ring. Refer to 图 14 for a detailed illustration of waveform criteria to ensure a
reliable sample on the VS pin. The first detail to examine is the duration of the leakage inductance reset
pedestal, TLK_RESET in 图 14. Since this can mimic the waveform of the secondary current decay, followed by a
sharp downslope, it is important to keep the leakage reset time less than 750 ns for IPRI minimum, and less than
3.0 µs for IPRI maximum. The second detail is the amplitude of ringing on the VAUX waveform following tLK_RESET
.
The peak-to-peak voltage at the VS pin should be less than approximately 250 mVp-p at least 250 ns before the
end of the demagnetization time, tDMAG. If there is a concern with excessive ringing, it usually occurs during light
or no load conditions, when tDMAG is at the minimum, tDMAG(min). The tolerable ripple on VS is scaled up to the
auxiliary winding voltage by RS1 and RS2, and is equal to 250 mV × (RS1+RS2) / RS2. The snubber designs can be
designed to allow the ripple voltage to meeting these requirements.
As mentioned in Device Functional Modes, when IPP < IPP(max), the device operation enters a “Wait” state during
each switching cycle of its non-switching portion as shown in 图 14. In the Wait state, the device bias current
changes to IWAIT (typical 70 µA) from IRUN (typical 2.3 mA), reducing its bias power to help boost efficiency at light
load and to reduce standby load power.
tLK_RESET
Entering Wait State
IPP < IPP(max)
VS ring p-p
(scaled)
RS2/(RS1+RS2
0 V
)
tDM_BLANK
tDMAG
tSW
图 14. Auxiliary Waveform Details
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Feature Description (接下页)
7.3.3 Primary-Side Constant Voltage (CV) Regulation
During voltage regulation (CV mode), the controller operates in frequency modulation mode and peak current
amplitude modulation mode as illustrated in 图 15 below. The UCC28704 incorporates internal voltage-loop
compensation circuits so that external compensation is not necessary, provided that the value of COUT is high
enough. The following equation determines a minimum value of COUT necessary to maintain a phase margin of
about 40 degrees over the full-load range,
IOCC
COUT í 100 ì
VOCV ì fMAX
(5)
The internal operating frequency limits of the device are fSW(max) and fSW(min), typically 85 kHz and 1 kHz,
respectively. The choice of transformer primary inductance and primary-peak current sets the maximum
operating frequency of the converter, which must be equal to or lower than fSW(max). Conversely, the choice of
maximum target operating frequency and primary-peak current determines the transformer primary-inductance
value. The actual minimum switching frequency for any particular converter depends on several factors, including
minimum loading level, leakage inductance losses, switch-node capacitance losses, other switching and
conduction losses, and bias-supply requirements. In any case, the minimum steady-state frequency of the
converter must always exceed fSW(min) or the output voltage may rise to the over-voltage protection level (OVP)
and the controller responds as described in Fault Protection.
To achieve a regulated output voltage in the CV mode operation, energy balance has to be maintained. As the
UCC28704 has a minimum switching frequency typical 1 kHz, together with the energy per switching cycle
determined by converter parameters, such as the transformer primary inductance Lp and the selected RCS
resistor, the converter has a minimum input power. A proper pre-load needs to be selected to ensure that this
minimum energy is balanced during the no-load condition. The selection of the line compensation resistor value
(RLC) connected to the CS pin can impact the energy per switching cycle based on low-line and high-line
conditions. Typical Application section provides a design example to show how to implement these
considerations.
In the CV mode operation, the cable compensation is in effect. The cable compensation is to adjust the output
voltage at board-end to be higher than the no-load setup point, noted as VOCV, then to compensate the voltage
drop due to the cable resistance through which the load current IO is flowing. The UCC28704 cable
compensation is fixed at 6% of VOCV at full load, and the board-end output voltage is described by 公式 6:
IO
VOUT = VOCV ì(1+ 0.06 ì
)
IOCC
(6)
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Feature Description (接下页)
Due to the cable compensation, the output voltage at board-end is seen higher than VOCV with a positive slope
when load current IO> 0. The output voltage at the cable's end can be flat, upturned, or downturned, depending
on the cable total resistance in use. Primary-Side Constant Current (CC) Regulation has more descriptions on
the cable compensation.
fSW
Control Law Profile in Constant Voltage (CV) Mode
IPP
IPP(max)
85 kHz
IPP
fSW
Region 2
FM
Region 1
25 kHz
1kHz
IPP(max)/4
AM
FM
Region 3
Region 4
4.85 V
1.3 V
2.2 V
3.0 V
Control Voltage, E/A Output - VCL
图 15. Frequency and Amplitude Modulation Modes
(during CV mode)
In CV mode operation, the control consists of four regions, namely, region 1 through 4. The device internal error
op-amp output VCL sets a particular region operation. Refer to 图 12 for VCL. The steady-state control-law
voltage, VCL, ranges between 1.3 V to 4.85 V. Heavy load operation is usually in region 4 where frequency
modulation to output regulation is used and primary-peak current is controlled at its maximum. Region 3 is
usually for medium-load range typically from 10% load and above. In this region switching frequency is fixed at
nominal 25 kHz along with primary-peak current varying from 25% to 100% of its maximum. A low operating
frequency range (region 2) is for lighter loads to achieve stable regulation at low frequencies. In region 2, peak-
primary current is always maintained at IPP(max)/4 in the lower frequency level. Transitions between levels are
automatically accomplished by the controller depending on the internal control-law voltage, VCL. During a load
transient condition when VCL > 4.85 V, the device operates in constant current mode. When load is in step-down
transient demanding frequency lower than 4 kHz, first, the device stays at 4 kHz for up to 500 ms, or the output
voltage reaches about 10% over the VOCV within 500 ms, then the device adjusts the switching frequency to be
lower than 4 kHz as needed. More details can be found in Load Transient Response.
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Feature Description (接下页)
7.3.4 Primary-Side Constant Current (CC) Regulation
Timing information at the VS pin and current information at the CS pin allow accurate regulation of the secondary
average current. The control law dictates that as power is increased in CV regulation and approaching CC
regulation the primary-peak current is at IPP(max). Referring to 图 16 below, the primary peak current (IPP), turns-
ratio (NS/NP), secondary demagnetization time (tDMAG), and switching period (tSW) determine the secondary
average output current. Ignoring leakage inductance effects, the average output current is given by 公式 7. By
regulating the secondary rectifier conduction duty cycle, the output average current is constant for given IPP and
transformer turns-ratio. When the load increases, the secondary-side rectifier conduction duty cycle keep
increasing. Once it reaches preset value of 0.475, the converter switching frequency is then reduced to maintain
0.475 secondary-side duty cycle. Therefore, the output current is kept constant. Because the current is kept
constant, the increasing load results in lower output voltage. Converter can shut down in this condition if the
output voltage drops below CCUV protection level, or UCC28704 VDD drops below its UVLO turn-off threshold.
i
IPP
ISP x NS/NP
t
tON
tDMAG
tSW
图 16. Transformer Currents
IPP NP tDMAG
IOUT
=
ì
ì
2
NS
tSW
(7)
As shown in 图 17 below, CV mode operation is from IO = 0 to IOCC; at IO = IOCC, the operation enters CC mode
and VO starts to drop as the load resistance becomes further lower while IO is maintained at IOCC until Vo reaches
the CCUV threshold. Details of the CCUV operation are given in Constant Current Under-Voltage Protection. 图
17 shows the output at board-end and at cable-end. The cable compensation nominally compensates 300 mV
for a 5V-output at the IOCC level.
Vo (Board-End) =
VOCV x (1+ 0.06 x IO/IOCC
)
VOCV
VO_CCUV at
Board-End
Vo at Cable-End
Fixed Cable Compensation
VO_CCUV at
Cable-End
0
IOCC
Output Current IO
图 17. Typical Target Output V-I Characteristic
16
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Feature Description (接下页)
7.3.5 Valley-Switching and Valley-Skipping
The UCC28704 utilizes valley switching to reduce switching losses in the MOSFET, reduce induced-EMI, and
minimize the turn-on current spike at the sense resistor. The controller operates in valley-switching in all load
conditions unless the VDS ringing diminished.
Referring to 图 18 below, the UCC28704 operates in a valley-skipping mode in most load conditions to maintain
an accurate voltage or current regulation point and still switch on the lowest available VDS voltage.
VDS
0 V
VDRV
t
0 V
图 18. Valley-Skipping Mode
The UCC28704 forces a controlled minimum switching period corresponding to the power supply operating
frequency. In each switching cycle, after the minimum period is expired, the UCC28704 looks for the next
resonant valley on the auxiliary winding. The controller initiates a new power cycle at this valley point which
corresponds to a reduced voltage level on the power MOSFET. If at the point in time when the minimum period
expires ringing on the transformer winding has decayed such that no further resonant valleys can be detected a
new power cycle is initiated following a fixed time, tZTO
.
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Feature Description (接下页)
7.3.6 Start-Up Operation
Upon application of input voltage to the converter, the start up resistance connected to VDD from the bulk
capacitor voltage (VBULK) charges the VDD capacitor. During charging of the VDD capacitor, the device supply
current is less than 1.5 µA. When VDD reaches the 21-V UVLO turn-on threshold, the controller is enabled and
the converter starts switching. The peak-primary currents with initial three cycles are limited to IPP(min). This allows
sensing any initial input or output faults with minimal power delivery. When confirmed that the input voltage is
above the programmed converter turn-on voltage and with no faults detected, the start-up process proceeds and
normal power conversion follows. The converter remains in discontinuous conduction mode operation during
charging of the output capacitor(s), maintaining a constant output current until the output voltage is in regulation.
Initial power-on to the UCC28704 device is achieved by one of the two approaches that are described in Initial
Power-On with a Start-Up Resistor and Initial Power-On with A Depletion-Mode FET.
7.3.6.1 Initial Power-On with a Start-Up Resistor
A common used initial power-on approach for UCC28704 is to use a start-up resistor, RSTR, to tie VDD to VBLK
,
as show in 图 19. With this approach, the VDD pin is connected to a bypass capacitor to ground and a start-up
resistance to the input bulk capacitor (+) terminal. The VDD turn-on UVLO threshold is 21 V (VVDD(on))and turn-off
UVLO threshold is 7.7 V (VVDD(off)), with an available operating range up to 35 V. The USB charging practice
requires the output current to operate in constant-current mode from 5 V to typical about 3 V; this is easily
achieved with a nominal VDD of approximately 15 V. The additional VDD headroom up to 35 V allows for VDD to
rise due to the leakage energy delivered to the VDD capacitor in high-load conditions. Also, the wide VDD range
provides the advantage of selecting a relatively small VDD capacitor and high-value start-up resistance to
minimize no-load stand-by power loss in the start-up resistor.
The RSTR value has effect to power-on delay time and no-load standby power losses. Both are usually part of the
design specifications. Increase RSTR reduces standby power losses while increases power-on delay time. A
typical range of RSTR is from 10 MΩ to 15 MΩ as initial design start point for off-line AC-to-DC adapters where
power-on delay time usually requires less than two seconds. Due to the limited voltage rating, RSTR is normally
implemented by two or three resistors in series.
VBLK
D1
VREG
COUT
T1
CB1
CB2
NP
NS
VOUT
wt[
+
RSTR
VAC
UCC28704
D2
VAUX
2
VDD
CDD
Q1
NA
w{1
DRV
CS
3
4
6
1
VS
w[/
w{2
NTC/SU
GND
5
w/{
wbÇ/
-t°
图 19. Power-On with Start-Up Resistor
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Feature Description (接下页)
7.3.6.2 Initial Power-On with A Depletion-Mode FET
The UCC28704 NTC/SU pin can control an external depletion-mode FET to provide more efficient start-up. This
provides a fast start-up time with eliminating the loss associated with the start-up circuit. Therefore, the standby
power at no load can be minimized. This gives an alternative method to power on the device initially. As shown
in 图 20, the depletion mode FET HV start-up circuit consists of QST1, QST2, CST, RILIM, and RST1 to RST3
.
Before VDD reaches VVDD(on), NTC/SU stays low, QST1 turns on, which enables the quick charge of CDD thereby
achieving a shorter power-on delay time. After VDD ≥ VVDD(on), NTC/SU starts sourcing 105 µA to turn on QST2
then turns off QST1. This stops QST1 providing current to UCC28704 and minimizes the loss in the start-up circuit.
In normal operation when IPP < IPP(max), the device enters wait state in each switching cycle, see 图 14 for wait
state time. During wait state, NTC/SU stops sourcing 105 µA; which turns off QST2 and can potentially cause
QST1 to turn on. Hence CST is added to ensure that QST1 is off even during wait state. For reference, RST1 = RST2
= 2 MΩ, RST3 = 100 kΩ, CST = 1 nF, RILIM = 365 kΩ, as an example. To select a depletion-mode FET for QST1
,
BSS126 or similar can be an option.
VBLK
CB2
D1
VREG
COUT
T1
CB1
NP
NS
VOUT
wt[
+
RLIM
QST1
VAC
w{Ç1
UCC28704
VDD
VAUX
NA
D2
2
CDD
Q1
w{1
DRV
3
4
6
1
VS
CS
w[/
w{Ç2
w{2
NTC/SU
GND
5
QST2
w/{
CST
w{Ç3
wbÇ/
-t°
图 20. Power-On with a Depletion-Mode FET
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Feature Description (接下页)
7.3.7 Fault Protection
There is comprehensive fault protection incorporated into the UCC28704. Protection functions include:
•
•
•
•
•
•
•
•
•
Output Over-Voltage
Input Under-Voltage
Primary Over-Current Fault
CS Pin Open Fault
CS Pin Short-to-GND Fault
VS Pin Fault
External NTC Over-Temperature
Device Internal Over-Temperature
Constant Current Under Voltage Output Shutdown (CCUV) for Soft-Short Protection
Output Over-Voltage: The output over-voltage function is determined by the voltage feedback on the VS pin. If
the voltage sample on VS exceeds 4.67 V, 115% of the nominal regulating level, for three consecutive switching
cycles an OV fault is asserted. Once asserted the device stops switching, initiating a UVLO reset and re-start
fault cycle. During the fault, the VDD bias current remains at the run current level, discharging the VDD pin to the
UVLO turn-off threshold, VVDD(off). After that, the device returns to the start state, VDD now charging to VVDD(on)
where switching is initiated. The UVLO sequence repeats as long as the fault condition persists.
Input Under-Voltage: The line input run and stop thresholds are determined by current information at the VS pin
during the MOSFET on-time. While the VS pin is clamped close to GND during the MOSFET on-time, the current
through RS1, out of the VS pin, is monitored to determine a sample of the bulk capacitor voltage. A wide
separation of run and stop thresholds allows clean start-up and shut-down of the power supply with the line
voltage. From the start state, the sensed VS current, IVSL, must exceed the run current threshold, IVSL(run) (typical
220 µA), within the first three cycles after switching starts as VDD reaches VVDD(on). If it does not, then switching
stops and the UVLO reset and re-start fault cycle is initiated. Once running, IVSL must drop below the stop level,
IVSL(stop) (typically 80 µA), for three consecutive cycles to initiate the fault response.
Primary Over-Current: The UCC28704 always operates with cycle-by-cycle primary-peak current control. The
normal operating range of the CS pin is 0.75 V to 0.188 V. If the voltage on CS exceeds the 1.5-V over-current
level, any time after the internal leading edge blanking time and before the end of the transformer
demagnetization, for three consecutive cycles the device shuts down and the UVLO reset and re-start fault cycle
begins.
CS Pin Open: The CS pin has a 2-µA minimum pull-up that brings the CS pin above the 1.5-V OC fault level if
the CS pin is open. This causes the primary over-current fault after three cycles.
CS Pin Short to GND: On the first, and only the first cycle at start-up, the device checks to verify that the
VCST(min) threshold is reached at the CS pin within 4 µs of DRV going high. If the CS voltage fails to reach this
level then the device terminates the current cycle and immediately enters the UVLO reset and re-start fault
sequence.
VS Pin: Protection is included in the event of component failures on the VS pin. If the high-side VS divider
resistor opens the controller stops switching. VDD collapses to its VVDD(off) threshold, a start-up attempt follows
with a single DRV on-time when VDD reaches VVDD(on). The UVLO cycle will repeat. If the low-side VS divider
resistor is open then an output over-voltage fault occurs.
NTC Over-Temperature: UCC28704 uses the NTC/SU pin to program thermal shutdown threshold with an
external NTC thermistor on this pin. The NTC shutdown threshold is 0.95 V with an internal 105-µA current
source which results in a 9.05-kΩ thermistor shutdown threshold. If the NTC/SU pin voltage is below 0.95 V at
the end of the secondary current demagnetization time for three consecutive cycles switching stops and the
UVLO reset and re-start fault sequence is initiated.
Device Internal OTP: The internal over-temperature protection threshold is 150°C. If the junction temperature of
the device reaches this threshold the device initiates the UVLO reset and re-start fault cycle. If the temperature is
still high at the end of the UVLO cycle, the protection cycle repeats.
Constant Current Under-Voltage: Output shutdown (CCUV) for soft-short protection. Constant Current Under-
Voltage Protection provides detailed description for this fault and fault response.
20
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Feature Description (接下页)
7.3.8 Constant Current Under-Voltage Protection
The constant current output under voltage shutdown (CCUV) feature is to provide protection for USB connectors
from over-heat or burn-out due to soft-short circuit fault. A partial or soft-short can happen due to the presence of
foreign objects at the terminals of the USB upstream facing port, UFP, for example, smartphones with USB
Micro-B or USB Type-C connectors. When this happens along with the converter operates in CC mode with
enough VDD voltage (VDD > VVDD(off)) available from auxiliary winding, the converter can sustain operation at this
condition resulting in a potential USB burn-out condition which is named as soft-short fault to distinguish from a
hard-short circuit fault. Traditional over-current protection and short-circuit protection cannot tell a soft-short fault.
The UCC28704 provides protection when soft-short circuit fault occurs with the corresponding converter V-I
characteristics as shown in 图 21.
As shown in 图 22, the CCUV feature of UCC28704 detects the operation of the converter under this condition
when the controller is operating in CC mode and when the output voltage drops out of regulation, reaching the
CCUV threshold. If the controller detects that the VS pin voltage is below VCCUV threshold continuously for 120
ms, then it initiates a CCUV fault and sets the CCUV latch. Once the CCUV latch is set, the controller goes
through 3 cycles of VDD-UVLO without any PWM operation and clears the latch on the 4th VDD UVLO power-
up. If the CCUV condition still exists, then the controller enters into CCUV fault after 120 ms and repeats the
UVLO cycles. This 120-ms time delay allows converter normal start up without triggering the CCUV protection.
The flyback design should allow output voltage rise above CCUV protection level under normal operating
conditions within 120ms or the CCUV fault may be triggered.
+/-5%
5.25 V
5.0
4.75 V
Board-End
Cable-End
4.0
3.0
2.0
1.0
3.0 V
2.7 V
0
IOCC
Output Current (A)
图 21. Typical Target Output V-I Curves
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Feature Description (接下页)
VBULK
CC UV Fault œ Shutdown and Auto - Restart
VDD(on)
VDD
VDD(off)
2.5 mA
mA
2
1.5µA
1.5µA
1.5µA
1.5µA
1.5µA
IVDD
t
CCUV_ FAULT_ TIMER
120 ms
DRV
DRV
CCUV_ FAULT_ LATCH
IOCC
VOUT = VOCV
_ CCUV
VOUT
VOUT
IOUT
图 22. Timing Diagram of CCUV and Output Re-Start
22
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Feature Description (接下页)
7.3.9 Load Transient Response
The UCC28704 can provide excellent transient performance for most load steps. However the response of PSR
controller is always limited by the operating frequency of the converter, since the controller only samples or reads
the output voltage once every switching cycle. At zero external load, or standby, the operating frequency is set
by any preload together with the bias power needed. This frequency, fSW(standby), sets a maximum incremental
response delay. The preload can always be adjusted, at the expense of standby power, to increase the standby
frequency. The actual response delay depends on the relative timing of the load step within the switching cycle.
Thus for a given load step, IOUT(step), the output deviation can be as large as:
IOUT(step)
DVOUT
=
COUT ì fSW(s tandby)
(8)
In the case of repeating load transients the situation is aggravated. Whenever the load steps from a modest
current level to zero, there is a period of time when there is a slight over-shoot in the output voltage and the
control loop saturates and force the converter operating at to its minimum switching frequency, fSW(min), or 1 kHz
regardless what preload setting is. If the next positive load step occurs during this time the output deviation will
be larger, remembering that fSW(standby) must be > fSW(min)
.
A special transient response algorithm in this controller dynamically adjusts the minimum controlled switching
frequency, such that during a mid to high current level condition the loop's minimum switching frequency is raised
to fSW(lim), typically 4 kHz. This raised minimum switching frequency is maintained following a load step-down
change until the output voltage rises momentarily to 10% above its normal regulating level or has stayed above
its normal regulating level for 500 ms. During this time the response to a load step-up change benefits from the
decreased response delay afforded by the 4-kHz switching frequency. This is illustrated in 图 23. Application
Curves provides test results and further description in regarding to this technique.
注
In applications where standby power is not critical the minimum operating frequency of the
loop can be kept higher than 4 kHz. In these cases controller will continuously maintain a
4-kHz minimum frequency.
Transient response from standby
Periodic Transient Response
VOUT(nom) x 1.1
VOUT(nom)
VOUT
IOUT
fSW(min) = 4 kHz
fSW(min) = 4 kHz
fSW(standby)
fSW(min) = 1 kHz
fSW(standby)
fSW
fSW(min)
VOUT Recovers to nom Level,
fSW(min) < fSW(standby)
Standby Zero Load
Steady State
Load = 0,
4 kHz > fSW(standby)
Standby Zero Load
Steady State
Periodic Load Steps
图 23. Dynamic Load Response
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7.4 Device Functional Modes
The UCC28704 operates in different modes according to input voltage, VDD voltage, and output load conditions:
•
At start-up, when VDD is less than the turn-on threshold, VVDD(on) , the device is simply waiting for VDD to
reach this threshold while the VDD capacitor is getting charged.
•
When VDD exceeds VVDD(on), the device starts switching to deliver power to the converter output. The initial 3
switching cycles control the primary-peak current to IPP(min). This allows sensing any initial input or output
faults with minimal power delivery. When confirmed with input voltage above predetermined level and no fault
conditions, start up process proceeds and normal power conversion follows. The converter will remain in
discontinuous current mode operation during charging of the output capacitor(s), maintaining a constant
output current until the output voltage reaches its regulation point.
–
CV mode means that the converter keeps the output voltage constant. When the load current is less than
the current limit level, the converter operates in CV mode to keep the output voltage at the regulation level
over the entire load and input line ranges.
–
–
CC mode means that the converter keeps the output current constant. When the output voltage is below
the regulation level, the converter operates in CC mode to limit the output current.
In CC mode, when the output voltage starts to drop below regulation and if it reaches below the CCUV
threshold VCCUV, sensed at the VS pin, the controller declares a CCUV fault and disables PWM. The
controller initiates a shutdown-restart operation. This protection mode helps avoid USB terminals from
getting over-heated and thereby preventing a burn-out condition, which is also called soft-short protection.
Detailed description is in Constant Current Under-Voltage Protection.
•
•
When operating in CV mode where IPP reaches IPP(max), the UCC28704 operates continuously in the run state.
In this state, the VDD bias current is always at IRUN plus the average gate-drive current.
When operating in CV mode where IPP is less than IPP(max), the UCC28704 operates in the wait state between
switching cycles and in the run state during a switching cycle. In the wait state, the VDD bias current is
reduced to IWAIT after demagnetizing time of each switching cycle to improve efficiency at light loads. This
helps reduce light-load power losses, particularly for achieving higher efficiency at 10% and 25% load
conditions.
•
•
When a dynamic load change occurs in CV mode, the UCC28704 provides an enhanced transient response
to reduce load step caused VOUT dip in periodic load change operation. Detailed description is in Load
Transient Response.
The device operation can be stopped by the events listed below:
–
If VDD drops below the VVDD(off) threshold, the device stops switching, its bias current consumption is
lowered to ISTART until VDD rises above the VVDD(on) threshold. The device then resumes switching.
–
If a fault condition is detected, the device stops switching and its bias current consumption becomes
IFAULT. This current level discharges VDD to VVDD(off) where the bias current changes from IFAULT to ISTART
until VDD rises above the VVDD(on) threshold.
–
By pulling down NTC/SU pin to below VNTCTH, the device responds similar to that of an NTC fault wherein
PWM is disabled and converter is shutdown. On releasing the pull-down on NTC, normal operation into
CV mode will be restored.
•
If a fault condition persists, the operation sequence described above in repeats until the fault condition or the
input voltage is removed. Refer to Fault Protection for fault conditions and post-fault operation.
24
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8 Applications and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The UCC28704 device is a PSR controller optimized for isolated-flyback AC-to-DC single-output supply
applications, typically in the range from 5 W to 25 W, providing constant-voltage (CV) mode control and constant
current (CC) mode control for precise output regulation; and to help meet USB-compliant adaptors and charger
requirements as well as help meeting DOE Level VI or CoC V5 Tier 2 efficiency performance. The device uses
the information obtained from auxiliary winding sensing (VS) to control the output voltage without requiring
optocoupler/TL431 feedback circuitry. Not requiring optocoupler feedback reduces the component count and
makes the design more cost effective.
8.2 Typical Application
图 24 illustrates a typical circuit diagram for AC-to-DC adapter applications. It is a flyback converter with primary-
side regulation (PSR) controlled by UCC28704. Such applications widely exist in ac-dc adapters for
smartphones, tablet-computers, and e-readers and so forth. The following sub-sections provide critical design
formulas.
VBLK
D1
VREG
COUT
T1
CB1
NP
NS
VOUT
wt[
+
RSTR
VAC
UCC28704
VDD
D2
VAUX
2
6
CDD
NA
Q1
w{1
DRV
3
4
VS
CS
w[/
w{2
1
NTC/SU
GND
5
w/{
wbÇ/
-t°
图 24. Typical Application Circuit
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Typical Application (接下页)
8.2.1 Design Requirements
The following table illustrates a typical subset of high-level design requirements for a particular converter of
which many of the parameter values are used in the various design equations in this section. Many other
necessary design parameters, such as fSW(MAX) and VBULK(min) for example, may not be listed in such a table.
These values may be selected based on design experience or other considerations, and may be iterated to
obtain optimal results.
表 1. UCC28704 Design Parameters
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
VIN
AC-line input voltage
Line frequency
85
47
115/230
50/60
43
265
63
VRMS
Hz
fLINE
PSTBY
No-load input power
VIN = typ, IO = 0A
50
mW
OUTPUT CHARACTERISTICS (MEASUREMENT AT 150-mΩ CABLE-END)
VO
DC output voltage
Output voltage ripple
Output rated current
VIN = typ, IO = 0 to IOR
VIN = typ, IO = IOR
VIN = min to max
VIN = typ, IO > IOR
2.7V < VO < 5V
4.75
2.1
5
5.25
80
V
mV
A
VRIPPLE
IOR
2.0
2.2
2.7
IOCC
Output constant current
2.3
A
V
VCCUV
ηAVG
η10
CC UV shutdown interception
Average efficiency
VIN= typ, IO = IOCC
VIN= typ, average of 25%, 50%,
75%, and 100% Load
80%
75%
Light-load efficiency
VIN= typ, 10% load
SYSTEMS CHARACTERISTICS
fsw
Switching frequency
1
65
kHz
s
VIN = min
TON-Delay
Power-on delay time
1.8
IO= IOR (constant resistor load)
26
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8.2.2 Detailed Design Procedure
This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the
UCC28704 controller. Please refer to the 图 24 for circuit details and section 器件命名规则 for variable definitions
used in the applications equations below.
8.2.2.1 VDD Capacitance, CDD
The capacitance on VDD needs to supply the device operating current until the output of the converter reaches
the target minimum operating voltage. At this time the auxiliary winding can sustain the voltage to the
UCC28704. The total output current available to the load and to charge the output capacitors is the constant-
current regulation target. The equation below assumes the output current of the flyback is available to charge the
output capacitance until the minimum output voltage VOCC is achieved. The gate-drive current depends on
particular MOSFET to be used. If with an estimated 1.0 mA of gate-drive current, CDD is determined by 公式 9.
COUT ì VOCC
I
+1.0mA ì
(
)
RUN
IOCC
DD(on),min - VDD(off),max
CDD
=
V
(9)
8.2.2.2 VDD Start-Up Resistance, RSTR
Once the VDD capacitance is known, the start-up resistance from VBULK to achieve the power-on delay time
(tSTR) target can be determined.
2 ì V
IN(min)
RSTR
=
VDD(on) ìCDD
ISTART
+
tSTR
(10)
8.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum
Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency,
minimum input rms voltage, and minimum AC input frequency are used to determine the input capacitance
requirement.
Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target. An initial estimate of
84% can be assumed for the full-load efficiency for a 5-V/2-A design.
VOCV ìIOCC
P =
IN
h
(11)
公式 12 provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage.
To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target
capacitance.
≈
∆
’
÷
≈
’
VBULK(min)
1
∆
∆
«
÷
÷
◊
P ì 0.5 + ìarcsin
IN
p
∆
÷
2 ì V
IN(min)
«
◊
CBULK
=
2VI2N(min) - VB2ULK(min) ì f
LINE
(12)
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8.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current
The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at
full load, the minimum input capacitor bulk voltage, and the estimated DCM resonant time.
Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on
target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have
an estimate from previous designs. For the transition mode operation limit, the period required from the end of
secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs
assuming 500-kHz resonant frequency. DMAX can be determined using 公式 13.
t
≈
’
◊
R
DMAX = 1-
ì fMAX ÷ -DMAGCC
∆
«
2
(13)
Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation
below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It
is set internally by the UCC28704 at 0.475. The total voltage on the secondary winding needs to be determined;
which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC). For the 5-V
USB charger applications, a turns ratio range of 12 to 15 is typically used for a 10-W design.
DMAX ì VBULK(min)
NPS(max)
=
DMAGCC ì V
+ VF + VOCBC
OCV
(14)
NPS is determined also with other design factors such as primary MOSFET, secondary rectifier diode, as well as
secondary MOSFET if synchronous rectifier is used. Once an optimum turns-ratio is determined from a detailed
transformer design, use this ratio for the following parameters.
The UCC28704 controller constant-current regulation is achieved by maintaining DMAGCC = 0.475 at the
maximum primary current setting. The transformer turns ratio and constant-current regulating voltage determine
the current sense resistor for a target constant current limit.
Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term
is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias
power ratio to rated output power. For a 5-V, 2-A charger example, bias power of 0.5% is a good estimate. An
overall transformer efficiency of 94.5% is a good estimation of assuming 2% leakage inductance, 3% core and
winding loss, and 0.5% bias power.
RCS is used to program the primary-peak current with 公式 15:
VCCR ìNPS
RCS
=
ì hXFMR
2 ìIOCC
(15)
The primary transformer inductance can be calculated using the standard energy storage equation for flyback
transformers. Primary current, maximum switching frequency, output and transformer efficiency are included in
公式 16. Initially determine transformer primary current.
Initially the transformer primary current should be determined. Primary current is simply the maximum current
sense threshold divided by the current sense resistance.
VCST(max)
IPP(max)
=
RCS
(16)
2ì V
+ VF + VOCBC ìI
(
)
OCV
OCC
LP =
hXFMR ìIP2P(max) ì fMAX
(17)
The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target
operating output voltage in constant-current regulation and the VDD UVLO of the UCC28704. There is additional
energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be
used in many designs. The VOCC lower than CCUV level is not achievable because the CCUV protection is going
to be triggered first.
VDD(off) + VFA
NAS
=
VOCC + VF
(18)
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8.2.2.5 Transformer Parameter Verification
The transformer turns-ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage so these
should be reviewed. The UCC28704 controller requires a minimum on time of the MOSFET (tON) and minimum
DMAG time (tDMAG(min)) of the secondary rectifier in the high line, minimum-load condition. The selection of fMAX, LP
and RCS affects the minimum tON and tDMAG
The secondary rectifier and MOSFET voltage stress can be determined by the equations below.
IN(max) ì 2
.
V
VREV
=
+ VOCV + VOCBC
NPS
(19)
For the MOSFET VDS voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.
VDSPK = V
ì 2 + V
+ VF + VOCBC ìNPS + VLK
(
)
IN(max)
OCV
(20)
The following equations are used to determine for the minimum tON target of 0.3 µs and minimum de-mag
time, tDMAG(min), target of 1.7 µs. The minimum tDMAG(min) target needs to be typically 2.45 µs when a
synchronous rectifier is used on the secondary-side instead of a Schottky diode rectifier. Additional details
are provided in Design Considerations in Using with Synchronous Rectifiers.
IPP(max)
LP
IN(max) ì 2
tON(min)
=
ì
KAM
V
(21)
(22)
tON(min) ì VIN(max) ì 2
tDMAG(min)
=
NPS ì V
+ VF
OCV
8.2.2.6 VS Resistor Divider, Line Compensation, and NTC
The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side
divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1
is initially determined based on the transformer auxiliary to primary turns-ratio and the desired input voltage
operating threshold.
V
IN(run) ì 2
RS1
=
NPA ìIVSL(run)
(23)
The low-side VS pin resistor is selected based on desired VO regulation voltage. IVSL(run) is VS pin run current
with a typical value 220 µA for a design.
RS1 ì VVSR
RS2
=
NAS ì V
+ VF - V
OCV
VSR
(24)
The UCC28704 can maintain tight constant-current regulation over input line by utilizing the line compensation
feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected gate
drive and MOSFET turn-off delay. Assume a 50-ns internal delay in the UCC28704.
KLC ì RS1 ìRCS ì(tD + tGATE_ OFF)ìNPA
RLC
=
LP
(25)
The NTC function on NTC/SU-pin is to program with a NTC resistor for the desired over-temperature shutdown
threshold. The shut-down threshold is 0.95 V with an internal 105-μA current source which results in a 9.05-kΩ
thermistor shut-down threshold. The SU function on NTC/SU-pin is described in Initial Power-On with A
Depletion-Mode FET. Pulling down this pin to GND stops switching and can be used for remote enable and
disable control. This pin should be left floating if not used.
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8.2.2.7 Standby Power Estimate
Assuming no-load standby power is a critical design parameter, determine the estimated no-load power based
on target converter maximum switching frequency and output power rating. The following equation estimates the
stand-by power of the converter.
POUT ì fMIN
hìK2AM ì fMAX
PSB _ CONV
@
(26)
For a typical USB charger application, the bias power during no-load is approximately 2.1 mW. This is based on
21-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in
the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias
power estimated at 2.1 mW. Preload resistor value is estimated in 公式 27 :
VO2CV
RPL
=
PSB _ CONV - 2.1mW
(27)
Typical start-up resistance values for RSTR range from 10 MΩ to 15 MΩ to achieve less than 2-s start-up time.
The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement,
typically 325 VDC
.
2
(VBULK - VDD
)
PRSTR
=
RSTR
(28)
For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the start-up resistance and
converter stand-by power loss.
PSB = PSB _ CONV + PRSTR + PSNBR
(29)
8.2.2.8 Output Capacitance
The output capacitance value is typically determined by the transient response requirement from no-load. For
example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a
load-step transient of 0 mA to 500 mA . 公式 30 assumes that the switching frequency can be at the UCC28704
minimum of fSW(min)
.
≈
’
1
ITRAN
+ 50ms
∆
∆
«
÷
÷
◊
fSW(min)
COUT
=
DVO
(30)
公式 5 should be observed together with 公式 30 for stability consideration when determine COUT
.
Another consideration of the output capacitor(s) is the ripple voltage requirement. The output capacitors and their
total ESR are the main factors to determine the output voltage ripple. 公式 31 provides a formula to determine
required ESR value RESR, and 公式 31 provides a formula to determine required capacitance. The total output
ripple is the sum of these two parts with scale factors and 10mV to consider other noise as shown in 公式 33,
1
RESR
=
ì VRIPPLE_R
IPP(max) ìNPS
(31)
LP ìIP2P(max)
1
COUT
=
ì
4 ì(VOCV + VCBC
)
VRIPPLE _ C
(32)
(33)
VRIPPLE = 0.81ì VRIPPLE_R +1.15ì VRIPPLE_C +10mV
Example: if require VRIPPLE = 70 mV, assume 0.81 × VRIPPLE_R = 1.15 × VRIPPLE_C = 30 mV, then RESR = 4.05
mΩ, and COUT = 643 µF, with assumption of LP = 700 µH, IPP(max) = 0.713 A, NPS = 13, VOCV = 5 V, VCBC = 0.3 V.
30
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8.2.2.9 Design Considerations in Using with Synchronous Rectifiers
Special design considerations need to be observed when using synchronous rectifiers (SR) with the UCC28704.
图 14 depicts the de-mag time partition. When using UCC28704 with SR, a portion of the de-mag time needs to
be reserved for tbw, as shown in 图 25, which is the body diode conduction time when SR MOSFET turns off
before the de-mag time ends.
tLK_RESET
tBW
VS ring p-p
(scaled)
0 V
RS2 / (RS1 + RS2
)
tDM_BLANK
tDMAG
tSW
图 25. Auxiliary Waveform Details
The critical parameter dictating the maximum switching frequency when UCC28704 is used with an SR is
determined based on tDMAG(min). The tDMAG(min) needs to be typically 2.45 µs including the SR bump width (tBW) is
750 ns. The 750-ns (tBW) is required for the internal circuit to filter out the SR bump change caused by MOSFET
body diode conduction that is sensed on the VS pin waveform. The corresponding switching frequency measured
at starting point of constant current operation should not be greater than 55 kHz.
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UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
8.2.3 Application Curves
6.0
5.0
4.0
3.0
2.0
1.0
0.0
85.0%
80.0%
75.0%
70.0%
65.0%
60.0%
Board-End (115Vac)
Board-End (230Vac)
0.15W Cable-End (115Vac)
0.15W Cable-End (230Vac)
Board-End
Cable-End (150mW)
10% 20% 30% 40% 50% 60% 70% 80% 90% 100%
Output Power
D026
0.0
0.2
0.5
0.8
1.0
1.2
1.5
1.8
2.0
2.2
Iout (A)
D027
图 26. Efficiency
图 27. Output V-I Curves
120 ms
VOUT
VDD(on)
(1)
(2)
(3)
(4)
VDD
VDD(off)
IOUT
10 ms
VOUT
2 A
fsw
fsw > 4 kHz
IOUT
4 kHz
< 4 kHz
DRV
图 28. Soft-Short Protection
图 29. Response to Load Step-Down
1.1 x VOCV
VOUT
5.45 V
VOCV (V)
4.44 V
10 ms
IOUT
2 A
0 A
200 ms
图 31. Typical Output Load Transient Response
图 30. Typical VOUT Start Up at No Load
32
版权 © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
图 26 shows efficiency test result based on a 5-V/2-A, 10-W adapter using UCC28704. The efficiency
performance exceeds CoC V5 Tier 2 (79% for average and 69.7% for a 10%-load) and DOE Level VI (78.7% for
average) measured at 150-mΩ cable-end. As comparison, the measured result at board-end shown in 图 26.
图 27 shows typical VI curves from the same 10-W board. The board-end output voltage has cable compensation
to achieve cable-end output voltage with very well-regulated result in constant voltage mode operation range. In
constant current mode operation, the result depicts a good constant current operation from the vertical line of
current along with the output voltage drop until reaches CCUV. Notice that the CCUV difference at board-end
and at cable-end is about 300 mV that is the same as cable compensation voltage at full load.
图 28 illustrates the timing diagram when the operation is in CCUV. The response of the controller to a soft-short
circuit is shown wherein VOUT reaches to less than the VCCUV threshold. The converter is in CC mode and any
additional load tending higher than IOCC causes VOUT to drop below regulation due to the soft-short. As VOUT is
able to sustain VDD above its UVLO and the soft-short circuit condition persists continuously for 120 ms, the
CCUV fault is initiated. The waveform shows the 3 VDD UVLO cycles that the controller goes through after the
fault and it attempts to restart on the 4th VDD UVLO cycle with the response repeating due to the sustained soft
short-circuit fault. The 120 ms is to blank any possible noise interference which may cause unnecessary CCUV
protection to interrupt a normal operation.
图 29 provides the test result to explain the enhanced load transient scheme that is described in Load Transient
Response. When the load steps down and demands a lower switching frequency, the controller clamps the
switching frequency at 4 kHz until either the output has gone above its regulation level for more than 500 ms or
has reached more than 10% of its VOCV. This enables the converter to have a better response to an ensuing load
step up from the reduced response time. If either of the condition is met, then the controller starts to adjust the
fSW below 4 kHz if the converter operation demands such a frequency.
Associated to this enhancement, the output voltage may experience a 10% overshoot as shown in 图 29 during a
load step-down or as shown in 图 30 during a no-load start up.
图 31 shows the output load transient with load step change between 0-A and 2-A full load.
8.3 Do's and Don'ts
•
During no-load operation, do allow sufficient margin for variations in VDD level to avoid the UVLO shutdown
threshold. Also, at no-load, keep the average switching frequency greater than 1.5 × fSW(min) typical to avoid a
rise in output voltage. RLC needs to be adjusted based on no-load operation accounting for both low-line and
high-line operation..
•
•
Do clean flux residue and contaminants from the PCB after assembly. Uncontrolled leakage current from VS
to GND causes the output voltage to increase, while leakage current from VDD to VS can cause output
voltage to increase.
If ceramic capacitors are used for VDD, do use quality parts with X7R or X5R dielectric rated 50 V or higher
to minimize reduction of capacitance due to DC-bias voltage and temperature variation.
•
•
Do not use leaky components if low stand-by input power consumption is a design requirement.
Do not probe the VS node with an ordinary oscilloscope probe; the probe capacitance can alter the signal and
disrupt regulation.
•
•
Do observe VS indirectly by probing the auxiliary winding voltage at RS1 and scaling the waveform by the VS
divider ratio.
Do follow 公式 5, 公式 30, 公式 31 to 公式 33 for COUT
.
版权 © 2016, Texas Instruments Incorporated
33
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
9 Power Supply Recommendations
The UCC28704 is intended for AC-to-DC adapters and chargers with universal input voltage range of 85 VRMS to
265 VRMS, 47 Hz to 63 Hz, using flyback topology. It can also be used in other applications and converter
topologies with different input voltages. Be sure that all voltages and currents are within the recommended
operating conditions and absolute maximum ratings of the device.
10 Layout
10.1 Layout Guidelines
In order to increase the reliability and feasibility of the project it is recommended to adhere to the following
guidelines for PCB layout. In 图 32, a typical 5-V/2-A USB adapter design schematic is shown in 图 32.
•
Minimize stray capacitance on the VS node. Place the voltage sense resistors (RS1 and RS2 in 图 24) close to
the VS pin.
•
Arrange the components to minimize the loop areas of the switching currents as much as possible. These
areas include such loops as the transformer primary winding current loop (a), the MOSFET gate-drive loop
(b), the primary snubber loop (c), the auxiliary winding loop (d) and the secondary output current loop (e). In
practice, trade-offs may have to be made. Loops with higher current should be minimized with higher priority.
As a rule of thumb, the priority goes from high to low as (a) – (e) – (c) – (d) – (b).
•
•
The RLC resistor location is critical. To avoid any dv/dt induced noise (for example MOSFET drain dv/dt)
coupled onto this resistor, it is better to place RLC closer to the controller and avoid nearby the MOSFET.
To improve thermal performance increase the copper area connected to GND pins.
T1
VBLK
D1
+
-
COUT
CB1
CB2
NP
NS
VOUT
wt[
+
(e)
(a)
CSN1
DSN1
L
(C)
w{b1
RSTR
w{b2
Optional, short
across if not used
VAC
DIN
N
UCC28704
VDD
D2
VAUX
Q1
2
wD1
CDD
NA
w{1
DRV
3
(B)
6
1
VS
CS
w[/
Isolation
Boundary
4
(d)
w{2
NTC/SU
GND
5
w/{
CY
wbÇ/
-t°
图 32. 10-W, 5-V/2-A USB Adapter Schematics
34
版权 © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
10.2 Layout Example
图 33 demonstrates a 10-W, 5-V/2-A, layout with trade-offs to minimize the loops while effectively placing
components and tracks for low noise operation on a single-layer printed circuit board. In addition to the
consideration of minimal loops, one another layout guideline is always to use the device GND as reference point.
This applies to both power and signal to return to the device GND pin (pin 5).
CO1
Loop (e)
Loop (c)
D1
Transformer Isolation Boundary
Loop (a)
+ VOUT
-
Y-Cap
Loop (b)
CB2
Loop (d)
UCC28704
Input Rectifier DIN
图 33. Layout Example
版权 © 2016, Texas Instruments Incorporated
35
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
11.1.1.1 电容术语（以法拉为单位）
CBULK
CDD
CB1 和 CB2 的总输入电容。
VDD 引脚所需的最小电容。
COUT
所需的最小输出电容。
11.1.1.2 占空比术语
DMAGCC CC 中二次侧二极管导通占空比，0.475。
DMAX 最大 MOSFET 导通时间占空比。
11.1.1.3 频率术语（以赫兹为单位）
fLINE
最低线路频率。
fMAX
转换器的最高目标满载开关频率。
fMIN
转换器的最低开关频率，在器件 fSW(min)限值基础上增加 15％ 的裕度。
负载减小后的瞬态开关频率
fSW(lim)
FSW(min)
fSW(max)
最低开关频率（见Electrical Characteristics表）
最大开关频率（见Electrical Characteristics表）
fSW(standby) 轻负载条件下负载变化之前的开关频率
11.1.1.4 电流术语（以安培为单位）
IOCC
转换器输出恒流目标。
IOR
转换器额定输出电流。
IPP(max)
ISTART
ITRAN
IVSL(run)
IWAIT
变压器一次侧最大电流。
启动偏置电源电流（见Electrical Characteristics表）。
所需的正负载阶跃电流。
VS 引脚运行电流（见Electrical Characteristics表）。
等待状态期间的 VDD 偏置电流。（见Electrical Characteristics表）。
11.1.1.5 电流和电压调节术语
KAM
KCo
KLC
一次侧峰峰值电流比（见Electrical Characteristics表）。
稳定性因子为 100，用于计算 COUT
电流调节常量（见Electrical Characteristics表）。
。
36
版权 © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
器件支持 (接下页)
11.1.1.6 变压器术语
LP
变压器一次侧电感。
LS
变压器二次侧电感。
NAS
NPA
NPS
NA
变压器辅助绕组与二次侧绕组匝数比。
变压器一次侧绕组与辅助绕组匝数比。
变压器一次侧绕组与二次侧绕组匝数比。
变压器辅助绕组的匝数。
NP
变压器一次侧绕组的匝数。
NS
变压器二次侧绕组的匝数。
11.1.1.7 功率术语（以瓦特为单位）
PIN
转换器最大输入功率。
转换器的满载输出功率。
VDD 启动电阻功耗。
总待机功耗。
POUT
PRSTR
PSB
PSB_CONV
PSB 与启动电阻和缓冲器功耗的差值。
11.1.1.8 电阻术语（以 Ω 为单位）
RCS
RESR
RPL
一次侧电流编程电阻
输出电容的总 ESR。
转换器输出端的预载电阻。
高侧 VS 引脚电阻。
RS1
RS2
低侧 VS 引脚电阻。
RSTR
高电压与 VDD 之间连接的启动电阻
11.1.1.9 时序术语（以秒为单位）
tD
电流感测延迟。
tDMAG(min)
tGATE_OFF
tON(min)
tR
二次侧整流器最短导通时间。
一次侧主 MOSFET 关断时间。
MOSFET 最短导通时间。
tDMAG 之后的谐振环周期。
tSTR
由于 VDD 电容 CDD 需要充电时间所造成的上电延时。
tZTO
tZTO：未检测到过零点时 VS 引脚上的过零点超时延迟（见Electrical Characteristics表）
版权 © 2016, Texas Instruments Incorporated
37
UCC28704
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
www.ti.com.cn
器件支持 (接下页)
11.1.1.10 电压术语（以伏特为单位）
VBLK 或 VBULK 大容量电容电压。
VBULK(max)
VBULK(min)
VBULK(run)
VCBC
用于待机功耗测量的大容量电容最高电压。
满功率条件下 CB1和 CB2 的最低电压。
转换器启动（运行）高电压。
满载时电路板端输出的电缆补偿电压。
VCCR
恒流调节电压（见Electrical Characteristics表）。
恒流输出电压关断的 VS 阈值（见Electrical Characteristics表）
CS 引脚的最大电流感测阈值（见Electrical Characteristics表）。
CS 引脚的最小电流感测阈值（见Electrical Characteristics表）。
UVLO 关断电压（见Electrical Characteristics表）。
UVLO 导通电压（见Electrical Characteristics表）。
电流接近零时的二次侧整流器正向压降。
辅助整流器正向压降。
VCCUV
VCST(max)
VCST(min)
VVDD(off)
VVDD(on)
VF
VFA
VLK
估计的漏感能量复位电压。
VOCV
经稳压的转换器输出电压。
VOCC
恒流稳压条件下的最低目标转换器输出电压。
满载条件下的输出峰峰值纹波电压。
VRIPPLE
VVSR
VS 输入端的 CV 调节电平（见Electrical Characteristics表）。
11.1.1.11 交流电压术语（以 VRMS 为单位）
VIN(max)
VIN(min)
VIN(run)
转换器的最大输入电压。
转换器的最小输入电压。
转换器输入启动（运行）电压。
11.1.1.12 效率术语
η
转换器总体效率。
η10
10% 负载时的效率。
ηAVG
ηXFMR
25%、50%、75% 和 100% 负载时的算术平均效率。
变压器一次侧与二次侧之间的功率传输效率。
38
版权 © 2016, Texas Instruments Incorporated
UCC28704
www.ti.com.cn
ZHCSEQ1A –FEBRUARY 2016–REVISED FEBRUARY 2016
11.2 文档支持
11.2.1 相关文档ꢀ
相关文档如下：
《使用 UCC28704-1EVM-724，评估模块》，SLUUBF1
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC28704DBVR-1
UCC28704DBVT-1
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
7041
7041
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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相关型号：
UCC28704DBVR-1
具有初级侧调节 (PSR) 功能的高效离线 CV 和 CC 反激控制器 | DBV | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28704DBVT-1
具有初级侧调节 (PSR) 功能的高效离线 CV 和 CC 反激控制器 | DBV | 6 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28710
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28710D
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28710DR
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28710_14
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28711
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28711D
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28711DR
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28712
Constant-Voltage, Constant-Current Controller With Primary-Side RegulationWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28712D
具有 PSR、谷底开关、NTC 选项和 150mV 电缆补偿功能的恒压、恒流 PWM | D | 7 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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UCC28712DR
具有 PSR、谷底开关、NTC 选项和 150mV 电缆补偿功能的恒压、恒流 PWM | D | 7 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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