UCC28782_V01_技术文档

UCC28782

SLUSDK4D – MAY 2020 – REVISED MAY 2021

UCC28782 High-Density Active-Clamp Flyback Controller with EMI Dithering, X-Cap

Discharge, and Bias Power Management

1 Features

3 Description

•

Active clamp recovers leakage inductance energy

Adaptive control for fast zero voltage switching

(ZVS) tracking and dead time optimization

Integrated switching bias regulator supports USB

Type-C^™PD wide output voltage range with one

auxiliary winding

EMI frequency dithering without trade-offs on

transient response or audible noise

Dynamic bias power management for digital

isolator and GaN driver

Programmable Adaptive Burst Mode (ABM) with

internal compensation

Active X-capacitor (X-cap) discharge

Over-temperature, over-voltage, output short-

circuit, over-current, over-power, and pin-fault

protections

The UCC28782 is a high-density active-clamp flyback

(ACF) controller for USB Type C™ PD applications

and allows for efficiencies over 93% by recovering the

leakage inductance energy and adaptive ZVS tracking

over the full load range.

•

With a maximum frequency of 1.5 MHz the magnetics

can be minimized. Frequency dithering helps to

improve EMI margin. The UCC28782 also integrates

dynamic bias power management to optimize the gate

drive for Si or GaN MOSFETs.

•

Adaptive Burst Mode (ABM) combined with Low

Power Mode (LPM) and Standby Power mode (SBP)

work together to increase light-load efficiency while

reducing ripple and audible noise.

•

The UCC28782 also integrates an X-Cap discharge

function to discharge the residual input voltage when

power is removed.

•

Auto-recovery and group-latch fault options with

fast latch-reset capability

4x4-mm 24-pin QFN package

The UCC28782 has multiple protection modes and

options for retry or latch-off responses depending on

the application needs. See Device Comparison Table.

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE

UCC28782

WQFN-24

4.0 mm × 4.0 mm

2 Applications

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

High-density Type-C^™PD adapters for laptop,

tablet, TV, set-top box, and printer

USB power delivery and fast phone chargers

AC-to-DC or DC-to-DC auxiliary power supply

Audio soundbars and smart speakers

Battery chargers for power tools and E-bikes

USB wall outlets

•

V_OUT

~

C_X

GaN

œ

+

Power IC

V_SW

~

Isolator

GaN

SR Controller

Power IC

LED lighting

P13

VS

PGND

SWS

P13

UCC28782

AGND

XCD

FB

REF

CC / CV

Controller

T

Simplified Typical Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCC28782

SLUSDK4D – MAY 2020 – REVISED MAY 2021

www.ti.com

6 Pin Configuration and Functions

UCC28782A

20

19

24

23

22

21

1

18

17

16

15

14

13

FLT

AGND

SWS

PWMH

P13

2

RTZ

3

RDM

25

4

EP

IPC

5

BUR

6

S13

FB

8

9

10

11

12

7

UCC28782AD,

UCC28782BDL,

UCC28782CD

20

19

24

23

22

21

1

2

3

4

5

6

18

17

16

15

14

13

FLT

RTZ

RDM

IPC

XCD

SWS

PWMH

P13

25

EP

BUR

S13

FB

8

9

10

11

12

7

Figure 6-1. RTW Package 24-Pin WQFN Top View

2

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Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NUMBER

FLT

1

I

The controller enters into the fault state if the FLT-pin voltage is pulled above 4.5 V or below 0.5

V. A 50-µA current source interfaces directly with an external NTC (negative temperature coefficient)

thermistor to AGND pin for remote temperature sensing. The current source is active during the run

state and inactive during the wait state. A 50-µs fault delay allows a filter capacitor to be placed on

the FLT pin without false triggering the 0.5-V OTP fault when the controller enters into a run state

from a wait state. Alternatively, a high-resistance voltage divider can be used to sense the bulk input

capacitor voltage for line-OVP detection, and a 750-µs fault delay helps to prevent false triggering

the 4.5-V input line-OVP from a short-duration bulk capacitor voltage overshoot during line surge and

ESD strike events. When FLT-pin voltage is used for line-OVP detection, the external OTP can be

implemented on CS pin.

RTZ

2

3

I

A resistor between this pin and AGND pin programs an adaptive delay for transition to zero voltage

from the turn-off edge of the high-side clamp switch to the turn-on edge of the low-side switch. The

parasitic capacitance between this pin and AGND needs to be minimized to avoid its effect on the

dead-time calculation.

RDM

A resistor between this pin and AGND pin programs a synthesized demagnetization time used to

control the on-time of the high-side switch to achieve zero voltage switching on the low-side switch.

The controller applies a voltage on this pin that varies with the output voltage derived from the VS

pin signal. The parasitic capacitance between this pin and AGND needs to be minimized to reduce its

influence on the internal PWMH on-time calculation.

IPC

4

I

This pin is an intelligent power control (IPC) pin to optimize the converter efficiency. A 50-µA current

source directly interfaces with a resistor (R_IPC) to AGND pin to program an increase in the peak

current level at very light load; the burst frequency can be further reduced, helping to achieve low

standby power and tiny-load power. If the IPC pin is connected to AGND without R_IPC, the peak

current level in very light load is set to a minimum level for the output ripple or audible noise sensitive

designs. R_IPCcan also be connected between this pin and the CS pin or IPC pin can be directly

connected to CS pin, so the 50-µA IPC current can create an output voltage dependent offset voltage

on the CS pin for reducing output ripple in adaptive burst mode and improving light-load efficiency at

lower output voltage level of a wide output voltage range design. IPC pin can be used to disable the

PFC controller at all load condition of 5 V and 9 V outputs through a control switch to further improve

the light load efficiency of higher power adapters.

BUR

5

I

This pin is used to program the burst threshold of the converter at light load. A resistor divider

between REF pin and AGND pin is used to set a voltage at this pin to determine the peak current

level when the converter enters adaptive burst mode (ABM). In addition, the Thevenin resistance on

BUR pin (equivalent resistance of the divider resistors in parallel) is used to set an offset voltage

for smooth mode transition. A 2.7-µA pull up current increases the peak current threshold when the

converter enters low power mode (LPM) from ABM. A 5-µA pull down current reduces the peak

current threshold when the converter enters into heavy load mode (adaptive amplitude modulation,

AAM) from ABM.

FB

6

7

I

The feedback current signal to close the converter regulation loop is coupled to this pin. This pin

presents a 4.25-V output that is designed to have 0-µA to 75-µA current pulled out of the pin

corresponding to the converter operating from full-power to zero-power conditions. A 220-pF filter

capacitor between FB pin and REF pin is recommended to desensitize the feedback signal from noise

interference.

REF

O

The pin is a 5-V reference output that requires a 0.22-µF ceramic bypass capacitor to the AGND pin.

This reference is used to power internal circuits and can supply a limited external load current. Pulling

this pin low shuts down PWM action and initiates a VDD restart.

AGND

CS

8

9

G

I

Analog ground and the ground return of PWMH and RUN drivers. Return all analog control signals to

this ground.

This is the current-sense input pin. This pin couples to the current-sense resistor through a line-

compensation resistor to control the peak primary current in each switching cycle. An internal current

source on this pin, proportional to the converter’s input voltage, creates an offset voltage across

the line-compensation resistor to balance the OPP level across line. The CS pin can also provide

an alternative OTP function, when the FLT pin is being used for the line input-OVP. A small-signal

diode in series with an NTC resistor is connected between PWMH pin and CS pin to form the

OTP detection. When PWMH is high, the NTC resistor and the line-compensation resistor become

a resistor divider from 5 V and creates a temperature dependent voltage on CS pin. When CS pin

voltage is higher than 1.2 V in PWMH on state for 2 consecutive cycles, the OTP fault on CS pin is

triggered.

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TYPE⁽¹⁾

DESCRIPTION

NAME

NUMBER

RUN

10

O

G

This output pin is high when the controller is in a run state. This output is low during start-up, wait,

and fault states. A 2.2-µs timer delays the initiation of PWML switching after this pin has gone high

and S13-pin voltage is above the 10-V power good threshold. The pull up driving capability of both

RUN and PWMH pins allows bias power management of a digital isolator and GaN power IC through

a common-cathode small-signal diode, so the power consumption can be reduced in wait state.

PGND

11

Low-side ground return of the PWML driver. The internal level shifter allows the common return

impedance to be eliminated, and improving higher frequency operation. For a GaN-based gate-

injection transistor (GIT), this pin can be directly connected to the separate source pin of a GIT

GaN device, which enhances the turn-off speed and decouples the additional voltage spike on the

current-sense resistor and layout parasitic inductance of the gate driving loop. For a silicon (Si) power

FET, this pin can be connected to the source for a smaller gate driving loop. For a GaN power IC with

a logic PWM input, this pin can be referred to AGND.

PWML

S13

12

13

O

Low-side switch gate driver output. The high-current capability (-0.5A/+1.9A) of PWML enables driving

of a silicon power MOSFET with higher capacitive loading, a GIT GaN with continuous on-state

current, or a GaN power IC with logic input. The maximum voltage level of PWML is clamped to the

P13 pin voltage.

S13 is coupled to P13 through an internal 2.8-Ω switch controlled by the RUN pin. When RUN is

high, the S13 decoupling capacitor is charged up to 13 V by an internal soft-start current limiter.

The S13 pin voltage needs to increase above 10 V to initiate PWML switching. When RUN is low,

S13 is discharged by the S13 pin loading, such as GaN power IC. The power-on delay of the GaN

power IC on S13 must be less than 2 µs to be responsive to PWML. A 22-nF ceramic capacitor

between S13 and the driver ground is recommended. S13 can also perform power management on

the PFC controller at the same time through a diode, such that PFC can be disabled at deep light load

condition.

P13

14

O

P13 is a regulated 13-V output voltage derived from V_VDD. During V_VDDstartup, P13 pin is connected

to the VDD pin internally, so the external high-voltage depletion MOSFET, such as BSS126, can

provide the controlled startup current to charge the VDD capacitor. After the initial startup, P13

recovers back to 13-V regulation. A 1-µF ceramic bypass capacitor is required from P13 to AGND. A

20-V Zener between this pin and AGND is recommended to protect this pin from overstress, when the

connection between this pin and the BSS126 gate is fail-open or line surge energy is coupled to this

pin.

PWMH

SWS

15

16

O

I

PWM output signal used to control the gate of the high-side clamp switch through an external high-

voltage gate driver. The driving capability is designed to bias an external level-shifting isolator through

a small-signal diode or can also transmit the signal to high-side driving circuitry through a pulse

transformer. The maximum voltage level of PWMH is clamped to 5-V REF level.

This sensing input is used to monitor the switch-node voltage as it nears zero volts in normal

operation for ZVS auto-tuning. The source of a high-voltage depletion-mode MOSFET, such as

BSS126, is coupled to this pin through a current-limiting resistor, so only the useful switching

characteristic below 15 V is monitored. During start-up, this pin is connected to the VDD pin

internally to allow BSS126 to provide start-up current. The external current-limit resistor and a small

bidirectional TVS across BSS126 gate and source should be added to protect the gate-to-source

voltage from potential abnormal voltage stress. The resistor should be higher than 500 Ω. The

clamping voltage of TVS should be less than BSS126 voltage rating but greater than 15 V. Moreover,

the resistor and a 22-pF ceramic capacitor between the SWS pin and the bulk input capacitor ground

form a small sensing delay to help the internal detection circuit to identify the ZVS characteristic

correctly.

4

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TYPE⁽¹⁾

DESCRIPTION

NAME

NUMBER

XCD

17, 18

I

X-cap discharge input pins with 2-mA maximum discharge current capability. The 6.5-V line zero-

crossing (LZC) threshold on XCD pins is used to detect AC-line presence. When LZC is missing over

an 84-ms timeout period, the discharge current is enabled for a maximum period of 300 ms followed

by a 700-ms no current blanking time. For the latched-off fault protections, when AC-line recovers

and LZC is detected again, the controller can reset the latch fault state almost immediately and will

attempt to restart without waiting to fully discharge the bulk input capacitor. For the auto-recovery fault

protections, if the controller is in 1.5-s auto-recovery fault state, LZC can reset the timer and speed up

the restart attempt. The two redundant XCD pins help to provide the X-cap discharge function even

when one pin is in fail-open condition. To form the discharge path, an anode of two high-voltage diode

rectifiers is connected to each X-cap terminal, the two diode cathodes are connected together to a

26-kΩ high-voltage current-limiting resistance, and the drain-to-source connection of a high-voltage

depletion MOSFET couples the resistance to the XCD pins. Two series 13-kΩ SMD resistors in 1206

size can be used as the current limiting device, and share the potential transient voltage from the

AC-line. A 600-V rated MOSFET such as BSS126 is needed as the high voltage blocking device. The

MOSFET gate is connected to the P13 pin, so the XCD pins can obtain enough signal headroom

for LZC detection. If the X-cap discharge function is not needed, XCD pins must be connected to

AGND pin to disable the function, and the diode-resistor-MOSFET path must be removed. Different

from UCC28782AD, UCC28782BDL, and UCC28782CD, the same pin locations on UCC28782A are

defined as two additional AGND pins, keeping the XCD-pin function disabled.

VDD

19

P

Controller bias power input. VDD pin is also the integrated boost converter output pin. A hold-up

capacitor to BGND pin is required. For fixed-output applications where the boost converter is optional,

VDD pin can directly connect to the rectified primary-side auxiliary winding voltage, so the boost-

converter components can be eliminated. For wide-output design with the boost converter, a ceramic

capacitor with 10-µF or 15-µF capacitance is recommended, and the minimum voltage rating is 25 V.

BGND

BSW

20

21

G

I

Boost converter return pin connected to the source terminal of the internal 30-V boost switch. The

separate ground return simplifies PCB layout design to minimize the high di/dt switching loop along

with the boost diode and VDD capacitor, so the noise-coupling effect to other sensitive nodes can be

mitigated.

Boost converter switch node, connected to the drain terminal of internal 30-V boost switch. For wide

output voltage applications, the boost inductor and boost diode anode are connected to this pin.

For a fixed output voltage design, BIN and BSW pins should be connected to BGND pin, so the

boost-converter control is disabled in order to lower the controller run current. A 22-µH inductor with

higher than 0.4-A saturation current capability and less than 1 Ω resistance is recommended for boost

inductor selection. If the maximum VDD-pin voltage is less than 30V, a 30-V rated Schottky diode not

smaller than SOD-323 package is recommended as boost diode, so the BSW voltage stress from the

diode reverse recovery effect can be avoided when the converter operates in short-duration CCM.

BIN

22

I

Boost converter input pin. For a wide output voltage application, when the boost converter is needed

to improve the converter efficiency, BIN is connected to the rectified auxiliary-winding voltage. A 33-µF

energy storage capacitor in parallel with a 10-µF ceramic capacitor is recommended. The 33-µF

capacitor should be placed close to the auxiliary rectification diode and the auxiliary-winding ground

terminal to minimize the rectification switching loop. The 10-µF cap can be placed close to the boost

inductor and BGND pin to minimize the boost input switching loop. Together with a Schottky-type

auxiliary diode in a SOD-123 package, less than 0.1-Ω winding resistance on the auxiliary winding is

required to ensure the boost converter receives sufficient transformer energy under a very low output

voltage condition, especially for the 3.3-V to 21-V output range. A small unidirectional 24-V TVS

between BIN and AGND can protect the pin from exceeding its 30-V rating, when potential abnormal

voltage stress occurs. If the boost converter is not needed, BIN and BSW should be connected to

BGND pin.

VS

23

I

This voltage-sensing input pin is coupled to an auxiliary winding of the converter’s transformer via a

resistor divider. The pin and the associated external resistors are used to monitor the output and input

voltages and switching edges of the converter at different moments within each switching cycle. The

parasitic capacitance between this pin and AGND needs to be minimized to avoid the impact on the

output voltage sensing and the dead-time calculation.

SET

EP

24

25

I

This pin is used to configure the controller to be optimized for gallium nitride (GaN) power FETs or

silicon (Si) power FETs on the primary side. Depending on the setting, it will optimize parameters of

the ZVS control loop, dead-time adjustment, and protection features. When pulled high to REF pin, it

is optimized for Si FETs. When pulled low to AGND, it is optimized for GaN FETs.

G

The thermal pad must be connected to AGND.

(1) I = Input, O = Output, P = Power, G = Ground

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 6

5 Device Comparison Table...............................................7

6 Pin Configuration and Functions...................................2

Pin Functions.................................................................... 3

7 Specifications.................................................................. 8

7.1 Absolute Maximum Ratings........................................ 8

7.2 ESD Ratings............................................................... 9

7.3 Recommended Operating Conditions.........................9

7.4 Thermal Information....................................................9

7.5 Electrical Characteristics.............................................9

7.6 Typical Characteristics..............................................14

8 Detailed Description......................................................18

8.1 Overview...................................................................18

8.2 Functional Block Diagram.........................................20

8.3 Detailed Pin Description............................................21

8.4 Device Functional Modes..........................................39

9 Application and Implementation..................................68

9.1 Application Information............................................. 68

9.2 Typical Application Circuit.........................................68

10 Power Supply Recommendations..............................80

11 Layout...........................................................................82

11.1 Layout Guidelines................................................... 82

11.2 Layout Example...................................................... 85

12 Device and Documentation Support..........................90

12.1 Documentation Support.......................................... 90

12.2 Receiving Notification of Documentation Updates..90

12.3 Support Resources................................................. 90

12.4 Trademarks.............................................................90

12.5 Electrostatic Discharge Caution..............................90

12.6 Glossary..................................................................90

13 Mechanical, Packaging, and Orderable

Information.................................................................... 91

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (August 2020) to Revision D (May 2021)

Page

•

Revised Features list and Description text ........................................................................................................ 1

Corrected minor typos, spacings, ambiguities, etc. throughout datasheet, beginning on first page ..................1

Updated Simplified Typical Schematic ...............................................................................................................1

Revised Device Comparison Table for new device versions ............................................................................. 7

Revised device-version references in text throughout datasheet ......................................................................7

Revised Pin Configurations drawing for new device versions ........................................................................... 2

Fixed minor typos, spacing, etc., throughout datasheet beginning in Absolute Maximum Ratings table .......... 8

Clarified numerous Parameters and Test Conditions in Electrical Characteristics table ................................... 9

Added Electrical Characteristics specifications f_BSW, V_RUNL, t_ON(MIN), V_PWMHL, t_R(PWMH), t_OPP, t_FDR, t_DM(MAX)

,

t_DM(MIN), t_XCD(STEP)for new device versions .......................................................................................................9

Revised text and expanded guidance to numerous topics throughout the datasheet ..................................... 18

Renamed K_RTZfactor in Equation 9 to distinguish from K_TZin Electrical Characteristics table .......................33

Changed K_DMfactor in Equation 11 from 5.0×10⁹to 5.25×10⁹....................................................................... 34

Revised text and Figure 8-37 and added Figure 8-38 and text in Brown-In and Brown-Out section ...............57

Updated Typical Application Circuit image .......................................................................................................68

•

Changes from Revision B (June 2020) to Revision C (August 2020)

Page

•

t_{DZCD (UL)}Electrical Characteristic specification changed from 75.3 ns to 81 ns ...............................................8

t_DZCD(LL)Electrical Characteristic specification changed from 30 ns to 23 ns ................................................... 8

f_{BSW (UL)}: Electrical Characteristic specification changed from 457 kHz to 467 kHz .........................................8

V_{CSTMAX_LV666 (LL)}Electrical Characteristic specification changed from 549.4 mV to 546 mV .......................... 8

t_{FRUN (UL)}Electrical Characteristic specification changed from 30 ns to 32 ns ..................................................8

R_{NTCTH (UL)}Electrical Characteristic specification changed from 10.93 kohm to 11.18 kohm .......................... 8

R_{NTCR (UL)}Electrical Characteristic specification changed from 25.54 kohm to 26.4 kohm ..............................8

t_{FLTNTC (UL)}Electrical Characteristic specification changed from 85 us to 100 us ............................................. 8

Removed 376-uA MIN specification from I_FAULT................................................................................................8

Changes from Revision A (May 2020) to Revision B (June 2020)

Page

•

Changed marketing status from Advance Information to initial release .............................................................1

6

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5 Device Comparison Table

ORDERABLE PART

EMI Dither

X-CAPACITOR DISCHARGE

FAULT RESPONSE

NUMBER

All are auto-recovery

(retry)

UCC28782A

Disabled

Enabled

No

All are auto-recovery

(retry)

UCC28782AD

Yes

OVP, OPP, OCP, SCP, and OTP-on-FLT-pin

are latch-off faults

UCC28782BDL

UCC28782CD

Enabled

Yes

OVP and OTP-on-FLT-pin are latch-off faults

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

MAX

UNIT

VDD

38

SWS

–6

–10

–20

–0.3

–0.75

–1

38

SWS (transient, negative pulse width of 20 ns max., duty cycle ≤ 1%)

38

VDD-SWS

CS

38

3.6

VS

Input Voltage

7

V

VS (transient, 100 ns max.)

7

PGND

–1

4

PGND (transient, 25 ns max.)

RTZ, BUR, SET, RDM, IPC, FLT, FB

XCD, BIN, BSW

5

–0.3

–1

7

30

BSW (transient, 150 ns max.)

30

REF, PWMH, RUN

Output Voltage

–0.3

7

V

P13, S13, PWML

20

REF, P13, RTZ, RDM, IPC

S13 (average)

Self–limiting

15

VS

2

VS (transient, 100 ns max.)

Source Current FB

RUN (continuous)

2.5

1

mA

5

PWML (continuous)

PWMH (continuous)

CS (transient, 30 ns max.)

RUN (continuous)

50

10

1

8

PWML (continuous)

PWMH (continuous)

50

10

Sink Current

SWS, BSW

XCD

Self–limiting

mA

25

0.3

1

FLT

BIN

Operating

junction

temperature

T_J

–40

–65

125

150

°C

Storage

temperature

T_stg

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated

under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

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7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

14

NOM

MAX

UNIT

V

V_VDD

C_VDD

C_P13

C_REF

T_J

Bias supply operating voltage

VDD capacitor

34

10

µF

°C

P13 bypass capacitor

1

REF bypass capacitor

Operating junction temperature

0.22

–40

125

7.4 Thermal Information

DEVICE

THERMAL METRIC⁽¹⁾

RTW + Pad (WQFN)

UNIT

24 PINS

43.1

31.6

20.3

0.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

20.3

5.7

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

Unless otherwise stated: V_VDD= 20 V, V_BIN= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ,

V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VDD INPUT

I_RUN(STOP)

I_RUN(SW)

Supply current, run state

No switching

0.88

2.66

2.2

3

2.66

3.55

mA

Switching, I_VSL= 0 µA

I_FB= -85 µA, V_BIN= V_BSW= V_VDD= 20 V,

sum of I_BIN, I_BSW, and I_VDD

452

580

540

695

658

µA

I_WAIT

Supply current, wait state

I_FB= -85 µA, BIN and BSW pins to

AGND, I_VDDonly

465

150

I_START

I_FAULT

Supply current, start state

Supply current, fault state

V_VDD= V_VDD(ON)- 100 mV, V_VS= 0 V

fault state

235

500

301

630

µA

V_VDDincreasing, V_SWS- V_VDD= 1 V,

V_VDD= 16.5 V

I_VDD(LIMIT)

VDD startup current limit during startup

1.2

2

2.53

mA

V_VDD(ON)

V_VDD(OFF)

VDD turnon threshold

VDD turnoff threshold

V_VDDincreasing

V_VDDdecreasing

16.31

9.94

17 17.91

10.6 11.17

V

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UCC28782

SLUSDK4D – MAY 2020 – REVISED MAY 2021

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Unless otherwise stated: V_VDD= 20 V, V_BIN= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ,

V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Offset to power cycle for long output voltage

overshoot

V_VDD(PCT)

V_VDD(RST)

Offset above V_VDD(OFF), I_FB= -85 µA

1.54

2.2

2.98

V

Voltage that VDD must cross H-L to

reset a latched-off fault condition

Logic reset threshold for latched fault

3.3

4.3

4.61

19.4

V

V_VDD(BOOST)VDD regulation level in boost mode

I_VDD= 0 mA to 30 mA, V_BIN= 9 V

17.6

18.5

BIN INPUT

V_BIN(ON)

V_BIN(OFF)

V_BIN(EN)

V_BIN(DIS)

UVLO on voltage of V_BINin boost mode

V_BINincreasing

V_BINdecreasing

V_BINincreasing

2.03

1.13

2.2

2.42

1.33

V

UVLO hysteresis below V_BIN(ON)in boost

mode

1.23

Highest V_BINto enable boost mode

14.44

0.12

14.9 15.47

Hysteresis above V_BIN(EN)to disable boost

mode

0.16

0.18

BSW INPUT

R_BSW

R_DS(on)of internal boost switch

0.94

1.4

2.28

0.38

247

Ω

A

I_BSW(MAX)

t_BLEB

Peak current threshold in CPC control

Leading edge blanking time in boost mode

0.27 0.335

129

389

190

420

ns

Maximum switching frequency in CPC

control, for UCC28782A only

f_BSW

V_BIN= 9 V

467

499

kHz

Maximum switching frequency in CPC

control, for UCC28782AD, UCC28782BDL, V_BIN= 9 V

and UCC28782CD only

f_BSW

389

420

I_FB= -85 µA

Minimum off time in COT control

I_BSW= 500 mA

198

2.9

255

353

5.9

ns

μs

t_BOFF(MIN)

4.35

P13 OUTPUT

0 mA to 60 mA out of P13, run state,

V_VDD= 20 V

V_P13

P13 voltage level including load regulation

12.0

12.8

2.2

13.6

3.04

V

I_P13(START)

I_P13(MAX)

Max sink current of P13 pin during startup

Current sourcing limit of P13 pin

Line regulation of V_P13

V_P13= 14 V

1.53

103.3

-6

mA

mV

V

P13 shorted to AGND, V_VDD= 20 V

V_VDD= 15 V to 35 V

133 154.5

VR13_(LINE)

V_P13(OV)

2

8.7

Over voltage fault threshold above V_P13

1.35

2.54

Dropout resistance of P13 regulator switch (V_VDD- V_P13) / 30 mA, V_VDD= 11 V,

R_P13

8.5

2.1

13

22.7

Ω

between VDD and P13 pins

30 mA out of P13

S13 OUTPUT

R_S13

R_DS(on)of internal disconnect switch

between P13 and S13 pins

(V_P13- V_S13) / 30 mA, V_VDD= 11 V,

30 mA out of S13

2.8

3.82

10.7

Ω

V_{S13_OK}

S13_OK threshold to enable switching

Current sourcing limit of S13 pin

V_RUN= 5 V

9.63

10.2

V

I_S13(MAX)

REF OUTPUT

V_REF

S13 shorted to AGND, V_VDD= 20 V

260.7

350 452.5

mA

REF voltage level

I_REF= 0 A

4.9

14.3

-7

5

17

-3

5.13

20.3

1

V

I_REF(MAX)

VR5_(LINE)

Current sourcing limit of REF pin

Line regulation of V_REF

REF shorted to AGND, V_VDD= 20 V

V_VDD= 12 V to 35 V

mA

mV

0 mA to 1 mA out of REF, change in

V_REF

VR5_(LOAD)

Load regulation of V_REF

-16

0.1

25

mV

VS INPUT

V_VSNC

V_ZCD

Negative clamp level

I_VSL= -1.25 mA, voltage below ground

V_VSdecreasing

221

12.4

287

35

0

344

67.2

0.31

mV

µA

Zero-crossing detection (ZCD) level

Input bias current

I_VSB

V_VS= 4 V

-0.23

242.4

V_VS(SM1)

VS threshold voltage in SM1 startup mode

282 318.3

mV

10

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Unless otherwise stated: V_VDD= 20 V, V_BIN= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ,

V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_VS(SM2)

V_VSLV(UP)

V_VSLV(LR)

t_ZC

VS threshold voltage in SM2 startup mode

458.3

500

543

2.6

mV

V

VS upper threshold out of low output voltage

mode (LV mode)

V_VSincreasing

2.41

2.49

VS lower threshold into low output voltage

mode (LV mode)

V_VSdecreasing

2.3

1.95

23

2.39

2.3

50

2.49

2.73

81

V

Zero-crossing timeout delay

µs

ns

Propagation delay from ZCD high to PWML

10 % high

t_D(ZCD)

V_VSstep from 4 V to -0.1 V

CS INPUT

I_VSL= 0 μA, V_VS≥ V_VSLV(UP)

I_VSL= -333 μA, V_VS≥ V_VSLV(UP)

I_VSL= -666 μA, V_VS≥ V_VSLV(UP)

I_VSL= -1.25 mA, V_VS≥ V_VSLV(UP)

I_VSL= 0 mA, V_VS≤ V_VSLV(LR)

767.4

650

801 836.4

727 788.7

600 651.8

mV

Peak-power threshold on CS pin out of LV

mode

V_CST(MAX)

570

537.2

593.7

546

570

612

628 663.9

570 609.5

540 584.7

153 200.1

V_{CST(MAX)_LV}Peak-power threshold on CS pin in LV mode I_VSL= -666 μA, V_VS≤ V_VSLV(LR)

I_VSL= -1.25 mA, V_VS≤ V_VSLV(LR)

511.2

120.7

V_CST(MIN)

K_LC

Minimum CS threshold voltage

Line-compensation current ratio

V_CSincreasing, I_FB= -85 µA

I_VSL= -1.25 mA, I_VSL/ current out of CS

21.6

78.4

29.3

25

96

36

29

113.6

42.7

A/A

mV

EMI dithering magnitude on CS pin out of LV (V_BUR/ K_BUR-CST) < V_CST< V_CST(MAX)

,

(1)

V_CST(EMI)

mode

I_VSL< -646 μA, V_VS≥ V_VSLV(UP)

V_{CST(EMI)_LV}EMI dithering magnitude on CS pin in LV

(V_BUR/ K_BUR-CST) < V_CST< V_CST(MAX)

I_VSL< -646 μA, V_VS≤ V_VSLV(LR)

,

(1)

mode

V_CST(SM1)

V_CST(SM2)

CS threshold voltage in SM1 startup mode

CS threshold voltage in SM2 startup mode

V_VS< V_VS(SM1)

177.5

470.4

171.2

94.4

200 222.9

500 531.4

190 216.1

mV

ns

V_VS< V_VS(SM2)

V_SET= 5 V, V_CS= 1 V

V_SET= 0 V, V_CS= 1 V

t_CSLEB

Leading-edge-blanking time

108

26

125

ns

Propagation delay of CS comparator high to

PWML 90 % low

t_D(CS)

V_CSstep from 0 V to 1 V

10

20

34.8

ns

(V_BUR/ K_BUR-CST) < V_CST< V_CST(OPP)

I_VSL< -646 μA

,

(1)

f_DITHER

EMI dithering frequency on CS pin

23

27

kHz

BUR INPUT and Low-power MODE

K_BUR-CST

I_BUR(LPM)

I_BUR(AAM)

Ratio of V_BURto V_CST

V_BURbetween 0.7 V and 2.4 V

V_CST> V_BUR/ K_BUR-CST

3.82

2.09

3.76

3.98

2.65

4.85

4.09

3.16

5.81

V/V

µA

Bias source current of V_BURoffset in LPM

Bias sink current of V_BURoffset in AAM

First upper threshold of burst frequency in

ABM

f_BUR(UP1)

f_BUR(UP2)

30.7

41.8

34.4

51.2

38.5

58.9

kHz

Second upper threshold of burst frequency

in ABM

V_VS= 2.2 V

f_BUR(LR)

f_LPM

Lower threshold of burst frequency in ABM

Burst frequency in low-power mode

21.3

23.3

24.5

25

28.1

26.9

kHz

IPC INPUT and SBP2 MODE

Highest programmable V_CSTrange of SBP2

V_{CST_IPC(UP)}

V_IPC= 5 V

373.8

59.3

405 438.5

64

273 307.7

mV

by IPC pin

Ratio of the programmable IPC voltage to

V_CST

K_IPC

V_IPCbetween 1.8 V and 3.8 V

V_IPC= 1 V

68.4 mV/V

mV

Lowest programmable V_CSTrange of SBP2

by IPC pin

V_{CST_IPC(LR)}

247.5

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Unless otherwise stated: V_VDD= 20 V, V_BIN= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ,

V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Minimum V_CSTof SBP2 by grounding IPC

V_{CST_IPC(MIN)}

V_IPC= 0 V

I_FB= -85 µA

128.1

154 191.5

mV

I_IPC(SBP2)

f_SBP2(UP)

f_SBP2(LR)

RUN

Bias source current of V_IPCoffset in SBP2

Upper threshold of burst frequency in SBP2

40.7

6

49

8.5

1.7

55.7

13.4

2

µA

kHz

Lower threshold of burst frequency in SBP2 V_IPC= 2 V

1

V_RUNH

RUN pin high-level

I_RUN= -0.2 mA

4.6

4.78

0.25

5

V

V_RUNL

RUN pin low-level, for UCC28782A only

I_RUN= 1 mA

0.23

0.3

RUN pin low-level, for UCC28782AD,

UCC28782BDL, and UCC28782CD only

V_RUNL

0.1

0.25

0.3

V

V_RUN= 2.3 V

V_RUN= 3 V

33

14

44

20

52

25

1

mA

µs

I_SRC(RUN)

RUN peak source current

t_R(RUN)

t_F(RUN)

PWML

V_PWMLH

V_PWMLL

Turn-on rise time of RUN, from 0 V to 2.5 V C_RUN= 22 nF, V_RUNfrom 0 V to 2.5 V

0.4

0.79

20

Turn-off fall time of RUN, 90 % to 10 %

C_RUN= 10 pF

32

ns

PWML pin high-level

I_PWML= -1 mA

I_PWML= 1 mA

V_PWML= 0 V

12.1 12.85

0.002

13.6

0.1

0.8

2.8

6.1

1.9

53

V

PWML pin low-level

(1)

I_SRC(PWML)

PWML peak source current

PWML peak sink current

0.25

1.2

3.1

0.5

1.9

4.3

1.1

30

A

(1)

I_SNK(PWML)

V_PWML= 13 V

I_PWML= -20 mA

I_PWML= 20 mA

C_PWML= 1.5 nF

V_S13> 11 V

A

R_SRC(PWML)

R_SNK(PWML)

t_R(PWML)

PWML pull-up resistance

Ω

PWML pull-down resistance

Turn-on rise time of PWML, 10 % to 90 %

Turn-off fall time of PWML, 90 % to 10 %

Ω

ns

µs

t_F(PWML)

9

20

t_D(RUN-PWML)Delay from RUN high to PWML high

1.92

68

4.7

7.43

Minimum on-time of PWML in LPM, for

UCC28782A only

t_ON(MIN)

V_SET= 5 V, I_FB= -85 µA, V_CS= 1 V

105 172.5

ns

Minimum on-time of PWML in LPM,

for UCC28782AD, UCC28782BDL, and

UCC28782CD only

t_ON(MIN)

68

105

175

PWMH

V_PWMHH

V_PWMHL

PWMH pin high-level

I_PWMH= -1 mA

I_PWMH= 1 mA

4.39

4.66

4.83

0.21

V

PWMH pin low-level, for UCC28782A only

0.19 0.198

0.1 0.198

PWMH pin low-level, for UCC28782AD,

UCC28782BDL, and UCC28782CD only

V_PWMHL

I_PWMH= 1 mA

0.21

V

V_PWMH= 2.5 V

V_PWMH= 3.5 V

16.5

3.8

21

6

26.2

7.6

mA

I_SRC(PWMH)

PWMH peak source current

Turn-on rise time of PWMH, 10 % to 90 %,

for UCC28782A only

t_R(PWMH)

C_PWMH= 10 pF

8

20

24

ns

Turn-on rise time of PWMH, 10 % to

90 %, for UCC28782AD, UCC28782BDL,

and UCC28782CD only

t_R(PWMH)

C_PWMH= 10 pF

t_F(PWMH)

Turn-off fall time of PWMH, 90 % to 10 %

22

18

29

28

ns

Dead time between VS high and PWMH

10 % high

t_D(VS-PWMH)

10

PROTECTION

V_OVP

Over-voltage threshold

Over-current threshold

V_VSincreasing

V_CSincreasing

4.4

4.55

1.22

4.67

1.27

V

V_OCP

1.14

12

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SLUSDK4D – MAY 2020 – REVISED MAY 2021

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Unless otherwise stated: V_VDD= 20 V, V_BIN= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ,

V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Ratio of over-power threshold to peak-power V_CST(OPP)/ V_CST(MAX), and

K_OPP-PPL

0.72

0.75

0.78

V/V

threshold

V_{CST(OPP)_LV}/ V_{CST(MAX)_LV}

Current out of VS pin increasing

Current out of VS pin decreasing

I_VSL(STOP)/ I_VSL(RUN)

I_VSL(RUN)

I_VSL(STOP)

K_VSL

VS line-sense run current

VS line-sense stop current

VS line sense ratio

313

255

365 408.6

305 336.4

µA

A/A

kΩ

°C

0.72 0.836

0.9

70

R_RDM(TH)

T_J(STOP)

R_RDMthreshold for CS pin fault

Thermal-shutdown temperature

35

55

Internal junction temperature

125

162

Shut-down voltage of V_VDDfor boost output

OVP

V_BOVPTH

21.5

25

20

28.2

23.3

V

Recovery voltage of V_VDDfor boost output

OVP

V_BOVPR

t_OPP

t_BO

16.8

V

OPP fault timer, for UCC28782A only

I_FB= 0 A

133.3

164 201.1

ms

OPP fault timer, for UCC28782AD,

UCC28782BDL, and UCC28782CD only

I_FB= 0 A

130

28.8

1.6

ms

µs

Brown-out detection delay time

I_VSL< I_VSL(STOP)

V_SET= 5 V

55

85.2

2.5

Maximum PWML on-time for detecting CS

pin fault

t_CSF1

2.05

Maximum PWML on-time for detecting CS

pin fault

t_CSF0

t_FDR

R_RDM< R_RDM(TH)for V_SET= 0 V

0.85

1.2

1.05

1.5

1.27

2.22

2.25

µs

s

Fault reset delay timer, for UCC28782A only OCP, OPP, OVP, SCP or CS pin fault

Fault reset delay timer, for UCC28782AD,

OCP, OPP, OVP, SCP or CS pin fault

UCC28782BDL, and UCC28782CD only

1.2

1.5

s

FLT INPUT

V_NTCTH

R_NTCTH

R_NTCR

NTC shut-down voltage

FLT voltage decreasing

R_NTCdecreasing

0.47

8.9

0.5

9.91

23

0.52

11.18

26.4

0.1

V

kΩ

µA

V

NTC shut-down resistance

NTC recovery resistance

R_NTCincreasing

21.2

-0.1

4.3

I_FLT

Input bias current for V_FLTat V_IOVPTH

Shut-down voltage of input OVP

Hysteresis of input OVP

V_FLT= 4.5 V

0

V_IOVPTH

V_IOVPR

FLT voltage increasing

4.5

74

4.67

87

57.7

mV

t_FLT(NTC)

t_FLT(IOVP)

V_FLTZ

Delay time of NTC fault

14

555

50

750

5.5

100

917

µs

Delay time of input OVP fault

Clamp voltage of FLT pin

µs

V

I_FLT= 150 µA

5.08

5.61

RTZ INPUT

Ratio of t_Zat I_VSL= -200 µA to t_Zat I_VSL

= -733 µA

K_TZ

t_Zcompensation ratio

1.27

397.8

56.1

1.41

1.54

s/s

ns

Maximum programmable dead time from

PWMH low to PWML high

t_Z(MAX)

t_Z(MIN)

R_RTZ= 280 kΩ, I_VSL= -1 mA, V_SET= 5 V

R_RTZ= 78.4 kΩ, I_VSL= -1 mA, V_SET= 0 V

478 592.8

70 89.1

Minimum programmable dead time from

PWMH low to PWML high

I_VSL= -200 µA

I_VSL= -450 µA

I_VSL= -733 µA

152.2

129.2

109.7

175 212.7

150 190

125 147.2

ns

t_Z

Dead time from PWMH low to PWML high

SWS INPUT

V_SET= 5 V

V_SET= 0 V

8.1

3.7

8.5

4.04

17

9.1

4.4

V

V_TH(SWS)

SWS zero voltage threshold

t_D(SWS-PWML)Time between SWS low to PWML 10 % high V_SWSstep from 5 V to 0 V

11.4

24.8

ns

FB INPUT

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UCC28782

SLUSDK4D – MAY 2020 – REVISED MAY 2021

www.ti.com

Unless otherwise stated: V_VDD= 20 V, V_BIN= 20 V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_BUR= 1.2 V, V_SET= 0 V, R_NTC= 50 kΩ,

V_VS= 4 V, V_SWS= 0 V, I_FB= 0 μA, C_PWML= 0 pF, C_PWMH= 0 pF, C_REF= 0.22 µF, C_P13= 1 µF, and -40⁰C < T_J= T_A< 125⁰C

PARAMETER

TEST CONDITIONS

MIN

64.2

4.02

7.5

TYP

MAX UNIT

I_FB(SBP)

V_FB(REG)

R_FBI

Maximum control FB current

Regulated FB voltage level

FB input resistance

I_FBincreasing

75

87.1

4.53

9.6

µA

V

4.25

8.3

kΩ

A/s

dI_COMP/dt⁽¹⁾

Slope of internal ramp compensation current

0.192 0.214 0.236

Magnitude of internal ramp compensation

current

I_COMP

4

6.75

8

µA

RDM INPUT

t_DM(MAX)

Maximum PWMH width with maximum

tuning, for UCC28782A only

V_SWS= 12 V

V_SWS= 0 V

6.32

6.0

6.95

3.43

7.53

3.77

µs

Maximum PWMH width with maximum

tuning, for UCC28782AD, UCC28782BDL,

and UCC28782CD only

t_DM(MAX)

t_DM(MIN)

Minimum PWMH width with minimum

tuning, for UCC28782A only

3.11

3.0

Minimum PWMH width with minimum

tuning, for UCC28782AD, UCC28782BDL,

and UCC28782CD only

XCD INPUT (for UCC28782AD, UCC28782BDL, and UCC28782CD only)

V_XCD(LR)

V_XCD(UP)

I_XCD(0)

XCD lower zero-crossing threshold

XCD upper zero-crossing threshold

Leakage current in XCD wait state

First-step XCD sense current

5.9

6.8

6.62

7.5

0.3

0.4

7.2

7.9

V

V_XCD= 15 V

I_XCD= 20 mA

1.7

µA

mA

V

I_XCD(1)

0.32

0.46

0.91

1.6

I_XCD(2)

Second-step XCD sense current

Third-step XCD sense current

Fourth-step XCD sense current

Maximum XCD discharge current

Clamping voltage for XCD OVP

0.61 0.775

I_XCD(3)

0.73

1.2

1.15

1.53

2

I_XCD(4)

1.81

2.5

I_XCD(MAX)

V_XCD(OVP)

1.65

23

26

30

Dwell time for each XCD sense step, for

UCC28782A only

t_XCD(STEP)

10

12

14

ms

Dwell time for each XCD sense step,

for UCC28782AD, UCC28782BDL, and

UCC28782CD only

t_XCD(STEP)

9

t_XCD(MAX)

t_XCD(WAIT)

Maximum XCD discharge time

XCD wait time

230.4

300 373.3

700 1071

ms

(1) Ensured by design, not tested in production

7.6 Typical Characteristics

V_VDD= 20V, R_RDM= 115 kΩ, R_RTZ= 140 kΩ, V_SET= 0 V, and T_J= T_A= 25 ⁰C (unless otherwise noted)

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10

I_RUN

I_WAIT

1

I_RUN(STOP)

I_FAULT

0.1

0.01

1

I_RUN(WAIT)

I_START

0.1

0.001

0

5

10

15

20

25

30

35

40

45

-50

-25

0

25

50

75

100

125

V_VDD- Bias Supply Voltage (V)

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

Figure 7-1. VDD Bias-Supply Current vs. VDD Bias-

Supply Voltage

Figure 7-2. VDD Bias-Supply Current vs.

Temperature

415

4

3

395

(V_CST(MIN)- 0.15 V) / 0.15 V

2

I_VSL(RUN)

375

(V_CST(MAX)- 0.8 V) / 0.8 V

1

355

0

-1

-2

-3

-4

335

I_VSL(STOP)

315

295

275

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

Figure 7-3. VS Line-Sense Currents vs.

Temperature

Figure 7-4. Percentage Variation of Maximum and

Minimum CS Thresholds vs. Temperature

0.9

0.8

V_CST(MAX)at 25öC

0.8

0.7

0.6

0.5

V_{CST(MAX)_LV}at 25öC

V_{CST(MAX)_LV}at -40öC

V_{CST(MAX)_LV}at 125öC

V_CST(MAX)at -40öC

V_CST(MAX)at 125öC

0.7

0.6

0.5

0

200

400

600

800

1000

1200

1400

1600

0

200

400

600

800

1000

1200

1400

1600

I_VSL- VS Line-Sense Current (mA)

Figure 7-5. CS Peak-Power Threshold for V_VS

V_VSLV(UP)vs. VS Line-Sense Currents

>

Figure 7-6. CS Peak-Power Threshold for V_VS

V_VSLV(LR)vs. VS Line-Sense Currents

<

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1.5

1.4

1.3

1.2

1.1

1

4.6

4.56

4.52

4.48

4.44

4.4

K_TZat 25öC

K_TZat -40öC

K_TZat 125öC

0.9

0

200

400

600

800

1000

1200

1400

1600

I_VSL- VS Line-Sense Current (JA)

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

Figure 7-7. t_ZCompensation Ratio (K_TZ) vs. VS

Line-Sense Currents

Figure 7-8. VS Over-Voltage Threshold vs.

Temperature

5.06

5.04

5.02

5

13.1

13

12.9

12.8

12.7

12.6

12.5

4.98

4.96

4.94

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

Figure 7-9. REF Voltage vs. Temperature

Figure 7-10. P13 Voltage vs. Temperature

25

7.6

V_XCD(UP)

23

R_NTCR

7.4

21

19

17

15

13

7.2

7

6.8

11

R_NTCTH

V_XCD(LR)

9

7

5

6.6

6.4

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

Figure 7-12. XCD Thresholds vs. Junction

Temperature

Figure 7-11. FLT OTP Thresholds vs. Junction

Temperature

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2.4

2.3

2.2

2.1

2

370

350

330

310

290

270

1.9

1.8

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

T_J- Çꢀu‰ꢀŒꢁšµŒꢀ ~ö/•

Figure 7-13. Max. XCD Discharge Current vs.

Junction Temperature

Figure 7-14. BSW Peak Current Thresholds vs.

Junction Temperature

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8 Detailed Description

8.1 Overview

The UCC28782 is a transition-mode (TM) active-clamp flyback (ACF) controller equipped with advanced control

schemes to enable significant size reduction of passive components for higher power density and higher

average efficiency. Its control law is optimized for Silicon (Si) and Gallium Nitride (GaN) power FETs in a

half-bridge configuration and is capable of driving high-frequency AC/DC converters up to 1.5 MHz.

The zero-voltage switching (ZVS) control of the UCC28782 is capable of auto-tuning the on-time of a high-side

clamp switch (Q_H) by using a unique lossless ZVS sensing network connected between the switch-node voltage

(V_SW) and theSWS pin. The ACF controller is designed to adaptively achieve targeted full-ZVS or partial-ZVS

conditions for the low-side main switch (Q_L) with minimum circulating energy over wide operating conditions.

Auto-tuning eliminates the risk of losing ZVS due to component tolerance, temperature, and input/output voltage

variations, since the Q_Hon-time is corrected cycle-by-cycle.

Dead-times between PWML (controls Q_L) and PWMH (controls Q_H) are optimally adjusted to help minimize the

circulating energy required for ZVS. Therefore, the overall system efficiency can be significantly improved and

more consistent efficiency can be obtained in mass production of the soft-switching topology. The programming

features of the RTZ, RDM, BUR, IPC, and SET pins provide rich flexibility to optimize the power stage efficiency

across a range of output power and operating frequency levels.

The UCC28782 uses five different operating modes in steady state to maximize efficiency over wide load

and line ranges. Adaptive amplitude modulation (AAM) adjusts the peak primary current at higher load levels.

Adaptive burst mode (ABM) modulates the pulse count of each burst packet in the medium load range. Low

power mode (LPM) reduces the peak primary current of each two-pulse burst packet in the light load range. Two

stand-by power modes (SBP1 and SBP2) minimize the power loss during very light load and no load conditions.

During the system transient events such as the output load step down and output voltage ramp down, V_VDDmay

be reduced close to the 10.5-V UVLO-off threshold, so the survival mode is triggered to maintain V_VDDabove 13

V and to reduce the size of the hold-up VDD capacitor.

The frequency-dither function is active in AAM to help reduce conducted-EMI noise and allow EMI filter size

reduction. The 23-kHz dithering pattern and magnitude are designed to avoid audible noise, minimize efficiency

influence, and desensitize the effect of the output voltage feedback loop response effect on the EMI attenuation.

The two-level dither magnitude is adjusted automatically based on the output voltage level, so dither-induced

output ripple is reduced at lower output voltages to meet more stringent ripple requirements. The dither function

at low line can be programmed into disable mode based on the brown-in voltage setting, so the option provides

design flexibility to balance the worst-case low-line efficiency and EMI. The dither fading feature smoothly

disables the dither signal when the output load is close to the transition point between AAM and ABM. The

23-kHz dither frequency is high enough to allow a higher control-loop bandwidth for improved load transient

response without distorting the dither signal and impairing EMI.

The unique burst mode control in ABM, LPM, and two SBP modes maximizes the light-load efficiency of the ACF

power stage while avoiding the concerns of conventional burst operation - such as high output ripple and audible

noise. The internal ramp compensation can stabilize the burst control loop without an additional compensation

network. The burst control provides an enable signal through the RUN pin to dynamically manage the static

current of the half-bridge driver and also adaptively disables the drive signal of Q_H. The internal drivers of

RUN and PWMH can supply and disconnect the 5-V bias voltage to a digital isolator or a level-shifter through

a small-signal diode. The disconnect switch inside the S13 pin can directly control the 13-V bias voltage to

a low-side GaN driver. These power management functions with RUN, PWMH, and S13 pins can be used to

minimize the quiescent power consumed by those devices during burst off time, further improving the converter’s

light-load efficiency and reducing its stand-by power.

The S13 and IPC pins of the UCC28782 can be adapted to manage an upstream PFC stage to maximize the

light-load efficiency of higher power USB-PD adapters. The S13 pin can supply a 13-V bias voltage to the PFC

controller whenever the ACF controller is in the run state. The pin disconnects the bias voltage during the wait

states of the burst mode operation. When the burst frequency is reduced in very light load conditions, the bias

voltage will decay below UVLO and shut down PFC controller, so the power loss from PFC can be eliminated.

When ACF operates at 5-V and 9-V output levels, the IPC pin can control the gate of an external small signal

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MOSFET to pull down on the COMP pin of the PFC controller. When the power factor requirement is not needed

for the low-power output rails of USB-PD adapters, disabling the PFC converter and controller improves the

average efficiency and standby power significantly.

The PWML output is a strong driver for a Si power MOSFET with high capacitive loading, a GaN-based gate

injection transistor (GIT) with continuous on-state current, or a GaN power IC with logic input. The maximum

voltage level of PWML is clamped at 13 V to balance the conduction loss reduction and gate charge loss of Si

MOSFET. A dedicated driver ground return pin (PGND) minimizes the parasitic impedance and noise coupling

of the PWML gate-drive loop to achieve faster switching speed and reduced turn-off loss of Q_L. The short 15-ns

propagation delay and narrow 110-ns minimum on-time enable more accurate ZVS control and higher switching

frequency operation.

Controller bias power over a wide output voltage range is simplified with the integrated boost regulator of

the UCC28782 using a single auxiliary winding on the primary side. The boost conversion mode provides an

18.5-V regulation level for the VDD pin from the rectified auxiliary-winding voltage at the BIN pin. Compared

to the commonly-used high-voltage linear regulator plus multiple auxiliary windings, the boost-regulator power

consumption, component footprint, and thermal stress can be greatly reduced for a higher power-density design.

The boost switch, regulator control loop, and cycle-by-cycle robust protections are fully integrated. The boost

switch node pin (BSW) and the dedicated regulator ground return pin (BGND) interface with a small external

boost inductor, a boost schottky diode, and filter capacitors needed to form a tight switching loop.

During initial power up or VDD restart, the regulator is disabled and ACF stops switching, so UCC28782

starts up the VDD supply voltage with an external high-voltage depletion-mode MOSFET between the ACF

switch node and the SWS pin. Fast startup is achieved with low stand-by power overhead, compared with

using the conventional high-voltage startup resistance to VDD. Moreover, the P13 pin biases the gate of the

depletion-mode FET to also allow this MOSFET to be used in lossless ZVS-sensing. This arrangement avoids

additional sensing devices.

The enhanced switching control of UCC28782 mitigates excessive drain-to-source voltage stress on a

synchronous rectifier (SR) caused by over-charged clamping capacitor voltage or temporary continuous

conduction mode (CCM), so the power loss of an SR snubber can be reduced for higher efficiency. During

output voltage ramp-down and LPM-to-ABM transition events, a unique PWMH on-time control extends the Q_H

on-time momentarily. This control helps to avoid the case of Q_Hbeing turned off during an instant where a large

voltage-balancing negative current is flowing through Q_Hto equalize an over-charged clamp capacitor voltage

closer to the reflected output voltage. Additional PWML timing controls can avoid premature Q_Lturn-on before

the magnetizing current reaches to zero through an improved zero-crossing detection (ZCD) scheme of the VS

pin.

The UCC28782 also integrates more robust protection features tailored to maximize the system reliability and

safety. These features include active X-capacitor discharge, internal soft start, brown in/out, output over-voltage

(OVP), input line over-voltage (IOVP), output over-power (OPP), system over-temperature (OTP), switch over-

current (OCP), output short-circuit protection (SCP), and pin faults. The controller provides both auto-recovery

and latch-off response options for OVP, OPP, OTP, OCP, and SCP faults.

The X-capacitor discharge function can actively discharge the residual voltage on X2 safety capacitors to a safe

level after AC-line voltage removal is detected through the XCD pins of UCC28782 and its external sensing

circuit. If the AC-line voltage recovers within 2 seconds after the line removal, the controller will reset the fault

state immediately and will attempt to restart without waiting to fully discharge the bulk input capacitor or VDD

capacitor. Grounding the two XCD pins disables this function and eliminates the sensing circuit. Unlike other

conventional flyback controllers, UCC28782 provides the design flexibility of using the X-capacitor discharge

function based on application power level as it is decoupled from VDD startup and brown-in/out detection

functions. Since those two functions are implemented on the SWS and VS pins, respectively, UCC28782

maintains the two functions even when the XCD-related components are fully removed.

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8.2 Functional Block Diagram

BIN

INT_QH_OFF

PWML

INT_STOP

AGND

Survival Mode with

C_CLAMPAuto-Balancing

Switching

Regulator

Control

BSW

XCD

S13_OK

CSOT FAULT

XCD FAULT

RESET

X-Cap Discharge and

Latch Reset Control

BGND

VDD

OCP FAULT

LINE FAULT

LINE OV FAULT

OTP FAULT

P13 FAULT

VDD_OK

UVLO

V_VDD(ON)/ V_VDD(OFF)

OT Detect and

Line OV Detect

OP FAULT

Power and

Fault Management

FLT

OV FAULT

WAIT

T_J

Thermal

Shutdown

TSD FAULT

RUN_EN

S

R

S

R

REF

V_CST(DITHER)

QH_OFF

t_DM

PWMH

P13

Driver

Adaptive

ZVS

Control

TZ COMP

SWS

P13

DITHER_EN

S = Start

R = RUN

PWML

PGND

R

S

Q

Driver

INT_STOP

VDD

R

P13 Regulator

I_VSL

CS Offset

Control

I_CS

ZCD

CS

P13 FAULT

+

V_CST

+

Dynamic Bias

Control

œ

+

V_CST(EMI)

t_CSLEB

OCP FAULT

S13

+

RUN

S13_OK

V_OCP

œ

RDM

RTZ

VS

CSOT FAULT

t_Z

OT Detect

t_DM

SWS

TDM COMP

OV FAULT

TUNE

ZVS

Discriminator

ZCD

NVo

Sensing

SET

IPC

LOW_NVO

WAIT

OP FAULT

QH_OFF

V_CST(EMI)

Zero Crossing

Detect

ZCD

FB

ZCD

Over-Power &

Peak-Power

Protections

V_CST

OP COMP

BUR

Control Law

TZ COMP

Line

Sense

BUR Offset

Control

LINE FAULT

DITHER_EN

I_VSL

INT_QH_OFF

N_SWEND

DITHER_EN

INT_STOP

REF

WAIT

Adaptive Burst

Control

RUN_EN

VDD

PWML

RUN

Driver

REF

REF Regulator

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8.3 Detailed Pin Description

8.3.1 BUR Pin (Programmable Burst Mode)

The voltage at the BUR pin (V_BUR) sets a target peak current-sense threshold at the CS pin (V_CST(BUR)) which

programs the onset of adaptive burst mode (ABM). V_BURalso determines the clamped peak current level of

switching cycles in each burst packet. When V_BURis set higher, ABM will start at heavier output load conditions

with higher peak primary current, so the benefit is higher light-load efficiency but the side effect is larger

burst-mode output voltage ripple. Therefore, 50% to 60% of output load at high line is the recommended highest

load condition to enter ABM (I_O(BUR)) for both Si and GaN-based ACF designs.

The relationship between V_BURand V_CST(BUR)is a constant gain of K_BUR-CST, so targeting V_CST(BUR)just requires

properly selecting the resistor divider on the BUR pin formed by R_BUR1and R_BUR2. V_BURshould be set between

0.7 V and 2.4 V, which constitute internal limits. If V_BURis less than 0.7 V, V_CST(BUR)holds at 0.7 V / K_BUR-CST. If

V_BURis higher than 2.4 V, V_CST(BUR)holds at 2.4 V / K_BUR-CST. Targeting an excessively low or high percentage

of load for entering ABM will engage one of these internal limits.

R

_BUR1K_BUR-CSTV_{CST (BUR)}

4ì R_BUR1V_{CST (BUR)}

R_BUR2

=

V_REF- K_BUR-CSTV_{CST (BUR)}5V - 4ìV_{CST (BUR)}

(1)

In order to enhance the mode transition between ABM and LPM, a programmable offset voltage (ΔV_BUR(LPM)

)

is generated on top of the V_BURsetting in ABM through an internal 2.7-μA current source (I_BUR(LPM)), as shown

in Figure 8-1. In ABM, V_BURis set through the resistor voltage divider to fulfill the target average efficiency. On

transition from ABM to LPM, I_BUR(LPM)is enabled in LPM and flows out of the BUR pin, so ΔV_BUR(LPM)can be

programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

(

//

)

(2)

I_O

I_BUR(LPM)

LPM

REF

ûV_BUR(LPM)

R_BUR1

V_BUR

ûV_BUR(AAM)

BUR

ABM

LPM

R_BUR2

ABM

I_BUR(AAM)

C_BUR

Figure 8-1. Hysteresis Voltage Generation on BUR Pin

When V_BURsteps higher on transition into LPM, the initial peak magnetizing current in LPM is increased with

larger energy per switching cycle in each burst packet. This increases the output voltage which forces higher

feedback current to restore regulation. Higher feedback current causes UCC28782 to stay in LPM, forming a

hysteresis effect. If ΔV_BUR(LPM)is designed too small, it is possible that mode toggling between LPM and ABM

can occur resulting in audible noise. For that situation, ΔV_BUR(LPM)greater than 100 mV is recommended.

To minimize the effects of external noise coupling on V_BUR, a filter capacitor on the BUR pin (C_BUR) may

be needed. C_BURneeds to be properly designed to minimize the delay in generating ΔV_BURduring mode

transitions. It is recommended that C_BURshould be sized small enough to ensure ΔV_BUR(LPM)settles within

40 μs, corresponding to the burst frequency of 25 kHz in LPM (f_LPM). Based on three RC time constants,

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representing 95% of a settled steady-state value from a step response, the design guide for C_BURis expressed

as

R_BUR1+ R_BUR2

C_BURÇ 40ms ì

3R_BUR1R_BUR2

(3)

In order to enhance the mode transition between ABM and AAM, a programmable offset voltage (ΔV_BUR(AAM)

)

is generated to lower the V_BURwith an internal 5-μA pull-down current (I_BUR(AAM)), as shown in Figure 8-1. After

transition from ABM to AAM, I_BUR(AAM)is enabled in AAM and flows into the BUR pin, so ΔV_BUR(AAM)is also

programmed based on the Thevenin resistance on the BUR pin, which can be expressed as

(

//

)

(4)

When V_BURreduces after transition to AAM, the initial peak magnetizing current in AAM is reduced with less

energy per switching cycle, which forces UCC28782 to stay in AAM. If ΔV_BUR(AAM)is too small, it is possible

that either mode toggling between ABM and AAM or low-frequency ABM burst packets less than 20 kHz can

occur and result in audible noise concern. For that situation, ΔV_BUR(AAM)greater than 150 mV is recommended.

In some power stage designs, LPM in hard switching condition may cover a wider output load current range, so

the light-load efficiency in LPM may be lower than ABM with ZVS condition. Besides, the ABM-to-AAM mode

transition may be affected potentially when the load current condition of LPM-to-ABM transition is too close to

the load current condition of ABM-AAM transition.

In order to narrow down the output load current range in LPM, lower V_BUR(ABM), smaller ΔV_BUR(LPM), larger R_OPP

,

and smaller C_CShelp to reduce the peak magnetizing current in LPM. If the LPM energy needs to be further

reduced but V_BURin AAM is limited by the 0.7-V minimum programmable level, the optional application circuit

in Figure 8-2 can be considered. When the output load current is reduced, duty cycle of each burst packet

becomes smaller, so as the duty cycle of RUN-pin voltage. C_BURis discharged by the RUN driver through

the small-signal diode (D_BUR) and the current limit resistor (R_RUN). Proper selection of R_RUNvalue can further

reduce V_BUR(ABM)when the load current is reduced close to the transition point from ABM to LPM. One example

BUR-pin setting is R_BUR1= 182 kΩ, R_BUR2= 37.4 kΩ, C_BUR= 330 pF, and R_RUN= 20 kΩ.

I_O

RUN

R_RUN

REF

D_BUR

V_BUR

R_BUR1

ûV_BUR(AAM)

ûV_BUR(LPM)

BUR

ABM

LPM

R_BUR2

C_BUR

Figure 8-2. Optional Application Circuit to Reduce V_BURin LPM

8.3.2 FB Pin (Feedback Pin)

The FB pin usually connects to the collector of an optocoupler output transistor through an external current-

limiting resistor (R_FB). A maximum of 20 kΩ for R_FBis recommended. The feedback network of UCC28782 is

shown in Figure 8-3. A high-quality ceramic by-pass capacitor between FB pin and REF pin (C_FB) is required for

decoupling I_FBfrom switching noise interference. A minimum of 220 pF is recommended for C_FB. An internal

8-kΩ resistor (R_FBI) at the FB pin in conjunction with the external C_FBforms an effective low-pass filter. Section 9

provides a detailed design guide on the secondary-side compensation network of V_Ofeedback loop, to improve

the load transient response and also limit the I_FBripple of ABM mode within the recommended range.

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V_O

Compensation

Network

REF

FB

C_FB

I_FB

I_OPTO

V_FB(REG)

R_FBI

R_FB

I_FB

I_COMP

+

Internal Ramp

Compensation

-

OPTO

COUPLER

Regulator

RUN

Control

Law

Figure 8-3. External Feedback Network Connected to the FB Pin

Depending on the operating mode, the controller interprets the current flowing out of the FB pin (I_FB) to regulate

the output voltage. For AAM and LPM modes based on peak current control, I_FBis converted into an internal

peak current-sense threshold (V_CST) to modulate the amplitude of the current-sense signal on the CS pin. For

example, when the output voltage (V_O) is lower than the regulation level set by the shunt regulator, the absolute

current level of I_FBreduces, causing a higher V_CSTto increase more power to the output load. In ABM, the burst

control loop takes over the V_Oregulation, where V_CSTis clamped to V_CST(BUR)and the ripple component of I_FB

participates in the modulation of the burst off time.

Figure 8-4 illustrates the operating principle of the ABM. A burst of switching pulses raises the output voltage V_O

which increases I_FB. At the end of the burst, the load current discharges the output capacitor, which decreases

V_Oand I_FB. UCC28782 injects a noise-free internal ramp compensation current (I_COMP) superimposed on I_FBin

order to stabilize the ABM operation. When the RUN pin is high, I_COMPis reset to 0 μA. When the RUN pin goes

low, I_COMPis gradually increased to 6 μA with a positive slope of 0.214 A/s. The summation of I_FBand I_COMP

is compared with I_TH(FB)to trigger the next burst event. The magnitude and sharp slope of I_COMPhelp to push

switching ripple and high-frequency noise component of I_OPTOaway from I_TH(FB)

.

I_FB- I_COMP

I_TH(FB)

0.214 A/s

I_COMP

6µA

I_OPTO≈ I_FB

V_o

PWML

RUN

Figure 8-4. Concept of Burst Control with an Internal Ramp Compensation

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8.3.3 REF Pin (Internal 5-V Bias)

The output of the internal 5-V regulator of the controller is connected to the REF pin. REF provides bias current

to most of the functional blocks in the UCC28782. It requires a high-quality ceramic by-pass capacitor (C_REF) to

AGND to decouple switching noise and to reduce the voltage transients as the controller transitions from wait

state to run state. The minimum C_REFvalue is 0.22 μF, and a high quality dielectric material should be used,

such as a X7R.

The output short-circuit current (I_S(REF)) of the REF regulator is self-limited to approximately 17 mA. 5-V bias

is only available after the under-voltage lock-out (UVLO) circuit enables the operation of UCC28782 after V_VDD

reaches V_VDD(ON). This pin can be used to perform an external shutdown function. A small-signal switch can be

used to pull this pin voltage below the power-good threshold of 4.5V, so the controller will stop switching, force a

VDD restart cycle, and turn off the REF current.

8.3.4 VDD Pin (Device Bias Supply)

The VDD pin is the primary bias for the internal 5-V REF regulator, internal 13-V P13 regulator, other internal

references, and the undervoltage lock-out (UVLO) circuit. As shown in Figure 8-5, the UVLO circuit connected

to the VDD pin controls the internal power-path switches among VDD, P13, and SWS pins, in order to allow an

external depletion-mode MOSFET (Q_S) to be able to perform both V_VDDstartup and switch-node voltage (V_SW

)

sensing for ZVS control after startup. During startup, SWS and P13 pins are connected to VDD pin allowing Q_S

to charge the VDD capacitor (C_VDD) from the V_SW. After VDD startup completes, the ZVS discriminator block

and switching logic are enabled. Then, the transformer starts delivering energy to the output capacitor (C_O)

every switching cycle, so both output voltage (V_O) and auxiliary winding voltage (V_AUX) increase. As V_AUXis

high enough, the auxiliary winding will take over to power V_VDD. The UVLO circuit provides a turn-on threshold

of V_VDD(ON)at 17 V and turn-off threshold of V_VDD(OFF)at 10.6 V. For fixed output voltage ACF converter

designs, the wide V_VDDrange can accommodate lower values of VDD capacitor (C_VDD) and support shorter

power-on delays. For ACF designs requiring wide output voltage range, the integrated switching regulator

converts the rectified V_AUXto an 18.5-V regulation level of V_VDD. Compared with the conventional bias approach

with a high-voltage linear regulator and multiple auxiliary windings, the footprint and conversion efficiency of the

integrated switching regulator are improved greatly. For a wide-output design using the bias regulator, a 10 to

15-µF ceramic VDD capacitor is recommended to hold up V_VDDduring soft start and to provide decoupling for

the regulator switching loop. Section 8.4.10 of this datasheet describes the details on the startup sequencing

with the switching regulator.

For a fixed output voltage design, both the BIN and BSW pins should be shorted to BGND, and the rectified

V_AUXis directly connected to the VDD pin. As V_VDDreaches V_VDD(ON), the SWS pin is disconnected from the

VDD pin by the internal power path switch, so the C_VDDsize has to be sufficient to hold V_VDDhigher than

V_VDD(OFF)until the positive auxiliary winding voltage is high enough to take over bias power delivery during V_O

soft start. Therefore, the calculation of minimum capacitance (C_VDD(MIN)) needs to consider the discharging effect

from the sink current of the UCC28782 during switching in its run state (I_RUN(SW)), the average operating current

of driver (I_DR), and the average gate charge current of half-bridge FETs (I_Qg) throughout the longest time of V_O

soft start (t_SS(MAX)).

(I_{RUN (SW )}+ I_DR+ I_Qg)t_{SS(MAX )}

C_{VDD(MIN )}

=

V_{VDD(ON )}-V_{VDD(OFF )}

(5)

t_SS(MAX)estimation should consider the averaged soft-start current (I_SEC(SS)) on the secondary side of ACF, the

constant-current output load (I_O(SS)) (if any), maximum output capacitance (C_O(MAX)), and a 0.7-ms time-out

potentially being triggered in the startup sequence. 1 ms is applied in the equation to be the worst-case condition

of the 0.7-ms timer.

C_{O(MAX )}V_O

t_{SS(MAX )}

=

+1ms

I_{SEC(SS )}- I_{O(SS )}

(6)

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During V_Osoft start, V_CSTreaches the maximum current threshold on the CS pin (V_CST(MAX)) , so I_SEC(SS)at the

minimum voltage of the input bulk capacitor (V_BULK(MIN)) can be approximated as:

N_PSV_{CST (MAX )}

V_{BULK (MIN )}

I_{SEC(SS )}

=

2R_CS

V_{BULK (MIN )}+ N_PS(V_O+V_F)

(7)

where R_CSis the current sense resistor, N_PSis primary-to-secondary turns ratio, and V_Fis the forward voltage

drop of the secondary rectifier.

8.3.5 P13 and SWS Pins

The P13 pin provides a regulated voltage to the gate of the depletion-mode MOSFET (Q_S), enabling Q_Sto serve

both V_VDDstart-up and loss-less ZVS-sensing from the high-voltage switch node (V_SW) through the SWS pin.

During V_VDDstart-up, the UVLO circuit controls two power-path switches connecting SWS and P13 pins to VDD

pin with two internal current-limit resistors (R_DDSand R_DDH), as shown in Figure 8-5. In this configuration, Q_S

behaves as a current source to charge the VDD capacitor (C_VDD). R_DDSis set at 5 kΩ when V_VDD< 1.8 V to

limit the maximum fault current under a VDD short-to-GND condition. R_DDSis reduced to 500 Ω when V_VDD

>

1.8 V to allow V_VDDto charge faster. The maximum charge current (I_SWS) is affected by R_DDS, the external series

resistance (R_SWS) from SWS pin to Q_S, and the threshold voltage of Q_S(V_TH(Qs)). I_SWScan be calculated as

V_{TH (Qs)}

I_SWS

=

R_DDS+ R_SWS

(8)

C_VDD

UVLO

VDD

I_SWS

R_DDS

R_SWS

SWS

P13

V_SW

+

V_TH(Qs)

-

C_SWS

Q_S

R_DDH

D_SWS

C_P13

D_P13

Figure 8-5. Operation of the VDD Startup Circuit

After V_VDDreaches V_VDD(ON), the two power-path switches open the connections between SWS, P13, and VDD

pins. At this point, a third power-path switch connects an internal 13-V regulator to the P13 pin for configuring

Q_Sto perform loss-less ZVS sensing. Since Q_Sgate is fixed at 13 V, when the drain pin voltage of Q_Sbecomes

higher than the sum of Q_Sthreshold voltage (V_TH(Qs)) and the 13-V gate voltage, Q_Sturns off and the source

pin voltage of Q_Scan no longer follow the drain pin voltage change. This gate control method makes Q_Sact as

a high-voltage blocking device with the drain pin connected to V_SW. When the controller is switching, whenever

V_SWis lower than 13 V, Q_Sturns on and forces the source pin voltage to follow V_SW, becoming a replica of the

V_SWwaveform at the lower voltage level, as illustrated in Figure 8-6.

The limited window for monitoring the V_SWwaveform is sufficient for ZVS control of the UCC28782, since the

ZVS tuning threshold (V_TH(SWS)) is set at 8.5 V for V_SET= 5 V and set at 4 V for V_SET= 0 V. The 8.5-V threshold

is the auto-tuning target of the internal adaptive ZVS control loop for realizing a partial-ZVS condition on an ACF

using Si primary switches. On the other hand, performing full ZVS operation is more suitable for an ACF with

GaN primary switches. Using a 4-V threshold helps to compensate for sensing delay between V_SWand the SWS

pin.

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The internal 13-V regulator requires a high-quality ceramic by-pass capacitor (C_P13) between the P13 pin and

AGND pin for noise filtering and providing compensation to the P13 regulator. The minimum C_P13value is 1 μF

and an X7R-type dielectric capacitor with 25-V rating or better is recommended. The controller enters a fault

state if the P13 pin is open or shorted to AGND during V_VDDstart-up, or if V_P13overshoot is higher than V_P13(OV)

of 15 V in run state. The output short-circuit current of P13 regulator (I_P13(MAX)) is self-limited to approximately

130 mA.

During AAM and ABM if the negative magnetizing current is large enough, a low-side GaN device may operate

in the reverse conduction condition before it turns on each switching cycle, so V_SWmay be around -5 V for a

brief inteval and it appears on the SWS pin. The SWS-pin design of UCC28782 can sustain -6 V (continuous)

and -10 V (transient) stress to enhance the robust operation of the GaN ACF power stage.

During this interval, Q_Sis in the on-state and its body diode may conduct for a short time when the voltage drop

across the on-state resistance of Q_Sis high enough. The external R_SWScan limit the forward current flowing

through the Q_Sbody diode, so the reverse recovery charge of the body diode can be significantly reduced. Too

high of R_SWSvalue weakens the start-up charge current of C_VDDand results in a longer start-up time. R_SWS

should be slightly higher than 500 Ω. A small back-to-back TVS across BSS126 gate-to-source should be added

to protect the gate-to-source voltage from potential abnormal voltage stress. The TVS clamping voltage should

be less than the BSS126 gate-to-source voltage rating but should not conduct below 15 V.

R_SWSand a ceramic capacitor (C_SWS) between the SWS pin and the bulk input capacitor ground form a small

sensing delay to help the internal detection circuit to identify the ZVS characteristic correctly. The delay is to

ensure that the ZCD detection on the VS pin happens earlier than the ZVS detection on the SWS pin, such that

the ZVS control can auto-tune the PWMH on-time in the proper direction. The minimum value of C_SWSis 22 pF.

C_VDD

VDD

V_SW

V_BULK+N_PS(V_O+V_F)

R_SWS

ZVS

Discriminator

SWS

P13

V_SW

+

V_TH(Qs)

-

C_SWS

Q_S

V_SWS

13V+V_TH(Qs)

0V

13-V Regulator

D_SWS

C_P13

D_P13

PWML

Figure 8-6. ZVS Sensing by Reusing the VDD Startup Circuit

8.3.6 S13 Pin

As shown in Figure 8-7, the S13 pin (switched 13-V rail) is used to perform bias-power management for a

low-side GaN power IC of ACF, along with an example application where it also powers a PFC controller. This

configuration enables to minimize the power-loss contribution to so-called "tiny-load" input power and stand-by

power. One example of tiny-load input power requirement is that the input power must be less than 0.5 W with

an output load of 0.25 W at 20 V.

S13 is sourced by P13 through an internal 2.8-Ω switch controlled by the RUN pin. Figure 8-8 illustrates the

power-up sequence of the S13 pin. When RUN is high, the S13 decoupling capacitor is charged up to 13 V and

the charge current is controlled by an internal soft-start current limiter. The S13-pin voltage must increase above

the 10-V power-good threshold (V_S13(OK)) in order to initiate PWML switching of each burst cycle. When RUN is

low, V_S13is discharged by the loading on S13. The power-on delay of the GaN power IC on the S13 pin must

be less than 2 µs to be responsive to PWML. If not, the VDD or P13 pin may be a more suitable bias supply for

devices with long power-on delay, but the wait-state power consumption will be compromised. A 22-nF ceramic

capacitor as C_S13(ACF)is recommended. If the S13 pin is not used, it can be connected to the P13 pin in order to

eliminate the delay effect on PWML switching in every low-frequency burst cycle.

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GaN

+

Driver

R_S13D_S13

VCC

PFC

Controller

C_S13(ACF)

C_S13(PFC)

R_OPP

R_IPC

COMP

GND

S13

CS

Q_IPC

R_IPC3

R_CS

UCC28782

C_IPC

R_IPC2

IPC

D_IPC

Figure 8-7. Power Management Function for the ACF GaN Power IC and PFC Controller

RUN

t_D(RUN-PWML)

PWML

13V

V_P13

V_S13(OK)

10V

V_S13

0V

S13_OK

I_S13(OCP)

I_S13

Figure 8-8. Power-up Sequence of the S13 Pin

When the S13 pin supplies both an ACF GaN power IC and a PFC controller at the same time, a low-voltage

rectifier diode (D_S13) between the S13 pin and the PFC controller bias VCC pin is needed, so the local

decoupling capacitor for each powered device can be separated. The decoupling capacitor of the PFC controller

(C_S13(PFC)) is usually larger than the one for a GaN power IC, such that the bias voltage of the GaN power IC will

discharge more quickly without affecting the PFC bias voltage and PFC output voltage regulation. If the S13 pin

supplies a PFC controller only, the rectifier diode is not needed.

During start-up before VDD reaches the V_VDD(ON)threshold, the S13 switch stays off, so the S13-pin loading will

not consume any of the charging current of VDD capacitor flowing from SWS pin to VDD pin, thereby enabling

a fast start-up sequence. Under this condition, the PFC controller will be off resulting in a lower PFC bus voltage

below 400 V. For USB-PD adapter applications, the output voltage start-up condition is 5V/0A before the PD

power path switch between ACF output and USB-C port is applied. Hence, there is no need for the PFC bus

voltage to be immediately regulated to 400 V before ACF starts switching. Even for non USB-PD applications,

the integrated bias regulator of UCC28782 is able to perform 18.5-V VDD regulation when the output voltage is

at a very low level, so the S13 function still allows the PFC bus voltage to build up at the beginning of output

voltage start-up.

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8.3.7 IPC Pin (Intelligent Power Control Pin)

Under certain conditions, the IPC pin provides a 50-µA current from an internal source (I_IPC(SBP2)) which is

controlled by logic as shown in Figure 8-9. The voltage on the VS pin is sampled during the demagnetization

time to obtain an indication of the reflected output voltage (NVO). When the VS-pin voltage is lower than the

2.4-V lower LV mode threshold (V_VSLV(LR)), the LOW_NVO logic signal is pulled high, and the current source is

enabled during the run state of all normal control modes (SBP1, SBP2, LPM, ABM, and AAM).

When the sampled VS-pin voltage is higher than the 2.5-V upper LV mode threshold (V_VSLV(UP)), the LOW_NVO

logic signal becomes low. In the LOW_NVO = 0 V case, the 50-µA current source is enabled in the run state of

SBP2 mode only.

To minimize stand-by power, the 50-µA source is always disabled during the wait state of any control mode.

Additionally, if V_VDDfalls lower than the 13-V survival-mode threshold, the INT_STOP logic signal is pulled high

and the current source is disabled during survival mode operation, irrespective of the V_VSlevel.

LOW_NVO

I_IPC(SBP2)

INT_STOP

RUN

IPC

R_IPC

SBP2

Figure 8-9. Control Circuit Diagram to the IPC-Pin Current Source

The multi-function IPC pin can be programmed to obtain one or more of the following benefits:

1. Reduction of input power for special light-load and stand-by conditions.

2. Improvement of light-load efficiency at lower output voltages, such as 5 V and 9 V.

3. Reduction of burst-mode output ripple at lower output voltages.

4. Reduction of the over-power limit at lower output voltages.

5. Power management of a PFC controller, together with the S13 pin.

To implement the 1st benefit, a resistor R_IPCis connected from IPC pin to AGND pin. The 50-µA current source

establishes a voltage (V_IPC) across R_IPCto program an increase in the CS-pin peak primary current threshold at

very light loads. The transfer function between V_IPCand the CS threshold (V_{CST_IPC}) in SBP2 mode is illustrated

in Figure 8-10.

Proper sizing of R_IPCto AGND can further reduce the burst frequency in SBP2 for so-called "tiny-load" power

and for stand-by power. An example of a tiny-load input power specification is that the input power must be less

than 0.5 W when the output power is 0.25 W at the 20-V output. An example of a stand-by power specification is

that the input power must be less than 75 mW at no load at the 5-V output.

When V_IPCis less than 0.9 V (or IPC is shorted to AGND), V_{CST_IPC}threshold stays at the minimum level of

0.15 V. When V_IPCis set between 0.9 V and 1.8V, V_{CST_IPC}is clamped at 0.27 V. For V_IPCbetween 1.8 V and

3.8 V, there is a linear programmable V_{CST_IPC}range between 0.27 V and 0.4 V. When V_IPCis greater than 3.8

V, V_{CST_IPC}remains clamped to 0.4 V. Be aware that high settings of V_{CST_IPC}may, in some cases, introduce

higher output ripple in deep light-load condition or provoke audible noise.

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V_CST

V_{CST_IPC(UP)}

0.4V

V_{CST_IPC(LR)}

0.27V

0.15V

V_{CST_IPC(MIN)}

V_IPC

0V

0.9V

1.8V

3.8V

5V

Figure 8-10. IPC Transfer Function to Program the SBP2 Peak Current Threshold

Since the enable status of the IPC current source contains the very useful output voltage information from the

LOW_NVO logic state, the IPC pin can be used to further optimize power stage performance over a wide output

voltage range. To gain the 2nd, 3rd, and 4th benefits of the IPC function, R_IPCshould be connected between the

IPC pin and the CS pin, so that the current source can create additional CS-pin offset voltage on R_OPPwhen V_VS

< 2.4 V. With higher CS offset, the operating range of the V_CSTsignal will be higher than the actual power stage

peak current. This forces the controller to operate in AAM mode for a wider actual output load range, and forces

the burst-mode threshold down to a lower power level.

For 100-W USB-PD adapters as example, the 20-V output is designed to deliver 100 W full power, but the 5-V

output requires only 15 W full power. When the 20-V output enters ABM below 50 W, the majority of the 5-V

output load range may operate in burst mode. Figure 8-11 compares the control law difference between the two

IPC-pin connections.

When R_IPCis connected to AGND, the peak magnetizing current (i_M(+)) correlated with the V_CST(BUR)setting of

the higher power 20-V output is too high for the lower-power 5-V output. With higher energy per cycle at the

5-V output, the AAM mode must transition into ABM mode at a heavier load condition, and the hard switching

operating modes such as LPM will cover a wider output load range. Therefore, the 5-V average efficiency is

impaired by the hard switching operation, and the output ripple is compromised by the burst mode setting.

When the R_IPCis connected to CS, however, the output voltage feedback loop increases the V_CSTlevel to

overcome the CS offset voltage in AAM, such that the AAM-ABM transition point can be pushed to a lighter

output load. Since the output load range covered by the soft switching operating modes (AAM and ABM) is

extended with this IPC configuration, the average efficiency at the low-power voltage levels can be improved.

Moreover, since the peak current becomes lower in burst mode, the output ripple magnitude is reduced as well.

Figure 8-11 points out the side effect of the IPC-to-CS connection if the R_IPCsetting is the same. Since 50 µA

is enabled in the run state of SBP2, the lower peak magnetizing current of the IPC-to-CS connection makes the

SBP2 burst frequency higher and results in weakening the stand-by power improvement. Therefore, a higher

R_IPCis needed to increase V_{CST_IPC}to compensate the peak current change.

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20 V / 100 W

5 V / 15 W

Hard Switching

(LPM, SBP1, SBP2)

Soft Switching

(AAM, ABM)

V_CST

Soft Switching

(AAM, ABM)

50µA·R_OPP

V_CST(BUR)

P_O

I_M(+)

R_IPCto AGND

R_IPCto CS

R_IPCto AGND

R_IPCto CS

P_O

15W

100W

Figure 8-11. Effect of the CS-pin Offset Voltage from the IPC Pin

For the 5th benefit, the IPC pin can also be used to disable a PFC controller (if used) at all load conditions for

5-V and 9-V outputs to further improve the light-load efficiency of higher power adapters. As shown in Figure 8-7,

the diode D_IPCin series with R_IPCis placed between IPC and CS pins, and V_IPCestablished at IPC is used to

drive a small-signal switch Q_IPCto disable the PFC controller such as UCC28056.

When V_IPCis higher than its threshold voltage, Q_IPCcan pull low the COMP pin voltage of a PFC controller, so

its switching is disabled. As a consequence, PFC output voltage drops from the typical 400-V regulation level to

the peak value of the AC line. This lowers the ACF bulk voltage, which reduces the ZVS energy, which increases

ACF power stage efficiency for low voltage outputs. Furthermore, the power loss of the PFC power stage is out

of the efficiency equation. One design example for those components are C_S13(ACF)= 22 nF, C_S13(PFC)= 0.22 µF,

C_IPC= 10 nF, R_IPC= 69.8 kΩ, R_IPC2= 10 MΩ, and R_IPC3= 20 kΩ. Choose Q_IPCwith threshold voltage less than

1.5 V to ensure that V_IPCis sufficient to achieve low Rds(on) even at very low burst frequencies.

8.3.8 RUN Pin (Driver and Bias Source for Isolator)

The RUN pin is a logic-level output signal which enables PWM switching when active high. When RUN is low, all

PWML and PWMH switching is disabled and the controller enters a low-current wait state. (The boost regulator,

however, operates independently of the RUN signal.)

In addition to enabling switching, RUN is capable of sourcing considerable current to bias an external gate driver

and perform a power management function to a high-side digital isolator. It generates a 5-V logic output when

the driver should be active, and pulls down to less than 0.5 V when the driver should be disabled. During the

off-time of any burst mode, the RUN pin serves as a power-management function to dynamically reduce the

static bias current of the isolator/ driver, so light-load efficiency can be further improved and stand-by power can

be minimized.

As RUN goes high, while its voltage is less than 3 V, a 44-mA peak pull-up current is supplied from the internal

P13 regulator. With this current, the RUN driver can quickly charge the primary-side decoupling capacitor of

a digital isolator above its UVLO(ON) threshold. A Schottky diode can block discharge of this capacitor when

RUN goes low. When the RUN voltage goes above 3 V, P13 stops providing current and the pull-up is supplied

from the REF regulator, so the peak driving capability will be limited in order to avoid triggering the over-current

protection of the REF regulator. When RUN is low for a long burst off-time, the decoupling capacitor of the

digital isolator will be gradually discharged below its UVLO(OFF) threshold, so the isolator power loss can be

minimized.

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There are three delays between RUN going high to the first PWML pulse going high in each burst packet. The

first delay is a fixed 2.2-μs delay time, intended to provide an appropriate "wake-up" time for UCC28782 and

the gate driver to transition from a wait state to a run state. The second delay is gated by the 10-V power-good

threshold of the S13 pin. PWML will not go high until S13 voltage exceeds 10 V. The third delay is another

2.2-μs timeout, t_ZCin the electrical table, intended to turn on the low-side switch of the first switching cycle per

burst packet around the valley point of DCM ringing by waiting for the zero-crossing detection (ZCD) on the

auxiliary winding voltage (V_AUX). If ZCD is detected (on the VS input) before the t_ZCtimeout elapses, PWML

is immediately driven. If no ZCD is detected, PWML is driven when t_ZCelapses. The first two delays can be

concurrent; the third delay is sequential.

Therefore, the minimum total delay time is 2.2 μs typically if V_S13> 10 V and ZCD is detected immediately

after the 2.2-μs wake-up time. If V_S13< 10 V, the total delay time with tolerance over temperature is listed as

t_D(RUN-PWML)in the electrical table.

PWMH

RUN

D_RUN

VCC1

PWML

UCC28782

C_RUN

Digital

Isolator

V_RUN

IN

PWMH

AGND

V_CC1

≈ 3V

V_CC1(UVLO+)

GND

0V

Figure 8-12. Power Management Function for the Digital Isolator

8.3.9 PWMH and AGND Pins

The PWMH pin controls the gate of the high-side clamp switch through an external high-voltage gate driver. The

PWMH driver ground return is referenced to the AGND pin. The maximum voltage level of PWMH is clamped to

5-V REF level. As PWMH goes high, when its voltage is less than 3 V, a 21-mA peak pull-up current is supplied

from the P13 regulator. When the PWMH voltage goes above 3 V, the pull-up is supplied from the REF regulator

instead, so the peak driving capability will be limited less than 6 mA in order to avoid the high current loading

from tripping the over current protection of the REF regulator.

As shown in Figure 8-12, since the RUN driver charges the decoupling capacitor of a digital isolator first through

one small-signal diode at the beginning of every burst cycle, the sourcing current of PWMH is sufficient to

send the control signal to the isolator and supply the continuous isolator operating current together with the

RUN driver at the same time through another small-signal diode. The high peak driving capability of PWMH

provides the flexibility of signal transmission through a digitally isolated gate-driver with opto-compatible input.

If the PWMH pin is provided to a half-bridge GaN device with an internal high side driver, the PWMH driver is

mainly treated as a logic signal output.

In any case, it is prudent to choose a high-side isolator or gate-driver with minimal power-up delay on both input

and output sides to avoid missing several PWMH pulses to the high-side switch. Furthermore, signal transfer

from input to output should be edge-triggered to avoid asynchronous high-side turn-on in the middle of a PWMH

pulse, as may happen with level-triggered isolators. This can avoid high-side switch turn-off during significant

current and its resultant voltage spike.

AGND pin is the ground return for all the analog control signals, RUN driver, and PWMH driver. It is required to

implement a careful layout separation from other noisy ground return paths, such as PGND, BGND, and power

stage ground. The thermal pad should be connected to the AGND pin directly and could be a Kelvin connection

point to the related external components. For details of the grounding layout guideline and noise decoupling

techniques, one can refer to the Section 9.1 of this datasheet.

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8.3.10 PWML and PGND Pins

The PWML pin is the low-side switch gate-drive, for which ground return is referenced to the PGND pin. The

strong driver with 0.5-A peak source and 1.9-A peak sink capability can control either a silicon power MOSFET

with a higher gate-to-source capacitance, a cascode GaN, an E-mode gate-injection-transistor (GIT) GaN with

continuous on-state current, or a GaN power IC with logic PWM input. The maximum voltage level of PWML is

clamped to the P13 pin voltage. The 13-V clamped gate voltage provides an optimal gate-drive for low on-state

resistance and lower gate-driving loss. An external gate resistor in parallel with a fast recovery diode can be

used to further reduce the turn on speed without compromising the turn off switching loss. Slower turn on

speed mitigates the voltage stress across the secondary-side rectifier when the high-side switch is disabled

in deep light load condition, and reduces the switching-node dV/dt to a safe level for reducing stress on the

high-voltage high side driver. A decoupling capacitor much larger than the PWML capacitive loading should be

placed between P13 and PGND pins to decouple the gate drive loop to allow operation at higher switching

frequency. The 15-ns propagation delay of the PWML driver enables a higher frequency operation and more

consistent ZVS switching.

Figure 8-13 shows the example PWML driving network for a GIT GaN device and for a silicon MOSFET. The

turn on speed is controlled by R_G2. The turn off speed can be maintained by the two fast recovery diodes, D_G1

and D_G2. R_G1provides a continuous driving path to maintain the on state and low R_DS(on)of a GIT GaN. C_G

avoids the small R_G2from affecting the on state current. PGND can be directly connected to the separate source

terminal of a GIT GaN to achieve a kelvin connection, so the driver loop parasitic inductance can be decoupled.

Driving a GIT GaN Device

Driving a Si MOSFET

Q_L

UCC28782

R_G1

R_G

D_G

PWML

C_G

R_G2

D_G2

AGND

PGND

AGND

L_Stray

R_CS

L_Stray

R_CS

D_G1

Figure 8-13. The PWML Driver and the PGND Driver Ground Return

An internal low-voltage level shifter is included between PGND and the ground return pin for analog control

signals (AGND), so PGND can be connected separately to the top of the current sense resistor (R_CS) to

achieve a Kelvin connection. When hard switching condition occurs, the lumped parasitic capacitor on the

switch node is discharged, so a positive voltage spike is created across R_CS. In soft switching condition, the

negative magnetizing current flowing through R_CScan create a negative voltage spike on R_CS. The level shifter

is designed to handle 5-V positive transient spike and -1-V negative stress between PGND pin and AGND pin.

8.3.11 SET Pin

Due to different capacitance non-linearity between Si and GaN power FETs as well as different propagation

delays of their drivers, the SET pin is provided to program critical parameters of UCC28782 for the two different

power stages. Firstly, this pin sets the zero voltage threshold (V_TH(SWS)) at the SWS input pin to be two different

auto-tuning targets for ZVS control. When SET pin is tied to AGND, V_TH(SWS)is set at its low level of 4 V for

realizing full ZVS, which allows the low-side switch (Q_L) to be turned on when the switch-node voltage drops

close to 0 V. When SET pin is tied to REF pin, V_TH(SWS)is set at 8.5 V for implementing partial ZVS, which

makes Q_Lturn on at around 8.5 V. Secondly, the SET pin also selects the current sense leading edge blanking

time (t_CSLEB) to accommodate different delays of the gate drivers; 110 ns for V_SET= 0 V and 190 ns for V_SET= 5

V. Thirdly, the minimum PWML on-time (t_ON(MIN)) in low-power mode and standby-power mode is 110 ns for V_SET

= 0 V, and is 100 ns for V_SET= 5 V. Finally, the maximum PWML on-time to detect CS pin fault (t_CSF). t_CSFfor

V_SET= 5 V (t_CSF1) is set at 2 μs. t_CSFfor V_SET= 0 V (t_CSF0) depends on R_RDM, which is configured to 1 μs under

R_RDM< R_RDM(TH)and to 2 μs under R_RDM≥ R_RDM(TH)

.

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8.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)

The dead-time between PWMH falling edge and PWML rising edge (t_Z) serves as the wait time for V_SW

transition from its high level down to the target ZVS point. Since the optimal t_Zvaries with V_BULK, the internal

dead-time optimizer automatically extends t_Zas V_BULKis less than the highest voltage of the input bulk capacitor

(V_BULK(MAX)). The circulating energy for ZVS can be further reduced, obtaining higher efficiency at low line

versus a fixed dead-time over a wide line voltage range. A resistor on the RTZ pin (R_RTZ) programs the minimum

t_Z(t_Z(MIN)) at V_BULK(MAX), which is the sum of the propagation delay of the high-side driver (t_D(DR)) and the

minimum resonant transition time of V_SWfalling edge (t_LC(MIN)).

(9)

where K_RTZis equal to 11.2×10¹¹(unit: F^-1) for V_SET= 0 V, and 5.6×10¹¹(unit: F^-1) for V_SET= 5 V.

V_SW

N_PS(V_O+V_F)

V_BULK(MAX)

I_M

I_M-

t_D(DR)

t_LC(MIN)

t_Z(MIN)

PWMH

PWML

Figure 8-14. RTZ Setting for the Falling-edge Transition of V_SW

As illustrated in Figure 8-14, when PWMH turns off Q_Hafter t_D(DR)delay, the negative magnetizing current

(i_M-) becomes an initial condition of the resonant tank formed by magnetizing inductance (L_M) and the

switch-node capacitance (C_SW). C_SWis the total capacitive loading on the switch-node, including all junction

capacitance (C_OSS) of switching devices, stray capacitance of the boot-strap diode, intra-winding capacitance

of the transformer, the snubber capacitor, and parasitic capacitance of the PCB traces between switch-node

and ground. Unlike a conventional valley-switching flyback converter, the resonance of an active clamp flyback

converter at high line does not begin at the peak of the sinusoidal trajectory. The transition time of V_SWtakes

less than half of the resonant period. The following t_LC(MIN)expression quantifies the transition time for R_RTZ

calculation, where an arccosine term represents the initial angle at the beginning of resonance. As an example,

the value of π minus the arccosine term at V_BULK(MAX)of 375 V, V_Oof 20 V, and N_PSof 5 is around 0.585π,

which is close to one quarter of the resonant period.

N_PS(V_O+V_F)

V_{BULK (MAX )}

t_{LC(MIN )}= [

p

- cos^-1(

)]ì L_MC_SW

(10)

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8.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)

The R_RDMresistor provides the power stage information to the t_DMoptimizer for auto-tuning the on-time of

PWMH to achieve ZVS within a given t_Zdischarge time. The following equation calculates the resistance, based

on the knowledge of the primary magnetizing inductance (L_M), auxiliary-to-primary turns ratio (N_A/N_P), the values

of the resistor divider (R_VS1and R_VS2) from the auxiliary winding to VS pin, and the current sense resistor (R_CS).

Among those parameters, L_Mcontributes the most variation due to its typically wider tolerance. The optimizer

is equipped with wide enough on-time tuning range of PWMH to cover tolerance errors. Therefore, just typical

values are enough for the calculation.

N_AR_{VS 2}

K_DML_M

R_RDM

=

N_P(R_VS1+ R_{VS 2}) R_CS

(11)

where K_DMis equal to 5.25×10⁹(unit: F^-1) for both V_SET= 5 V and 0 V.

8.3.14 BIN, BSW, and BGND Pins

A high-impedance resistor is integrated inside the BIN pin to sense the bias regulator input voltage and

determine the regulator operating mode. A 30-V rated MOSFET (Q_BSW) with 1.4-Ω R_DS(on)is integrated in

the controller, whose drain is connected to the BSW pin and the source is to the BGND pin. When V_BINis less

than the 2.2-V UVLO(ON) threshold (V_BIN(ON)) and V_VDDis still higher than the 13-V survival mode threshold

(V_VDD(PCT)+ V_VDD(OFF)), the regulator remains in the disabled condition. If the survival mode is triggered by

V_VDD< 13 V, Q_BSWis forced to switch regardless of V_BIN< V_BIN(ON)or not, and the regulator operates in

continuous conduction mode (CCM) to charge C_VDDquickly. If V_VDD> 13 V, Q_BSWswitching is enabled when

V_BIN> V_BIN(ON), and the regulator operates in transition mode or discontinuous conduction mode (DCM) to

boost V_VDDto the 18.5-V regulation level (V_VDD(BOOST)). When the regulator starts switching, the 190-ns leading

edge blanking time of Q_BSWis used to sample V_BINfor under-voltage. If V_BINdrops below the 1-V UVLO(OFF)

threshold (V_BIN(ON)- V_BIN(OFF)), the regulator switching will be terminated immediately.

When the ACF output voltage increases and V_BINreaches to the 15-V boost disable threshold (V_BIN(EN)

+

V_BIN(DIS)), so the regulator will stop switching and V_VDDis directly supplied from the rectified auxiliary winding

voltage through the boost inductor and boost diode. When V_BINdrops below the 14.8-V boost enable threshold

(V_BIN(EN)), the switching regulator will take over boosting of the VDD supply.

Two separate capacitors are recommended for the regulator input capacitor bank of the BIN pin. One is placed

closer to the auxiliary winding and its rectification diode, so the switching loop of the primary auxiliary winding

output can be minimized. A 33-µF chip ceramic capacitor is recommended for energy storage. The other

capacitor is placed closer to the boost inductor, BSW, and BGND pins, so the regulator input switching loop

can be reduced as well. A 10-µF chip ceramic capacitor is recommended for high-frequency decoupling. Ground

return of the regulator output capacitor (C_VDD) should be connected back to the BGND pin as close as possible

in order to minimize the regulator output switching loop area. Rather than with the BGND pin, the low-noise

ground terminal of C_VDDshould be used to connect the BGND net to the AGND pin with a low impedance copper

trace or copper pour.

When the boost inductor current flowing through Q_BSWreaches to the 0.33-A peak current threshold, Q_BSW

turns off in every boost switching cycle. A 30-V rated Schottky diode with higher than 0.4-A rated peak current

capability is needed between the BSW and VDD pins in order to handle the 0.33-A switching current. The boost

inductor between the BIN and BSW pins should support higher than 0.4-A saturation current capability. Higher

current peaks may ring through the inductor whenever C_BINis charged higher than C_VDD

.

As the following equation shows, the inductance (L_B) is determined based on the largest total supply current

to the loading on the VDD pin and the highest boost switching frequency selection (f_BSW), which is limited by

maximum boost switching frequency (f_BSW(MAX)) of the control loop. The minimum inductance is 22 µH (±10%)

regardless of calculation result. Magnetic shielding is recommended to help avoid inducing noise into nearby

networks.

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(12)

The voltage drop on the DC winding resistance of the boost inductor (R_LB) and R_DS(ON)of Q_BSW(R_BSW) reduces

the actual voltage across the boost inductance from V_BIN. The boost inductor voltage needs to be high enough

to build up the inductor current quickly. Therefore, it is recommended to choose the R_LBlow enough to make the

total resistive voltage drop at 0.33 A lower than the 1-V boost UVLO(OFF) threshold.

(13)

When the ACF operates in the LPM, SBP1, and SBP2 modes, the high side switch is disabled, so the leakage

inductance energy will charge the clamping capacitor and C_BINin every ACF switching cycle. If the leakage

inductance energy is big enough to build up V_BINhigher than 30 V under those operating modes, a unidirectional

TVS between the BIN pin and AGND pin will be needed to protect the 30-V rated BIN and BSW pins. A

high-voltage Schottky auxiliary winding rectifier diode maximizes the C_BINvoltage in the survival mode, so

the regulator in CCM mode can transfer the stored C_BINcharge to C_VDD. The more survival mode energy is

absorbed by the auxiliary power supply, the less residual energy is delivered to the output capacitor. This will

ensure that the output voltage can stay within regulation range during survival mode under no-load condition.

8.3.15 XCD Pin

The XCD pin performs X-capacitor discharge and the fault-latch fast-reset functions in conjunction with the

recommended external detection circuits, shown in Figure 8-15. The first application circuit allows to perform

the two functions at the same time. The second application circuit achieves the fault-latch fast-reset only. The

two application circuits must be connected to the AC input but not the DC input, in order to avoid the

thermal issue of those sensing components caused by enabling the discharge current repetitively. If

neither function is needed, directly shorting the two XCD pins to the AGND pin disables the XCD pin functions,

so the controller wait-state current is further reduced. The external sensing circuit must be removed.

X-cap Discharge

+ Fault-Latch Fast Reset

Fault-Latch Fast Reset

Disable XCD-Pin

Functions

L

L or N

N

V_HV

R_XCD

Q_XCD

V_P13

XCD

Figure 8-15. XCD-pin Application Circuits

To form the discharge path in the first circuit, the anode nodes of two high-voltage diode rectifiers are connected

to each X-cap terminal, the two diode cathodes are connected together to a 26-kΩ current limit resistance

(R_XCD), and the drain-to-source of a high-voltage depletion MOSFET (Q_XCD) couples the resistance to XCD pins.

Since R_XCDneeds to sustain the high voltage drop from the XCD-pin current, two series 13-kΩ SMD resistors in

1206 size with 26-kΩ total resistance are required to meet the voltage de-rating. A 600-V rated MOSFET such

as BSS126 is needed as the high voltage blocking device. The MOSFET gate is connected to the P13 pin, so

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the highest voltage level of the XCD pins is limited to the sum of the P13-pin voltage and the threshold voltage of

BSS126. The voltage level gives sufficient headroom over the 6.5-V line zero-crossing (LZC) threshold.

In case of single-fault event where one XCD pin is in fail-open condition, the redundant XCD pin helps to

maintain the X-cap discharge function. In case of the single-fault event of BSS126 involving its drain-to-source

in fail-short condition, an internal 26-V clamp helps to protect the XCD pin from exceeding its voltage rating. The

current-limiting resistance (R_XCD) limits the fault current below the maximum clamping capability, however the

value of R_XCDshould avoid reducing the normal discharge current. A total resistance of 26 kΩ ±5% meets both

criteria. The internal clamping function can also help to dissipate some of the line surge energy accumulated on

the XCD pins in order to limit the pin voltage below its 30-V rating.

After the AC line is disconnected, X-capacitors in the EMI filters on the AC side of the diode-bridge rectifier

must have means to discharge its residual voltage to a safe level within a certain time. Typically a high voltage

discharge resistor bank is placed in parallel with the capacitor to form a discharge path. The value of the

resistance is chosen to discharge the capacitance within the required time period. However, if the capacitance

is large enough, the necessary lower value of discharge resistance will increase the standby power. UCC28782

provides an active X-capacitor discharge function with 2-mA maximum discharge current capability to reduce

the standby power. The discharge current is activated only when the detection criteria for the AC-line removal

condition is met. The 6.5-V line zero-crossing (LZC) threshold on XCD pins is used to detect AC-line presence.

When LZC is missing over an 84-ms detection timeout period, the discharge current is enabled for a maximum

period of 300 ms followed by a 700-ms blanking time with no current. To detect the zero crossing reliably, as

well as to save power consumption, a stair-case test current shown in Figure 8-16 is generated within the 84-ms

detection time. The worst-case discharge current and timing are designed to discharge the X-capacitor up to 1

µF.

I_XCD(MAX)

I_XCD(4)

I_XCD(3)

I_XCD(2)

I_XCD(1)

t_XCD(MAX)

I_XCD(0)

7 x t_XCD(STEP)

t_XCD(WAIT)

Figure 8-16. Step-current Profile into the XCD Pins for the X-cap Discharge Function

The four test current levels are designed to overcome the impact of leakage current from the bridge diode over

a wide line range. Without enough test current level in a 12-ms period, the diode leakage current will prevent

the XCD-pin voltage from reaching close to the 6.5-V LZC threshold. A higher AC line voltage or a higher

diode junction temperature requires a higher test current due to the increased diode leakage current. When the

AC line is connected, the four stair-case current levels and the 700-ms time out after the completion of LZC

detection helps to minimize the average current sink from AC main and thereby the static power loss. For the

first three current levels, every 12-ms time-out event commands the test current to increment. The last test

current level has to be sustained for 48 ms without LZC, before triggering the 2-mA discharge mode. Whenever

LZC is detected, any higher-level test-current steps are aborted and the 700-ms wait-state is initiated. Figure

8-17 shows the flow chart of X-capacitor discharge and the fault-latch reset sequence.

Note that the XCD-LATCH referenced in Figure 8-17 is not the same as the Fault-Latch. XCD-LATCH is a latch

that is set when loss of AC line is confirmed. When set, this state allows the Fault-Latch to be reset and allows

X-capacitor discharge to proceed.

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V_XCD> 4V

Y

AFTER FIRST V_VDD

STARTUP

700ms

DONE

N

Disable XCD

700ms BLANK &

XCD_LATCH RESET

12ms LZC

DETECT

12ms

WAIT

LZC = 1

700ms

WAIT

(I_XCD(0)

)

(I_XCD(1)

)

12ms_DONE & LZC = 0

LZC = 1

12ms LZC

DETECT

12ms

WAIT

(I_XCD(2)

)

LZC = 1

12ms_DONE & LZC = 0

12ms LZC

DETECT

12ms

WAIT

(I_XCD(3)

)

LZC = 1

12ms_DONE & LZC = 0

48ms LZC

DETECT

48ms

WAIT

(I_XCD(4)

)

700ms

DONE

48ms_DONE & LZC = 0

300ms

DISCHARGE

(I_XCD(MAX)

700ms BLANK

(I_XCD(0)

XCD_LATCH

SET

)

300ms_DONE

OR LZC = 1

)

700ms

WAIT

300ms

WAIT

Figure 8-17. The State Diagram of the XCD-pin Function

Whenever any system protection triggers the fault-latch, the converter switching is terminated and V_VDDrestart

cycle occurs between V_VDD(ON)and V_VDD(OFF). In this mode, the XCD pin function continues to operate, since

the internal circuitry is separately biased from V_VDDinstead of from V_REF. When the AC line is disconnected, the

large bulk input capacitor of the ACF prevents V_VDDfrom decaying below the 4.3-V fault reset threshold quickly

enough. If the AC line recovers too fast without the XCD pin detection, the controller will still stay in a latched

condition and output voltage fails to retry. The two XCD-pin detection circuits can inform the controller the instant

of AC line recovery based on the LZC detection concept, so the controller can directly reset the fault condition

more quickly.

The second application circuit performs the fault-latch fast-reset without the need for the two high voltage

diodes, so essential sensing components become fewer. In the first application circuit with both line and neutral

connections, the frequency of the XCD-pin signal is twice the AC-line frequency, and the 12-ms timeout is long

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enough for V_XCDto reach the LZC threshold when the test current becomes sufficient. On the other hand, since

the current-limit resistor is connected directly to either line or neutral of the AC input in the second application

circuit, only the line-frequency waveform on the XCD pins can trigger the LZC threshold. Because the 12-ms

timeout is shorter than a 50-Hz or 60-Hz line cycle, the LZC detection time requires two 12-ms timeout periods to

allow the latch reset function to be triggered correctly. Considering the average static current into the XCD pins

and the circuit power loss, the second application circuit is lower than the first one. At a high-line condition, the

second circuit only needs to use the second step current of 775 µA to detect LZC, while the first circuit may need

to increase to the third or fourth step current in order to obtain a valid LZC detection.

Shorting the XCD pins to AGND disables both functions automatically. After V_VDDfirst reaches V_VDD(ON), a 80-µA

test current is sourced out of the XCD pin, in order to reliably identify the XCD-pin short with a low-impedance

path to the AGND pin. If XCD is shorted to AGND, any path to L and N must be open to prevent R_XCDfrom

overheating. When V_XCDis lower than 4 V before the RUN-pin first pulls high, the function is disabled and

the internal circuit will stop sourcing current from V_VDD. Different from the first two application circuits, when a

latch-off fault happens, the only way to reset the fault condition for this connection is to wait for V_VDDto drop

below the 4.3-V logic reset threshold (V_VDD(RST))) first before the next V_VDDrestart cycle occurs. With large bulk

capacitance, V_VDDmay cycle for several minutes before its energy is depleted low enough to drop to 4.3V. This

connection may be more useful for the all auto-recovery fault setting, or for the latch-off fault setting with no

stringent latch reset time limitation.

8.3.16 CS, VS, and FLT Pins

The CS pin is the current-sense input. The internal peak current control loop limits the highest magnetizing

current, and Section 8.4.4 in this datasheet describes the peak current change in different operation modes.

The VS pin is a multi-function sensing input, which detects the input voltage, the output voltage, and the

zero-current-crossing (ZCD) through the auxiliary winding voltage, for optimizing ACF performance and providing

critical protections. The FLT pin is a dual-purpose fault detection pin for the over-temperature protection or the

input over-voltage protection. The system protection functions of the three pins are introduced in Section 8.4.14.

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8.4 Device Functional Modes

8.4.1 Adaptive ZVS Control with Auto-Tuning

Figure 8-18 shows the simplified block diagram explaining the ZVS control of UCC28782. A high-voltage sensing

network provides a replica of the switch node voltage waveform (V_SW) with a limited “visible” lower voltage range

that the SWS pin can handle. The ZVS discriminator identifies the ZVS condition and determines the adjustment

direction for the on-time of PWMH (t_DM) by detecting if V_SWreaches a predetermined ZVS threshold, V_TH(SWS)

,

within t_Z, where t_Zis the targeted zero voltage transition time of V_SWcontrolled by the PWMH-to-PWML dead-

time optimizer.

In Figure 8-18, V_SWof the current switching cycle in the dashed line has not reached V_TH(SWS)after t_Zexpires.

The ZVS discriminator sends a TUNE signal to increase t_DMfor the next switching cycle in the solid line, such

that the negative magnetizing current (I_M-) can be increased to bring V_SWdown to a lower level in the same t_Z.

After a few switching cycles, the t_DMoptimizer settles and locks into ZVS operation of the low-side switch (Q_L).

In steady-state, there is a fine adjustment on t_DM, which is the least significant bit (LSB) of the ZVS tuning loop.

This small change of t_DMin each switching cycle is too small to significantly move the ZVS condition away from

the desired operating point. Figure 8-19 demonstrates how fast the ZVS control can lock into ZVS operation.

Before the ZVS loop is settled, UCC28782 starts in a valley-switching mode as t_DMis not long enough to create

sufficient I_M-. Within 15 switching cycles, the ZVS tuning loop settles and begins toggling t_DMwith an LSB.

t_D(PWML-H)

V_CST

L_K

D_SEC

I_M/ R_CS

PWML

PWMH

N_P:N_S

V_BULK

V_O

I_M

L_M

R_Co

C_O

R_O

C_CLAMP

t_DM

Q_H

SET

VS

RTZ

Adaptive ZVS Control

High-side

Driver

PWMH

PWML

RDM

SET

t_Z

t_DM

Optimizer

Dead-Time Optimizer

(t_D(PWML-H)and t_Z)

Q_L

V_SW

R_CS

TUNE

t_Z

V_TH(SWS)

Peak Current

Loop

V_CST

ZVS Discriminator

PWMH

PWML

SET

SWS

HV Sense

P13

Figure 8-18. Block Diagram of Adaptive ZVS Control

PWML

PWMH

1.2

0.8

0.4

0

I_M(A)

18

12

6

V_SWS(V)

V_TH(SWS)

0

400

300

200

V_SW(V)

100

0

5 µs/div

12

6

12

6

12

6

V_SWS(V)

0

400

V_SW(V)

200

0

200

0

200

0

Figure 8-19. Auto-Tuning Process of Adaptive ZVS Control

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8.4.2 Dead-Time Optimization

The dead-time optimizer in Figure 8-18 controls the two dead-times: the dead-time between PWMH falling edge

and PWML rising edge (t_Z), as well as the dead-time between PWML falling edge and PWMH rising edge

(t_D(PWML-H)).

Similar to UCC28780, the adaptive control law for t_Zof UCC28782 utilizes the line feed-forward signal to extend

t_Zas V_BULKreduces, as shown in Figure 8-20. The VS pin senses V_BULKthrough the auxiliary winding voltage

(V_AUX) when the low-side switch (Q_L) is on. The auxiliary winding creates a line-sensing current (I_VSL) out of

the VS pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1). Minimum t_Z(t_Z(MIN)) is set

at V_BULK(MAX)through the RTZ pin. When I_VSLis lower than 666 μA, t_Zlinearly increases and the maximum t_Z

extension is 140% of t_Z(MIN)

.

140%

100%

t_Z(I_VSL

)

t_Z(MIN)

I_VSL

233 µA

666 µA

Figure 8-20. t_ZControl Optimized for Wide Input Voltage Range

I_SEC

I_PRI

ZCD

PWMH

V_BULK

t_Z

V_SW

PWML

Figure 8-21. The Enhanced t_ZControl for CCM Avoidance

The enhanced t_Zcontrol of UCC28782 helps to avoid voltage stress on the secondary rectifier due to temporary

continuous conduction mode (CCM) operation. If the high side switch turns off under a higher than normal

negative resonant current instance, the switch node voltage (V_SW) and the auxiliary winding voltage (V_AUX) will

drop very fast, because a higher di/dt current flows through the leakage inductance. At the same instant, if the

magnetizing current has not decayed down to zero yet, the current will continue to flow in the secondary rectifier,

so the switch node voltage will recover back to a high level again and results in a short-duration voltage dip

behavior within the t_Zperiod. If a ACF controller turns on the low-side switch after t_Zexpires but the magnetizing

current is still positive, the limited turn off speed of the synchronous rectifier (SR) will result in a higher di/dt

current as the low-side switch turns on, so a high voltage spike is generated on the SR drain-to-source voltage.

Then, the FET voltage rating or the snubber design on the secondary side may need to be compromised, which

are the typical concerns of flyback topology in CCM. Therefore, the VS pin of UCC28782 can detect this event

and avoid low-side switch turn on after t_Zexpires under this situation.

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The concept is to detect the ZCD signal once again at the instant of t_Zexpiration, such that the controller will

not respond to the false ZCD signal after the high side switch turns off. When the duration of the voltage dip

is shorter than t_Zsetting, the ZCD signal will change back to its original low state at the t_Zexpiration instance.

When there is no valid switch node voltage transition detected from the ZCD signal at the instance, the controller

will wait for another ZCD rising edge to trigger the low-side switch turn-on of the next cycle. Since the next ZCD

signal could be a real indication of the magnetizing current reached to 0 A, the CCM turn-off event of secondary

rectifier will not occur. Figure 8-21 illustrates the issue and the operation principle of the improved switching

control in UCC28782.

The control law for t_D(PWML-H)of UCC28782 is adaptive with the slope variation of the switching node voltage,

regardless of the SET-pin voltage. One reason of applying the adaptive control is to generate a minimum dead

time for reducing the body diode conduction time of the high-side Si switch or the reverse conduction time of the

high-side GaN switch. Another reason is to avoid the risk of hard switching. Since the rising slope of the switch

node voltage varies with different peak magnetizing currents as output load changes, using a fixed dead-time

can potentially cause hard-switching on the high-side clamp switch (Q_H) if the dead-time is not long enough.

UCC28782

UCC28780 (V_SET= 5V)

Heavy Load

Light Load

Heavy Load

Light Load

V_SW

V_AUX

ZCD

0 V

V_AUX

ZCD

40-ns

delay

PWML

PWMH

PWML

t_D(PWML-H)

PWMH

t_D(PWML-H)

Figure 8-22. t_D(PWML-H)Control Optimized for GaN and Si FETs

For the GaN ACF with UCC28780, a fixed 40-ns dead time from PWML falling edge to PWMH rising edge is

applied for the SET pin connected to GND. For the Si ACF with UCC28780, the adaptive dead time adjustment

based on the ZCD falling edge plus 40-ns delay is applied for the SET pin connected to the REF pin. The

enhanced t_D(PWML-H)control of UCC28782 helps to further reduce the body diode conduction time of the high

side Si switch or the reverse conduction time of the high-side GaN switch without risk of hard switching on the

high side switch. Moreover, the same dead time control is generalized for both SET-pin connections. After the

ZCD falling edge is detected, the PWMH driver of UCC28782 will pull high immediately, and the extra 40-ns

delay in UCC28780 is removed. For the GaN ACF with UCC28782, as long as the VS-pin delay from the

parasitic capacitive loading is reduced by a proper layout arrangement, it is possible to shorten the reverse

conduction time in heavy load, and also eliminate the concern of high-side hard switching in light load. For the

Si ACF with UCC28782, the propagation delay of the high-side driver already provides enough margin for switch

node voltage settled to a high level after ZCD falling edge is triggered, so there is no need to introduce an extra

40-ns delay like UCC28780.

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8.4.3 EMI Dither and Dither Fading Function

The frequency dither function in AAM reduces the conducted EMI noise and results in EMI filter size reduction.

Conventionally, the dither carrier frequency is in the range of hundreds of Hz. However, when the control loop

bandwidth is pushed higher in order to improve the load transient response, the control loop will be able to

correct the disturbance from the dither signal, and weakens the EMI frequency spreading effectiveness. Even

though increasing the dither frequency to few kHz can reduce the influence of the control loop, the audible noise

issue will occur. For UCC28782, since the ACF is able to run at a higher switching frequency in AAM, the dither

frequency can be optimized at 23 kHz, so as to avoid audible noise and desensitize the loop response effect on

the EMI attenuation.

UCC28782 enhances the response of the ZVS control loop, such that the ZVS performance can be maintained

in most switching cycles even under a strong EMI dither condition. A triangular dither signal is superimposed on

the feedback voltage signal V_CST, so it is challenging to calculate the proper PWMH on time cycle by cycle to

keep similar negative magnetizing current for ZVS. The novel feed-forward control method is applied to allow the

ZVS loop to correct the timing error much faster, so ZVS can be maintained and the efficiency will not suffer.

Conventionally, the dither magnitude is fixed across the whole output voltage range. Since the higher output

voltage condition needs to deliver a higher output power, the EMI issue is typically more severe, so a stronger

dither signal is needed for more conducted EMI reduction. In the lower output voltage condition, the output ripple

specification is usually much tighter, so a strong dither signal may aggravate the output voltage ripple and create

the design tradeoff. For UCC28782, the two-level dither magnitude is adjusted automatically based on the output

voltage level, so the perturbed output ripple at the lower output voltage condition can be reduced to meet a more

stringent ripple requirement, and the strong dither can still be applied to the higher output voltage condition for

the better EMI performance. Specifically, when V_VSis lower than 2.4 V during the demagnetization time (the

LOW_NVO logic signal is high), the peak-to-peak dither magnitude on CS pin is reduced to around 36 mV. When

V_VSis higher than 2.5 V, the peak-to-peak dither magnitude on CS pin is increased to around 98 mV.

Since the low-line efficiency usually determines the power stage thermal limit, the efficiency will drop further

when EMI dither is enabled. Since the bulk capacitor ripple voltage at low line is bigger than at high line and

AAM mode forces variable frequency operation, the line frequency causes nature dither frequency anyway even

without applying the internal EMI dither. Therefore, taking advantage of AAM mode, the dither function at low line

can be disabled based on the brown-in voltage setting, so the option provides design flexibility to trade-off the

worst-case low-line efficiency and EMI. Specifically, when i_VSLis higher than 646 μA, the EMI dither function is

enabled. When i_VSLis lower than 580 μA, the EMI dither function is disabled. If the brown-in point is set at 75

Vac, this means that the EMI dither is disabled for 90 Vac and 115 Vac.

The dither fading feature allows the dither signal to be smoothly disabled, when the output load current is close

to the transition point between AAM and ABM. As shown in Figure 8-23, V_CST(MAX)and V_CST(BUR)are used as

the two voltage-clamping targets to the perturbed V_CSTsignal. When the V_CSTreaches V_CST(MAX), the top of the

V_CSTripple content is clipped by the internal clamp circuit, so the influence of the EMI dither on the peak power

capability can be eliminated. When the V_CSTreaches V_CST(BUR), the bottom of the V_CSTripple content is clipped

by an another internal clamp circuit, so the influence of the EMI dither on the ABM waveform is removed.

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I_O

I_O(MAX)

I_O(OPP)

I_O(BUR)

V_CST(MAX)

V_CST(OPP)

V_CST+ V_CST(EMI)

V_CST

V_BUR/4

FAULT_OPP

ABM

DITHER_EN

Figure 8-23. Dither Fading Feature in AAM

8.4.4 Control Law across Entire Load Range

UCC28782 contains six modes of operation summarized in Table 8-1. Starting from heavier load, the AAM mode

forces PWML and PWMH into complementary switching with ZVS tuning enabled. ABM mode generates a group

of PWML and PWMH pulses as a burst packet, and adjusts the burst off-time to regulate the output voltage.

At the same time, the burst frequency variation is confined above 20kHz by adjusting the number of PWML

and PWMH pulses per packet to mitigate audible noise and reduce burst output ripple. In LPM, SBP1, and

SBP2 modes, PWMH and the ZVS tuning loop are disabled, so the converter operates in valley-switching. The

survival mode is to maintain V_VDDhigher than V_VDD(OFF)in a long burst off time, and also performs the clamping

capacitor balancing function to reduce the voltage stress of the secondary-side rectifier.

Table 8-1. Functional Modes

MODE

Adaptive

Amplitude

Modulation

OPERATION

PWMH

ZVS

AAM

ABM

ACF operation with PWML and PWMH in complementary

switching

Enabled

Yes

Adaptive Burst

Mode

Variable f_BUR> f_BUR(LR), ACF operation in complementary

switching

Enabled

Yes

LPM

Low Power Mode Fix f_BUR≈ f_LPM, valley-switching

Disabled

No

SBP1

First StandBy

Power Mode

Variable f_BURbetween f_SBP2(LR)and f_SBP2(UP), valley-

switching

SBP2

Second StandBy Variable f_BUR< f_SBP2(UP)as V_BUR< 0.9 V; Variable f_BUR

<

Disabled

No

Power Mode

f_SBP2(LR)as V_BUR> 0.9 V; Both are in valley-switching

INT_STOP

Survival Mode

When V_VDD< V_VDD(OFF)+ V_VDD(PCT), a series of PWML

pulses followed by a long PWMH pulse is generated

Enabled in the last

switching cycle of

a survival-mode

burst packet

Figure 8-24 and Figure 8-25 show the critical parameter changes among the five operating modes, where V_CST

is the peak current threshold compared with the current-sense voltage from the CS pin, f_SWis the switching

frequency of PWML, f_BURis the burst frequency, and N_SWis the pulse number of PWML cycles per burst packet.

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Figure 8-24 represents the control mode difference under the two VS-pin voltage ranges, when the IPC-pin

voltage is less than 0.9 V or IPC is connected to AGND. Figure 8-25 illustrates the modified control mode, when

the IPC-pin voltage setting is higher than 0.9 V. The following section explains the detailed operation of each

mode. The VS-pin voltage and IPC-pin voltage effects will also be introduced in the following section.

Control law for V_VS< V_VSLV(LR)

(LOW_NVO = 1)

Control law for V_VS> V_VSLV(UP)

(LOW_NVO = 0)

SBP2 SBP1

LPM

SBP2 SBP1

LPM

V_CST

ABM

AAM

ABM

AAM

V_CST(OPP)

V_{CST(OPP)_LV}

V_CST(BUR)

V

^CST_IPC(MIN)=V_CST(MIN)

V

_{CST_IPC(MIN)}=V_CST(MIN)

P_O

Frequency

f_SW

f_BUR(UP2)

f_BUR(UP1)

f_BUR(UP2)

f_BUR(LR)

f_BUR

f_BUR(LR)

f_BUR

f_LPM

f_SBP2(UP)

f_LPM

f_SBP2(UP)

P_O

N_SW

9

5

4

2

4

2

P_O

P_O(BUR)

P_O(OPP)

P_O(BUR)P_{O(OPP)_LV}

Figure 8-24. Control Law Over Entire Load Range Based on the V_VSCondition as V_IPC< 0.9 V

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Full load to light load

Light load to full load

SBP2 SBP1

LPM

SBP2 SBP1

LPM

V_CST

ABM

AAM

ABM

AAM

V_CST(OPP)

V_CST(BUR)

V_{CST_IPC}

V_CST(MIN)

V_{CST_IPC}

V_CST(MIN)

P_O

Frequency

f_SW

f_BUR(UP2)

f_BUR(UP1)

f_BUR

f_BUR(LR)

f_BUR

f_BUR(LR)

f_LPM

f_SBP2(UP)

f_SBP2(LR)

f_LPM

f_SBP2(UP)

f_SBP2(LR)

P_O

N_SW

9

4

2

4

2

P_O

P_O(OPP)

P_O

P_O(BUR)

P_O(OPP)

Figure 8-25. Control Law Under Different Load Sweep Direction as V_IPC> 0.9 V and V_VS> V_VSLV(UP)

8.4.5 Adaptive Amplitude Modulation (AAM)

The switching pattern in AAM forces PWML and PWMH to alternate in a complementary fashion with dead-time

in between, as shown in Figure 8-26. As the load current reduces, the negative magnetizing current (I_M-) stays

the same, while the positive magnetizing current (I_M+) reduces by the internal peak current loop to regulate the

output voltage. I_M+generates a current-feedback signal (V_CS) on the CS pin through a current-sense resistor

(R_CS) in series with Q_Lsource and a peak current threshold (V_CST) in the current loop controls the peak

current variation. Due to the nature of transition-mode (TM) operation, lowering the peak current with lighter load

conditions results in higher switching frequency. When the load current increases to an over-power condition

(I_O(OPP)) where V_CSTcorrespondingly reaches an OPP threshold (V_CST(OPP)) of the peak current loop, the OPP

fault response will be triggered after a 160-ms timeout. The RUN signal stays high in AAM, so the half-bridge

driver remains active.

Heavy Load

I_M

Light Load

0 A

I_M-

PWML

PWMH

RUN

Figure 8-26. PWM Pattern in AAM

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8.4.6 Adaptive Burst Mode (ABM)

As the load current reduces to I_O(BUR)where V_CSreaches the V_CST(BUR)threshold, the control mode transitions

to ABM starts and V_CSis clamped. The peak magnetizing current and the switching frequency (f_SW) of each

switching cycle are fixed for a given input voltage level. V_CST(BUR)is programmed by the BUR pin voltage (V_BUR).

The PWM pattern of ABM is shown in Figure 8-27. When RUN goes high, a delay time between RUN and

PWML (t_D(RUN-PWML)) is given to allow both the gate driver and the UCC28782 time to wake up from a wait

state to a run state. PWML is set as the first pulse to build up the bootstrap voltage of the high-side driver

before PWMH starts switching. The first PWML pulse turns on Q_Lclose to a valley point of the DCM ringing

on the switch-node voltage (V_SW) by sensing the condition of zero crossing detection (ZCD) on the auxiliary

winding voltage (V_AUX). The following switching cycles operate in a ZVS condition, since PWMH is enabled. As

the number of PWML pulses (N_SW) in the burst packet reaches its target value, the RUN pin pulls low after the

ZCD of the last switching cycle is detected, and forces the half-bridge driver and UCC28782 into a wait state for

the quiescent current reduction of both devices. In this mode, the minimum off-time of the RUN signal is 2.2 µs

and the minimum on-time of PWML is limited to the leading-edge blanking time (t_CSLEB) of the peak current loop.

However, more grouped pulses means more risk of higher output ripple and higher audible noise. The following

equation estimates how burst frequency (f_BUR) varies with output load and other parameters.

I_O

f_SW

f_BUR

=

I_O(BUR)N_SW

(14)

As I_O< I_O(BUR), f_BURcan become lower than the audible noise range if N_SWis fixed. In ABM, N_SWis modulated

to ensure f_BURstays above 20 kHz by monitoring f_BURin each burst period. As I_Oreduces, f_BURbecomes lower

and reaches a predetermined low-level frequency threshold (f_BUR(LR)) of 25 kHz. The ABM loop commands N_sw

of both PWML and PWMH to be reduced by one pulse to maintain f_BURabove f_BUR(LR). At the same time, the

burst frequency ripple on the output voltage reduces as N_SWdrops with the load reduction. As I_Oincreases,

f_BURbecomes higher and reaches a predetermined high-level frequency threshold (f_BUR(UP)). The ABM loop

commands N_SWto be increased by one pulse to push f_BURback below f_BUR(UP)

.

The maximum N_SWand the f_BUR(UP)thresholds are modified based on the output voltage condition, i.e., the

positive VS-pin voltage level. When the V_VSsampled at the PWMH falling edge is less than the 2.4-V threshold

(V_VSLV(LR)), the maximum N_SWis 5 pulses and the f_BUR(UP2)is 50 kHz. When the sampled V_VSis higher than the

2.5-V threshold (V_VSLV(UP)), the maximum N_SWis 9 pulses, the f_BUR(UP2)is 50 kHz for N_SW≤ 3, and the f_BUR(UP1)

is 34 kHz for N_SW> 3. The IPC-pin voltage does not affect the parameters in ABM mode.

This algorithm maximizes the number of pulses in each burst packet to improve light-load efficiency, while also

limiting the burst output ripple and audible noise. As I_Ois close to the boundary between AAM and ABM, the

two burst packets with the maximum pulse count may start to bundle together. In order to mitigate the output

ripple and audible noise concerns, when the bundled burst packet appears two times within eight sequential

burst cycles, the 5-µA current sink into the BUR pin is enabled to reduce V_BUR. The less energy per cycle with

a lower V_BURwill force the control loop to transition from ABM to AAM smoothly in order to allow the peak current

increase to maintain the output voltage regulation.

t_D(RUN-PWML)

V_CST(BUR)/ R_CS

I_M

0 A

ZCD

through V_aux

f_SW

ZVS

t_CSLEB

PWML

PWMH

f_BUR

2.2 µs

RUN

Figure 8-27. PWM Pattern in ABM

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8.4.7 Low Power Mode (LPM)

As N_SWdrops to two in ABM and the condition of f_BURless than f_BUR(LR)is qualified under two consecutive burst

periods, UCC28782 enters into LPM mode and disables PWMH. The purpose of LPM is to provide a soft peak

current transition between V_CST(BUR)and V_CST(MIN). LPM fixes N_SWat two and sets f_BURequal to f_LPMof 25 kHz.

In LPM mode, V_CSTis controlled to regulate the output voltage. At the start of each burst packet, after RUN pulls

high, t_D(RUN-PWML)is used to wake up both the gate driver and UCC28782. With PWMH disabled, the two PWML

pulses turn on Q_Lclose to valley-switching by sensing ZCD. When ZCD is detected again at the end of the

second pulse, the RUN pin goes low and the UCC28782 enters its low-power wait state. For LPM mode with the

SET pin connected to REF, the minimum on-time of PWML can be further reduced to t_ON(MIN), to allow the peak

magnetizing current to be reduced below the level limited by t_CSLEBof the peak current loop. In this condition,

operation of the LPM control loop is changed from a current-mode control to a voltage-mode control, so the

on-time adjustment of PWML is not limited to t_CSLEB. When the silicon ACF is used and the SET pin is connected

to REF, the high capacitance region of the low-side switch will introduce a higher peak current overshoot than

the GaN ACF. With this feature, before f_BURstarts to fall below f_LPMand enters the audible frequency range of

SBP mode, the peak current is low enough to limit the magnitude of audible excitation. For the LPM mode with

GaN ACF by connecting the SET pin to AGND, the minimum on-time of PWML will still be limited by t_CSLEB

.

t_D(RUN-PWML)

V_CST(BUR)/ R_CS

V_CST(MIN)/ R_CS

I_M

0 A

t_ON(MIN)

ZCD through V_AUX

PWML

f_BUR= f_LPM

PWMH

RUN

Figure 8-28. PWM Pattern in LPM

8.4.8 First Standby Power Mode (SBP1)

As V_CSTdrops to V_CST(MIN), UCC28782 enters into SBP1 mode and PWMH continues to stay disabled. The

purpose of SBP1 is to lower f_BURin order to minimize power loss. SBP1 fixes N_SWat two and V_CSTto

V_CST(MIN), while the burst off-time is adjusted to regulate the output voltage. As f_BURis well below f_LPM, the

switching-related loss can be minimized. In addition, lowering f_BURforces both the gate driver and UCC28782 to

remain in wait states longer to minimize the static power loss. The equivalent static current of the UCC28782 in

SBP can be represented as

2

I_VDD(SBP)= (I_RUN- I_WAIT)(

+ t_D(RUN-PWML)) f_BUR+ I_WAIT

f_{SW (SBP)}

(15)

t_D(RUN-PWML)

V_CST(MIN)/ R_CS

I_M

t_ON(MIN)

PWML

PWMH

f_BUR

RUN

I_VDD

I_RUN

I_WAIT

Figure 8-29. PWM Pattern in SBP1

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8.4.9 Second Standby Power Mode (SBP2)

When f_BURis below the 8.5-kHz upper burst frequency threshold (f_SBP2(UP)), UCC28782 exits SBP1 mode

and enters into SBP2 mode. Compared with the SBP1 mode, the pulse count is doubled and V_CSTcan be

programmed by the IPC pin. The V_CSTprogrammable range in SBP2 is between 0.27 V and 0.4 V. The purpose

of SBP2 is to further lower f_BURin order to minimize standby power.

The f_BURcondition to trigger the mode transition from SBP2 to SBP1 depends on the IPC pin voltage setting as

well. If V_IPCis set lower than 0.9 V or the IPC pin is shorted to AGND, V_CSTis equal to V_{CST_IPC(MIN)}, and the

mode transition occurs when f_BURis increased above the same 8.5-kHz threshold. On the other hand, if V_IPC

is set higher than 0.9 V, V_CSTis higher than 0.27 V, and the mode transition occurs when f_BURis increased

above the 1.7-kHz lower burst frequency threshold (f_SBP2(LR)). The purpose of skipping the burst frequency range

between 1.7 kHz and 8.5 kHz is to avoid the most sensitive audible frequency range to the human ear. The

frequency skipping is only enabled, when the peak current is set higher by V_IPC> 0.9 V.

SBP2 for V_IPC< 0.9 V

SBP2 for V_IPC≥ 0.9 V

t_D(RUN-PWML)

V_{CST_IPC}/ R_CS

V_CST(MIN)/ R_CS

I_M

t_ON(MIN)

PWML

PWMH

PWML

PWMH

RUN

I_VDD

RUN

I_VDD

I_RUN

I_WAIT

Figure 8-30. PWM Pattern in SBP2

8.4.10 Startup Sequence

Figure 8-31 shows the simplified block diagram related with the VDD startup function of UCC28782, and Figure

8-32 addresses the startup sequence. The detailed description on the startup waveforms is :

1. Time interval A: The UVLO circuit commands the two internal power-path switches (Q_DDSand Q_DDP) to close

the connections between SWS, VDD, and P13 pins through two serial current-limiting resistors (R_DDSand

R_DDP). The depletion-mode MOSFET (Q_S) starts sourcing charge current (I_SWS) safely from the high-voltage

switch-node voltage (V_SW) to the VDD capacitor (C_VDD). Before V_VDDreaches 1.8 V, I_SWSis limited by the

high-resistance R_DDSof 5 kΩ to prevent potential device damage if C_VDDor VDD pin is shorted to ground.

2. Time interval B: After V_VDDrises above 1.8 V, R_DDSis reduced to a smaller resistance of 0.5 kΩ. I_SWSis

increased to charge C_VDDfaster. The maximum charge current during VDD startup can be quantified by

Equation 8.

3. Time interval C: As V_VDDreaches V_VDD(ON)of 17 V, the ULVO circuit turns-off Q_DDSto disconnect the

source pin of Q_Sto C_VDD, and turns-off Q_DDPto break the gate-to-source connection of Q_S, so Q_Sloses its

current-charge capability. V_VDDthen starts to drop, because the 5-V regulator on REF pin starts to charge

up the reference capacitor (C_REF) to 5 V, for which the maximum charge current (I_SE(REF)) is self-limited at

around 17 mA. After V_REFis settled, the UVLO circuit turns-on another power-path switch (Q_P13), so an

internal 13-V regulator is connected to the P13 pin. The voltage on the P13 pin capacitor (C_P13) starts to be

discharged by the regulator.

4. Time interval D: While discharging the recommended 1 µF on C_P13, the sink current of the 13-V regulator

(I_P13(START)) is self-limited at around 2.2 mA, so it takes longer than 10 μs to settle to 13 V. If V_P13reaches 13

V in less than 10 μs, the P13 pin open fault is triggered to protect the device. Once V_P13has settled to 13 V

without the fault event, RUN pin goes high and UCC28782 enters a run state with I_VDD= I_RUN

.

5. Time interval E: There is a minimum 2.2-μs delay from RUN going high to PWML starting to switch in order

to wake-up the gate driver and UCC28782. In this interval, the 2.8-Ω power path switch between the P13 pin

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and the S13 pin is enabled, so the S13-pin decoupling capacitor (C_S13) is charged up and the charge current

is supplied from C_P13and the P13 regulator. If 2.2-μs delay is timed out before V_S13reaches to the 10-V

power good threshold (V_{S13_OK}), the PWML switching instance will be further delayed.

6. Time interval F: This is the soft-start region of peak magnetizing current. The first purpose is to limit the

supply current if the output is short. The second purpose is to push the switching frequency higher than

the audible frequency range during repetitive startup situations. At the beginning of V_Osoft-start, the peak

current is limited by two V_CSTthresholds. The first V_CSTstartup threshold (V_CST(SM1)) is clamped at 0.2 V

and the following second threshold (V_CST(SM2)) is 0.5 V. When V_CST= V_CST(SM1), PWMH is disabled if the

sampled VS pin voltage (V_VS) < 0.28 V, and the first five PWML pulses are forced to stay at this current

level. After the sampled V_VSexceeds 0.28 V and the first five PWML pulses are generated, the peak current

threshold changes from V_CST(SM1)to V_CST(SM2). In case of the inability to build up V_Owith V_CST(SM1)at the

beginning of the V_Osoft-start due to excessively large output capacitor and/or constant-current output load,

there is an internal time-out of 0.7 ms to force V_CSTto switch to V_CST(SM2). At this moment, the BIN-pin

capacitor voltage increases with V_Oproportionally. If V_BINis less than the 2.2-V UVLO threshold (VBIN(ON)),

the bias switching regulator is disabled.

7. Time interval G: When V_BINis higher than 2.2 V, the bias switching regulator enters into the boost switching

mode, and starts to build up the V_VDDtoward the 18.5-V regulation level.

8. Time interval H: When V_VSrises above 0.5 V, V_CSTis allowed to reach V_CST(MAX), so the ramp rate of

V_Ostartup becomes faster. When PWML is in a high state, I_VDDcan be larger than I_RUN, because the 5-V

regulator provides the line-sensing current pulse (I_VSL) on the VS pin to sense V_BULKcondition.

9. Time interval I: Higher V_BINresults in a lower switching frequency of the bias regulator, because more energy

in the boost inductor (L_B) is transferred to C_VDDevery switching cycle.

10. Time interval J: When V_BINincreases above the 15-V boost disable threshold, the V_VDDstarts to decay back

to the rectified auxiliary winding voltage minus the forward voltage drop of the boost diode (D_B). Also, when

V_Ogets close to the target regulation level, V_CSTstarts to reduce from V_{CST(MAX )}

.

11. Time interval K: V_Oand V_CSTsettle, and the auxiliary winding takes over the VDD supply.

D_AUX

V_AUX

BSW Control

PWMB

BIN

AGND

SWS

L_B

C_BIN

BSW

Q_BSW

I_SWS

R_SWS

Q_S

N_AUX

Q_DDS

BGND

V_SW

D_B

R_DDS

Q_DDP

I_VDD

C_SWS

VDD

UVLO

D_SWS

C_VDD

R_DDP

13-V

Regulator

5-V

Regulator

P13

S13

Q_P13

RUN

I_P13

C_P13

I_REF

D_P13

Q_S13

REF

C_REF

C_S13

Figure 8-31. Functional Startup Block Diagram

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V_VDD(BOOST)

V_VDD(ON)

V_VDD

V_P13

V_P13(OV)

13V

V_VDD(OFF)

1.8 V

I_P13

I_P13(START)

I_VDD(LIMIT)

I_SWS

RUN

V_{S13_OK}

V_REF

V_{REF_OK}

V_S13

PWML

I_VSL

I_RUN

I_VDD

V_CST(SM2)

V_CST(MAX)

V_CST

V_CST(SM1)

V_O

V_BIN(EN)+V_BIN(DIS)

V_BIN(ON)

V_BIN

PWMB

(A)

(B)

(D)

(F)

(H)

(I)

(K)

(C)

(E)

(G)

(J)

Figure 8-32. Startup Timing Waveforms

8.4.11 Survival Mode of VDD (INT_STOP)

When an output voltage overshoot occurs during step-down load transients, the V_Ofeedback loop commands

the UCC28782 to stop switching quickly by increasing I_FB, in order to prevent additional energy from aggravating

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the overshoot. Since V_VDDdrops during this time, the typical way to prevent a controller from shutting down is

to oversize the VDD capacitor (C_VDD) so as to hold V_VDDabove V_VDD(OFF). Instead, UCC28782 is equipped with

survival-mode operation to hold V_VDDabove V_VDD(OFF)during a transient event. Therefore, the size of C_VDDcan

be significantly reduced and the PCB footprint for the auxiliary power can be minimized. Specifically, there is a

ripple comparator to regulate V_VDDabove a 13-V threshold, which is V_VDD(OFF)plus V_VDD(PCT)in the electrical

table. The ripple regulator is enabled when the V_Ofeedback loop requests the UCC28782 to stop switching due

to V_Oovershoot.

The regulator initiates unlimited PWML pulses when V_VDDdrops lower than 13 V, and stops switching after

V_VDDrises above 13 V. Since V_VDDor V_BINis lower than the reflected output voltage overshoot, most of the

magnetizing energy is delivered to the auxiliary winding and brings V_BINabove 2.2 V or V_VDDabove 13 V quickly.

After V_Omoves back to the regulation level, V_Ofeedback loop forces the UCC28782 to begin switching again by

reducing I_FB, and the PWML and PWMH pulses are then controlled by the normal operating mode.

To prevent the controller from getting stuck in survival mode continuously or toggling between SBP and survival

mode at zero load, some guidelines on the auxiliary power delivery path to VDD should be considered:

1. For fixed output voltage applications where the switching bias regulator is not required, the normal V_VDD

level under regulated V_Omust be designed to be above the 13-V threshold by an appropriate turns count for

the auxiliary winding.

2. C_VDDshould not be over-sized, but designed just large enough to hold V_VDD> V_VDD(OFF)under the longest

V_Osoft-start time.

3. For variable output voltage applications where the bias regulator is used, C_VDDvoltage can be ramped

up faster if the turns count of the auxiliary winding (N_AUX) can be increased, because the switching bias

regulator can process more energy from its input, especially under the lowest output voltage condition. The

design limitation on N_AUXis the maximum voltage rating of BIN and BSW pins under the highest output

voltage condition.

4. The BIN-pin capacitor (C_BIN) provides energy storage for the bias regulator. Higher C_BINvalue, such as >33

uF, can help avoid excess survival-mode operation and reduce the potential increase of V_Ounder no-load

conditions.

5. When the bias regulator is not required, an auxiliary resistor in series with the auxiliary rectifier diode (D_AUX

)

should not be too large of value, because the lower series impedance can help the VDD capacitor to charge

faster.

6. When the bias regulator is used, a series auxiliary resistor should not be used since it limits the energy

transfer to C_BIN. When the resistor is removed, one effective way to prevent C_BINfrom being overcharged

by high leakage inductance or other potential energy source is to parallel a small 24-V TVS diode between

the BIN pin and the AGND pin. If there is a layout limitation which forces the TVS diode connected to BGND

pin instead, the impedance between BGND and AGND needs to be as small as possible, such that the TVS

diode can clamp the voltage below the two pin ratings more effectively.

7. If the output voltage dynamic range is very wide, such as from 3.3 V to 20 V, low auxiliary winding resistance

less than 0.1 Ω and a Schottky-type auxiliary diode are recommended, such that the majority of the survival

mode energy can be transferred to C_BINinstead of diverting to the output capacitor under the lowest output

voltage condition.

8. Ensure good coupling between the auxiliary winding (N_AUX) and the secondary winding (N_S) of the

transformer.

When the control loop is inevitably stuck in the survival mode at no load, it is important to ensure that the

high-side switch can be responsive to the PWMH signal of the survival mode switching pattern entirely, such that

the survival mode energy can be diverted to the boost converter and the risk of output voltage drifting higher

than the regulation level can be mitigated. It is essential to choose the high-side driver with short power-on delay

less than 10 μs.

8.4.12 Capacitor Voltage Balancing Function

ACF contains two energy storage devices on primary and secondary sides. One is the clamping capacitor

(C_CLAMP) and the other is the output capacitor. When the PWMH signal is enabled, the clamping capacitor

voltage (V_CLAMP) is close to the reflected output voltage (N_PSx V_O). When the PWMH is disabled in LPM mode,

V_CLAMPbecomes higher, because some of the leakage energy will be stored on C_CLAMP, instead of recycling

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to the output, as it does in AAM and ABM. During the control mode transition from LPM to ABM, the capacitor

voltage balancing current in the first PWMH on time is normally bigger than the following PWMH pulses. If the

PWMH on time is too short to discharge C_CLAMP, a high di/dt change of the switching current will flow through

the transformer winding at the turn-off instant of the high side switch, so the leakage inductance will introduce

a high voltage stress across the secondary-side rectifier. Instead of using a strong RC snubber to damp the

voltage spike or a lossy bleed resistor in parallel with C_CLAMP, UCC28782 automatically extends the first PWMH

pulse width around 140% longer than the following PWMH pulse. When the high side switch turns off at lower

di/dt current instance, the voltage stress can be reduced, and the efficiency compromise can be eliminated with

this new voltage balancing function. Moreover, another possibility of triggering the on-time extension function is

under the output voltage ramp down condition, which is a very common transient event of a USB-PD adapter.

If the USB-PD controller on the secondary side is able to program the step size of the reference output voltage

change, the LPM-to-ABM transition will occur during the voltage change. This behavior allows the V_CLAMPto

follow the reflected output voltage change, and minimize the voltage stress on the rectifier.

However, some USB-PD controllers can not smoothly change the reference output voltage, but only offer a

one-step voltage change to a lower reference level. This rapid change prevents the controller from switching in

general, so the chance of voltage balancing during voltage transition is gone. Once the output voltage is settled

to the lower level and PWMH is enabled back again, a big voltage difference between V_CLAMPand the reflected

voltage occurs, and the magnitude of the balancing current may be large enough to create a high voltage stress

and damage the secondary rectifier. In order to resolve this issue, UCC28782 utilizes a patent pending unique

switching pattern in the survival mode to achieve the capacitor voltage balancing, as shown in the following

figure.

With a rapid reference voltage (V_REF(Vo)) change, the feedback current (i_FB) increases and the controller enters

into SBP1 mode. Since this event is like an output overshoot condition, the output voltage feedback loop

prevents the ACF from switching and V_VDDdrops. When V_VDDreaches the 13-V survival mode threshold, the

unique burst packet contains a series of PWML pulses followed by a long PWMH pulse. The PWML pulse

train helps to charge up the bootstrap capacitor voltage, so that the high-side switch can respond to the

PWMH command. When the PWMH is in on state, the unbalanced voltage between V_CLAMPand the reflected

V_BINforces the additional energy to charge up C_BIN. The charge current becomes a useful energy source to

keep V_VDDaway from V_VDD(OFF). At the same time, C_CLAMPcan be discharged gradually. Through the multiple

survival mode events, V_CLAMPcan be discharged to be very close to the reflected output voltage, so the voltage

stress can be reduced. The minimum number of PWML pulses of the first survival-mode event is 9. The rest

survival-mode burst packets contain at least 3 PWML pulses.

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20 V

2

V_O

V_CLAMP/ N_PS

V_REF(Vo)

5 V

i_FB

i_FB(SBP1)

SBP1

PWML

PWMH

Feedback loop

V_VDD

Feedback loop

13 V

V_VDD(OFF)

Figure 8-33. Capacitor Balancing During Output Voltage Transition

8.4.13 Device Functional Modes for Bias Regulator Control

When there is no overlapping between PWML on time and BSW on time and the survival mode is not triggered,

there are two operating modes for the bias regulator when V_BINis between the UVLO(ON) threshold and the

disable threshold. The first is the constant peak current (CPC) control mode for a heavier VDD load condition,

and the second is the burst mode (BM) control for a light VDD load condition. The 18.5-V regulation in CPC

is maintained by varying the boost switching frequency, and the peak current of the boost inductor is fixed at

approx. 0.33 A. The 18.5-V regulation in BM is maintained by changing the burst frequency with a constant peak

current for each switching cycle of a burst packet. There are at least 3 switching cycles in a burst packet for BM.

E.g. when a 22-µH boost inductor (L_B) is used, the mode transition point is at approx. 3-mA VDD load.

In CPC mode, the V_VDDregulation is achieved by changing the boost switching frequency (f_BSW) with a

fixed 0.33-A peak current. When f_BSWis reduced to the minimum controllable frequency, the control loop will

automatically transition into BM. Figure 8-34 illustrates the switching pattern in CPC mode operating in the

transition mode or discontinuous conduction mode (DCM). The internal ZCD detection on BSW pin only allows

the turn on instant of the next boost switching cycle to happen after the BSW-pin voltage falls below the BIN-pin

voltage, so that the boost inductor current drops to zero first.

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DCM Operation in CPC Mode

CCM Operation in COT Mode

BSW_ZC

PWMB

250ns Timer

PWMB

V_BSW

V_VDD+V_DB

V_BSW

V_BIN

I_BSW(MAX)

I_LB

Figure 8-34. Switching Pattern of Boost Converter in CPC and COT Modes

If survival mode is enabled, the regulator will start switching regardless of V_BINlevel and enter into constant

off time (COT) control mode. The COT control mode disables the ZCD detection on the BSW pin and creates

a 250-ns off time in order to force the regulator into the continuous conduction mode (CCM). More energy per

cycle can transfer from the BIN-pin capacitor to the VDD capacitor in CCM, so V_VDDcan be ramped up above

the 13-V survival mode threshold faster than DCM, and minimize the survival mode energy transfer to the output

capacitor on the ACF secondary side, as a result of the drop in V_BIN. When V_VDDis higher than 13 V, the

regulator will automatically change the operation mode back to CPC or BM.

Besides survival mode, when the voltage difference between V_VDDand V_BINis less than 1 V, the regulator will

also disable ZCD detection and allows CCM operation. If ZCD is not disabled, the low voltage difference makes

the demagnetization time of the boost inductor current very long, so V_VDDwould not be able to build up to the

regulation level. The CCM operation can transfer the energy to VDD capacitor quickly, so V_VDDcan recover back

to the regulation level.

8.4.13.1 Mitigation of Switching Interaction with ACF Converter

When the ACF control law is in AAM and ABM modes, the high side switch and ZVS control loop are enabled.

In order to desensitize the boost switching noise interfering with the peak current loop and the ZVS control loop

of the ACF converter, a unique switching misalignment function is activated for these two modes. When the

ACF control law enters into LPM, SBP1, and SBP2 modes, the high side switch is disabled and the converter

operates in valley switching, so switching misalignment function is disabled.

Since the bias regulator switch (Q_BSW) turns off at the highest peak current of the boost inductor, the lumped

parasitic inductance from the BGND-pin bond wire and the PCB traces may create a voltage disturbance on the

current sense signal, and might potentially result in prematurely turn-off of the PWML signal. When the PWML

on time is disturbed, the ZVS control loop may introduce a small calculation error in the PWMH on time, so the

ZVS switching may not be maintained for all switching cycles. To resolve this effect in UCC28782, the switching

misalignment function will automatically avoid the intersection between the Q_BSWturn off edge and the PWML

turn off edge to mitigate the noise interference. Specifically, if Q_BSWstill stays in the on-state when the PWML

signal reaches 70% on time, Q_BSWwill be forced to be turned off earlier, so that the turn off instant for both the

boost converter and ACF converter will not be aligned. Therefore, it is normal that the peak current of the boost

inductor may not be consistent in AAM and ABM because of this misalignment function.

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PWML

PWMB

70%

V_BSW

V_BIN

I_BSW(MAX)

I_LB

Figure 8-35. Switching Misalignment Function

Besides the above di/dt coupling effect, both the dV/dt coupling through the parasitic capacitance of the boost

switching node on the BSW pin and the dB/dt coupling through the inductor flux change need to be considered

in the design. It is important that the noise-sensitive traces or components must be kept away from the high

dV/dt BSW node and the high dB/dt boost inductor flux loop in order to minimize the coupling. A shielded chip

ferrite inductor or a powder core chip inductor is preferred to minimize the flux coupling. If a non-shielding chip

ferrite inductor has to be used, the inductor must not be close to the noise-sensitive components and controller

pins.

8.4.13.2 Protection Functions for the Bias Regulator

The protection features for the integrated bias regulator are summarized in Table 8-2.

Table 8-2. Fault Protections of the Bias Regulator

PROTECTION

SENSING

THRESHOLD

V_BIN≤ V_BIN(ON)

DELAY TO ACTION

ACTION

UVLO ON in boost

mode

BIN voltage

None

Disable BSW switching

UVLO OFF in boost

mode

BIN voltage

V_BIN≤ V_BIN(OFF)

1 Min. BSW LEB time (t_BLEB

None

)

Disable BSW switching

Max. disable threshold

of boost mode

V_BIN≥ V_BIN(DIS)

V_BIN(EN)

+

)

Max. enable threshold of BIN voltage

boost mode

V_BIN≥ V_BIN(EN)

Over current protection BSW current I_BSW≥ I_BSW(MAX)

of boost mode

1 Min. BSW LEB time (t_BLEB

1 BSW pulse

)

Minimum off-time of 4 µs before

another BSW cycle

Missing ZCD timeout

BSW and BIN V_BSW≥ V_BIN

voltages

Delay 700 µs and retry

VDD over-voltage

protection

VDD voltage

V_VDD≥ V_BOVPTH

None

Disable BSW switching, and retry

after V_VDD≤ V_BOVPR

8.4.13.3 BIN-Pin Related Protections

The 2.2-V UVLO(ON) threshold, 1-V UVLO(OFF) threshold, and the 30-V Max. voltage rating on the BIN pin

allows the switching bias regulator to generate a usable bias power for a wide output voltage range application.

The 15-V boost mode disable threshold allows the rectified auxiliary winding voltage to supply the bias power

directly without the boost conversion loss. For example, when a 3.3-V to 21-V output voltage range is needed,

the turns ratio between the auxiliary winding and the secondary winding should be set to one. The boost mode

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operation will regulate V_VDDat 18.5 V for the 3.3-V to 14.9-V output range. The boost operation is disabled in the

15-V to 21-V output voltage range, V_VDDfollows the output voltage change with a boost diode drop.

8.4.13.4 BSW-Pin Related Protections

In constant peak current (CPC) mode, the zero crossing detect (ZCD) on the BSW pin is critical to trigger the

switching instant of the next cycle, so the missing ZCD timeout feature can avoid the risk of inability to sense

ZCD in a given switching cycle. The normal peak current threshold is approx. 0.33 A for every BSW switching

cycle. In DCM operation of the CPC mode, the ZCD detection is enabled to allow the boost inductor current to

decay to zero before the next switching cycle. The internal detection network compares the V_BSWand V_BINto

qualify for a valid ZCD event. If the ZCD event can not be detected for a given cycle, a 700-µs timer is enabled

and then the next switching cycle occurs after the 700-µs has expired.

4.35-µs Timer for BSW OCP

t_BOFF(MIN)Timer of COT control

t_BLEBTimer

PWMB

V_VDD+V_DB

V_BIN

V_BSW

I_LB

I_BSW(MAX)

Figure 8-36. Operation Principle of Over Current Protection in Boost Mode

In constant off time (COT) mode, it is critical to prevent the inductor from reaching the saturation limit. Due

to the CCM operation of COT mode, if the peak current is higher than 0.33 A after the 190-ns leading edge

blank time, a 4.35-µs timer is enabled and then the next switching cycle cannot be initiated until after the 4.35

µs has elapsed. The operating principle is shown in Figure 8-36. This built-in over current protection prevents

the chance of accumulated peak current overshoot in CCM, so the risk of boost inductor saturation can be

eliminated.

8.4.14 System Fault Protections

The UCC28782 provides extensive protections on different system fault scenarios. The protection features are

summarized in Table 8-3.

•

The system fault responses of UCC28782A and UCC28782AD are all auto-recovery.

The fault responses of UCC28782BDL are latch-off for OVP, OPP, PPL, OCP, SCP, OTP on the FLT pin, and

OTP on the CS pin. The remaining faults are auto-recovery.

•

The fault responses of UCC28782CD are latch-off for OVP and OTP on the FLT pin. The remaining faults are

auto-recovery.

The response for any latch-off fault will disable the switching until a latch-reset event is detected. Resetting a

latched fault can be achieved by either discharging V_VDD< V_VDD(RST)or triggering the LZC detection on the

XCD pin. Due to the large input bulk capacitor, V_VDDcan stay above V_VDD(RST)for a long time at no output load

after the AC line is removed. If there is a need to reset the fault condition quickly for fast recovery of the output

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voltage, the application circuit for the XCD pin can be used. The detection timing of the XCD pin allows the latch

to be reset and initiate the switching attempt, after reapplying the AC line in less than 2 seconds.

Table 8-3. System Fault Protection

DELAY TO ACTION BY

ACTION UCC28782A,

UCC28782AD

ACTION BY

UCC28782BDL

ACTION BY

UCC28782CD

PROTECTIO SENSIN

THRESHOLD

V_VDD(OFF)≤ V_VDD≤ V_VDD(ON)

I_VSL≤ I_VSL(RUN)

N

G

VDD UVLO

VDD

None

UVLO reset

voltage

Brown-in

detection

VS

current

4 PWML UVLO reset

pulses

Brown-out

detection

VS

current

I_VSL≤ I_VSL(STOP)

t_BO(60ms) UVLO reset

plus 3

confirming

PWML

pulses

Over-power

protection

(OPP)

CS

voltage

V_CST(OPP)≤ V_CST≤ V_CST(MAX)

t_OPP(160 t_FDRrestart (1.5s)

ms)

Latch off

t_FDRrestart

Peak-power CS

V_CST≤ V_CST(MAX)

V_CS≥ V_OCP

limit (PPL)

voltage

Over-current CS

3 PWML t_FDRrestart

pulses

Latch off

t_FDRrestart

protection

(OCP)

voltage

Output short- CS, VS, (1) V_VDD= V_VDD(OFF)& V_CST

≥

≤ t_OPP

t_FDRrestart

circuit

protection

(SCP)

and VDD V_CST(OPP); (2) V_VDD= V_VDD(OFF)

voltages V_VS≤ V_VS(SM2)

&

Output over- VS

V_VS≥ V_OVP

3 PWML t_FDRrestart

pulses

Latch off

voltage

protection

(OVP)

voltage

Over-

FLT

R_NTC≤ R_NTCTH

t_FLT(NTC)(50 UVLO reset until

temperature voltage

protection on

FLT pin

µs)

R_NTC≥ R_NTCR

(OTP)

Over-

temperature voltage

protection on

CS

V_CS≥ V_OCP

2 PWMH t_FDRrestart

pulses

Latch off

t_FDRrestart

CS pin (OTP)

Input over-

voltage

protection

(IOVP)

FLT

voltage

V_FLT≥ V_IOVPTH

t_FLT(IOVP)UVLO reset until

UVLO reset until

(750 µs)

V_FLT< V_IOVPTH

V_IOVPR

-

V_FLT< V_IOVPTH

V_IOVPR

-

V_FLT< V_IOVPTH

V_IOVPR

-

Thermal

shutdown

Junction T_J≥ T_J(STOP)

temperat

ure

3 PWML UVLO reset

pulses

UVLO reset

8.4.14.1 Brown-In and Brown-Out

The VS pin senses the negative voltage level of the auxiliary winding during the on-time of the low-side switch

(Q_L) to detect an under-voltage condition of the input AC line. When the bulk voltage (V_BULK) is too low,

UCC28782 stops switching and no V_Orestart attempt is made until the AC input line voltage is back into normal

range. As Q_Lturns on with PWML, the negative voltage level of the auxiliary winding voltage (V_AUX) is equal to

V_BULKdivided by primary-to-auxiliary turns ratio (N_PA) of the transformer, which is N_P/ N_A. During this time, the

voltage on VS pin is clamped to about 250 mV below GND. As a result, V_AUXcan create a line-sensing current

(I_VSL) out of the VS pin flowing through the upper resistor of the voltage divider on VS pin (R_VS1). With I_VSL

proportional to V_BULK, it can be used to compare against two under-voltage thresholds, I_VSL(RUN)and I_VSL(STOP)

.

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The target brown-in AC voltage (V_AC(BI)) can be programmed by the proper selection of R_VS1. For every UVLO

cycle of VDD, there are at least four initial test pulses from PWML to check I_VSLcondition. I_VSLof the first

test pulse is ignored. If I_VSL≤ I_VSL(RUN)is valid for the next three consecutive test pulses, the controller stops

switching, the RUN pin goes low, and a new UVLO start cycle is initiated after V_VDDreaches V_VDD(OFF). On the

other hand, if I_VSL> I_VSL(RUN)occurs, V_Osoft start sequence is initiated.

V_{AC(BI )}

2

V_{AC(BI )}2

N_A

R_VS1

=

N_PAì I_{VSL(RUN )}N_P365

m

A

(16)

The brown-out AC voltage (V_AC(BO)) is set internally by approximately 83% of V_AC(BI), which provides enough

hysteresis to compensate for possible sensing errors through the auxiliary winding.

I_VSL(STOP)

V_AC(BO)

=

V_{AC(BI )}= 0.83ìV_{AC(BI )}

I_{VSL(RUN )}

(17)

A 60-ms timer (t_BO) is used to bypass the effect of line ripple content on the I_VSLsensing. Only when the I_VSL

≤

I_VSL(STOP)condition lasts longer than 60 ms (i.e. typically three line cycles of 50 Hz) and 3 additional switching

cycles verify the condition, the brown-out fault is triggered. If switching is interrupted, the brown-out fault will

remain pending without shut-down until the 3 verification cycles complete. The fault is reset after V_VDDreaches

V_VDD(OFF). Figure 8-37 shows an example of the timing sequence of brown-out and brown-in protections for the

case of an actual input brown-out condition.

Figure 8-37. Timing Diagram of Brown-Out/Brown-In Response on AC Line Events

The t_BOtimer is started at the moment I_VSL≤ I_VSL(STOP)is detected during the PWML on-time. The timer is

cleared when I_VSL> I_VSL(STOP)is detected. In the case of an overshoot voltage on the output, switching will stop

until the output voltage recovers to the regulation level. If the t_BOtimer is triggered by I_VSL≤ I_VSL(STOP)while in

the valley of the bulk ripple voltage, and then switching is stopped the status of I_VSLcannot be detected and

updated. The timer cannot be cleared without switching to sample I_VSL, and the 60-ms timer may elapse even

though no brown-out condition exists. To prevent an unwarranted shut-down, the 3 additional switching cycles

sample the condition once switching does resume, to verify or dismiss the pending apparent brown-out fault. An

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extended output overshoot condition longer than t_BOcan result from a sudden load drop combined with a drop

in the regulation reference due to reduction of cable compensation. Figure 8-38 shows an example of the timing

sequence for the case of an apparent brown-out cancelled by 3 verifying pulses.

Figure 8-38. Timing Diagram of Brown-Out Response on Extended Output Overshoot

8.4.14.2 Output Over-Voltage Protection (OVP)

The VS pin is used to sense the positive voltage level of the auxiliary winding voltage (V_AUX) to detect an

over-voltage condition of V_O. When an OVP event is triggered, the auto-recovery version of OVP stops switching

and there is a 1.5-s fault recovery time (t_FDR) before any V_Orestart attempt is made. As Q_Lturns off, the settled

V_AUXis equal to (V_O+V_F) x N_AS, where N_ASis the auxiliary-to-secondary turns ratio of the transformer, N_A/ N_S,

and V_Fis the forward voltage drop of the secondary-side rectifier. The VS pin senses V_AUXthrough a voltage

divider formed by R_VS1and R_VS2. The pin voltage (V_VS) is compared with an internal OVP threshold (V_OVP). If

V_VS≥ V_OVPcondition is qualified for three consecutive PWML pulses, the controller stops switching, brings RUN

pin low, and initiates the 1.5-s time delay. During this long delay time, only the UVLO-cycle of V_VDDis active, and

there are no test pulses of PWML. After the 1.5-s timeout is completed and V_VDDreaches the next V_VDD(OFF), a

normal start sequence begins. The calculation of R_VS2is

R_VS1ìV_OVP

R_VS1ì4.5V

R_VS2

=

N_ASì(V_O(OVP)+V_F) -V_OVP(N_A/ N_S)(V_O(OVP)+V_F) - 4.5V

(18)

The long t_FDRtimer helps to protect the power stage components from the large current stress during every

restart. After OVP is triggered, V_Omay be brought down quickly by the output load current. If OVP were reset

directly after one UVLO cycle of VDD without the 1.5-s delay, the first PWMH pulse turns on Q_Hunder the

condition of a large voltage difference between the high clamp capacitor voltage (V_CLAMP) and the low reflected

voltage. A large current can flow through the clamp switch (Q_H) and secondary rectifier. Therefore, the 1.5-s

timer of UCC28782 allows V_CLAMPto drop to a lower voltage level through a bleeding resistor (R_BLEED) in parallel

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with C_CLAMPbefore the next V_Orestart attempt, such that the current stress can be minimized. A large R_BLEED

can be used with the long time-out to minimize the impact on standby power. For example, to discharge V_CLAMP

to 10% of its normal level in 1.5 s, only 3 mW of additional standby power is added with R_BLEED= 2.8 MΩ and

C_CLAMP= 220 nF. The Timing Diagram of C_CLAMPDischarging During 1.5-s Recovery Time illustrates the timing

sequence as V_CLAMPis discharged to a residual voltage (V_RESIDUAL) in 1.5 s. R_BLEEDalso helps to reduce the

voltage overcharge on the clamp capacitor in LPM, SBP1, and SBP2 modes in which PWMH is disabled, so the

voltage stress in the passive-clamp operation can be controlled.

t_FDRTimer

V_VDD(ON)

V_VDD

1.5 s

V_VDD(OFF)

V_CLAMP

N_PS(V_O+V_F)

V_RESIDUAL

PWML

Figure 8-39. Timing Diagram of C_CLAMPDischarging During 1.5-s Recovery Time

8.4.14.3 Input Over Voltage Protection (IOVP)

The UCC28782 provides an input OVP function on the FLT pin. Figure 8-40 shows the application circuit for the

input OVP sensing. A resistor divider senses the bulk capacitor voltage, and the IOVP fault is triggered when

V_FLT> 4.5 V for longer than 750 µs. The 750 µs delay helps to desensitize the abrupt bulk voltage spike during

the line surge condition, such that the output voltage will not drop accidentally. After the IOVP fault is asserted,

the switching will be terminated immediately and V_VDDwill restart. When V_VDDreaches V_VDD(ON)of the following

VDD cycle, the controller will check V_FLTfirst before switching, to avoid the switching device from being exposed

to a high-voltage stress condition. The fault will be cleared when V_FLT< 4.43 V.

If longer than 750 µs delay is required, a filter capacitor between the FLT pin and AGND pin can create

additional programmable delay. If the filter capacitor is too large, it may trigger the OTP fault on the FLT pin,

if the ramp up time for V_FLTto rise above V_NTCTHis longer than t_FLT(NTC)after the RUN pin is pulled high. The

resistor divider design does not need to consider the offset voltage effect from the 50 µA current source out of

the FLT pin, because the controller will disable the current source once V_FLT> 2.5 V.

The goal of the internal 5.5-V clamp device on the FLT pin is to protect the pin from exceeding the voltage limit

when one of the IOVP upper sensing resistor fails short. The maximum clamp current is 150 µA, so the resistor

divider design needs to consider this limitation.

V_BULK

I_FLT

R_FLT1

V_IOVP

R_FLT2

INPUT OVP FAULT

OTP FAULT

œ

t_FLT(IOVP)delay

(750µs)

(4.5V/4.43V)

FLT

+

V_FLTZ

(5.5V)

R_FLT3

C_FLT

+

t_FLT(NTC)delay

(50µs)

V_NTCTH

(0.5V/1.15V)

œ

Figure 8-40. Bulk Capacitor Voltage Sensing for Input OVP

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8.4.14.4 Over-Temperature Protection (OTP) on FLT Pin

The UCC28782 uses an external NTC resistor (R_NTC) tied to the FLT pin to program a thermal shutdown

temperature near the hotspot of the converter. The NTC shutdown threshold (V_NTCTH) of 0.5 V with an internal

50-μA current source flowing through R_NTCresults in a 10-kΩ thermistor shutdown threshold. If the NTC

resistance stays lower than 10 kΩ for more than 50 μs, an OTP fault event is triggered. The 50-μs delay

(t_FLT(NTC)) allows a filter capacitor (C_FLT) to be placed between the FLT pin and the AGND pin, when the NTC

resistor is located far away from the controller but close to the hot spot. To avoid the OTP fault from false trigger

as RUN goes high, C_FLTshould be designed to allow V_FLTincreased above V_NTCTHwithin t_FLT(NTC). On the other

hand, if the NTC resistor is close to the controller and there is no potential noise coupling path to the sensing

traces, C_FLTis not needed.

For auto-recovery mode, the 0.5-V threshold is increased to 1.15 V after the OTP fault, so the NTC resistance

has to increase above 23 kΩ to reset the OTP fault. This threshold change provides a safe temperature

hysteresis to help the hot-spot temperature cool down before the next V_Orestart attempt, reducing the thermal

stress to the components. If the FLT pin is not used, the pin can be left floating but can not be connected to REF

pin, since the line OVP will be falsely triggered.

The thermal issue in the heavy output load condition is the main design consideration for OTP, and the heavy

load operating mode, AAM, allows the controller to stay in the run state continuously, so the 50-μs delay allows

V_FLTto trigger OTP. Based on the practical BUR-pin setting, 50% to 60% load is operated in AAM. The 50-μA

current source is disabled in the burst off time of the light load modes such as ABM, LPM, SBP1, and SBP2, in

order to save standby power. However, when the run state becomes shorter than the 50-μs in these modes but

the current source is disabled in the wait state, the OTP will not be able to trigger because there is not enough

time to detect the fault. Therefore, if certain design considerations still require the OTP to be armed in light load

modes, a second OTP configuration can be considered by reusing the 4.5-V threshold of input OVP. As shown

in Figure 8-41, the upper NTC resistor and the lower resistor form a resistor divider from the REF pin to the

FLT pin. The 750-μs delay is independent to the wait state condition of controller, so the OTP fault can still be

triggered in the light load mode. This configuration provides auto-recovery mode only.

1^stOTP Sensing

2^ndOTP Sensing

REF

R_NTC

FLT

R_NTC

R_FLT

C_FLT

Figure 8-41. Two Connections to Implement OTP on the FLT Pin

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1.15 V

0.5 V

V_NTC

t_FLT(NTC)

OTP Fault

V_VDD

V_VDD(ON)

V_VDD(OFF)

PWML

Figure 8-42. OTP Timing Diagram for a NTC between the FLT Pin and AGND Pin

8.4.14.5 Over-Temperature Protection (OTP) on CS Pin

In case the FLT pin is already used for the input OVP sensing, UCC28782 provides the third and fourth OTP

functions on the CS pin. The two configurations do not affect the current sense signal on the CS pin and the

OPP level, because the two sensing circuits are only biased after PWML is off. Figure 8-43 shows the two

application circuits. For the third OTP configuration, when the PWMH pin is pulled high, R_NTCand R_OPPform

a resistor divider to create a temperature-dependent voltage signal on the CS pin. When the voltage exceeds

the 1.2-V threshold sampled before the end of the demagnetization time (T_DM) for two successive cycles, the

OTP fault will be triggered. The OTP sensing circuit will not affect the operation of the peak current loop, since

the PWMH is pulled low in the PWML on time duration. For auto-recovery mode, the long 1.5-s timer starts and

the controller stays in fault state without switching. This long recovery time provides a temperature hysteresis

to help the hot-spot temperature cool down before the next V_Orestart attempt. Compared with the first OTP

configuration on the FLT pin, this configuration allows the OTP armed in both AAM and ABM, so the OTP can

still be triggered at around 25% output load. Compared with the second OTP configuration from FLT pin, this

configuration supports both auto-recovery and latch-off modes.

The fourth configuration with a small-signal PMOS is the most comprehensive way to cover a wide output load

range and support both auto-recovery and latch-off modes at the same time. The RUN pin is used to bias the

sensing circuit, and the PMOS gate is controlled by the PWML pin to only allow the detection to occur when

PWML is low.

3^rdOTP Sensing

4^thOTP Sensing

RUN

PWML

PWMH

Q_RUN

R_NTC

R_OPP

CS

R_CS

C_CS

Figure 8-43. Two Connections to Implement OTP on the CS Pin

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8.4.14.6 Programmable Over-Power Protection (OPP)

The over-power protection (OPP) enables the ACF to operate in an over-power condition for a limited amount of

time, so the UCC28782 can support a power stage design with peak power requirements. As shown in Figure

8-44, when V_CSTis higher than the threshold voltage of the OPP curve (V_CST(OPP)), a 160-ms timer starts. For

the auto-recovery mode, if V_CSTremains higher than V_CST(OPP)continuously for 160 ms, the 1.5-s timer starts

and the controller stays in fault state without switching. This long recovery time reduces the average current

during a sustained over-power event. The system benefits includes the reduction of thermal stress in high

density adapters and the protection of its output cable.

The OPP function uses I_VSLas a line feed-forward signal to vary V_CST(OPP)depending on V_BULK, in order to

make the OPP trigger point constant over a wide line voltage range. The UCC28782 allows programmability of

the OPP curve by adding a line-compensation offset voltage on the CS pin through a resistor (R_OPP) connected

between the CS pin and current-sense resistor (R_CS). An internal current source flowing out of CS pin creates

the offset voltage on R_OPP. This current level is equal to I_VSLdivided by a constant gain of K_LC. As R_OPP

increases, the OPP trigger point becomes lower at high line, so lower peak magnetizing current is allowed to run

continuously.

The OPP function uses V_VSas an output voltage feed-forward signal to modify the line-dependent V_CST(OPP)

curve into the two different sets, such that the OPP trigger point can be more consistent across a wide output

voltage range. The higher OPP threshold under V_VS> 2.5 V contains two piece-wise linear regions, and the

lower OPP threshold under V_VS< 2.4 V contains one piece-wise linear region.

The highest threshold of OPP curve (V_CST(OPP1)) of 0.6 V helps to determine R_CSvalue at V_BULK(MIN)

.

V_{CST (OPP1)}

R_CS=

P

V_{BULK (MIN )}t_{D(CST )}

2

O(OPP)

-

V_{BULK (MIN )}

h

D_MAX

L_M

(19)

where P_O(OPP)is the output power that triggers OPP, and t_D(CST)is the sum of all delays in the peak current loop

which contributes additional peak current overshoot. t_D(CST)consists of propagation delay of the low-side driver,

current sense filter delay (R_OPPx C_CS), internal CS comparator delay (t_D(CS)), and nonlinear capacitance delay of

Q_L. After R_CSis determined, R_OPPcan be adjusted to keep a similar OPP point at highest line. Note that setting

the OPP trigger point too far away from the full power may introduce more challenge on the thermal design,

since the converter runs continuously with more power as long as the corresponding peak current is slightly less

than OPP threshold.

V_CST

V_CST(MAX)for V_VS> V_VSLV(UP)

0.8 V

V_{CST(MAX)_LV}for V_VS< V_VSLV(LR)

V_CST(OPP)for V_VS> V_VSLV(UP)

V_{CST(OPP)_LV}for V_VS< V_VSLV(LR)

0.655 V

0.628 V

0.6 V

0.57 V

0.491 V

0.471 V

0.54 V

0.4275V

0.405V

i_VSL

233 µA 433 µA

966 µA

Figure 8-44. V_CSTOPP curve across I_VSL

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t_OPPTimer

160ms

t_FDRTimer

1.5s

V_VDD(ON)

V_VDD

V_VDD(OFF)

I_O

V_CST(MAX)

V_CST(OPP)

V_CST

V_CST(SM2)

V_CST(SM1)

PWML

V_O

Figure 8-45. Timing Diagram of OPP

8.4.14.7 Peak Power Limit (PPL)

The peak current threshold of the OPP curve is used to initiate the 160-ms timer, while the peak power limit

(PPL) determines the highest controllable peak current of the peak current loop, V_CST(MAX). Regardless of V_VS

,

the ratio between V_CST(MAX)and V_CST(OPP)is fixed at approx. 4/3. In other words, this feature provides the

highest “short duration” peak power (P_O(MAX)) that the converter can reach. The line-dependent PPL curve is

able to achieve a consistent peak power level over a wide input voltage range. For example, to supply a highest

peak power of 150%, R_CSshould be chosen to ensure that the peak current at 150% load and V_BULK(MIN)must

not be above V_CST(MAX). Then, the threshold of the OPP power (P_O(OPP)) can be programmed to around 112% to

support 150% peak power design, based on the following equation. Additionally, before V_Oreaches steady state

during V_Osoft-start, the highest V_CSTcan also reach to V_CST(MAX). The transformer must have enough design

margin separating its maximum flux density from the saturation limit of the core material under the peak current

level in PPL.

V_{CST (OPP1)}

0.6V

0.8V

P

=

P

=

P

O(MAX )

O(OPP)

O(MAX )

V_{CST (MAX )}

(20)

8.4.14.8 Output Short-Circuit Protection (SCP)

When an output short-circuit is applied, the peak current reaches the PPL limit and triggers the 160-ms OPP

fault timer. During this event, the VDD power supply is lost due to the auxiliary winding voltage being close to

0 V. Without additional short-circuit detection, if V_VDDreaches V_VDD(OFF)before the 160-ms timeout, the 1.5-s

recovery time for the OPP fault cannot be triggered but only a UVLO recycle is performed. To remedy this

scenario, as V_VDDreaches V_VDD(OFF), the auto-recovery version of UCC28782 checks two additional parameters

to identify the short-circuit event at the output, and triggers the fault response without waiting for 160 ms to

expire. Specifically, when V_VDDreaches V_VDD(OFF), if either V_CSTis greater than the OPP threshold (V_CST(OPP)

)

or the VS-pin voltage is less than 0.5 V, the 1.5-s recovery delay is initiated for auto-recovery mode. With

this additional layer of intelligence, the average load current during continued short-circuit event can be greatly

reduced, and thus also the thermal stress on the power supply.

8.4.14.9 Over-Current Protection (OCP)

The UCC28782 operates with cycle-by-cycle primary-peak current control. The normal operating range of the CS

pin is between V_CST(MIN)and V_CST(MAX). If the CS-pin voltage exceeds the 1.2-V over-current level, any time after

the internal leading edge blanking time (t_CSLEB) and before the end of the transformer demagnetization, for three

consecutive PWML cycles, the device stops switching, RUN pin goes low, and the fault response is triggered.

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Similar to OVP, OPP, and SCP, only the UVLO-cycle of VDD is active, there are no test PWML pulses at all. For

auto-recovery mode, after the 1.5-s time-out is completed and V_VDDreaches the next V_DD(OFF), a normal start

sequence begins.

8.4.14.10 External Shutdown

The REF pin can be used as an external shutdown function by shorting this pin to AGND with a small-signal

control switch. This provides an additional design flexibility for the control function extension with external

circuitry. When the REF-pin voltage drops lower than its power good threshold, the switching action will be

terminated and V_VDDwill drop to V_VDD(OFF), so the controller will need to restart V_VDD. When the external switch

keeps shorting the REF pin continuously, switching action is inhibited until the external pull-down on REF is

released. During the switch-short condition, the falling slope of V_VDDwill drop faster than normal case because

the 17-mA over-current limit of the REF regulator discharges VDD capacitor faster than the normal I_VDDcurrent

in run state and wait state.

8.4.14.11 Internal Thermal Shutdown

The internal over-temperature shutdown threshold is higher than 125°C. If the junction temperature of the device

reaches this threshold, the device initiates a UVLO reset and restart fault cycle. If the temperature is still high at

the end of the UVLO cycle, the protection cycle repeats. This internal protection is not suitable as a substitute

for the NTC for hot-spot temperature protection. The NTC thermistor can provide more accurate and remote

temperature sensing with less compromise on PCB layout.

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8.4.15 Pin Open/Short Protections

As summarized in Table 8-4, UCC28782 strengthens the protections of several critical pins under "open"

and "short" conditions, such as CS, P13, RDM, and RTZ pins. The pin protections are all in auto-recovery

modes. UCC28782A does not have the XCD-pin over voltage protection. All "short" conditions are defined as

short-circuits to AGND.

Table 8-4. Protections for Open and Short of Critical Pins

DELAY TO

ACTION

PROTECTION

SENSING

CONDITION

> 2 μs (V_SET= 5 V)

ACTION

PWML on-time at first PWML

pulse only

CS pin short

> 2 μs (V_SET= 0 V, R_RDM≥ R_RDM(TH)

)

none

t_FDRrestart (1.5 s)

> 1 μs (V_SET= 0V, R_RDM< R_RDM(TH)

)

3 PWML

pulses

CS pin open

P13 pin open

CS voltage

P13 voltage at UVLO_ON

P13 voltage

V_CS≥ V_OCP

t_FDRrestart (1.5 s)

UVLO reset

V_P13drops to 14 V within 10 μs

V_P13≥ V_P13(OV)+ V_P13(REG)

none

P13 pin over

voltage

3 PWML

pulses

UVLO reset

RDM pin short

RDM pin open

RTZ pin short

RTZ pin open

RDM current at UVLO_ON

RTZ current at UVLO_ON

V_RDM= 0 V, self-limited I_RDM

RDM = Open

none

UVLO reset

V_RTZ= 0 V, self-limited I_RTZ

RTZ = Open

XCD pin over

voltage

XCD voltage

V_XCD> V_XCD(OVP)

750 μs

UVLO reset

8.4.15.1 Protections on CS pin Fault

UCC28782 identifies a fail-short event on the CS pin by monitoring the on-time pulse width of the first PWML

pulse after V_VDDstartup is completed. As shown in Figure 8-32, the normal first on-time pulse width should be

limited by the clamped V_CST(SM1)level of 0.2 V and the rising slope of the current-loop feedback signal from

the current-sense resistor (R_CS) to the CS pin. When the current feedback path is gone due to a CS pin short

to GND, the peak magnetizing current increases and potentially can damage the power stage. Therefore, a

maximum on-time of the first PWML pulse for V_SET= 5 V, t_CSF1of 2 μs in the electrical table, is used to limit

the first peak-current stress of the silicon-based converter and then will trigger a CS pin short protection which

initiates the t_FDRrecovery of 1.5 s in auto-recovery mode.

Additionally, t_CSF0in the electrical table confines the maximum on-time of the first PWML pulse on the GaN-

based converter with V_SET= 0 V. There are two corresponding values based on two predetermined ranges

of the RDM pin setting in order to provide the protection over a wider switching frequency range. Specifically,

t_CSF0is set at 2 μs with R_RDMhigher than the R_RDM(TH)threshold of 55 kΩ, while t_CSF0is reduced to 1 μs

under R_RDM< R_RDM(TH). Since a GaN-based converter is capable of operating at higher switching frequency

with lower magnetizing inductance (L_M), it is possible that the peak current can be increased higher than a

lower switching-frequency design under the same V_CST(SM1)level and same on-time of PWML. The RDM pin can

provide a good indication of the switching frequency range of a GaN power stage, since the lower L_Mrequires

smaller R_RDMsetting. With a different t_CSF0setting, the CS pin fault adapts to a wide switching frequency range.

Unlike a CS pin short protection which senses only the first on-time pulse width of PWML only, CS pin open

protection monitors the fail-open condition cycle-by-cycle. An internal 4-μA current source out of the CS pin is

used to pull the CS pin voltage up to 3.3 V as the CS pin exhibits high impedance during a fail-open condition. If

the CS voltage is higher than the 1.2-V threshold of the OCP limit and lasts for three consecutive PWML pulses,

the CS pin open protection is triggered which initiates the 1.5-s recovery.

8.4.15.2 Protections on P13 pin Fault

As shown in Figure 8-32, after V_VDDreaches V_VDD(ON), an internal 13-V regulator on the P13 pin should force

V_P13back to the regulation level before PWML starts switching. If the recommended P13-pin capacitor (C_P13) of

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1 µF and the connection to the depletion-mode MOSFET (Q_S) are in place, the settling time of V_P13to 14 V is

much longer than 10 μs with a limited 1.9-mA sink current of the regulator (I_P13(START)) to discharge C_P13

.

The first fault scenario is that if C_P13is too small, or the P13 pin is open, the pin is not able to control Q_Scorrectly

for the high-voltage sensing function of ZVS control, so no switching action will be performed. When either two

situations happen, V_P13settles to 13 V very quickly instead. Therefore, after a 10-μs delay from the instant of

V_VDDreaching V_VDD(ON), UCC28782 checks if V_P13is below 14 V for the pin-fault detection, and then performs

one UVLO cycle of VDD directly without switching as the protection response.

The above protection is to prevent the controller from generating PWM signals. However, when the P13 pin is

open and disconnected from the Q_Sgate, the source voltage of Q_Skeeps increasing. To protect the P13-pin

open event, a small Zener diode (D_P13) between Q_Sgate to AGND should be used to limit the Q_Ssource

voltage. D_P13should be higher than V_VDD(ON), so as to prevent interference with normal VDD startup. A 20-V

Zener diode is recommended.

The second fault scenario is the over-voltage condition of P13 pin after the converter starts switching. When

the switch-node voltage (V_SW) rises with a high dV/dt condition, there is a charge current flowing through the

junction capacitance of Q_S, and part of the current can charge up C_P13. If the overshoot is too large, the voltage

on the SWS pin also increases due to the nature of depletion-mode MOSFET operation. UCC28782 detects the

overshoot event on P13 pin with a 15-V over-voltage threshold cycle-by-cycle. When V_P13is higher than 15 V for

three consecutive PWML pulses, the P13 over-voltage protection is triggered which performs one UVLO cycle of

VDD.

The third fault scenario is an P13 pin short event at the beginning of VDD startup, and Q_Sis unable to charge up

the VDD capacitor to V_DD(ON), so there is no chance to enable the controller.

8.4.15.3 Protections on RDM and RTZ pin Faults

Since RDM and RTZ pins are the critical programming pins for ZVS control, UCC28782 offers both open-circuit

and short-to-GND protections for those pins. At initial start-up when V_VDDreaches V_VDD(ON)and before switching

begins, a fixed voltage level is applied to each pin and the corresponding current level flowing out of the pin is

sensed to detect a pin-fault condition. As a result, too small of a current represents the pin-open state, and too

large of a current represents the pin-short state where the short-circuit current level is self-limited.

In general, maintain 2 kΩ < R_RDM< 500 kΩ and 20 kΩ < R_RTZ< 1.1 MΩ with ample margins to avoid triggering

one of these faults. When a pin-fault condition is identified, no switching is allowed and one UVLO cycle of VDD

is triggered as the protection response. The normal start-up sequence will proceed on the next VDD cycle after

the fault condition is removed.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

A typical application of a high-frequency active-clamp flyback (ACF) converter, using the UCC28782 ACF

controller, is to enable high-density AC-to-DC power supply design which complies with stringent global

efficiency standards and high-density power packaging. Both Silicon (Si) and Gallium Nitride (GaN) power

MOSFETs may be used, with appropriate gate drivers for each.

9.2 Typical Application Circuit

The following 65-W USB-PD application circuit applies to a GaN-based power stage with the SET pin connected

to the AGND pin.

L_DAMP

V_O

Transformer

D_BG

F_AC

V_BUS

V_BULK

V_AC

Q_PD

L_K

L_O

C_X

C_BULK

L_M

N_P

N_S

C_CLAMP

C_O1

C_O2

Q_SEC

D_BOOT

GND

C_REG

V_S13

GaN

Power IC

D_RUN

C_BOOT

VCC2

C_RUN

VD VG VS

V_O

SR Controller

REG

VDD

PWM

VCC1

V_P13

ISO7710F

OUT

IN

C_VDDH

Q_S

GND1

GND2

D_SWS

PWMH

RUN

V_S13

C_DIFF

GaN

Power IC

V_P13

C_S13

PWM

V_SWS

PWML

PGND

C_VDDL

V_RCS

C_SWS

V_BIN

D_AUX

L_B

D_B

R_CS

C_BIN1

C_BIN2

C_VDD1

N_A

V_P13

V_S13

D_BIN

D_P13

C_VDD2

C_P13

C_INT

VS

XCD

BIN BGND BSW

VDD

P13

S13

SWS

V_SWS

XCD

V_REF

RUN

UCC28782

PWMH

PWML

PGND

PWML

PGND

BUR

SET

REF

FB RDM RTZ EP AGND FLT IPC

CS

R_OPP

V_RCS

V_REF

C_FB

C_REF

C_CS

R_FB

Figure 9-1. Typical Application Circuit

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9.2.1 Design Requirements for a 65-W USB-PD Adapter Application

Table 9-1. UCC28782 Electrical Performance Specifications for GaN FET⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT CHARACTERISTICS

V_IN

Input line voltage (RMS)

90 115 / 230

264

63

V

f_LINE

Input line frequency

47

50 / 60

55

Hz

V_IN= 230 V_RMS, I_O= 0 A

70

mW

Input power at no-load,

V_O= 5 V

P_STBY

V_IN= 115 V_RMS, I_O= 0 A

45

70

V_IN= 230 V_RMS, P_O= 250 mW

V_IN= 115 V_RMS, P_O= 250 mW

399

359

470

Input power at 0.25-W load,

V_O= 20 V

P_0.25W

OUTPUT CHARACTERISTICS

Output voltage, 20-V setting

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3.25 A

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3 A

19.95

15.06

9.05

V

Output voltage, 15-V setting

Output voltage, 9-V setting

Output voltage, 5-V setting

V_O

5.05

Full-load rated output current,

20-V setting

3.25

A

I_O(FL)

V_IN= 90 to 264 V_RMS, V_O= 20 V

Full-load rated output current,

15-V, 9-V, 5-V settings

3.00

150

I_O(FL2)

V_IN= 90 to 264 V_RMS, V_O= 15 V, 9 V, 5V

Output ripple voltage, peak to

peak

20-V setting

600 mVpp

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3.25 A

V_IN= 90 to 264 V_RMS, I_O= 0 A to 3 A

Output ripple voltage, peak to

peak

15-V setting

450

300

200

V_{O_pp}

Output ripple voltage, peak to

peak

9-V setting

Output ripple voltage, peak to

peak

5-V setting

P_O(OPP)

t_OPP

Over-power protection threshold V_IN= 90 to 264 V_RMS

70

W

ms

Over-power protection duration

V_IN= 90 to 264 V_RMS, P_O> P_O(OPP)

160

Output voltage deviation during

step-load transient

V_O= 20 V, I_Ostep between 0 A to I_O(FL)at 100

Hz

-604 /

+340

±1000 mVpp

ΔV_O

SYSTEM CHARACTERISTICS

η_{FL_20}

V_IN= 230 V_RMS, I_O= 3.25 A

V_IN= 115 V_RMS, I_O= 3.25 A

V_IN= 90 V_RMS, I_O= 3.25 A

V_IN= 230 V_RMS

94%

93%

89%

79%

94.2%

93.3%

93.4%

92.4%

83.8%

89.0%

25°C

Full-load efficiency⁽³⁾

V_O= 20 V

,

4-point average efficiency⁽²⁾

V_O= 20 V

,

η_{avg_20}

η_{10%_20}

T_AMB

V_IN= 115 V_RMS

V_IN= 230 V_RMS, I_O= 10% of I_O(FL)

V_IN= 115 V_RMS, I_O= 10% of I_O(FL)

Efficiency at 10% load,

V_O= 20 V

Ambient operating temperature

range

V_IN= 90 to 264 V_RMS, V_O= 20 V, I_O= 0 to 3.25

A

(1) The performance listed in this table is achieved using secondary-resonance and based on the test results from a single board.

(2) Average efficiency of four load points, I_O= 100%, 75%, 50%, and 25% of I_O(FL)

.

(3) Power loss from external cable is not included in efficiency results.

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9.2.2 Detailed Design Procedure

9.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage

In an off-line rectified-AC application, the total input bulk capacitor (C_BULK) should be sized to provide energy

from the peak of the minimum input AC line voltage (V_IN(MIN)) to the minimum allowable voltage (V_BULK(MIN)

)

to the power conversion stage. Due to the transition-mode operation, too low of V_BULK(MIN)selection results

in higher RMS current at V_IN(MIN)and affects the full load efficiency, while too high of V_BULK(MIN)enlarges the

volume of the bulk capacitor. This equation does not account for the hold-up time requirement over AC-line dips

and drop-outs.

V_{BULK (MIN )}

P

1

O

ì[0.5+ ìarcsin(

)]

h

p

2 ìV_{IN (MIN )}

(2ìV_{IN (MIN )}-V_{BULK (MIN )}²) ì f_LINE

C_{BULK (MIN )}

=

2

(21)

C_BULKmay be made up of more than one capacitor. Select standard values with sufficient margin to the

calculated C_BULK(MIN)to allow for tolerance and aging.

9.2.2.2 Transformer Calculations

9.2.2.2.1 Primary-to-Secondary Turns Ratio (N_PS

)

N_PSis a ratio of primary winding turns to secondary winding turns and although each winding must have a whole

number of turns, the ratio of the two is not required to be a whole number. The choice of N_PSinfluences the

design tradeoffs on the voltage ratings between primary and secondary switches, and the balance between the

magnetic core and winding loss of the transformer, which are explained in detail as follows:

1. Maximum N_PS(N_PS(MAX)) is limited by the maximum derated drain-to-source voltage of Q_L(V_{DS_QL(MAX)}). In

the expression below, ∆V_CLAMPis a voltage deviation above the reflected output voltage. It can be either

the ripple voltage of C_CLAMPin AAM mode, or the voltage over-charge of C_CLAMPby the leakage inductance

energy when Q_His disabled in LPM. V_Ois the output voltage, and V_Fis the forward voltage drop of the

secondary rectifier.

V_{DS _QL(MAX )}-V_{BULK (MAX )}- DV_CLAMP

N_{PS(MAX )}

=

V_O+V_F

(22)

2. Minimum N_PS(N_PS(MIN)) is limited by the maximum derated drain-to-source voltage of the secondary rectifier

(V_{DS_SR(MAX)}). In the expression for N_PS(MIN), ∆V_SPIKEshould account for any additional voltage spike higher

than V_BULK(MAX)/N_PSthat occurs when Q_His active and turns-off at non-zero current in AAM mode.

V_{BULK(MAX )}

N_{PS(MIN )}

=

V_{DS _ SR(MAX )}-V_O- DV_SPIKE

(23)

3. Since the high-frequency transformer is usually a core-loss limited design instead of a saturation-limited

design, the minimum duty cycle (D_MIN) at V_BULK(MAX)is more important. Lower D_MINincreases core loss at

V_BULK(MAX), so this constraint creates another limitation on N_PS(MIN)

.

D_MINV_{BULK(MAX )}

N_{PS(MIN )}

=

(1- D_MIN)(V_O+V_F)

(24)

4. The winding loss distribution between the primary and secondary side of the transformer is the final

consideration. As N_PSincreases, primary RMS current reduces, while secondary RMS current increases.

Conversely, as N_PSdecreases, primary RMS current increases, while secondary RMS current reduces.

9.2.2.2.2 Primary Magnetizing Inductance (L_M)

After N_PSis chosen, L_Mcan be estimated based on minimum switching frequency (f_SW(MIN)) at V_BULK(MIN)

,

maximum duty cycle (D_MAX), and output power at highest nominal output voltage, nominal full-load current

(P_O(FL)). The choice of f_SW(MIN)should consider the expected range of switching frequency as bulk voltage

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increases from minimum to maximum and as load falls from maximum to the burst mode threshold. K_RES

represents the duty cycle loss to wait for the switch-node voltage transition from the reflected output voltage

to zero. Typically, f_SWmay extend to 200% to 300% f_SW(MIN)or higher. A K_RESvalue of 5% to 6% is used

as an initial estimate for GaN-based power stages, while ~10% is more appropriate for Si-based designs. The

selection of minimum switching frequency (f_SW(MIN)) should consider the impact on full-load efficiency and EMI

filter design.

N_PS(V_O+V_F)

V_{BULK(MIN )}+ N_PS(V_O+V_F)

D_MAX

=

(25)

(26)

2

D_MAXV_{BULK (MIN )}

2

h

(1- K_RES

f_{SW (MIN )}

)

L_M=

ì

2P

O(FL)

9.2.2.2.3 Primary Winding Turns (N_P)

The turn number on the primary side of the transformer (N_P) is determined by two design considerations:

1. The maximum flux density (B_MAX) must be kept below the saturation limit (B_SAT) of the magnetic core

under the highest peak magnetizing current (I_M+(MAX)) condition, a given cross-section area (A_E) of the core

geometry, and highest core temperature. When I_FB= 0 A, such as V_Osoft-start or step-up load transient,

the peak magnetizing current reaches I_M+(MAX), since V_CST= V_CST(MAX)in those conditions. I_M+(MAX)can be

calculated based on the output power triggering an OPP fault (P_O(OPP)) with V_CST= V_CST(OPP1)at V_BULK(MIN)

.

2P

V_{CST (MAX )}

V_{CST (OPP1)}

O(OPP)

I_{M +(MAX )}

=

D_MAXV_{BULK (MIN )}

h

(27)

L_MI_{M +(MAX )}

B_MAX

=

< B_SAT

N_PA_E

(28)

2. The AC flux density (ΔB) affects the core loss of a transformer. For a transition-mode active clamp flyback,

the core loss is usually highest at high line, since the switching frequency is highest and duty cycle is

smallest for a given load condition. The following equation is the ΔB calculation including the contribution

of negative magnetizing current (I_M-), used to put into the Steinmetz equation for more accurate core loss

estimation. For V_BULK≥ N_PS(V_O+V_F), I_M-is calculated with V_BULKdivided by the characteristic impedance of

L_Mand the lumped time-related switch-node capacitance (C_SW). The expression of f_SWis derived based on

the triangular approximation of the magnetizing current, which also considers I_M-effect over wide AC line

condition.

C_SW

I_{M -}= -

V_BULK

L_M

(29)

(30)

(31)

P

1

O(FL)

I_IN

=

h

V_BULK

N_PS(V_O+V_F)

D =

V_BULK+ N_PS(V_O+V_F)

D²V_BULK

2L_MI_IN- DL_MI_{M -}+ DV_BULKì0.5

f_SW

=

p

L_MC_SW

(32)

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2P

O(FL)

2

I_{M +}

=

+ I_{M -}

h

L_Mf_SW

(33)

(34)

L_M(I_{M +}- I_{M -}

N_PA_E

)

DB =

9.2.2.2.4 Secondary Winding Turns (N_S)

After N_Pis chosen, N_Scan be calculated through N_PS. N_Sand N_Pare adjusted to the nearest suitable integers.

With the new N_PS, Section 9.2.2.2.2 and follow-on parameters are recalculated to update the parameter change.

N_P

N_S=

N_PS

(35)

9.2.2.2.5 Auxiliary Winding Turns (N_A)

Turns of the auxiliary winding (N_A) is an integer value usually chosen to provide a nominal V_VDDthat satisfies

all devices powered from V_VDD, such as a gate driver, UCC28782, etc. N_Ais determined by the following design

considerations:

1. V_VDDmust be lower than the maximum rating voltage of VDD pin (V_VDD(MAX)) at maximum output voltage

and rectifier forward drop (V_O(MAX)+ V_F). V_VDD(MAX)is also limited by the lowest voltage rating of any other

devices connected to the VDD pin. Use the lower result of the two following options, where applicable.

a. For designs with a fixed output voltage or a narrow output range, the maximum Auxiliary winding turns

(N_A(MAX)) is given by the following equation.

V_{VDD(MAX )}

N_{A(MAX )}

=

N_S

V_{O(MAX )}+V_F

(36)

b. For designs with wide-output voltage range (such as with USB-PD or PPS or similar) where the boost

circuit is likely to be used, leakage inductance may peak-charge the BIN capacitance. The internal boost

switch has a maximum rating of 30 V, so a 24-V Zener diode is often used as a clamping device to avoid

overstress on BSW. This clamping voltage sets a lower limit on N_A(MAX)and is given by the following

equation.

248

0

#(/#:)

<

0

5

8_{1 /#:}_;+ 8

:

(

(37)

2. The nominal V_VDDshould consider the impact on the stand-by power. Higher V_VDDresults in a static-loss

increase with the total bias current of the devices connected to the VDD pin.

3. V_VDDshould be higher than the 13-V threshold voltage of survival mode (which is the sum of V_VDD(OFF)

and V_VDD(PCT)) at the minimum sustained output voltage (V_O(MIN)). ΔV here represents the voltage difference

between the nominal V_VDDand the survival-mode threshold. A minimum of 3 V is a recommended design

margin for ΔV.

V_{VDD(OFF )}+V_{VDD(PCT )}+ DV

N_S

N_{A(MIN )}

=

V_{O(MIN )}+V_F

(38)

N_A(MIN)must also accommodate the highest V_VDD(OFF)threshold of other devices powered by VDD, if any. Select

an integer value for N_Abetween the lowest N_A(MAX)and the highest N_A(MIN)with consideration of #2. For best

performance, design the DC resistance of the auxiliary winding to be < 0.1 Ω.

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9.2.2.2.6 Winding and Magnetic Core Materials

Besides the choice of AC flux density (ΔB) with L_Mand N_P, the core loss of the transformer can also be

significantly reduced by a proper selection of the magnetic core material. For converters operating at full-load

switching frequencies up to 250 kHz, ferrite materials such as 3C97 and 3C98 (by Ferroxcube) exhibit low core

loss density. For converters operating at full-load switching frequencies over 400 kHz, materials such as 3F36

from Ferroxcube and N49 from TDK/Epcos exhibit low core loss density. Other ferrite materials with equivalent

or similar loss characteristics may also be used. Litz wires are recommended for both primary and secondary

windings, in order to reduce the R_ACwinding loss caused by the proximity effect and the skin effect of the

transformer windings.

9.2.2.3 Clamp Capacitor Calculation

There are two resonant approaches for an active clamp flyback (ACF) converter, primary resonance and

secondary resonance, which affect the design guidance on the clamp capacitor (C_CLAMP). Referring to Figure

9-1, if C_O1serves as the main energy-storage capacitor at the output with large capacitance and C_O2is a smaller

high-frequency decoupling capacitor, leakage inductance of transformer (L_K) mainly resonates with C_CLAMP

during the demagnetization time of L_M. This configuration is called the primary-resonance ACF converter. On the

other hand, if C_O2serves as the main energy-storage capacitor at the output with larger capacitance and C_O1

is much smaller than the equivalent capacitance of C_CLAMPreflected to the secondary side (C_CLAMP*N_PS²), L_K

mainly resonates with C_O1. This configuration is called the secondary-resonance ACF converter.

9.2.2.3.1 Primary-Resonance ACF

For primary-resonance ACF, the design tradeoff between conduction loss and turn-off switching loss of Q_H

needs to be considered. Higher C_CLAMPresults in less RMS current flowing through the transformer windings

and switching devices, so the conduction loss can be reduced. However, a higher C_CLAMPdesign results in

Q_Hturning-off before the clamp current returns to zero. The condition of not having zero current switching

(ZCS) increases the turn-off switching loss of Q_H. This is aggravated if the turn-off speed of Q_His not fast

enough. Therefore, C_CLAMPneeds to be fine-tuned based on the loss attribution. If the resonance between L_K

and C_CLAMPis designed to be completed by the time Q_His turned-off, the clamp current should reach close

to zero at approximately three quarters of the resonant period. The following equation can be used to design

C_CLAMPfor obtaining ZCS at V_BULK(MIN)and full load. This design results in a non-ZCS condition at V_BULK(MAX)

,

since the switching frequency at V_BULK(MAX)is higher in transition-mode operation. A low-ESR clamp capacitor

is recommended to minimize the conduction loss. If a ceramic capacitor is used as the low-ESR capacitor, the

DC-bias effect on capacitance reduction also needs to be considered.

L_MI_{M +(FL)}

1

2

]

C_CLAMP

=

[

L_K1.5

p

N_PS(V_O+V_F)

(39)

9.2.2.3.2 Secondary-Resonance ACF

For secondary-resonance ACF, C_O1is used to adjust the resonant time with L_Kto fulfill the ZCS condition, so

a large C_CLAMPwill not compromise ZCS. Besides, during the on-time of low-side switch (Q_L), the small C_O1

is partially discharged by the load current at the same time. After Q_Lturns off and the resonance begins, the

discharged C_O1makes the initial resonance voltage lower than the reflected clamp capacitor voltage across

C_CLAMP, which forces more magnetizing current to be delivered to the output, so the conduction loss is reduced

with less RMS current flowing through Q_Hand the primary winding.

9.2.2.4 Bleed-Resistor Calculation

R_BLEEDis used to discharge the clamp capacitor voltage to a residual voltage (V_RESIDUAL) during the 1.5-s

fault delay recovery time (t_FDR). After the converter recovers from the fault mode, lower V_RESIDUALreduces

the maximum current stress (I_SHORT(MAX)) flowing through the switching devices within their respective safe

operating areas, even if the output voltage is shorted. V_RESIDUALcan be determined by the target I_SHORT(MAX)

multiplied with the characteristic impedance between the leakage inductance (L_K) and the clamp capacitor

(C_CLAMP). I_SHORT(MAX)is based on the de-rated maximum pulse current of Q_Hor the output-rectifier current

reflected to the primary side, whichever is lower. This design guide can be applied to both primary and

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secondary resonance ACF converters. An excessively low value of R_BLEEDresults in over-discharging of

C_CLAMP, and introduces excess continuous power loss which affects standby power.

L_K

V_RESIDUALö I_{SHORT (MAX )}

C_CLAMP

(40)

t_FDR

R_BLEED

=

N_PS(V_O+V_F) + DV_CLAMP

V_RESIDUAL

C_CLAMPln[

]

(41)

9.2.2.5 Output Filter Calculation

The bulk output capacitor of active clamp flyback (ACF) converters, C_O1of the primary-resonance ACF or C_O2

of the secondary-resonance ACF, is often determined by the load-step transient-response requirement from

no-load to full-load transition. For a target output voltage undershoot (ΔV_O) with the load step-up transient of ΔI_O,

the minimum bulk output capacitance (C_O(MIN)) can be expressed as

¿+₁P_4'52

%

=

1(/+0)

¿8 F ¿+₁4_%K

1

(42)

where t_RESPis the response time delay from the moment ΔI_Ois applied to the moment when I_FBfalls below 10

μA. At ~10 μA, full power is available to prevent further drop of V_Oand to recharge C_O. The response delay

time consists of the time for the secondary regulator to stop driving the opto-coupler input plus the time for the

opto-coupler output transistor to turn off. R_Cois the equivalent series resistance (ESR) of the output capacitor

C_O.

The output filter inductor (L_O) is an essential component for the secondary-resonance ACF, not only to filter the

large switching voltage ripple across C_O1but also to decouple the effect of C_O2on the resonant period. The

sum of L_Oimpedance, ESR of C_O2(R_Co2), and C_O2impedance at minimum switching frequency (f_SW(MIN)) must

be much higher than C_O1impedance at the same frequency to force most of switching resonant current to flow

through C_O1only. L_Ois chosen with minimal ESR to achieve minimal conduction loss.

1

R_Co2

L_O>>

-

(2p

f_{SW (MIN )})²C_O1(2

p

f_{SW (MIN )})²C_O2

2p

f_{SW (MIN )}

(43)

One benefit of lowering the ESR on C_O1(R_Co1) is to help to reduce the switching ripple on the output voltage.

Another benefit is reducing the conduction loss of C_O1for the secondary-resonance ACF converter. However,

the issue is that the damping between L_Oand C_O1is weakened. Without proper damping, the magnitude of

low-frequency resonant ripple between L_Oand C_O1enlarges output ripple, affects the loop stability, and affects

the operation of synchronous rectifier (Q_SEC). The secondary-resonance ACF converter is the most vulnerable

since C_O1with low capacitance significantly weakens the damping. To resolve this issue, it is found that a

serial damping network formed by L_DAMPand R_DAMPis a very effective way to minimize the impact. However,

too much damping results in noticeable conduction loss increase and full-load efficiency drop. Therefore, it

is recommended that L_DAMPand R_DAMPshould be higher than the theoretical strong damping value as the

following equations suggest. Even though the damping network is an additional component, the physical size or

the footprint is much smaller than L_O, not only because of the small value but also the wide availability of small-

size chip inductors with high winding resistance can provide "free" R_DAMP. For the 65-W secondary-resonance

ACF design with primary GaN FETs and a polymer-type C_O2, when a 0.68-µH chip inductor is in parallel with a

1-µH output filter inductor, there is only 0.15% full-load efficiency drop at 90-V AC input, and there is a negligible

efficiency difference at 230-V AC input.

L_DAMP> 0.13ì L_O

(44)

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L_O

R_DAMP

>

C_O1

(45)

The equation for R_DAMPassumes that C_O2>> C_O1. Select a standard component available with parameter

values that satisfy both of these two equations. It is usually not necessary to use two separate components.

9.2.2.6 Calculation of ZVS Sensing Network

There are three components in the application circuit to help the depletion MOSFET (Q_S) perform ZVS

sensing safely: C_SWS, R_SWS, and D_SWS. Design considerations and selection guidelines for the values of these

components are given here.

At the rising edge of the switch node voltage, the fast dV/dt coupling through the drain-to-source capacitance

of Q_S(C_OSS(Qs)) generates a charge current flowing into the circuit loading on the Q_Ssource pin. The result

is a possible voltage overshoot on both the SWS pin and across the gate-to-source of Q_S(V_GS(Qs)) since the

gate is tied to P13. The SWS pin, with an absolute maximum voltage rating of 38 V, can handle higher voltage

stress than V_GS(Qs). Therefore, a capacitor (C_SWS) between the SWS pin and GND should be selected properly

to prevent the voltage overshoot from damaging the Q_Sgate. Since C_OSS(Qs)and C_SWSform a voltage divider,

the minimum C_SWS(C_SWS(MIN)) can be derived as

:

c

_155(3O)× 8_{$7.- (/#:)}+ 0₂₅8 + 8

1 (

;

g

%

=

595(/+0)

8

+ 8

)5_/#:(3O)

213

(46)

where V_{GS_MAX(Qs)}is the de-rated maximum gate-to-source voltage of Q_Sand V_P13is the steady-state voltage

level of 13 V.

Without resistive damping, both the charge current on the rising edge of V_SWand the discharge current on the

falling edge of V_SWare oscillatory with the parasitic series inductance within the ZVS sensing network resonating

with C_SWS. Therefore, a series resistor (R_SWS) between SWS pin and source-pin of Q_Sis used to dampen

any high-frequency ringing, helping to obtain a cleaner sensing signal on the SWS pin and preventing any

high-frequency current from interfering with other noise-sensitive signals. R_SWScan be expressed as:

L_SWS

R_SWS

>

C_SWS+ C_Dz

(47)

where L_SWSis the lumped parasitic inductance including the packaging of Q_Sand PCB traces of Q_Sand C_SWS

return path.

A bidirectional TVS across BSS126 gate and source should be added to protect the gate-to-source voltage from

potential abnormal voltage stress. The clamping voltage of TVS should be less than BSS126 voltage rating

but greater than 15 V. The resistor should be slightly higher than 500 Ω. The resistor and a 22-pF ceramic

capacitor between the SWS pin and the bulk input capacitor ground form a small sensing delay to help the

internal detection circuit to identify the ZVS characteristic correctly.

Based on the above design guide, even though R_SWSand C_SWSmay be sufficient to manage the voltage

overshoot in normal operation, a low-capacitance bi-directional TVS diode (D_SWS) across BSS126 gate and

source is highly recommended to serve as a safety backup of the ZVS sensing network. Regular Zener diodes

are not suitable due to high capacitance and slow clamping response. The clamping voltage of TVS should be

less than BSS126 voltage rating but greater than 15 V.

A general recommendation is to use a 50-V 22-pF C0G-type ceramic capacitor for C_SWS, a 510-Ω chip resistor

for R_SWS, and a bi-directional TVS diode with clamp voltage of 18 V for D_SWS. Too large of R_SWSor C_SWS

introduces a sensing delay between the actual V_SWand the SWS pin, causing the ZVS control to unnecessarily

extend t_DMin order to pull down V_SWearlier than expected before the end of t_Z. As shown in Figure 8-5, the

larger R_SWSis, the smaller supply current to charge the VDD capacitor. If the reduced charge current (I_SWS) is

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lower than the total consumed current from the controller (I_START) and from the external circuitry on the VDD pin

and P13 pin, V_VDDmay not be able to reach V_VDD(ON)and the controller can not initiate any switching event.

9.2.2.7 Calculation of BUR Pin Resistances

Referring back to Section 8.3.1, it is recommended that ABM is entered at no higher than 50% to 60% of

full load. Equation 1 and Equation 2, or Equation 1 and Equation 4, provide two equations for calculating

two unknowns for the BUR-pin resistor values. However, first the target values of V_CST(BUR), ΔV_BUR(AAM), and

ΔV_BUR(LPM)must be chosen. Since the ratio of I_BUR(AAM)to I_BUR(LPM)is fixed at 1.852 (5 µA / 2.7 µA), it is

necessary to target ΔV_BUR(AAM)= 185 mV to ensure that ΔV_BUR(LPM)= 100 mV, per guidance in Section 8.3.1.

The procedure to determine the value of V_CST(BUR)is quite complex and is not provided in this datasheet.

Instead, the UCC28782 Excel Calculator Tool automatically calculates this value based on user input and

determines the V_BURtarget voltage V_{BUR_tgt}. Using this target value, it further determines the appropriate

values for R_BUR2and R_BUR1to meet the BUR pin targets based on user selections for the following set of

equations. Note that expected values are used to determine recommended resistances, then actual resistances

are selected from standard value series and the resulting actual voltages are calculated from the selected

resistor values. Actual voltage results should be close to the targeted values.

Calculate expected ΔV_BUR(LPM)value based on ΔV_BUR(AAM)target value.

+

$74(.2/)

¿8_$74(.2/)= ¿8_$74(##/)

×

= ¿8_$74(##/)× 0.54

+

$74(##/)

(48)

(49)

Calculate the expected value for the parallel combination of R_BUR1with R_BUR2

.

4_$741||4_$742= ¿8_$74(##/)/+_$74(##/)

Calculate the recommended value for R_BUR1and choose a standard 1% tolerance value for R_{BUR1_act}that is

close to the recommended value.

¿8_$74(##/)

8

4'(

4_{$741_NA?}

=

× F

8_{$74_PCP}+ ¿8_$74(##/)

G

+

$74(##/)

(50)

Calculate the recommended value for R_BUR2using R_{BUR1_act}and choose a standard 1% tolerance value for

R_{BUR2_act}that is close to the recommended value.

k 8_{$74_PCP}+ ¿8_$74(##/)

o

4_{$742_NA?}= 4_$741× H

I

8

F k 8_{$74_PCP}+ ¿8_$74(##/)

o

4'(

(51)

Calculate the actual values for V_BUR, ΔV_BUR(AAM), and ΔV_BUR(LPM)using R_{BUR1_act}and R_{BUR2_act}

.

4_$742

4_$741× 4_$742

4_$741+ 4_$742

8_{$74_=?P}= 8 × l

4'(

p F +_$74(##/)× l

p

4_$741+ 4_$742

(52)

(53)

(54)

4_$741× 4_$742

¿8_$74(##/)= +_$74(##/)× l

p

4_$741+ 4_$742

4_$741× 4_$742

¿8_$74(.2/)= +_$74(.2/)× l

p

4_$741+ 4_$742

Finally, verify that the total summation of the BUR voltage with hysteresis does not exceed the BUR-pin upper

clamp voltage of 2.4 V.

8_{$74_=?P}+ ¿8_$74(##/)+ ¿8_$74(.2/)Q 2.48

(55)

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9.2.2.8 Calculation of Compensation Network

UCC28782 integrates two control concepts to benefit high-efficiency operation: peak current-mode control and

burst-ripple control. The peak current loop in AAM can be analyzed based on the linear control theory, so the

compensation target is to obtain enough phase margin and gain margin for the given small-signal characteristic

of an active clamp flyback converter. For Transition-Mode operation, the power stage can be modeled as a

voltage-controlled current source charging an output capacitor (C_O) with an equivalent-series resistance (R_Co)

and the output load (R_O) as shown in Figure 9-2. The first-order plant characteristic and high switching frequency

operation in AAM make the peak current loop easier to stabilize than ABM.

^

Equivalent Circuit of ACF

V_O

^

K_FV_BULK

K_EI_FB

R_Co

C_O

R_O

R_E

H_V(s)

Compensation

V_O(REF)

^

I_FB

Figure 9-2. Small-Signal Model of ACF in AAM Loop

The adaptive burst mode (ABM) uses ripple-based control, so the linear control theory for AAM cannot be

applied. As illustrated in Figure 8-4, the internal ramp compensation feature of UCC28782 stabilizes the ABM

control loop, so the external compensation network can be simplified.

Figure 9-3. Compensation Network, H_v(s)

The transfer function from I_FBto V_Oguides the pole/zero placement of the general secondary-side compensation

network in Figure 9-3. In the primary-side control circuitry, two poles at ω_FBand ω_OPTOintroduce phase-delay

on I_FB. ω_FBpole is formed by the external filter capacitor C_FBand the parallel resistance of the internal R_FBIand

the external current-limiting resistor (R_FB). ω_OPTOpole is formed by the parasitic capacitance of the optocoupler

output (C_OPTO) and the series resistance of R_FBIand R_FB. For C_FB= 220 pF, R_FBI= 8 KΩ, and R_FB= 20 KΩ, the

delay effect of ω_FBpole located at 139 kHz is negligible. C_OPTOis in the range of a few nF contributed by the

Miller effect of the collector-to-base capacitance of the BJT in the optocoupler output, so ω_OPTOpole is located

at less than 10 kHz. If the control loop bandwidth needs to be designed at higher frequency for a faster transient

response, the phase delay effect of ω_OPTOon the stability margin must be taken into account. Therefore, an

RC network (R_DIFFand C_DIFF) in parallel with R_BIAS1is used to compensate the phase-delay of the optocoupler,

which introduces an extra pole/zero pair located at ω_P1and ω_Z1respectively. The basic design guide is to place

the ω_Z1zero close to the ω_OPTOpole, and to place ω_P1pole away from highest f_BUR. On the other hand, if the

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stability margin and transient response are sufficient to meet the requirements without R_DIFFand C_DIFF, then

these two components are optional for UCC28782.

I_FB(s) CTR 1+ (s /

w

)

1

1+ (s /

_P1) 1+ (s /

w

)

1

Z 0

Z1

=

V_O(s) R_BIAS1(s /

w

_{Z 0}) 1+ (s /

w

) 1+ (s /

w

)

FB

OPTO

(56)

(57)

(58)

(59)

(60)

(61)

1

w

=

Z 0

Z1

P1

(R_Vo1+ R_INT)C_INT

1

w

(R_DIFF+ R_BIAS1)C_DIFF

1

R_DIFFC_DIFF

1

=

OPTO

(R_FB+ R_FBI)C_OPTO

1

w

=

FB

(R_FBI/ /R_FB)C_FB

The step-by-step design procedure of the compensator without R_DIFFand C_DIFFis:

1. R_FBselection needs to consider both the output voltage regulation and compensation challenge on the

low-frequency pole at ω_OPTO. R_FBshould be less than the maximum value of 28 kΩ to provide a sufficient

feedback current of 95 μA for the output voltage regulation in SBP2 mode, under the worst-case V_FB(REG)

and R_FBI. However, R_FB= 28 kΩ and C_OPTO= 2 nF result in an ω_OPTOpole located at 2.8 kHz. This

low-frequency pole may reduce phase margin at the cross-over frequency. If the control bandwidth is around

this frequency range, R_FBvalue should be designed even lower to move the pole to a higher frequency.

V_FB(REG)-V_CE(OPTO)

I_FB(SBP)

R_{FB(MAX )}

=

- R_FBI

(62)

2. R_BIAS1is determined based on a given current transfer ratio (CTR) of the optocoupler, ΔV_O(ABM), and target

4~5 μA of ΔI_FBas example. At collector currents less than 100 μA, the CTR of most optocouplers can be as

low as 10%, or 0.1 (used in this example), although some high performance devices can have higher CTR.

%64

0.1

4_$+#51

=

¿8

=

¿8

1(#$/)

¿+_($

5ä#

(63)

3. R_INTselection is not designed for the small-signal compensation, but to resolve the slow large-signal

response of the shunt regulator. Specifically, after a step-down load change from heavy load to no load

occurs, the output voltage overshoot and the long settling time forces ATL431 to reduce the cathode voltage

continuously by the integrator configuration until the output voltage gets back to normal regulation level. If

the load step-up transient happens before the output voltage is settled from the previous load step-down

event, the low voltage across ATL431 becomes the initial voltage level for the integrator to move to a new

steady-state. Since the time for ATL431 to move from lower voltage to a high voltage delays i_FBreduction,

the controller response from SBP mode to AAM mode is delayed as well, which slows down the energy

delivery to the output and results in a large voltage undershoot.

To resolve this problem, R_INTbehaves like a current-limiting resistor for C_INT, which slows down the

reduction of the cathode voltage of ATL431. R_INTneeds to be adjusted based on the voltage undershoot

requirement under the highest repetitive rate of load change.

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9.2.3 Application Curves

Figure 9-5. 10%-Load Efficiency vs. Input Voltage

Figure 9-4. 4pt-Average Efficiency vs. Input Voltage

Figure 9-7. Average Switching Frequency vs. Input

Voltage for 20-V Output, Full-load

Figure 9-6. Full-Load Efficiency vs. Input Voltage

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10 Power Supply Recommendations

The UCC28782 is intended to control active-clamp flyback (ACF) converters in high-efficiency off-line

applications, and is optimized to be used with universal AC input, from 85 V_ACto 265 V_AC, at 47 Hz to 63

Hz. An external depletion-mode MOSFET connected between the switch node of the converter and the SWS /

P13 pins of this controller is required to charge the VDD capacitor during start-up, and to perform ZVS sensing

during normal operation.

Once the V_VDDreaches the UVLO turn-on threshold at 17 V (typical), the VDD rail should be kept within the bias

supply operating voltage range listed in the Recommended Operating Conditions table in Section 7.3 . To avoid

the possibility that the device might stop switching, V_VDDshould not be allowed to fall below the maximum UVLO

turn-off threshold at 11.17 V.

Under the condition of LPM operation, the clamp capacitor C_CLAMPis charged higher than the reflected voltage

by the primary leakage inductance energy. On transition from LPM to ABM, this over-charge of C_CLAMPis

delivered to the output during the first event where PWMH is high. The peak current is determined by the

impedance formed by the resonance of the leakage inductance with the clamp capacitance, and it may be

quite high. On the secondary side, the primary current is multiplied by the transformer turns-ratio. Verify that the

pulse-current ratings of the high-side MOSFET and the output rectifier are adequate for these peak currents.

During power-stage switching, high dv/dt may appear to induce positive or negative noise on various pins of the

UCC28782 that apparently exceeds their respective Absolute Maximum ratings. This kind of noise is often less

than 10~20 ns in duration. If such measurements are made, ensure that "tip & barrel" probing techniques are

used to eliminate ground-bounce and noise pickup on oscilloscope probe grounding wires. Make sure that the

probe's GND reference is an AGND node as close to the IC as possible. If excess voltage is still measured,

verify that the maximum source or sink current of the pin is not exceeded.

Under certain special circumstances, such as a brief short-circuit or an extended overshoot on the converter

output, switching slows or stops until the condition clears and the clamp capacitor C_CLAMPmay be

overdischarged by a low R_BLEEDvalue. A low V_CLAMPreflects to the Auxiliary winding and may cause VS to

go low before PWMH goes low. If this happens the UCC28782 will stop switching and VDD will fall to the UVLO

threshold and cycle through a restart. If this situation occurs, it may be mitigated by one or more of the following

steps:

•

Use an edge-triggered (not level-triggered) isolator/driver with short power-up delay for the high-side switch

on the primary side.

•

Ensure the value of R_BLEEDis not too low.

Reduce the value of the RDM resistor judiciously.

In cases where there is no DCM ringing after PWMH goes low, try adding a positive offset voltage to VS to

raise the apparent ZCD threshold.

Mitigation of Voltage Stresses on the Output Rectifier

The rectifier on the output winding may be a P-N diode, a Schottky diode, or a synchronous-rectifier (SR)

MOSFET for higher efficiency. The current rating of this rectifier should be appropriate for the resonant flyback

current and its peak current rating should accomodate the C_CLAMPcharge balancing peak current. Besides the

output voltage plus reflected bulk voltage impressed across the rectifier during PWML on-time, consideration

for additional voltage spikes from various transient conditions should be made. Sources of voltage spikes on

the rectifier include: hard switching of the low-side MOSFET on the primary, non-ZCS turn-off of the high-side

MOSFET on the primary, and non-ZCS turn-off of an SR-MOSFET.

Regardless of cause of each of these spike sources, it is important to ensure that the peak voltage across the

rectifier does not exceed its maximum rating. This may be accomplished in several ways, by implementing one

or more of the alternative methods listed here:

•

Choose a rectifier with a higher voltage rating.

Add a TVS-type voltage-clamping device across the rectifier.

Add or improve an R-C snubber across the rectifier.

Slow down falling dv/dt of the low-side switch on the primary side.

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•

Minimize leakage inductance of the transformer secondary winding.

Use an edge-triggered (not level-triggered) isolator/driver with short power-up delay for the high-side switch

on the primary side.

•

Minimize the stray inductance in the V_DS-sense path of the SR controller.

In case of reverse current conduction, choose an SR controller with shorter minimum on-time.

Add or increase the value of a resistor in series with the gate of the SR-MOSFET, to slow down its di/dt

during non-ZCS turn-off.

•

Reduce the value of the RDM resistor judiciously, to reduce the maximum negative peak primary current by

reducing maximum PWMH on-time.

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11 Layout

11.1 Layout Guidelines

The active clamp flyback converter (ACF) designed with the UCC28782 not only recovers clamp energy but

also eliminates switching loss with minimum circulating energy, so higher switching frequencies, efficiencies,

and greater power densities can be achieved. However, when designing for higher switching frequencies, good

layout practices as discussed below should be followed to ensure a reliable and robust design.

11.1.1 General Considerations

Designing for high power density requires consideration of noise coupling and thermal management. A four-layer

PCB structure is highly recommended to use inner layers to help reduce current-loop areas and provide heat-

spreading for surface-mount semiconductors.

•

Provide internal-layer copper areas to improve heat dissipation of high-power SMDs, particularly for switching

MOSFETs and power diodes. Use multiple thermal-vias to conduct heat from outer pads to inner-layers and

supporting copper areas.

•

To avoid capacitive noise coupling, do not cross outer-layer signals over copper areas that carry high-

frequency switching voltage.

To avoid inductive noise coupling, keep switching current loops as small as possible, and do not run signal

tracks in parallel with such loops.

Arrange the conducted-EMI filter components such that they do not allow switching noise to bypass them and

affect the input. Avoid running switching signals through the EMI filter area.

Use multiple vias to connect high-current tracks and planes between layers.

Figure 11-1 summarizes the critical layout guidelines, and more detail is further elaborated in the descriptions

below.

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Keep control loop away

from dB/dt coupling of

transformer

Minimize the high di/dt switching loops to reduce EMI, voltage

stress on power devices, and noise coupling to control loop

L_DAMP

V_O

Transformer

D_BG

F_AC

V_BUS

V_BULK

V_AC

Q_PD

L_K

L_O

C_X

C_BULK

L_M

N_P

N_S

C_CLAMP

Primary Power Ground

C_O1

C_REG

C_O2

Q_SEC

D_BOOT

Shorten high dv/dt

traces for less EMI

and noise coupling;

run orthogonally

across other traces

V_P13

GND

V_S13

GaN

Power IC

Secondary

Power

Ground

D_RUN

C_BOOT

C_RUN

VD VG VS

V_O

SR Controller

REG

VDD

PWM

VCC1

VCC2

ISO7710F

OUT

IN

C_VDDH

Q_S

Keep signal and

power grounds

separate

GND1

GND2

D_SWS

PWMH

RUN

V_S13

C_DIFF

GaN

Power IC

V_P13

C_S13

Shorten V_SWStrace

with dv/dt; keep away

from feedback loop

PWM

V_SWS

Shorten VAUX trace

with dv/dt; keep away

from feedback loop

PWML

PGND

C_VDDL

V_RCS

C_SWS

To C_BULK

ground

V_BIN

D_AUX

L_B

D_B

R_CS

Minimize high di/dt

switching loops

Dedicate C_SWS

return to R_CS

ground node

C_BIN1

C_BIN2

C_VDD1

N_A

V_P13V_S13

Keep compensator

D_BIN

D_P13

C_VDD2

C_P13

C_INT

away from dv/dt, di/

dt, and dB/dt noise

sources

VS

BIN BGND BSW

VDD

P13

S13

SWS

XCD

Secondary Signal

Ground Plane

V_SWS

V_REF

RUN

UCC28782

PWMH

Follow grounding

arrangements shown in

this schematic diagram

PWML

PGND

PWML

PGND

BUR

SET

REF

FB RDM RTZ EP AGND FLT IPC

CS

R_OPP

To R_CS

ground

V_RCS

V_REF

C_FB

C_REF

C_CS

Primary Signal Ground Plane

R_FB

Keep signal

components close

to IC to minimize

noise coupling

Minimize FB loop area, keep away from noise sources, and

route emitter return back to AGND in parallel with FB path

Figure 11-1. Typical Schematic with Layout Considerations

11.1.2 RDM and RTZ Pins

Minimize stray capacitance to RDM and RTZ pins.

•

Place R_RDMand R_RTZas close as possible between the controller pins and AGND pin.

Avoid putting ground plane or any other tracks under RDM and RTZ pins to minimize parasitic capacitance.

This can be accomplished by putting cutouts in the layers below these pins.

11.1.3 SWS Pin

Minimize potential stray noise coupling from SWS pin to noise-sensitive signals.

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•

Keep some distance between SWS network and other connections.

The RC damping network (R_SWS, C_SWS) and the TVS diode (D_SWS) should be as close to the source pin of

Q_Sas possible instead of SWS pin, so the gate-to-source pin of Q_Scan be effectively protected.

Keep the return path for di/dt current through C_SWSand D_SWSseparate from the IC local GND and FB signal

return paths. Return C_SWSback to the ground node at R_CS, not at the IC.

•

11.1.4 VS Pin

Minimize stray capacitance at the VS pin to reduce the time-delay effect on ZVS control.

•

Avoid putting GND plane under VS pin to reduce parasitic capacitance. This can be accomplished by putting

a cutout in the ground plane below this pin pad and the tracks an pads of components connected to VS.

minimize the track length of the VS net.

•

Do not run other tracks or planes over or under the VS net.

Do not run other tracks or planes under R_VS1and R_VS2

.

11.1.5 BUR Pin

The resistor divider (R_BUR1and R_BUR2) and the filter capacitor (C_BUR) on the BUR pin should to be as close to

the BUR pin and IC AGND as possible.

•

It is recommended to provide shielding on the BUR-pin trace with ground planes to minimize the noise-

coupling effect on peak current variation during burst-mode operation. This can be accomplished by adding a

ground plane under the BUR traces and pins.

11.1.6 FB Pin

This pin can be noise-sensitive to capacitive coupling from the high dV/dt switch nodes, or the flux coupling from

magnetic components and high di/dt switching loops.

•

Minimize the loop area for the PCB traces from the opto-coupler to the FB pin in order to avoid the possible

flux coupling effect. Run the opto-coupler emitter return track from AGND at the IC in parallel with the FB to

collector path, to minimize loop-area.

•

Keep PCB traces away from the high dv/dt signals, such as the switch node of the converter (V_SW), the

auxiliary winding voltage (V_AUX), and the SWS-pin voltage (V_SWS). If possible, it is recommended to provide

shielding for the FB trace with ground planes.

•

The filter capacitor between FB pin and REF pin (C_FB) needs to be as close to the two IC pins as possible.

The current-limiting resistor of FB pin (R_FB) should be as close to the FB pin as possible to enhance the noise

rejection of nearby capacitively-coupled noise sources.

11.1.7 CS Pin

The OPP-programming resistor (R_OPP) and the filter capacitor (C_CS) should be as close to the CS pin as

possible to improve the noise rejection of nearby capacitively-coupled noise sources, and to filter any ringing that

may be present during non-ZVS conditions.

11.1.8 BIN Pin

This pin monitors the boost input voltage to determine if the level is correct to allow the boost circuit to switch.

When the boost circuit is used, the BIN signal usually originates from the rectified and filtered Auxiliary voltage.

•

Place the AUX voltage rectifier and main filter capacitor (C_BIN1) near the transformer pins to minimize the

AUX switching current loop. Return that capacitor's negative lead directly back to the transformer pin. Then

run the negative track to the BGND pin and the positive net to the boost inductor input.

Place another filtering capacitor (C_BIN2) at the input to the boost inductor and return that negative lead directly

to the BGND pin to minimize boost switching current loop area.

•

Connect the BIN pin to (C_BIN2) at the input of the boost inductor.

If the boost circuit is not used, connect BIN directly to BGND.

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11.1.9 BSW Pin

The BSW pin is the drain of the internal boost switch and carries high-frequency switching current internally to

BGND. To avoid self-generated noise and interference with control signals, minimize the boost switching current

loop area.

•

Place the boost inductor (L_B) close to the controller to minimize the track length from the inductor output to

the BSW pin. To avoid inducing switching noise into control signals, do not run such signal tracks over, under,

or through the boost switching loop.

•

Place the boost output diode (D_B) at the output of the boost inductor is such a way that minimized the loop

area with the boost output filter capacitor (C_VDD1) and return that capacitor's negative lead directly to the

BGND pin to minimize boost switching current loop area.

If the boost circuit is not used, connect BSW directly to BGND.

11.1.10 AGND Pin

The AGND pin is the bias-power and signal-ground connection for the controller. The effectiveness of the filter

capacitors on the signal pins depends upon the integrity of this ground return.

•

Place the decoupling capacitors for VDD, REF, CS, BUR, and P13 pins as close as possible to the device

pins and AGND pin with short traces.

The device ground and power ground should meet at the return of the current-sense resistor (R_CS). Try to

ensure that high frequency/high current from the power stage does not go through the signal ground.

The thermal pad of the QFN package should be tied to the AGND pin with a short trace, and be connected

to the signal ground plane with multiple vias which becomes a low-impedance ground return of external

components to the AGND pin.

11.1.11 BGND Pin

The BGND pin is the boost ground connection for the controller. The effectiveness of the filter capacitors on the

boost input and output depends upon the integrity of this ground return.

•

Place the filter capacitors on BIN and VDD as close as possible to the device pins and BGND pin with short

traces.

Minimize the loop areas of the boost circuit and BGND to avoid coupling boost switching noise to other

circuits.

BGND should be tied to AGND at a location such that switching currents in the BGND return do not pass into

the AGND network. Only low-ripple DC current should pass from BGND to AGND.

11.1.12 PGND Pin

The PGND pin is the gate-drive return for the PWML signal. It is NOT a ground return; do not confuse it as a

power ground pin. It is not connected to AGND or BGND within the IC.

•

The PGND signal is normally connected to the source pin of the low-side switching device, and run in parallel

with PWML to minimize loop area.

In certain cases, PGND may be connected to AGND at a location where PWML return currents do not create

ground noise to disturb control signals referenced to AGND.

For the individual low-side GaN power IC with logic PWM input, it is recommended to connect PGND to the

bottom of the current sense resistor (R_CS) directly.

11.1.13 EP Thermal Pad

The EP pad is internally connected to the device substrate by an indeterminate impedance. Connect this pad

externally to AGND at the AGND pin and at other pins that may be tied to AGND for the application. This pad

also functions as a thermal dissipater for the device. Use multiple vias to connect this pad to other copper planes

and areas to help dissipate heat and maintain the lowest GND impedance for signal integrity.

11.2 Layout Example

The layout techniques described in above sections were applied to the layout of the 65-W USB-PD high-density

GaN active clamp flyback converter.

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Figure 11-2. Schematic Page 1 of the 65-W EVM

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Figure 11-3. Schematic Page 2 of the 65-W EVM

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Make current loops as small and short as possible

Isolation Boundary

Keep GND-plane away from RDM, RTZ, and VS nets to minimize capacitance

Ground-plane shielding

Figure 11-4. Top Assembly and Top (First Layer) of PCB

Use multiple vias to

increase current

handling capability

and to help

dissipate heat

through pcb to

additional copper

planes

Figure 11-5. Inner Layer 1 (Second Layer) of PCB

88

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Keep BGND and

BIN loop as small

as possible.

Keep BGND

separate from

AGND until after

the boost output

filter capacitor

Keep GND-plane away from RDM, RTZ, and VS nets to minimize capacitance

Ground-plane shielding

Figure 11-6. Inner Layer 2 (Third Layer) of PCB

Make current loops as small and short as possible

Keep C41, R41 and D14 close to the SR-MOSFET

Keep supporting components as close as possible to the UCC28782

Figure 11-7. Bottom Assembly and Bottom (Fourth Layer) of PCB

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

UCC28782 Design Calculator Tool is an Excel-based calculation tool for UCC28782 design

Using the UCC28782EVM-030 65-W USB-C PD High-Density Active-Clamp Flyback Converter is a User

Guide for the EVM

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

90

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RTW0024B

4.15

3.85

A

B

4.15

3.85

PIN 1 INDEX AREA

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

(0.2) TYP

2X 2.5

EXPOSED

THERMAL PAD

12

7

20X 0.5

6

13

25

SYMM

2X

2.5

2.45±0.1

1

18

0.3

24X

0.18

19

0.5

24

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.05

C

24X

0.3

4219135/B 11/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RTW0024B

(

2.45)

SYMM

24

19

24X (0.6)

1

18

24X (0.24)

(0.97)

25

SYMM

(3.8)

20X (0.5)

(R0.05)

TYP

13

6

(Ø0.2) TYP

VIA

7

12

(0.97)

(3.8)

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219135/B 11/2016

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK-NO LEAD

RTW0024B

4X( 1.08)

(0.64) TYP

19

24

(R0.05) TYP

24X (0.6)

25

1

18

(0.64)

TYP

24X (0.24)

SYMM

(3.8)

20X (0.5)

13

6

7

12

METAL

TYP

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25:

78% PRINTED COVERAGE BY AREA UNDER PACKAGE

SCALE: 20X

4219135/B 11/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC28782_V01
厂家：	TEXAS INSTRUMENTS
描述：	UCC28782 High-Density Active-Clamp Flyback Controller with EMI Dithering, X-Cap Discharge, and Bias Power Management
文件：	总98页 (文件大小：5231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC28782_V01 [TI]

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