UCC2893PWG4 [TI]

CURRENT-MODE ACTIVE CLAMP PWM CONTROLLER; ??电流模式有源钳位PWM控制器


型号：	UCC2893PWG4
厂家：	TEXAS INSTRUMENTS
描述：	CURRENT-MODE ACTIVE CLAMP PWM CONTROLLER ??电流模式有源钳位PWM控制器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管信息通信管理
文件：	总41页 (文件大小：1030K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

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FEATURES

DESCRIPTION

Low Output Jitter

The UCC2891/2/3/4 family of PWM controllers is

designed to simplify implementation of the various

active clamp/reset switching power topologies.

Soft−Stop Shutdown of MAIN and AUX

Ideal for Active Clamp/Reset Forward,

Flyback Converters

The UCC289x is a peak current-mode, fixed-

frequency, high-performance pulse width modulator.

It includes the logic and the drive capability for the

auxiliary switch with a simple method of

programming the critical delays for proper active

clamp operation.

Provides Complementary Auxiliary Driver

with Programmable Deadtime (Turn-On

Delay) between AUX and MAIN Switches

Peak Current-Mode Control with

Cycle-by-Cycle Current Limiting

110-V Input Startup Regulator on UCC2891/3

TrueDrivet 2-A Sink, 2-A Source Outputs

Accurate Line UV and Line OV Threshold

Programmable Slope Compensation

1.0-MHz Synchronizable Oscillator

The UCC2891/3 includes a 110-V start-up

regulator for initial start-up and to provide

keep-alive power during stand-by.

Additional features include an internal

programmable slope compensation circuit,

precise D

limit, and a single resistor

MAX

Precise Programmable Maximum Duty Cycle

Programmable Soft Start

programmable synchronizable oscillator. An

accurate line monitoring function also programs

the converter’s ON and OFF transitions with

regard to the bulk input voltage. Along with the

UCC2897, this UCC289x family allows the power

supply designer to eliminate many of the external

components, reducing the size and complexity of

the design.

APPLICATIONS

150-W to 700-W SMPS

High-Efficiency, Low EMI/RFI Off-Line or

DC/DC Converters

Server, 48-V Telecom, Datacom

High Power Adapter, LCD-TV and PDP-TV

BIAS

WINDING

UCC2891

DEL

+VIN

VIN

RDEL

BULK

LOAD

RTON LINE UV

OFF

BIAS

RTOFF

VREF

VDD 14

OUT 13

CLAMP

OUT

DRIVE

VREF

AUX

SYNC

GND

AUX

PGND 11

SS/SD

AUX

SECONDARY

SIDE E/A

RSLOPE

SLOPE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

UNIT

Line input voltage, V

120

Supply voltage, V

< 10 mA)

16.5

−0.3 to (V

REF

+ 0.3)

not to exceed 6

Analog inputs

FB, CS, SYNC, LINEOV, LINEUV

OUT, AUX

Output source current (peak), I

2.5

O_SOURCE

O_SINK

Operating junction temperature range, T

Output sink current (peak), I

−2.5

−55 to 150

−65 to 150

2000

°C

Storage temperature, T

stg

Human body model, (HBM)

Change device model (CDM)

ESD rating

500

Lead temperature, T

sol,

1,6 mm (1/16 inch) from case for 10 seconds

300

°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is

not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to

GND. Currents are positive into and negative out of, the specified terminal.

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX UNIT

Line input voltage, V

110

Supply voltage, V

Supply bypass capacitance

8.5

12.0

16.0

µF

Timing resistance, R

operation)

= R

OFF

(for 250-kHz

kΩ

Operating junction temperature, T

Reference bypass capacitance, C

−40

0.1

105

°C

µF

REF

ORDERING INFORMATION

PART NUMBERS

AUX

OUTPUT

POLARITY

THRESHOLD

(INCLUDES

SLOPE COM-

PENSATION)

110-V START-UP

CIRCUIT

SOIC−16

(D)

TSSOP−16

APPLICATION

(PW)

DC−DC

DC-DC/Sec. Side

DC−DC

0.75 V

1.27 V

0.75 V

1.27 V

Yes

UCC2891D

UCC2892D

UCC2893D

UCC2894D

UCC2891PW

UCC2892PW

UCC2893PW

UCC2894PW

P-Channel

N-Channel

−40°C to 125°C

Yes

Off−Line

†

The D and PW packages are available taped and reeled. Add R suffix to device type (e.g. UCC2891DR) to order quantities of 2,500

devices per reel (for the D package) and 2,000 devices per reel (for the PW package). Bulk quantities are 40 units per tube (for the D

package) and 90 units per tube (for the PW package).

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

THERMAL RESISTANCE INFORMATION

PACKAGE

THERMAL RESISTANCE

UNITS

θjc

36.9 to 38.4

73.1 to 111.6

33.6 to 35.0

108.4 to 147.0

SOIC−16 (D)

°C/W

θja (0 LFM)

θjc

TSSOP−16 (PW)

°C/W

θja (0 LFM)

PIN ASSIGNMENTS

UCC2891 AND UCC2893

D and PW PACKAGEs

(TOP VIEW)

UCC2892 AND UCC2894

D AND PW PACKAGE

(TOP VIEW)

RTDEL

RTON

RTOFF

VREF

SYNC

GND

RTDEL

RTON

RTOFF

VREF

SYNC

GND

LINEOV

LINEUV

VDD

OUT

AUX

PGND

SS/SD

VIN

LINEUV

VDD

OUT

AUX

PGND

SS/SD

RSLOPE

ELECTRICAL CHARACTERISTICS

(1)

= 12 V , 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, R

= R

= 75 kΩ, R

= 10 kΩ,

OFF

DEL

= 50 kΩ, −40 °C ≤ T = T ≤ 125°C (unless otherwise noted)

SLOPE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OVERALL

Start-up current

< V

UVLO

300

500

µA

STARTUP

= 0 V,

(1)(2)

Operating supply current

Outputs not switching

HIGH-VOLTAGE BIAS SECTION (UCC2891, UCC2893)

Current available from VDD during Start-

(3)

VDD startup current

JFET leakage current

DD−ST

up, VIN = 36 V, T = −40°C to 85°C

VIN = 120 V; VDD = 14 V

µA

VIN

UNDERVOLTAGE LOCKOUT

(1)

Start threshold voltage

12.2

7.6

12.7

8.0

13.2

8.4

Minimum operating voltage after start

Hysteresis

4.4

4.7

5.0

LINE MONITOR

Line UV and Line OV voltage threshold

Line UV and Line OV hysteresis current

1.243 1.268

1.293

14.5

LINEUV

11.8

12.5

µA

LINEHYS

SOFT-START

Charge current

= 75 kΩ

−10.5

10.5

0.4

−18.5

18.5

0.6

TON

µA

Discharge current

TON

Discharge/shutdown threshold voltage

0.5

SS/SD

(1)

(2)

(3)

Set VDD above the start threshold before setting at 12 V.

Does not include current of the external oscillator network.

The power supply starts with I load on VDD, part will start up with no load up to 125°C. For more detailed information, see pin descriptions

DD−ST

for VIN and VDD.

(4)

and I

SS/SD

are directly proportional to I . See equation 7.

RON

SSC

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

ELECTRICAL CHARACTERISTICS

(1)

= 12 V , 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, R

= R

OFF

= 75 kΩ, R

= 10 kΩ,

DEL

= 50 kΩ, −40 °C ≤ T = T ≤ 125°C (unless otherwise noted)

SLOPE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Voltage Reference

T = 25°C

4.85

4.75

−20

5.00

−11

5.15

5.25

−8

Reference voltage

REF

0 A < I

REF

< 5 mA,

over temperature

T = 25°C

Short circuit current

REF = 0 V,

INTERNAL SLOPE COMPENSATION

R_CS

(3)

Slope

FB = High

-10%

+10%

R_SLOPE

250

OSCILLATOR

Oscillator frequency

T = 25°C

237

225

263

270

OSC

kHz

Total variation

−40 °C < T 125°C; 8.5 V < 14.5 V

P_P

Oscillator amplitude (peak-to-peak)

SYNCHRONIZATION

SYNC theshold voltage

SYNC-to-output delay

1.6

2.3

3.0

SYNCH

DEL

PWM

Maximum duty cycle

Minimum duty cycle

PWM offset

66%

0.43

70%

0.50

74%

CS = 0 V

0.61

CURRENT SENSE

Current sense level shift voltage

Maximum voltage error (clamped)

0.40

4.8

0.50

5.0

0.60

5.2

LVL

ERR(max)

UCC2891

UCC2893

Current sense threshold

0.71

1.23

0.75

1.27

0.79

1.31

UCC2892

UCC2894

(1)

(2)

Set VDD above the start threshold before setting at 12 V.

Does not include current of the external oscillator network.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

ELECTRICAL CHARACTERISTICS

(1)

= 12 V , 1-µF capacitor from VDD to GND, 0.01-µF capacitor from VREF to GND, R

= R

OFF

= 75 kΩ, R

= 10 kΩ,

DEL

= 50 kΩ, −40 °C ≤ T = T ≤ 125°C (unless otherwise noted)

SLOPE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT (OUT AND AUX)

Rise time

Fall time

= 2 nF

LOAD

= 2 nF

= 2 nF,

Delay time (AUX to OUT)

Delay time (OUT to AUX)

Output source current

Output sink current

= 10 kΩ

110

115

−2

DEL1

DEL2

OUT(src)

DEL

OUT(sink)

Low-level output voltage

High-level output voltage

= 150 mA

0.4

11.1

OUT(low)

OUT

= −150 mA

OUT(high)

OUT

50%

OUT

AUX

50%

(N−channel)

AUX

50%

(P−channel)

DEL2

DEL1

Figure 1. Output Timing Diagram

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

FUNCTIONAL BLOCK DIAGRAM

TYP: VREF = 5.0 V

VREF

0.05 * IRDEL

92/94

1/2 x V

REF

VREF

VIN (UCC2891/3)

LINEOV (UCC2892/4)

0.05 * IRDEL

IRDEL

1.27 V

RDEL

RTON

91/93

1/2 x V

REF

15 LINEUV

CLOCK

VDD

1.27 V

13 V/ 8 V

VDD

1/2 x V

REF

1−DMAX

OUT

PWM

OFF

14 VDD

RTON

VREF

VDD

RTOFF

VREF

SYNC

RDEL

VDD

OUT

REF

GEN

PWM Offset

0.5 V

TURN−ON

DELAY

13 OUT

SYNC

VREF

75k

VREF

VDD

91/92

IRDEL

P−Ch.

5 * ISLOPE

1−DMAX

AUX

GND

TURN−ON

DELAY

93/94

N−Ch.

11 PGND

10 SS/SD

OV OFF

VREF

UV OFF

= 0.43 x I

RTON

3 * R

2 * R

UCC2892/4 1.27 V

UCC2891/3 0.75 V

VDD

UVLO

AND

VREF

ISLOPE

ENABLE

RSLOPE

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

UCC2891 UCC2892

NAME

UCC2893 UCC2894

This output drives the auxiliary clamp MOSFET which is turned on when the main PWM

switching device is turned off. The AUX pin can directly drive the auxiliary switch with 2-A

source turn-on current and 2-A sink turn-off current.

AUX

This pin is used to sense the peak current utilized for current mode control and for current

limiting functions. The peak signal which can be applied to this pin before pulse-by-pulse

current limiting activates is approximately 0.75 V for the UCC2891 and UCC2893 and 1.27 V

for the UCC2892 and UCC2894.

This pin is used to bring the error signal from an external optocoupler or error amplifier into

the PWM control circuitry. Often, there is a resistor tied from FB to VREF, and an optocoup-

ler is used to pull the control pin closer to GND to reduce the pulse width of the OUT output

driving the main power switch of the converter.

This pin serves as the fundamental analog ground for the PWM control circuitry. This pin

should be connected to PGND directly at the device.

GND

−

LINEOV

For the UCC2892/4, provides the LINE overvoltage function.

This pin provides a means to accurately enable/disable the power converter stage by moni-

toring the bulk input voltage or another parameter. When the circuit initially starts (or restarts

from a disabled condition), a rising input on LINEUV enables the outputs when the threshold

of 1.27 V is crossed. After the circuit is enabled, then a falling LINEUV signal disables the

outputs when the same threshold is reached. The hysteresis between the two levels is pro-

grammed using an internal current source.

LINEUV

This output pin drives the main PWM switching element MOSFET in an active clamp control-

ler. It can directly drive an N-channel device with 2-A source turn-on current and 2-A sink

turn-off current. A 10−kΩ resistor is recommended to connect this pin to PGND.

OUT

−

The PGND should serve as the current return for the high-current output drivers OUT and

AUX. Ideally, the current path from the outputs to the switching devices, and back would be

as short as possible, and enclose a minimal loop area.

PGND

A resistor connected from this pin to GND programs an internal current source that sets the

slope compensation ramp for the current mode control circuitry.

RSLOPE

RTDEL

RTOFF

RTON

A resistor from this pin to GND programs the turn-on delay of the two gate drive outputs to

accommodate the resonant transitions of the active clamp power converter.

A resistor connected from this pin to GND programs an internal current source that dis-

charges the internal timing capacitor.

A resistor connected from this pin to GND programs an internal current source that charges

the internal timing capacitor.

A capacitor from SS/SD to ground is charged by an internal current source of I

to pro-

RTON

gram the soft-start interval for the controller. During a fault condition this capacitor is dis-

SS/SD

SYNC

VDD

charged by a current source equal to I

RTON

The SYNC pin serves as a unidirectional synchronization input for the internal oscillator. The

synchronization function is implemented such that the user programmable maximum duty

cycle (set by RTON and RTOFF) remains accurate during synchronized operation.

This is the power supply for the device. There should be a 1-µF capacitor directly from VDD

to PGND. The capacitor value should be minimum 10 times greater than that on VREF.

PGND and GND should be connected externally and directly from PGND to GND.

−

For the UCC2891 and UCC2893, this pin is connected to the input power rail directly. Inside

the device, a high-voltage start-up device is utilized to provide the start-up current for the

controller until a bootstrap type bias rail becomes available.

VIN

This is the 5-V reference voltage that can be utilized for an external load of up to 5 mA.

Since this reference provides the supply rail for internal logic, it should be bypassed to

AGND as close as possible to the device. The VREF bias profile may not be monotonic

before VDD reached 5 V.

VREF

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

DETAILED PIN DESCRIPTIONS

RDEL (pin 1)

This pin is internally connected to an approximately 2.5-V DC source. A resistor (R

) to GND (pin 6) sets the

DEL

turn-on delay for both gate drive signals of the UCC2981 family of controllers. The delay time is identical for both

switching transitions, between OUT (pin 13) is turning off and AUX (pin 14) is turning on as well as when AUX

(pin 14) is turning off and OUT (pin 13) is turning on. The delay time is defined as:

*12

+ t

+ 11.1 10

R ) 15 10

DEL

seconds

DEL1

DEL2

(1)

For proper selection of the delay time refer to the various references describing the design of active clamp power

converters.

RTON (pin 2)

This pin is internally connected to an approximately 2.5-V DC source. A resistor (R ) to GND (pin 6) sets the

charge current of the internal timing capacitor. The RTON pin, in conjunction with the RTOFF pin (pin 3) are used

to set the operating frequency and maximum operating duty cycle of the UCC2891 family.

RTOFF (pin3)

This pin is internally connected to an approximately 2.5-V DC source. A resistor (R

discharge current of the internal timing capacitor. The RTON and RTOFF pins are used to set the switching

) to GND (pin 6) sets the

OFF

period (T ) and maximum operating duty cycle (D

) according to the following equations:

MAX

*12

+ 36.1 10

R * t

seconds

DEL1

(2)

*12

+ 15 10

+ t ) t

OFF

) t

OFF

) 170 10

seconds

OFF

DEL1

(3)

(4)

MAX

(5)

VREF (pin 4)

The controller’s internal, 5-V bias rail is connected to this pin. The internal bias regulator requires a good quality

ceramic bypass capacitor (C ) to GND (pin 6) for noise filtering and to provide compensation to the regulator

VREF

circuitry. The recommended C

value is 0.22-µF. The minimum bypass capacitor value is 0.022-µF limited

by stability considerations of the bias regulator, while the maximum is approximately 22-µF. Also, capacitor

value on VDD should be minimum 10 times greater than that on VREF.

The VREF pin is internally current limited and can supply approximately 5-mA to external circuits. The 5-V bias

is only available when the undervoltage lock out (UVLO) circuit enables the operation of UCC289x controllers.

For the detailed functional description of the undervoltage lock out (UVLO) circuit refer to the Functional

Description section of this datasheet.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

DETAILED PIN DESCRIPTIONS (continued)

SYNC (pin 5)

This pin provides an input for an external clock signal which can be used to synchronize the internal oscillator

of the UCC289x family of controllers. The synchronizing frequency must be higher than the free running

frequency of the onboard oscillator

t T

. The acceptable minimum pulse width of the

SYNC

synchronization signal is approximately 50 ns (positive logic), and it should remain shorter than

1 * D

where D

SYNC

is set by R

and R

. If the pulse width of the synchronization signal stays

MAX

OFF

MAX

within these limits, the maximum operating duty ratio remains valid as defined by the ratio of R

and R

OFF

and D

is the same in free running and in synchronized modes of operation. If the pulse width of the

MAX

synchronization signal would exceed the 1 * D

limit, the maximum operating duty cycle is

SYNC

MAX

defined by the synchronization pulse width.

For more information on synchronization of the UCC2891 family refer to the Functional Description section of

this datasheet.

GND (pin 6)

This pin provides a reference potential for all small signal control and programming circuitry inside the UCC2891

family.

CS (pin 7)

This is a direct input to the PWM and current limit comparators of the UCC2891 family of controllers. The CS

pin should never be connected directly across the current sense resistor (R ) of the power converter. A small,

customary R−C filter between the current sense resistor and the CS pin is necessary to accommodate the

proper operation of the onboard slope compensation circuit and in order to protect the internal discharge

transistor connected to the CS pin (R , C ).

Slope compensation is achieved across R by a linearly increasing current flowing out of the CS pin. The slope

compensation current is only present during the on-time of the gate drive signal of the main power switch (OUT)

of the converter. The internal pull-down transistor of the CS pin is activated during the discharge time of the

timing capacitor. This time interval is 1 * D

long and represents the guaranteed off time of the

MAX

main power switch.

RSLOPE (pin 8)

A resistor (R

) connected between this pin and GND (pin 6) sets the amplitude of the slope compensation

SLOPE

current. During the on time of the main gate drive output (OUT) the voltage across R

of the internal timing capacitor waveform. As the timing capacitor is being charged, the voltage across R

is a representation

SLOPE

also increases, generating a linearly increasing current waveform. The current provided at the CS pin for slope

compensation is proportional to this current flowing through R

SLOPE

Due to the high speed, AC voltage waveform present at the RSLOPE pin, the parasitic capacitance and

inductance of the external circuit components connected to the RSLOPE pin should be carefully minimized.

For more information on how to program the internal slope compensation refer to the Setup Guide section of

this datasheet.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

DETAILED PIN DESCRIPTIONS (continued)

FB (pin 9)

This pin is an input for the control voltage of the pulse width modulator of the UCC2891 family. The control

voltage is generated by an external error amplifier by comparing the converters output voltage to a voltage

reference and employing the compensation for the voltage regulation loop. Usually, the error amplifier is located

on the secondary side of the isolated power converter and its output voltage is sent across the isolation

boundary by an opto coupler. Thus, the FB pin is usually driven by the opto coupler. An external pull-up resistor

to the VREF pin (pin 4) is also needed for proper operation as part of the feedback circuitry.

The control voltage is internally buffered and connected to the PWM comparator through a voltage divider to

make it compatible to the signal level of the current sense circuit. The useful voltage range of the FB pin is

between approximately 1.25 V and 4.5 V. Control voltages below the 1.25-V threshold result in zero duty cycle

(pulse skipping) while voltages above 4.5 V result in full duty cycle (D

) operation.

MAX

SS/SD (pin 10)

A capacitor (C ) connected between this pin and GND (pin 6) programs the soft start time of the power

converter. The soft-start capacitor is charged by a precise, internal DC current source which is programmed by

the R

resistor connected to pin 2. The soft-start current is defined as:

REF

+ 0.43 I

+ 0.43

RTON

(6)

This DC current charges C from 0 V to approximately 5 V. Internal to the UCC2891 family of controllers, the

soft start capacitor voltage is buffered and ORed with the control voltage present at the FB pin (pin 9). The lower

of the two voltages manipulates the controller’s PWM engine through the voltage divider described with regards

to the FB pin. Accordingly, the useful control range on the SS pin is similar to the control range of the FB pin

and it is between 1.25 V and 4.5 V approximately.

PGND (pin 11)

This pin serves as a dedicated connection to all high-current circuits inside the UCC2891 family of parts. The

high-current portion of the controller consists of the two high-current gate drivers, and the various bias

connections except VREF (pin 4). The PGND (pin 11) and GND (pin 6) pins are not connected internally, a

low-impedance, external connection between the two ground pins is also required. It is recommended to form

a separate ground plane for the low current setup components (R

, R , R

, C

, C , R

, C and

DEL ON OFF VREF

SLOPE SS

the emitter of the opto-coupler in the feedback circuit). This separate ground plane (GND) should have a single

connection to the rest of the ground of the power converter (PGND) and this connection should be between pin

6 and pin 11 of the controller.

AUX (pin 12)

This is a high-current gate drive output for the auxiliary switch to implement the active clamp operation for the

power stage. The auxiliary output (AUX) of the UCC2891 and UCC2892 drives a P-channel device as the clamp

switch therefore it requires an active low operation (the switch is ON when the output is low). The UCC2893

and UCC2894 controllers are optimized for N-channel auxiliary switch therefore it employs the traditional active

high drive signal.

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DETAILED PIN DESCRIPTIONS (continued)

OUT (pin 13)

This high-current output drives an external N-channel MOSFET. Each controller in the UCC2891 family uses

active high drive signals for the main switch of the converter.

Due to the high speed and high-drive current capability of these outputs (AUX, OUT) the parasitic inductance

of the external circuit components connected to these pins should be carefully minimized. A potential way of

avoiding unnecessary parasitic inductances in the gate drive circuit is to place the controller in close proximity

to the MOSFETs and by ensuring that the outputs (AUX, OUT) and the gates of the MOSFET devices are

connected by wide, overlapping traces.

VDD (pin 14)

The VDD rail is the primary bias for the internal, high-current gate drivers, the internal 5-V bias regulator and

for parts of the undervoltage lockout circuit. To reduce switching noise on the bias rail, a good quality ceramic

capacitor (C ) must be placed very closely between the VDD pin and PGND (pin 11) to provide adequate

filtering. The recommended C

value is 1-µF for most applications but its value might be affected by the

properties of the external MOSFET transistors used in the power stage.

In addition to the low-impedance, high-frequency filtering, the controller’s bias rail requires a larger value energy

storage capacitor (C

) connected parallel to C . The energy storage capacitor must provide the hold up time

BIAS

to operate the UCC2891 family (including gate drive power requirements) during start up. In steady state

operation the controller must be powered from a bootstrap winding off the power transformer or by an auxiliary

bias supply. In case of an independent auxiliary bias supply, the energy storage is provided by the output

capacitance of the bias supply. When using the internal JFET for startup, the external load on VDD must be

limited to less than 4 mA.

LINEUV (pin 15)

This input monitors the incoming power source to provide an accurate undervoltage lockout function with user

programmable hysteresis for the power supply controlled by the UCC2891 family. The unique property of the

UCC2891 family is to use only one pin to implement these functions without sacrificing on performance. The

input voltage of the power supply is scaled to the precise 1.27-V threshold of the undervoltage lockout

comparator by an external resistor divider (R , R

exceeded, an internal current source gets connected to the LINEUV pin. The current generator is programmed

in Figure 7). Once the line monitor’s input threshold is

IN1 IN2

by the R

resistor connected to pin 1 of the controller. The actual current level is given as:

DEL

REF

0.05

HYST

DEL

(7)

As this current flows through R

of the input divider, the undervoltage lockout hysteresis is a function of I

HYST

IN2

and R

allowing accurate programming of the hysteresis of the line monitoring circuit.

IN2

For more information on how to program the line monitoring function refer to the Setup Guide of this datasheet.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

DETAILED PIN DESCRIPTIONS (continued)

VIN (pin 16 − UCC2891 and UCC2893 only)

The UCC2891 and UCC2893 controllers are equipped with a high voltage, P-channel JFET start up device to

initiate operation from the input power source of the converter in applications where the input voltage does not

exceed the 110-V maximum rating of the start up transistor. In these applications, the VIN pin can be connected

directly to the positive terminal of the input power source. The internal JFET start up transistor provides

approximately 15-mA charge current for the energy storage capacitor (C

) connected across the VDD (pin

BIAS

14) and PGND (pin 11) terminals. Note that the start up device is turned off immediately when the voltage on

the VDD pin exceeds approximately 13.5 V, the controller’s undervoltage lockout threshold for turn-on. The

JFET is also disabled at all times when the high-current gate drivers are switching to protect against excessive

power dissipation and current through the device. When using the internal JFET for startup, the external load

on VDD must be limited to less than 4 mA.

For more information on biasing the UCC2891 family, refer to the Setup Guide and Additional Application

Information Sections of this datasheet.

LINEOV (pin 16 − UCC2892 and UCC2894 only)

In the UCC2892 and UCC2894 controllers the high-voltage start-up device is not utilized thus pin 16 is used

for a different function. This input monitors the incoming power source to provide an accurate overvoltage

protection with user programmable hysteresis for the power supply controlled by the controller. The circuit

implementation of the overvoltage protection function is identical to the technique used for monitoring the input

power rail for undervoltage lockout. This allows implementing an accurate threshold and hysteresis using only

one pin. The input voltage of the power supply is scaled to the precise 1.27-V threshold of the overvoltage

protection comparator by an external resistor divider (R , R

threshold is exceeded, an internal current source gets connected to the LINEOV pin. The current generator is

in Figure 7). Once the line monitor’s input

IN3 IN4

programmed by the R

resistor connected to pin 1 of the controller. The actual current level is given as:

DEL

REF

0.05

HYST

DEL

(8)

As this current flows through R

of the input divider, the overvoltage protection hysteresis is a function of I

HYST

IN4

and R

allowing accurate programming of the hysteresis of the line monitoring circuit.

IN4

For more information on how to program the overvoltage protection, refer to the Setup Guide of this datasheet.

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FUNCTIONAL DESCRIPTION

JFET Control and UVLO

The UCC2891 and UCC2893 controllers include a high voltage JFET start up transistor. The steady state power

consumption of the of the control circuit which also includes the gate drive power loss of the two power switches

of an active clamp converter exceeds the current and thermal capabilities of the device. Thus the JFET should

only be used for initial start up of the control circuitry and to provide keep-alive power during stand-by mode

when the gate drive outputs are not switching. Accordingly, the start-up device is managed by its own control

algorithm implemented on board the UCC2891 and UCC2893. The following timing diagram illustrates the

operation of the JFET start up device.

13.5V

10.0V

8V <VDD < 10V

8.0V

Bootstrap bias

OFF

JFET

ENABLE

(See diagram on p.6)

SS/SD

OFF

SWITCHING

OFF

OUTPUTs

SWITCHING

UDG−03148

Figure 2. JFET Control Startup and Shutdown

During initial power up the JFET is on and charges the C

and C capacitors connected to the VDD pin (pin

BIAS

14). The VDD pin is monitored by the controller’s undervoltage lockout circuit to ensure proper biasing before

the operation is enabled. When the VDD voltage reaches approximately 12.7 V (UVLO turn-on threshold) the

UVLO circuit enables the rest of the controller. At that time, the JFET is turned off and 5 V appears on the VREF

terminal (pin 4). Switching waveforms might not appear at the gate drive outputs unless all other conditions of

proper operation are met. These conditions are:

sufficient voltage on the VREF pin (V

> 4.5V)

VREF

the voltage on the CS pin is below the current limit threshold

the control voltage is above the zero duty cycle boundary (V > 1.25 V)

the input voltage is in the valid operating range (V

protections are not activated.

<V <V

) i.e. the line under or overvoltage

VON VIN VOFF

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FUNCTIONAL DESCRIPTION

As the controller starts operation it draws its bias power from the C

capacitor until the bootstrap winding

BIAS

takes over (refering to Figure 12). During this time VDD voltage is falling rapidly as the JFET is already off but

the bootstrap voltage is still not sufficient to power the control circuits. It is imperative to store enough energy

in C

to prevent the bias voltage to dip below the turn off threshold of the UVLO circuit during the start up

BIAS

time interval. Otherwise the power supply goes through several cycles of retry attempts before steady state

operation might be established.

During normal operation the bias voltage is determined by the bootstrap bias design. The UCC289x family can

tolerate a wide range of bias voltages between the minimum operating voltage (UVLO turn-off threshold) and

the absolute maximum operating voltage as defined in the Recommended Operating Conditions.

In applications where the power supply must be able to go to stand by in response to an external command,

the bias voltage of the controller must be kept alive to be able to react intelligently to the control signal. In stand

by mode, switching action is suspended for an undefined period of time and the bootstrap power is unavailable

to bias the controller. Without an alternate power source the bias voltage would collapse and the controller would

initiate a re-start sequence. To avoid this situation, the on board JFET of the UCC289x controllers can keep the

VDD bias alive as long as the gate drive outputs remain inactive. As shown in the timing diagram in Figure 2,

the JFET is turned on when VDD = 10 V and charges the C

capacitor to approximately 13.5 V. At that time

BIAS

the JFET turns off and VDD gradually decreases to 10 V then the procedure is repeated. When the power supply

is enabled again, the controller is fully biased and ready to initiate its soft start sequence. As soon as the gate

drive pulses appear the JFET are turned off and bias must be provided by the bootstrap bias generator.

During power down the situation is different as switching action might continue until the VDD bias voltage drops

below the controller’s own UVLO turn-off threshold (approximately 8 V). At that time the UCC289x shuts down

completely turning off its 5 V bias rail and returning to start up state when the JFET device is turned on and the

capacitor starts charging again. In case the converter’s input voltage is re-established, the UCC289x

BIAS

attempts to restart the converter.

Line Undervoltage Protection

As shown in Figure 3, when the input power source is removed the power supply is turned off by the line

undervoltage protection because the bootstrap winding keeps the VDD bias up as long as switching takes place

in the power stage. As the power supply’s input voltage gradually decreases towards the line cut off voltage the

converter’s operating duty cycle must compensate for the lower input voltage. At minimum input voltage the duty

cycle nears its maximum value (D

). Under these conditions the voltage across the clamp capacitor

MAX

approaches its highest value since the transformer must be reset in a relatively short time. The timing diagram

in Figure 3 highlights that in the instance when the converter stops switching the clamp capacitor voltage might

be at its maximum level. Since the clamp capacitor’s only load is the power transformer, this high voltage could

linger across the clamp capacitor for a long time when the converter is off. With this high voltage present across

the clamp capacitor a soft start would be very dangerous, due to the narrow duty cycle of the main switch and

the long on-time of the clamp switch. This could cause the power transformer to saturate during the next

soft-start cycle.

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FUNCTIONAL DESCRIPTION

OFF

VCLAMP, MAX

CLAMP

OUT

AUX

Figure 3. Line Undervoltage Shutdown Waveforms, P−Channel

To eliminate this potential hazard the UCC289x controllers safely discharge the clamp capacitor during power

down. The AUX and OUT output continues switching while the soft-start capacitor C is being slowly

discharged. Notice that the AUX and OUT pulse width gradually decreases as the clamp voltage decreases

never applying the high voltage across the transformer for extended period of time. From this, the function of

soft stop is achieved.

Line Overvoltage Protection

When the line overvoltage protection is triggered in the UCC2892 and UCC2894 controllers, the gate drive

signals are immediately disabled. At the same time, the slow discharge of C is initiated. While the soft-start

capacitor is discharging the gate drive signals remains disabled. Once V

= 0.5 V and the overvoltage

disappears from the input of the power supply, operation resumes through a regular soft-start of the converter

as it is demonstrated in Figure 4.

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FUNCTIONAL DESCRIPTION

OVP

OVH

OUT

AUX

UDG−03150

Figure 4. Line Overvoltage Sequence, P−Channel

Pulse Skipping

During output load current transients or light load conditions most PWM controllers needs to be able to skip

some number of PWM pulses. In an active clamp topology where the clamp switch is driven complementarily

to the main switch, this would apply the clamp voltage across the transformer continuously. Since operating

conditions might require skipping several switching cycles on the main transistor, saturating the transformer is

very likely if the AUX output stays on.

D = 0 Boundary

1.25 V

OUT

AUX

UDG−03151

Figure 5. Pulse Skipping Operation, P−Channel

To overcome this problem, the UCC2891 family incorporates pulse skipping for both outputs in the controller.

As can be seen above, when a pulse is skipped at the main output (OUT) because the feedback signal demands

zero duty ratio, the corresponding output pulse on the AUX output is omitted as well. This operation allows to

prevent reverse saturation of the power transformer and to preserve the clamp capacitor voltage level during

pulse skipping operation.

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FUNCTIONAL DESCRIPTION

Synchronization

The UCC2891 family has a synchronization input pin which can be used to synchronize their oscillator to a

constant frequency system clock. The synchronization signal must have a higher frequency than the free

running oscillator frequency and can be either in-phase or out-of-phase for interleaved operation.

The operation of the oscillator and relevant other waveforms in free running and synchronized mode are shown

in Figure 6.

SYNC

MAX

OUT

AUX

UDG−03152

Figure 6. Synchronization Waveforms, P−Channel

The most critical and unique feature of the oscillator is to limit the maximum operating duty cycle of the converter.

It is achieved by accurately controlling the charge and discharge intervals of the on board timing capacitor. The

maximum on-time of OUT (pin 13), which is also the maximum duty cycle of the active clamp converter is limited

by the charging interval of the timing capacitor. While the capacitor is being reset to its initial voltage level OUT

is guaranteed to be off.

When synchronization is used, the rising edge of the signal terminates the charging period and initiate the

discharge of the timing capacitor. Once the timing capacitor voltage reaches the predefined valley voltage, a

new charge period starts automatically. This method of synchronization leaves the charge and discharge slopes

of the timing waveform unaffected thus maintains the maximum duty cycle of the converter, independent of the

mode of operation.

Although the synchronization circuit is level sensitive, the actual synchronization event occurs at the rising edge

of the waveform. This allows the synchronizing pulse width to vary significantly but certain limitations must be

observed. The minimum pulse width should be sufficient to guarantee reliable triggering of the internal oscillator

circuitry, therefore it should be greater than approximately 50 nanoseconds. The other limiting factor is to keep

it shorter than 1 * D

where T is the period of the synchronization frequency.

SYNC

MAX

SYNC

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FUNCTIONAL DESCRIPTION

When a wider than 1 * D

pulse is connected to the SYNC input, the oscillator is not able to

SYNC

MAX

maintain the maximum duty cycle, originally set by the timing resistor ratio (R , R

). Furthermore, the timing

ON OFF

capacitor waveform has a flat portion as highlighted by the vertical marker in the timing diagram. During this

flat portion of the waveform both outputs is off which state is not compatible with the operation of active clamp

power converters. Therefore, this operating mode is not recommended .

Note that both outputs of the UCC289x controllers are off if the synchronization signal stays continuously high.

APPLICATION INFORMATION: SETUP GUIDE

IN2

IN4

IN1

IN3

IN2

IN1

UCC2892

UCC2894

UCC2891

UCC2893

DEL

RDEL

LINEOV

RDEL

VIN 16

BIAS

RTON

LINEUV

RTON LINEUV 15

RTOFF VDD 14

OFF

RTOFF VDD 14

VREF

SYNC

GND

OUT 13

AUX 12

VREF

SYNC

GND

OUT 13

AUX 12

PGND 11

SS/SD 10

−V

PGND 11

SS/SD 10

−V

SLOPE

RSLOPE FB

VREF

Isolated Feedback

VREF

Isolated Feedback

Figure 7. UCC289x Typical Setup

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APPLICATION INFORMATION: SETUP GUIDE

The UCC2891 family offers a highly integrated feature set and excellent accuracy to control an active clamp

forward or active clamp flyback power converter. In order to take advantage of all the benefits integrated in these

controllers, the following procedure can simplify the setup and avoid unnecessary iterations in the design

procedure. Refer to Figure 7 setup diagrams for component names.

Before the controller design begins, the power stage design must be completed. From the power stage design

the following operating parameters are needed to complete the setup procedure of the controller:

Switching frequency (f

)

Maximum operating duty cycle (D

)

MAX

Soft start duration (t

)

Gate drive power requirements of the external power MOSFETs (Q

, Q

)

G(main) G(aux)

Bias method and voltage for steady state operation (bootstrap or bias supply)

Gate drive turn-on delay (t

)

DEL

Turn−on input voltage threshold (V

)

Minimum operating input voltage (V

) where V

< V

IN (off) IN(on)

OFF

Maximum operating input voltage (V

overvoltage protection hysteresis (V

)

OVP

)

OVH

The down slope of the output inductor current waveform reflected across the primary side current sense

resistor dV ńdt

Step 1. Oscillator

The two timing elements of the oscillator can be calculated from f

and D

by the following two equations:

MAX

ǒ^WǓ ₊

ǒ^WǓ

*12

37.33 10

(9)

1 * D

OFF

MAX

ǒ^WǓ ₊

ǒ^WǓ

OFF

*12

16 10

(10)

where D

is a dimensionless number between 0 and 1.

MAX

Step 2. Soft Start

Once R

is defined, the charge current of the soft-start capacitor can be calculated as:

REF

+ 0.43

(11)

During soft start, C is being charged from 0 V to 5 V by the calculated I current. The actual control range

of the soft-start capacitor voltage is between 1.25 V and 4.5 V. Therefore, the soft-start capacitor value must

be based on this narrower control range and the required start up time (t ) according to:

4.5 V * 1.25 V

(12)

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APPLICATION INFORMATION: SETUP GUIDE

Note, that t defines a time interval to reach the maximum current capability of the converter and not the time

required to ramp the output voltage from 0 V to its nominal, regulated level. Using an open-loop start up scheme

does not allow accurate control over the ramp up time of the output voltage. In addition to the I and C values,

the time required to reach the nominal output voltage of the converter is a function of the maximum output

current (current limit), the output capacitance of the converter and the actual load conditions. If it is critical to

implement a tightly controlled ramp-up time at the output of the converter, the soft-start must be implemented

using a closed loop technique. Closed loop soft-start can be implemented with the error amplifier of the voltage

regulation loop when its voltage reference is ramped from 0 V to its final steady state value during the required

start up time interval.

Step 3. VDD Bypass Requirements

First, the high-frequency filter capacitor is calculated based on the gate charge parameters of the external

MOSFETs. Assuming that the basic switching frequency ripple should be kept below 0.1-V across C , its value

can be approximated as:

) Q

G(aux)

G(main)

0.1 V

(13)

The energy storage requirements are defined primarily by the start up time (t ) and turn-on (approximately

12.7 V) and turn-off (approximately 8 V) thresholds of the controller’s undervoltage lockout circuit monitoring

the VDD voltage at pin 14. In addition, the bias current consumption of the entire primary side control circuit (I

+ I

) must be known. This power consumption can be estimated as:

EXT

₎ǒ_Q

₊ƪ_I

) I

) Q

BIAS

EXT

G(main)

G(aux)

(14)

During start up (t ) this power is provided by C

threshold. This relationship can be expressed as:

while its voltage must remain above the UVLO turn-off

BIAS

²Ǔ

13 * 8.5

BIAS

(15)

Rearranging the equation yields the minimum value for C

BIAS

2 P

²Ǔ

BIAS

13 * 8.5

(16)

Step 4. Delay Programming

From the power stage design, the required turn-on delay (t

) of the gate drive signals is defined. The

DEL

corresponding R

resistor value to implement this delay is given by:

DEL

ǒ^WǓ

+ T

0.91 10

DEL

DEL1

(17)

(18)

ǒ^WǓ

+ T

0.91 10

DEL2

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

APPLICATION INFORMATION: SETUP GUIDE

Step 5. Input Voltage Monitoring

The input voltage monitoring functions is governed by the following two expressions of the voltage at the

LINEUV terminal (pin 15):

IN2

+ V

at turn on, and

LINEUV

) R

IN2

IN1

(19)

* V

₊ǒ^V

HYST

OFF

VON

) I

at turn off.

IN2

IN1

(20)

Since V

line monitor and I

and V

are given by the power supply specification, V equals the 1.27-V threshold of the

LINEUV

HYST

OFF

is already defined as:

REF

0.05

HYST

DEL

(21)

the two unknown, R

expressions for the input voltage divider:

and R

are fully determined. Solving the equations results the following two

IN1

IN2

_OFFǓ

* V

IN1

IN2

HYST

(22)

(23)

1.27 V

* 1.27 V

+ R

IN1

Similar methods can be used to define the divider components of the overvoltage protection input of the

UCC2892 and UCC2894 controllers.

Step 6. Current Sense and Slope Compensation

The UCC2891 family offers onboard, user programmable slope compensation. The programming of the right

amount of slope compensation is accomplished by the appropriate selection of two external resistors, R and

SLOPE

First, the current sense filter resistor value (R ) must be calculated based on the desired filtering of the current

sense signal. The filter consists of two components, C and R . The C filter capacitor is connected between

the CS pin (pin 7) and the GND terminal (pin 6). While the value of C can be freely selected as the first step

of the filter design, it should be minimized to avoid filtering the slope compensation current exiting the CS pin.

The recommended range for the filter capacitance is between 50 pF and 270 pF. The value of the filter resistor

can be calculated from the filter capacitance and the desired filter corner frequency f .

R +

2p f C

(24)

After R is defined R

can be calculated. The amount of slope compensation is defined by the stability

SLOPE

requirements of the inner peak current loop of the control algorithm and is measured by the number m. When

the slope of the applied compensation ramp equals the down slope of the output inductor current waveform

reflected across the primary side current sense resistor dV ńdt , m equals 1. The minimum value of m is 0.5

to prevent current loop instability. Best current mode performance can be achieved around m=1. The further

increase of m moves the control closer to voltage mode control operation.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

APPLICATION INFORMATION: SETUP GUIDE

In the UCC289x controllers, slope compensation is implemented by sourcing a linearly increasing current at the

CS pin. When this current passes through the current sense filter resistor (R ), it is converted to a slope

compensation ramp which can be characterized by its dV ńdt . The dV ńdt of the slope compensation

current is defined by R

according to:

SLOPE

5 2 V

ON SLOPE

(25)

where

2V is the peak−to−peak ramp amplitude of the internal oscillator waveform

5 is the multiplication factor of the internal current mirror

The voltage equivalent of the compensation ramp dV ńdt can be easily obtained by multiplying with R . After

introducing the application specific m and dV ńdt values, the equation can be rearranged for R

SLOPE

5 2 V R

SLOPE

ǒ Ǔ

(26)

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

ADDITIONAL APPLICATION INFORMATION

The UCC2891 family of controllers is dedicated to control current mode active clamp flyback or forward

converters in an isolated power supply. The key advantage of the active clamp topologies is the zero voltage

switching (ZVS) of the primary side semiconductors. This operating mode reduces the switching losses of the

converter, thus facilitates higher switching frequencies or improves efficiency when operated at similar

frequencies as its hard switched designs. The simplified schematics below demonstrate the typical

implementations of these converters.

This active clamp flyback converter shown in Figure 8 highlights a high-side clamp circuit using an N-channel

MOSFET transistor as the auxiliary clamp switch.

Load

CLAMP

Bootstrap

Bias

VIN

AUX

VDD

N−Channel

Gate Drive

AUX

Synchronous

Rectifier

UCC2893

OUT

Control

MAIN

BIAS

GND

Secondary−Side

Error Amplifier

and Isolation

−V

UDG−03153

Figure 8. Zero Voltage Switching Flyback Application

Load

Bootstrap

Bias

CLAMP

VIN

VDD

Synchronous

Rectifier

AUX

P−Channel

Gate Drive

AUX 12

Control

UCC2891

OUT

MAIN

BIAS

GND

Secondary−Side

Error Amplifier

and Isolation

−V

UDG−03154

Figure 9. Active Clamp Forward Converter

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

ADDITIONAL APPLICATION INFORMATION

Figure 9 shows an active clamp forward converter with high-side clamp utilizing a P-channel auxiliary switch.

Detailed analysis and design examples of active clamp converters are published in the references listed at the

end of this datasheet.

Gate Drive Implementations

Both topologies can make use of either the high-side or the low-side clamp arrangement. Depending on the

choice of the clamp circuit, the gate drive requirements of the auxiliary switch are different.

CLAMP

AUX

MAIN

AUX 12

MAIN

Figure 10. High-Side N-Channel (UCC2893/4)

Figure 11. Low-Side P-Channel (UCC2891/2)

Interfacing with a high side N-channel clamp switch is achievable by using high side gate drive integrated circuits

or through a gate drive transformer. When a transformer is used, special attention must be paid to the fact that

the clamp switch is operated by the complementary waveform of the main power switch. Since the operating

duty cycle of the converter can vary between 0 and D

, the gate drive transformer must be able to drive the

MAX

auxiliary switch with any duty cycle from 1−D

to near 1.

MAX

The low side P-channel gate drive circuit involves a level shifter using a capacitor and a diode which ensures

that the gate drive amplitude of the auxiliary switch is independent of the actual duty cycle of the converter.

Detailed analysis and design examples of these and many similar gate drive solutions are given in reference [6].

Bootstrap Biasing

Many converters use a bootstrap circuit to generate its own bias power during steady state operation. The

popularity of this solutions is justified by the simplicity and high efficiency of the circuit. Usually, bias power is

derived from the main transformer by adding a dedicated, additional winding to the structure. Using a flyback

converter as shown in Figure 12, a bootstrap winding provides a quasi-regulated bias voltage for the primary

side control circuits. The voltage on the VDD pin is equal to the output voltage times the turns ratio between

the output and the bootstrap windings in the transformer. Since the output is regulated, the bias rail is regulated

as well.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

ADDITIONAL APPLICATION INFORMATION

While the same arrangement can be used in a forward type converter, the bootstrap winding off the main power

transformer would not be able to provide a quasi-regulated voltage. In the forward converter, the voltage across

the bootstrap winding equals the input voltage times the turns ratio. Accordingly the bias voltage would vary with

the input voltage and most likely would exceed the maximum operating voltage of the control circuits at high

line. A linear regulator can be used to limit and regulate the bias voltage if the power dissipation is acceptable.

Another possible solution for the forward converter is to generate the bias voltage from the output inductor as

shown in Figure 13.

Bootstrap Bias 1

LOAD

VIN

VDD 14

UCC2891

BIAS

Synchronous

Rectifier

GND

MAIN

Control

UDG−03155

−V

Figure 12. Bootstrap Bias 1, Flyback Example

This solution uses the regulated output voltage across the output inductor during the freewheeling period to

generate a quasi-regulated bias for the control circuits.

Bootstrap Bias 2

LOAD

VIN

VDD 14

UCC2891

BIAS

Synchronous

Rectifier

MAIN

GND

Control

−V

UDG−03156

Figure 13. Bootstrap Bias 2, Forward Example

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

ADDITIONAL APPLICATION INFORMATION

This solution uses the regulated output voltage across the output inductor during the freewheeling period to

generate a quasi-regulated bias for the control circuits.

Both of the illustrated solution provides reliable bias power during normal operation. Note that in both cases,

the bias voltages are proportional to the output voltage. This nature of the bootstrap bias supply causes the

converter to operate in a hiccup mode under significant overload or under short-circuit conditions as the

bootstrap winding is not able to hold the bias rail above the undervoltage lockout threshold of the controller.

ADDITIONAL APPLICATION INFORMATION

References and Additional Development Tools

1. Evaluation Module: UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset.

2. User’s Guide: Using the UCC2891EVM, 48-V to 3.3-V, 30-A Forward Converter with Active Clamp Reset,

(SLUU178)

3. Application Note: Designing for High Efficiency with the UCC2891 Active Clamp PWM Controller, Steve

Mappus (SLUA303)

4. Power Supply Design Seminar Topic: Design Considerations for Active Clamp and Reset Technique, D.

Dalal, SEM1100−Topic3 (SLUP112)

5. Power Supply Design Seminar Topic: Active Clamp and Reset Technique Enhances Forward Converter

Performance, B. Andreycak, SEM1000−Topic 3. (SLUP108)

6. Power Supply Design Seminar Topic: Design and Application Guide for High Speed MOSFET Gate Drive

Circuits, L. Balogh, SEM1400−Topic 2 (SLUP169)

7. Datasheet: UCC3580, Single Ended Active-Clamp/Reset PWM Controller, (SLUS292A)

8. Evaluation Module: UCC3580EVM, Flyback Converters, Active Clamp vs. Hard−Switched (SLUU085)

9. Reference Designs: Highly Efficient 100W Isolated Power Supply Reference Design Using UCC3580−1,

Texas Instruments Hardware Reference Design Number PMP206−C (SLUU146)

10. Reference Designs: Active Clamp Forward Reference Design using UCC3580−1. Texas Instruments

Hardware Reference Design Number PMP368 (SLVR053, SLVR079, SLVR096)

Reference Circuit

For completeness, the schematic diagram of a complete active clamp forward converter is shown in Figure 14.

The detailed description of the circuit operation and design procedure can be found in SLUU178.

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

ADDITIONAL APPLICATION INFORMATION

Figure 14. UCC2891 EVM Schematic

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

TYPICAL CHARACTERISTICS

UVLO VOLTAGE THRESHOLDS

JUNCTION TEMPERATURE

QUIESCENT CURRENT

SUPPLY VOLTAGE

2.5

UVLO On

2.0

1.5

UVLO Off

1.0

0.5

UVLO Hysteresis

−50

−25

100

125

− Supply Voltage − V

− Junction Temperature − °C

Figure 15

Figure 16

SUPPLY CURRENT

REFERENCE VOLTAGE

SUPPLY VOLTAGE

TEMPERATURE

UCC2891/UCC2893

= 36 V

No Load

10 mA Load

−10

−20

−30

−20

−30

JFET Source Current

−40

−50

−40

−50

−25

100

125

− Junction Temperature − °C

− Supply Voltage − V

Figure 17

Figure 18

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

TYPICAL CHARACTERISTICS

SOFTSTART CURRENTS

LINE UV/OV VOLTAGE THRESHOLD

TEMPERATURE

JUNCTION TEMPERATURE

1.30

1.28

Softstart Discharge Current

1.26

1.24

1.22

−5

−10

−15

−20

Softstart Charge Current

1.20

−50

−25

100

125

−50

−25

100

125

− Junction Temperature − °C

Figure 20

Figure 19

SOFTSTART/SHUTDOWN THRESHOLD VOLTAGE

SWITCHING FREQUENCY

PROGRAMMING RESISTANCE

JUNCTION TEMPERATURE

0.60

0.58

10 M

0.56

0.54

1 M

0.52

0.50

100 K

0.48

0.46

0.44

0.42

0.40

10 K

1 K

−50

−25

100

125

100

− Timing Resistance − kΩ

1000

− Junction Temperature − °C

= R

OFF

Figure 21

Figure 22

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY

JUNCTION TEMPERATURE

MAXIMUM DUTY CYCLE

JUNCTION TEMPERATURE

275

270

= 75 kΩ

ON= OFF

= 75 kΩ

ON= OFF

265

260

255

250

245

240

235

230

225

−50

−25

100

125

−50

−25

100

125

− Junction Temperature − °C

Figure 23

Figure 24

CURRENT SENSE THRESHOLD VOLTAGE

SYNCHRONIZATION THRESHOLD VOLTAGE

JUNCTION TEMPERATURE

1.4

1.2

2.50

2.45

2.40

UCC2892/UCC2894

UCC2891/UCC2893

1.0

0.8

2.35

2.30

0.6

0.4

2.25

2.20

0.2

2.15

2.10

−50

−25

100

125

−50

−25

100

125

− Junction Temperature − °C

Figure 25

Figure 26

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SLUS542F − OCTOBER 2003 − REVISED JULY 2009

TYPICAL CHARACTERISTICS

DELAY TIME

DELAY RESISTANCE

OUT AND AUX RISE AND FALL TIME

JUNCTION TEMPERATURE

800

= 2 nF

LOAD

Rise Time

700

600

500

400

300

DEL1

DEL2

Fall Time

200

100

−50

−25

100

125

− Delay Resistance − kΩ

− Junction Temperature − °C

DEL

Figure 27

Figure 28

DELAY TIME

JUNCTION TEMPERATURE

DELAY TIME

JUNCTION TEMPERATURE

250

800

700

600

500

400

300

200

100

= 10 kΩ

= 50 kΩ

DEL

200

150

OUT to AUX

AUX to OUT

OUT to AUX

100

AUX to OUT

−50

−25

100

125

−50

−25

100

125

− Junction Temperature − °C

Figure 29

Figure 30

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PACKAGE OPTION ADDENDUM

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5-Mar-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

UCC2891D

UCC2891DG4

UCC2891DR

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SOIC

2500

Green (RoHS

& no Sb/Br)

UCC2891DRG4

UCC2891PW

UCC2891PWG4

UCC2891PWR

UCC2891PWRG4

UCC2892D

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC2892DG4

UCC2892DR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

UCC2892DRG4

UCC2892PW

UCC2892PWG4

UCC2892PWR

UCC2892PWRG4

UCC2893D

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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5-Mar-2011

Status ⁽¹⁾

ACTIVE

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

UCC2893DG4

UCC2893DR

SOIC

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

UCC2893DRG4

UCC2893PW

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

SOIC

Green (RoHS

& no Sb/Br)

UCC2893PWG4

UCC2893PWR

UCC2893PWRG4

UCC2894D

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

UCC2894DG4

UCC2894DR

SOIC

Green (RoHS

& no Sb/Br)

SOIC

2500

Green (RoHS

& no Sb/Br)

UCC2894DRG4

UCC2894PW

SOIC

Green (RoHS

& no Sb/Br)

TSSOP

Green (RoHS

& no Sb/Br)

UCC2894PWG4

UCC2894PWR

UCC2894PWRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

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5-Mar-2011

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

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14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC2891DR

UCC2891PWR

UCC2892DR

UCC2892PWR

UCC2893DR

UCC2893PWR

UCC2894DR

UCC2894PWR

SOIC

TSSOP

SOIC

2500

2000

2500

2000

2500

2000

2500

2000

330.0

16.4

12.4

16.4

12.4

16.4

12.4

16.4

12.4

6.5

6.9

6.5

6.9

6.5

6.9

6.5

6.9

10.3

5.6

2.1

1.6

2.1

1.6

2.1

1.6

2.1

1.6

8.0

16.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

10.3

5.6

TSSOP

SOIC

10.3

5.6

TSSOP

SOIC

10.3

5.6

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC2891DR

UCC2891PWR

UCC2892DR

UCC2892PWR

UCC2893DR

UCC2893PWR

UCC2894DR

UCC2894PWR

SOIC

TSSOP

SOIC

2500

2000

2500

2000

2500

2000

2500

2000

333.2

367.0

333.2

367.0

333.2

367.0

333.2

367.0

345.9

367.0

345.9

367.0

345.9

367.0

345.9

367.0

28.6

35.0

28.6

35.0

28.6

35.0

28.6

35.0

TSSOP

SOIC

TSSOP

SOIC

TSSOP

Pack Materials-Page 2

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UCC2893PWG4 [TI]

相关型号：

UCC2893PWR

UCC2893PWRG4

UCC2893_14

UCC2894

UCC2894D

UCC2894DG4

UCC2894DR

UCC2894DRG4

UCC2894PW

UCC2894PWG4

UCC2894PWR

UCC2894PWRG4