UCC28951PWR [TI]
具有 SR 控制功能的绿色环保相移全桥控制器，适用于宽输入电压范围 | PW | 24 | -40 to 125;
| 型号： | UCC28951PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SR 控制功能的绿色环保相移全桥控制器，适用于宽输入电压范围 | PW | 24 | -40 to 125 控制器 |
| 文件： | 总82页 (文件大小：3502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC28951
ZHCSIQ7A –AUGUST 2018 –REVISED DECEMBER 2021
UCC28951 适用于宽输入电压范围应用的相移全桥控制器
1 特性
3 说明
• 增强型零电压开关(ZVS) 范围
• 直接同步整流器(SR) 控制
• 轻负载效率管理包括：
UCC28951 控制器是 UCC28950 的增强版本。它是
UCC28950 完全兼容的快插替代器件。UCC28951 采
用全桥高级控制，并对同步整流器 (SR) 输出级进行主
动控制。
– 突发模式运行
– 不连续导通模式(DCM)，通过可编程阈值实现
的动态SR 开关控制
– 可编程自适应延迟
可编程的延迟确保了 ZVS 可在广泛的工作条件下运
行，而负载电流可合理调节次级侧同步整流器 (SR) 的
开关延迟。此功能最大程度地提高总体系统效率。
• 支持可编程斜坡补偿和电压模式控制的平均或者峰
值电流模式控制
• 闭环路软启动和使能功能
• 支持双向同步的高达1MHz 的可编程开关频率
• (±3%) 支持断续模式的逐周期电流限制保护
• 150µA 启动电流
24 引脚TSSOP 封装符合RoHS 要求。
器件信息
封装(1)
封装尺寸（标称值）
器件型号
UCC28951
TSSOP (24)
7.80mm × 4.40mm
• VDD 欠压锁定
• 宽温度范围：–40°C 至125°C
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 相移全桥转换器
• 服务器电源
• 工业电源系统
• 高密度电源架构
+
CREF
VBIAS
1
VREF
GND 24
VIN
RLF2
R2
C1
VDD
R1
CIN
CVDD
2
3
EA+
EA-
VDD 23
œ
R3
OUTA 22
A
B
VDD
VDD
R4
VSENSE
R5
4
COMP
OUTB 21
QA
QC
A
C
CT
T1
R6
5
6
7
8
SS/EN
DELAB
DELCD
DELEF
OUTC 20
OUTD 19
OUTE 18
OUTF 17
C
D
E
F
CSS
RAB
RCD
ENABLE
VDD
VDD
QD
REF
QB
D
LOUT
B
RTMIN
9
TMIN
SYNC 16
CS 15
SYNC
RAHI
RT
VOUT
VREF
10 RT
+
RAEFHI
RSUM
UCC27324
11 RSUM
12 DCM
ADEL 14
UCC27324
COUT
QE
QF
RDCMHI
E
F
ADELEF 13
VREF
RA
œ
RAEF
D
A
RLF1
RCS
CLF
RDCM
VSENSE
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDB2
UCC28951
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ZHCSIQ7A –AUGUST 2018 –REVISED DECEMBER 2021
Table of Contents
7.2 Functional Block Diagram.........................................20
7.3 Feature Description...................................................21
7.4 Device Functional Modes..........................................38
8 Application and Implementation..................................39
8.1 Application Information............................................. 39
8.2 Typical Application.................................................... 42
9 Power Supply Recommendations................................71
10 Layout...........................................................................72
10.1 Layout Guidelines................................................... 72
10.2 Layout Example...................................................... 73
11 Device and Documentation Support..........................74
11.1 Device Support........................................................74
11.2 Documentation Support.......................................... 74
11.3 Receiving Notification of Documentation Updates..74
11.4 Community Resources............................................74
11.5 Trademarks............................................................. 74
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements................................................10
6.7 Dissipation Ratings................................................... 10
6.8 Typical Characteristics..............................................12
7 Detailed Description......................................................19
7.1 Overview...................................................................19
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (September 2018) to Revision A (December 2021)
Page
• 通篇将旧术语更改为领导者 和跟随者 ................................................................................................................1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Changed note in Soft-Start and Enable (SS/EN) section ................................................................................ 22
• Updated all equations in Soft-Start and Enable (SS/EN) section .................................................................... 22
• Updated mo calculation equation......................................................................................................................29
• Updated all equations in Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode section.............33
• Updated ICINRMS calculation equation...............................................................................................................54
• Updated resistor RT calculation equation......................................................................................................... 59
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English Data Sheet: SLUSDB2
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5 Pin Configuration and Functions
1
24
23
22
21
20
19
18
17
16
15
14
13
VREF
EA+
GND
2
VDD
3
EA–
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
SYNC
CS
4
COMP
SS/EN
DELAB
DELCD
DELEF
TMIN
RT
5
6
7
8
9
10
11
12
RSUM
DCM
ADEL
ADELEF
图5-1. PW Package, 24-Pin TSSOP (Top View)
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
ADEL
ADELEF
COMP
CS
NO.
14
13
4
I
Dead-time programming for the primary switches over CS voltage range, tABSET and tCDSET.
I
Delay-time programming between primary side and secondary side switches, tAFSET and tBESET
Error amplifier output and input to the PWM comparator.
Current sense for cycle-by-cycle overcurrent protection and adaptive delay functions.
DCM threshold setting.
.
I/O
15
12
6
I
I
I
I
I
I
I
DCM
DELAB
DELCD
DELEF
EA+
Dead-time delay programming between OUTA and OUTB.
Dead-time delay programming between OUTC and OUTD.
Delay-time programming between OUTA to OUTF, and OUTB to OUTE.
Error amplifier noninverting input.
7
8
2
3
Error amplifier inverting input.
EA–
GND
24
22
21
20
19
18
17
11
10
5
Ground. All signals are referenced to this node.
—
O
O
O
O
O
O
I
OUTA
OUTB
OUTC
OUTD
OUTE
OUTF
RSUM
RT
0.2-A sink and source primary switching output.
Slope compensation programming. Voltage mode or peak current mode setting.
Oscillator frequency set. leader or follower mode setting.
Soft-start programming, device enable and hiccup mode protection circuit.
Synchronization out from leader controller to input of follower controller.
Minimum duty cycle programming in burst mode.
I
SS/EN
SYNC
TMIN
VDD
I
16
9
I/O
I
23
I
Bias supply input.
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
VREF
1
O
5-V, ±1.5%, 20-mA reference voltage output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
–0.4
–0.4
MAX
20
UNIT
V
(3)
Input supply voltage, VDD
OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
VDD + 0.4
V
Input voltage on DELAB, DELCD, DELEF, SS/EN, DCM, TMIN, RT, SYNC, RSUM, EA+, EA-,
COMP, CS, ADEL, ADELEF
VREF + 0.4
5.6
V
V
–0.4
–0.4
Output voltage on VREF
Continuous total power dissipation
Operating virtual junction temperature, TJ
Operating ambient temperature, TA
Lead temperature (soldering, 10 s)
Storage temperature, Tstg
See 节6.7
150
°C
°C
°C
°C
–40
–40
125
300
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under 节6.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See 节
Mechanical, Packaging, and Orderable Information for thermal limitations and considerations of packages.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
TYP
MAX
17
UNIT
V
Supply voltage, VDD
12
Operating junction temperature
125
1000
°C
–40
50
Converter switching frequency setting, FSW(nom)
Programmable delay between OUTA, OUTB and OUTC, OUTD set by resistors DELAB and
kHz
30
30
1000
1400
ns
ns
(1)
DELCD and parameter KA
Programmable delay between OUTA, OUTF and OUTB, OUTE set by resistor DELEF, and
(1)
parameter KEF
Programmable DCM as percentage of voltage at CS(1)
5%
30%
800
Programmable TMIN
100
ns
(1) Verified during characterization only.
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ZHCSIQ7A –AUGUST 2018 –REVISED DECEMBER 2021
6.4 Thermal Information
UCC28951
THERMAL METRIC(1)
PW (TSSOP)
24 PINS
93.3
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
24.2
47.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJT
47.4
ψJB
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VDD = 12 V, TA = TJ = –40°C to +125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ, REF = 13.3 kΩ, RSUM
=
124 kΩ, RTMIN = 88.7 kΩ, RT = 59 kΩconnected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200
kHz) (unless otherwise noted). All component designations are from 图8-3.
PARAMETER
TEST CONDITIONS
MIN
6.75
6.15
0.53
TYP
MAX
UNIT
UNDERVOLTAGE LOCKOUT (UVLO)
7.9
UVLO_RTH Start threshold
V
V
V
TA = 25°C
TA = 25°C
TA = 25°C
VDD = 5.2 V
7.3
6.7
0.6
7.2
Minimum operating voltage
UVLO_FTH
after start
0.75
UVLO_HYST Hysteresis
SUPPLY CURRENTS
270
10
IDD(off)
Startup current
µA
VDD = 5.2 V, TA = 25°C
150
5
IDD
Operating supply current
mA
TA = 25°C
VREF OUTPUT VOLTAGE
4.925
5.075
0 ≤IR ≤20 mA, 8 V ≤VDD ≤17 V
VREF
VREF total output range
V
0 ≤IR ≤20 mA, 8 V ≤VDD ≤17 V, TA =
25°C
5
ISCC
Short circuit current
VREF = 0 V
mA
–53
–23
108
SWITCHING FREQUENCY (½ OF INTERNAL OSCILLATOR FREQUENCY FOSC
)
92
FSW(nom)
Total range
kHz
TA = 25°C
TA = 25°C
100
97%
DMAX
Maximum duty cycle
95%
SYNCHRONIZATION
RT = 59 kΩbetween RT and GND, Input
pulses 200 kHz, D = 0.5 at SYNC
85
95
PHSYNC
Total range
°PH
RT = 59 kΩbetween RT and GND, Input
pulses 200 kHz, D = 0.5 at SYNC, TA = 25°C
90
RT = 59 kΩbetween RT and 5 V; –40 °C ≤
TJ ≤125°C
180
2.2
220
2.8
FSYNC
Total range
Pulse width
kHz
µs
TA = 25°C
200
2.5
TPW
TA = 25°C
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ZHCSIQ7A –AUGUST 2018 –REVISED DECEMBER 2021
VDD = 12 V, TA = TJ = –40°C to +125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ, REF = 13.3 kΩ, RSUM
=
124 kΩ, RTMIN = 88.7 kΩ, RT = 59 kΩconnected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200
kHz) (unless otherwise noted). All component designations are from 图8-3.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
VICM range ensures parameters, the
functionality ensured for 3.6 V < VICM < VREF
+ 0.4 V, and –0.4 V < VICM < 0.5 V
Common-mode input voltage
range
VICM
0.5
3.6
V
VIO
Offset voltage
7
1
mV
µA
–7
–1
IBIAS
Input bias current
V
mA
(EA+) –V(EA–) = 500 mV, IEAOUT = –0.5
3.9
EAHIGH
High-level output voltage
Low-level output voltage
V
V
V
(EA+) –V(EA–) = 500 mV, IEAOUT = –0.5
4.25
mA, TA = 25°C
V
mA
(EA+) –V(EA–) = –500 mV, IEAOUT = 0.5
0.35
EALOW
V
(EA+) –V(EA–) = –500 mV, IEAOUT = 0.5
0.25
mA, TA = 25°C
–8
–0.5
ISOURCE
Error amplifier source current
Error amplifier sink current
mA
mA
TA = 25°C
–3.75
2.7
5.75
ISINK
TA = 25°C
TA = 25°C
TA = 25°C
4.6
100
3
IVOL
Open-loop DC gain
dB
GBW
Unity gain bandwidth(1)
MHz
CYCLE-BY-CYCLE CURRENT LIMIT
1.94
2.06
CS pin cycle-by-cycle
threshold
VCS_LIM
V
TA = 25°C
2
INTERNAL HICCUP MODE SETTINGS
VCS = 2.5 V, VVSS = 4 V
15
3.2
1.9
25
4.2
3.2
Discharge current to set cycle-
by-cycle current limit duration
IDS
µA
V
VCS = 2.5 V, VVSS = 4 V, TA = 25°C
20
3.6
VHCC
Hiccup OFF time threshold
TA = 25°C
TA = 25°C
Discharge current to set
Hiccup Mode OFF Time
IHCC
µA
2.55
SOFT START/ENABLE
VSS = 0 V
TA = 25°C
20
0.25
3.3
30
0.7
ISS
Charge current
µA
V
25
0.5
VSS_STD
VSS_PU
VSS_CL
Shutdown, restart threshold
Pullup threshold
TA = 25°C
TA = 25°C
TA = 25°C
4.3
V
3.7
4.2
4.95
Clamp voltage
V
4.65
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VDD = 12 V, TA = TJ = –40°C to +125°C, CVDD = 1 µF, CREF = 1 µF, RAB = 22.6 kΩ, RCD = 22.6 kΩ, REF = 13.3 kΩ, RSUM
=
124 kΩ, RTMIN = 88.7 kΩ, RT = 59 kΩconnected between RT pin and 5-V voltage supply to set FSW = 100 kHz (FOSC = 200
kHz) (unless otherwise noted). All component designations are from 图8-3.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LIGHT-LOAD EFFICIENCY CIRCUIT
VDCM = 0.4 V, Sweep CS confirm there are
OUTE and OUTF pulses, TA = 25°C
0.37
0.39
0.39
0.41
V
V
VDCM = 0.4 V, Sweep CS, confirm there are
OUTE and OUTF pulses, 0°C ≤TA ≤
85°CDCM threshold, (6)
0.364
0.416
VDCM
DCM threshold
VDCM = 0.4 V, Sweep CS, confirm there are
OUTE and OUTF pulses, –40°C ≤TA ≤
125°C(6)
0.35
14
0.39
0.43
26
V
CS < DCM threshold
IDCM_SRC
DCM Sourcing Current
µA
CS < DCM threshold, TA = 25°C
20
OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
Sink and source peak
ISINK/SRC
TA = 25°C
0.2
A
current(6)
IOUT = 20 mA
10
5
35
30
RSRC
Output source resistance
Ω
IOUT = 20 mA, TA = 25°C
IOUT = 20 mA
20
10
RSINK
Output sink resistance
Ω
IOUT = 20 mA, TA = 25°C
THERMAL SHUTDOWN
Rising threshold(6)
TA = 25°C
TA = 25°C
160
140
20
°C
°C
°C
Falling threshold(6)
Hysteresis
(1) See 图7-1 for timing diagram and TABSET1, TABSET2, TCDSET1, TCDSET2 definitions.
(2) See 图7-4 for timing diagram and TAFSET1, TAFSET2, TBESET1, TBESET2 definitions.
(3) Pair of outputs OUTC, OUTE and OUTD, OUTF always going high simultaneously.
(4) Outputs A or B are never allowed to go high if both outputs OUTE and OUTF are high.
(5) All delay settings are measured relative to 50% of pulse amplitude.
(6) Verified during characterization only.
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
CYCLE-BY-CYCLE CURRENT LIMIT
Propagation delay from CS to OUTC and OUTD outputs
Input pulse between CS and GND from zero to 2.5 V
TCS
100
ns
PROGRAMMABLE DELAY TIME SET ACCURACY AND RANGE(1) (2) (3) (4) (5)
Short delay time set accuracy between OUTA and OUTB
CS = ADEL = ADELEF = 1.8 V
TABSET1
32
216
32
45
270
45
56
325
56
ns
ns
ns
ns
ns
ns
ns
ns
Long delay time set accuracy between OUTA and OUTB
CS = ADEL = ADELEF = 0.2 V
TABSET2
Short delay time set accuracy between OUTC and OUTD
CS = ADEL = ADELEF = 1.8 V
TCDSET1
Long delay time set accuracy between OUTC and OUTD
CS = ADEL = ADELEF = 0.2 V
TCDSET2
216
22
270
35
325
48
Short delay time set accuracy between falling OUTA, OUTF
CS = ADEL = ADELEF = 0.2 V
TAFSET1
Long delay time set accuracy between falling OUTA, OUTF
CS = ADEL = ADELEF = 1.8 V
TAFSET2
190
22
240
35
290
48
Short delay time set accuracy between falling OUTB, OUTE
CS = ADEL = ADELEF = 0.2 V
TBESET1
Long delay time set accuracy between falling OUTB, OUTE
CS = ADEL = ADELEF = 1.8 V
TBESET2
190
240
290
Pulse matching between OUTA rise, OUTD fall and OUTB
rise, OUTC fall
CS = ADEL = ADELEF = 1.8 V, COMP = 2 V
0
0
0
0
50
50
60
60
ns
ns
ns
ns
ΔTADBC
ΔTABBA
ΔTEEFF
ΔTEFFE
–50
–50
–60
–60
Half cycle matching between OUTA rise, OUTB rise and
OUTB rise, OUTA rise
CS = ADEL = ADELEF = 1.8 V, COMP = 2 V
Pulse matching between OUTE fall, OUTE rise and OUTF fall,
OUTF rise
CS = ADEL = ADELEF = 0.2 V, COMP = 2 V
Pulse matching between OUTE fall, OUTF rise and OUTF fall,
OUTE rise
CS = ADEL = ADELEF = 0.2 V, COMP = 2 V
LIGHT-LOAD EFFICIENCY CIRCUIT
TMIN
OUTPUTS OUTA, OUTB, OUTC, OUTD, OUTE, OUTF
425
525
625
ns
Total range, RTMIN = 88.7 kΩ
TR
TF
Rise time, CLOAD = 100 pF
Fall time, CLOAD = 100 pF
9
7
25
25
ns
ns
6.7 Dissipation Ratings
over operating free-air temperature range (unless otherwise noted)
DERATING FACTOR
PACKAGE
POWER RATING
TA = 70°C
ABOVE TA = 25°C
TA < 25°C
TA = 85°C
PW
10.7 mW/°C
1.07 W
0.59 W
0.429 W
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7.3-V rise, 6.7-V fall
VDD
VDD_GOOD
4.8-V rise, 4.6-V fall
VREF
VREF_GOOD
SS > 0.5 V, then release COMP, DCM, CS , Outputs A,B,C,D,E and F
CLK
TMIN
TMIN
Add 0.85 V offset to RAMP
No PWM pulses shorter than TMIN
except during cycle-by-cycle current limit
PWM
TMIN
COMP
RAMP
PWM
2 VP-P
A
B
C
D
E
F
Burst Mode at the beginning of
start up until PWM> TMIN pulses
No output delay shown, COMP-to-RAMP offset not included.
There is no pulse on OUTE during burst mode at start-up. Two falling edge PWM pulses are required before enabling the synchronous
rectifier outputs. Narrower pulse widths (less than 50% duty cycle) may be observed in the 1st OUTD pulse of a burst. The user must
design the bootstrap capacitor charging circuit of the gate driver device so that the first OUTC pulse is transmitted to the MOSFET gate
in all cases. Transformer based gate driver circuits are not affected. This behavior is described in more detail in the Gate Drive Outputs
on the UCC28950 and UCC28951 During Burst Mode Operation (SLAU787) application note.
图6-1. UCC28951 Start-Up Timing
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VDD failed and VDD_GOOD goes low,
Everything is shutdown
7.3V rise, 6.7V fall
VDD
VDD_GOOD
4.8V rise, 4.6V fall
VREF
VREF_GOOD
TMIN
CLK
TMIN
Add 0.85V offset to RAMP
COMP
2Vp-p
RAMP
PWM
No PWM pulses shorter than TMIN except
during cycle-by-cycle current limit
A
B
C
D
E
F
No output delay shown, COMP-to-RAMP offset not included.
图6-2. UCC28951 Steady-State and Shutdown Timing Diagram
6.8 Typical Characteristics
7.6
640
7.4
UVLO_RTH
630
620
7.2
7.0
6.8
6.6
6.4
UVLO_HYST
610
600
UVLO_FTH
590
580
6.2
-40
25
TJ - Temperature - °C
125
-40
25
TJ - Temperature - °C
125
图6-3. UVLO Thresholds vs Temperature
图6-4. UVLO Hysteresis vs Temperature
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250
200
150
3.9
3.8
3.7
3.6
3.5
100
50
3.4
-40
-40
25
125
25
125
TJ - Temperature - °C
TJ - Temperature - °C
图6-6. Start-Up Current vs Temperature
图6-5. Supply Current vs Temperature
5.010
5.001
4.999
4.997
I
LOAD = 10µA
VREF _ 10 mA _ 12 VDD
5.005
5.000
ILOAD = 1 mA
VREF _ 10 mA _ 10 VDD
4.995
4.990
4.995
4.993
ILOAD = 10 mA
4.985
4.991
4.989
VREF _ 10 mA _ 8 VDD
ILOAD = 20 mA
4.980
4.975
4.987
4.985
-40
25
TJ - Temperature - °C
125
-40
25
125
TJ - Temperature - °C
图6-7. Voltage Reference (VDD = 12 V) vs
图6-8. Line Voltage Regulation (ILOAD = 10 mA) vs
Temperature
Temperature
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38.5
38.0
95.4
95.2
95.0
94.8
94.6
94.4
94.2
94.0
37.5
37.0
36.5
36.0
35.5
35.0
93.8
93.6
-40
25
125
-40
25
125
TJ - Temperature - °C
TJ - Temperature - °C
图6-9. Short-Circuit Current vs Temperature
图6-10. Maximum Duty Cycle vs Temperature
95.4
1079
95.0
94.6
1059
1039
94.0
93.6
1019
999
-40
25
125
-40
25
125
TJ - Temperature - °C
TJ - Temperature - °C
图6-11. Nominal Switching Frequency vs
图6-12. Maximum Switching Frequency vs
Temperature
Temperature
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0.00
125
-0.05
-0.10
-0.15
120
115
110
-0.20
-0.25
-0.30
VIO = 500 mV
105
100
VIO = 3.6 V
-0.35
-0.40
-0.45
VIO = 2.5 V
95
90
85
-0.50
-40
25
TJ - Temperature - °C
125
-40
25
125
TJ - Temperature - °C
图6-13. Error Amplifier Offset Voltage vs
图6-14. Voltage Error Amplifier (Open-Loop Gain)
Temperature
vs Temperature
26.0
0.60
0.55
0.50
25.5
25.0
24.5
0.45
0.40
0.35
0.30
24.0
23.5
-40
25
125
-40
25
125
TJ - Temperature - °C
TJ - Temperature - °C
图6-15. ISS Charge Current vs Temperature
图6-16. Shutdown, Restart, and Reset Threshold
vs Temperature
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3.715
3.710
3.705
4.692
4.690
4.688
4.686
4.684
4.682
4.680
4.678
4.676
4.674
3.700
3.695
-40
25
125
-40
25
125
TJ - Temperature - °C
TJ - Temperature - °C
图6-17. SS Pullup Threshold vs Temperature
图6-18. SS Clamp Voltage vs Temperature
1.996
110
1.994
1.992
107
104
1.990
101
1.988
1.986
1.984
98
95
-40
25
125
-40
25
125
TJ - Temperature - °C
TJ - Temperature - °C
图6-19. Current Sense Cycle-by-Cycle Limit vs
图6-20. Current Sense Propagation Delay vs
Temperature
Temperature
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17.5
17.5
RSINK_OUTF
RSINK_OUTD
RSINK_OUTA
RSINK_OUTE
RSINK_OUTC
RSINK_OUTB
15.5
13.5
15.5
13.5
11.5
9.5
11.5
9.5
7.5
-40
7.5
25
TJ - Temperature - °C
125
-40
25
125
TJ - Temperature - °C
图6-21. Outputs Sink Resistance vs Temperature
图6-22. Outputs Sink Resistance vs Temperature
25
25
RSRC_OUTE
RSRC_OUTF
RSRC_OUTD
RSRC_OUTB
RSRC_OUTC
RSRC_OUTA
23
23
21
21
19
17
15
19
17
15
-40
25
125
-40
25
125
TJ - Temperature - °C
TJ - Temperature - °C
图6-24. Outputs Source Resistance vs
图6-23. Outputs Source Resistance vs
Temperature
Temperature
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50
280
TCDSET2
TCDSET1
270
260
TABSET1
45
TABSET2
40
35
30
250
240
TAFSET2
TAFSET1
TBESET2
230
220
TBESET1
-40
25
125
-40
25
TJ - Temperature - °C
125
TJ - Temperature - °C
图6-25. Dead Time Delay vs Temperature
图6-26. Dead Time Delay vs Temperature
0.405
0.400
0.395
0.390
0.385
0.380
0.380
0.375
-40
25
TJ - Temperature - °C
125
图6-27. DCM Threshold vs Temperature
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7 Detailed Description
7.1 Overview
The UCC28951 controller combines all the functions necessary to control a phase-shifted, full-bridge, power
stage in a 24-pin TSSOP package. The controller includes two synchronous-rectifier (SR), gate-drive outputs as
well as the outputs needed to drive all four switches in the full-bridge circuit. The dead times between the upper
and lower switches in the full bridge may be set using the DELAB and DELCD inputs. Further, this dead time
may be dynamically adjusted according to the load level using the ADEL pin. This adjustment allows the user to
optimize the dead time for their particular power circuit and to achieve ZVS over the entire operating range. In a
similar manner, the dead times between the full-bridge switches and the secondary SRs may be optimized using
the DELEF input. This dead time may also be dynamically adjusted according to the load, using the ADELEF
input to the controller. A DCM (discontinuous conduction mode) option disables the SRs at a user settable light
load to improve power circuit efficiency. The controller enters a light-load-burst mode if the feedback loop
demands a conduction time less than a user settable level (TMIN).
At higher-power levels, two or more UCC28951 controllers may be easily synchronized in a leader/follower
configuration. A SS/EN input may be used to set the length of the soft start process and to turn the controller on
and off. The controller may be configured for voltage mode or current mode control. Cycle-by-cycle current
limiting is provided in voltage mode and peak current mode. Users can set the switching frequency over a wide
range making this controller suited to both IGBT and MOSFET based designs.
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7.2 Functional Block Diagram
ADEL
14
VDD
VDD
22 OUTA
Thermal
UVLO
Shutdown
comparator
VDD 23
–
+
EN
Reference
Generator
Programmable
Delay AB
6
DELAB
+
–
ON/OFF
7.3-V Rise
6.7-V Fall
VDD
21 OUTB
20 OUTC
VREF
COMP
EA–
1
4
3
2
5-V LDO
PWM
comparator
–
+
–
+
+
EA+
Programmable
Delay CD
7
DELCD
Logic Block
Lower "+" Input
is Dominant
CLK
19 OUTD
13 ADELEF
18 OUTE
RT 10
Oscillator
RAMP
2.8 V
0.8 V
Ramp
Summing
RSUM 11
–
+
CS
Cycle-by-Cycle
ILIM
CS 15
Programmable
Delay EF
8
DELEF
Synchronization
Block
+
–
CS
Light-Load
Efficiency Block
Soft-start and Enable with 0.55-V
Threshold
17 OUTF
2 V
16
24
12
9
5
SYNC
GND
DCM
TMIN
SS/EN
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7.3 Feature Description
7.3.1 Start-Up Protection Logic
Before the UCC28951 controller will start up, the following conditions must be met:
• VDD voltage exceeds rising UVLO threshold 7.3-V typical.
• The 5-V reference voltage is available.
• Junction temperature is below the thermal shutdown threshold of 140°C.
• The voltage on the soft-start capacitor is not below 0.55-V typical.
If all those conditions are met, an internal enable signal EN is generated that initiates the soft-start process. The
duty cycle during the soft start is defined by the voltage at the SS pin, and cannot be lower than the duty cycle
set by TMIN, or by cycle-by-cycle current limit circuit depending on load conditions.
7.3.2 Voltage Reference (VREF)
The accurate (±1.5%) 5-V reference voltage regulator with a short-circuit protection circuit supplies internal
circuitry and provides up to 20-mA external output current. Place a low ESR and ESL, preferably ceramic
decoupling capacitor CREF in 1-µF to 2.2-µF range from this pin to GND as close to the related pins as possible
for best performance. The only condition where the reference regulator is shut down internally is during
undervoltage lockout.
7.3.3 Error Amplifier (EA+, EA–, COMP)
The error amplifier has two uncommitted inputs, EA+ and EA–, with a 3-MHz unity gain bandwidth, which allows
flexibility in closing the feedback loop. The EA+ is a noninverting input, the EA– is an inverting input and the
COMP is the output of the error amplifier. The input voltage common-mode range, where the parameters of the
error amplifier are ensured, is from 0.5 V to 3.6 V. The output of the error amplifier is connected internally to the
noninverting input of the PWM comparator. The range of the error amplifier output of 0.25 V to 4.25 V far
exceeds the PWM comparator input ramp-signal range, which is from 0.8 V to 2.8 V. The soft-start signal serves
as an additional noninverting input of the error amplifier. The lower of the two noninverting inputs of the error
amplifier is the dominant input and sets the duty cycle where the output signal of the error amplifier is compared
with the internal ramp at the inputs of the PWM comparator.
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7.3.4 Soft-Start and Enable (SS/EN)
The soft-start pin (SS/EN) is a multi-function pin used for the following operations:
• Closed-loop soft start with the gradual duty cycle increase from the minimum set by TMIN up to the steady-
state duty cycle required by the regulated output voltage.
• Setting hiccup mode conditions during cycle-by-cycle overcurrent limit.
• On/off control for the converter.
During the soft-start sequence, one of the voltages at the SS/EN or EA+ pins, whichever is lower (SS/EN –0.55
V) or EA+ voltage (see 节 7.2), sets the reference voltage for a closed feedback loop. Both SS/EN and EA+
signals are noninverting inputs of the error amplifier with the COMP pin being its output. Thus the soft-start time
always goes under the closed feedback loop and the voltage at COMP pin sets the duty cycle. The duty cycle
defined by the COMP pin voltage can not be shorter than TMIN pulse width set by the user. However, if the
shortest duty cycle is set by the cycle-by-cycle current limit circuit, then it becomes dominant over the duty cycle
defined by the COMP pin voltage or by the TMIN block.
The soft-start duration is defined by an external capacitor CSS, connected between the SS/EN pin and ground,
and the internal charge current that has a typical value of 25 µA. Pulling the soft-start pin externally below 0.55 V
shuts down the controller. The release of the soft-start pin enables the controller to start, and if there is no
current limit condition, the duty cycle applied to the output inductor gradually increases until it reaches the
steady-state duty cycle defined by the regulated output voltage of the converter. This increase happens when
the voltage at the SS/EN pin reaches and then exceeds by 0.55 V, the voltage at the EA+ pin. Thus for the given
soft-start time TSS, the CSS value can be defined by 方程式1 or 方程式2:
T
× 25 µA
SS
0.55 + V
C
=
(1)
(2)
SS leader
EA +
T
× 25 µA
SS
C
=
SS follower
20.6
20.6 − 0.55 − V
825 kΩ × ln
EA +
For example, in 方程式1, if the soft-start time TSS is 10 ms, and the EA+ pin is 2.5 V, then the soft-start capacitor
CSS is equal to 82 nF.
备注
If the converter is configured to operate in follower mode, connect a 825-kΩ (±5%) resistor from the
SS pin to ground.
7.3.5 Light-Load Power Saving Features
The UCC28951 offers four different light-load management techniques for improving the efficiency of a power
converter over a wide load current range.
1. Adaptive Delay,
a. ADEL, which sets and optimizes the dead-time control for the primary switches over a wide load current
range.
b. ADELEF, which sets and optimizes the delay-time control between the primary side switches and the
secondary side switches.
2. TMIN, sets the minimum pulse width as long as the part is not in current limit mode.
3. Dynamic synchronous rectifier on/off control in DCM Mode, For increased efficiency at light loads. The DCM
Mode starts when the voltage at CS pin is lower than the threshold set by the user. In DCM Mode, the
synchronous output drive signals OUTE and OUTF are brought down low.
4. Burst Mode, for maximum efficiency at very light loads or no load. Burst Mode has an even number of PWM
TMIN pulses followed by off time. Transition to the Burst Mode is defined by the TMIN duration set by the
user.
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7.3.6 Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
The resistor RAB from the DELAB pin, DELAB to GND, along with the resistor divider RAHI from CS pin to ADEL
pin and RA from ADEL pin to GND sets the delay TABSET between one of outputs OUTA or OUTB going low and
the other output going high 图 7-1. The total resistance of this resistor divider should be in the range between 10
kΩand 20 kΩ
TABSET2
TCDSET2
TABSET2
TCDSET2
OUTA
(OUTC)
TABSET1
TCDSET1
TABSET1
TCDSET1
OUTB
(OUTD)
图7-1. Delay Definitions Between OUTA and OUTB, OUTC and OUTD
This delay gradually increases as a function of the CS signal from TABSET1, which is measured at VCS = 1.8 V, to
TABSET2, which is measured at the VCS = 0.2 V. This approach ensures there will be no shoot-through current
during the high-side and low-side MOSFET switching and optimizes the delay for acheiving ZVS condition over a
wide load current range. The ratio between the longest and shortest delays is set by the resistor divider RAHI and
RA. The maximum ratio is achieved by tying the CS and ADEL pins together. If ADEL is connected to GND, then
the delay is fixed, defined only by the resistor RAB from DELAB to GND. The delay TCDSET1 and TCDSET2 settings
and their behaviour for outputs OUTC and OUTD are very similar to the one described for OUTA and OUTB. The
difference is that resistor RCD connected between DELCD pin and GND sets the delay TCDSET. The ratio
between the longest and shortest delays is set by the resistor divider RAHI and RA.
The delay time TABSET is defined by the following 方程式3.
æ
ç
è
ö
÷
ø
5 ´ RAB
TABSET
=
ns
0.26V + CS ´ KA ´ 1.3
(3)
where
• RAB is in kΩ
• CS is the voltage at the CS pin in Volts
• KA is a numerical coefficient in the range from 0 to 1
• the delay time TABSET is in ns and is measured at the IC pins
The same equation is used to define the delay time TCDSET in another leg, except RAB is replaced by RCD (see
方程式4).
æ
ç
è
ö
÷
ø
5 ´ RCD
TCDSET
=
ns
0.26V + CS ´ KA ´ 1.3
(4)
where
• RCD is in kΩ
• CS is the voltage at the CS pin in Volts
• KA is a numerical coefficient in the range from 0 to 1
• the delay time TCDSET is in ns and is measured at the IC pins
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These equations are empirical and they are approximated from measured data. Thus, there is no unit agreement
in the equations. As an example, assume RAB = 15 kΩ, CS = 1 V and KA = 0.5. Then the TABSET is
approximately 90 ns.
In both 方程式3 and 方程式4, KA is the same and is defined as 方程式5:
RA
KA =
RA + RAHI
(5)
KA sets how the delay varies with the CS pin voltage as shown in 图7-2 and 图7-3.
TI recommends starting by setting KA = 0 and set TABSET and TCDSET relatively large using equations or plots in
this data sheet to avoid hard switching or even shoot through current. The delay between outputs A, B and C, D
set by resistors RAB and RCD accordingly. Program the optimal delays at light load first. Then by changing KA set
the optimal delay for the outputs A, B at maximum current. KA for outputs C, D is the same as for A, B. Usually
outputs C, D always have ZVS if sufficient delay is provided.
备注
The allowed resistor range on DELAB and DELCD, RAB and RCD is 13 kΩ to 90 kΩ.
RA and RAHI define the portion of voltage at pin CS applied to the pin ADEL (see 图 8-3). KA defines how
significantly the delay time depends on CS voltage. KA varies from 0, where ADEL pin is shorted to ground (RA =
0) and the delay does not depend on CS voltage, to 1, where ADEL is tied to CS (RAHI = 0). Setting KA, RAB, and
RCD provides the ability to maintain optimal ZVS conditions of primary switches over load current because the
voltage at CS pin includes the load current reflected to the primary side through the current-sensing circuit. The
plots in 图 7-2 and 图 7-3 show the delay time settings as a function of CS voltage and KA for two different
conditions: RAB = RCD = 13 kΩ(图7-2) and RAB = RCD = 90 kΩ(图7-3).
350
300
250
200
150
100
50
2000
1800
1600
1400
1200
1000
800
KA = 0
KA = 0
KA = 0.1
KA = 0.25
KA = 0.5
KA = 0.75
KA = 1
KA = 0.1
KA = 0.25
KA = 0.5
KA = 0.75
KA = 1
600
400
200
0
0
0
0.5
1
CS Voltage - V
1.5
2
0
0.2 0.4 0.6 0.8
1
CS Voltage - V
1.2 1.4 1.6 1.8
2
G001
G001
图7-3. Delay Time set TABSET and TCDSET (Over CS
Voltage Variation and Selected KA for RAB and RCD
Equal 90 kΩ)
图7-2. Delay Time Set TABSET and TCDSET (Over CS
Voltage Variation and selected KA for RAB and RCD
Equal 13 kΩ)
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7.3.7 Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
The resistor REF from the DELEF pin to GND along with the resistor divider RAEFHI from CS pin to ADELEF pin
and RAEF from ADELEF pin to GND sets equal delays TAFSET and TBESET between outputs OUTA or OUTB
going low and related output OUTF or OUTE going low 图 7-4. The total resistance of this resistor divider should
be in the range between 10 kΩand 20 kΩ.
OUTA
(OUTB)
OUTD
(OUTC)
TAFSET1
TBESET1
OUTF
(OUTE)
TAFSET2
TBESET2
图7-4. Delay Definitions Between OUTA and OUTF, OUTB and OUTE
These delays gradually increase as function of the CS signal from TAFSET1, which is measured at VCS = 0.2 V, to
TAFSET2, which is measured at VCS = 1.8 V. This is opposite to the DELAB and DELCD behavior and this delay is
longest (TAFSET2) when the signal at CS pin is maximized and shortest (TAFSET1) when the CS signal is
minimized. This approach will reduce the synchronous rectifier MOSFET body diode conduction time over a wide
load current range thus improving efficiency. The ratio between the longest and shortest delays is set by the
resistor divider RAEFHI and RAEF. If CS and ADELEF are tied, the ratio is maximized. If ADELEF is connected to
GND, then the delay is fixed, defined only by resistor REF from DELEF to GND.
The delay time TAFSET is defined by the following 方程式6. 方程式6 also defines the delay time TBESET
.
æ
ö
æ
ç
è
ö
÷
ø
5´REF
TAFSET
=
ns + 4ns
ç
÷
ç
÷
2.65V - CS´KEF ´1.32
è
ø
(6)
where
• REF is in kΩ
• the CS, which is the voltage at pin CS, is in volts
• KEF is a numerical gain factor of CS voltage from 0 to 1
• the delay time TAFSET is in ns and is measured at the IC pins
方程式 6 is an empirical approximation of measured data, thus, there is no unit agreement in it. As an example,
assume REF = 15 kΩ, CS = 1 V and KEF = 0.5. Then the TAFSET is going to be 41.7 ns. KEF is defined as 方程式
7:
RAEF
KEF
=
RAEF + RAEF(hi)
(7)
RAEF and RAEFHI define the portion of voltage at pin CS applied to the pin ADELEF (see 图8-3). KEF defines how
significantly the delay time depends on CS voltage. KEF varies from 0, where ADELEF pin is shorted to ground
(RAEF = 0) and the delay does not depend on CS voltage, to 1, where ADELEF is tied to CS (RAEFHI = 0).
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备注
The allowed resistor range on DELEF, REF is 13 kΩto 90 kΩ.
The plots in 图 7-5 and 图 7-6 show delay time settings as function of CS voltage and KEF for two different
conditions: REF = 13 kΩ(图7-5) and REF = 90kΩ(图7-6)
350
300
250
200
150
100
50
2000
1800
1600
1400
1200
1000
800
KA = 0
KA = 0
KA = 2.5
KA = 0.5
KA = 0.75
KA = 0.9
KA = 1
KA = 2.5
KA = 0.5
KA = 0.75
KA = 0.9
KA = 1
600
400
200
0
0
0
0.2
0.4
0.6
0.8
CS Voltage (V)
1
1.2
1.4
1.6
1.8
0
0.2
0.4
0.6
0.8
CS Voltage (V)
1
1.2
1.4
1.6
1.8
D007
D008
图7-5. Delay Time TAFSET and TBESET (Over CS
Voltage and Selected KEF for REF Equal 13 kΩ)
图7-6. Delay Time TAFSET and TBESET (Over CS
Voltage and Selected KEF for REF Equal 90 kΩ)
7.3.8 Minimum Pulse (TMIN)
The resistor RTMIN from the TMIN pin to GND sets a fixed minimum pulse width. This pulse is applied to the
transformer and enables ZVS at light load. If the output PWM pulse demanded by the feedback loop is shorter
than TMIN, then the controller proceeds to burst mode operation where an even number of TMIN pulses are
followed by the off time dictated by the feedback loop. The proper selection of the TMIN duration is dictated by
the time it takes to raise sufficient magnetizing current in the power transformer to maintain ZVS. The TMIN
pulse is measured from the rising edge of OUTA to the falling edge of OUTD – or from the rising edge of OUTB
to the falling edge of OUTC. The minimum pulse TMIN is then defined by 方程式8.
TMIN = 5.92´R
(
ns
)
TMIN
(8)
where
• TMIN is in ns
• RTMIN is in kΩ
Various propagation and response time delays in the power circuit modify (usually increase) the pulse width that
is measured at the transformer. Select the correct TMIN setting using an iterative process due to the propagation
and response time delays in the power circuit.
备注
The minimum allowed resistance on the TMIN pin, RTMIN is 10 kΩ.
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The related plot is shown in 图7-7.
800
700
600
500
400
300
200
100
0
0
20
40
60
80
100
120
140
RTMIN (kW)
D001
图7-7. Minimum Time TMIN Over Setting Resistor RTMIN
The value of minimum duty cycle DMIN is determined by 方程式9.
DMIN = TMIN´FSW(osc) ´10-4
%
(
)
(9)
where
• FSW(osc) is oscillator frequency in kHz
• TMIN is the minimum pulse in ns
• and DMIN is in percent
7.3.9 Burst Mode
If the converter is commanding a duty cycle lower than TMIN, then the controller will go into Burst Mode. The
controller will always deliver an even number of Power cycles to the Power transformer. The controller always
stops its bursts with an OUTB and an OUTC power delivery cycle. If the controller is still demanding a duty cycle
less than TMIN, then the controller goes into shut down mode. Then it waits until the converter is demanding a
duty cycle equal or higher than TMIN before the controller puts out TMIN or a PWM duty cycle as dictated by
COMP voltage pin.
7.3.10 Switching Frequency Setting
Connecting an external resistor RT between the RT pin and VREF pins sets the fixed frequency operation and
configures the controller as a leader providing synchronization output pulses at SYNC pin with 0.5 duty cycle and
frequency equal to the internal oscillator. Connect an external resistor RT between the RT and GND pins to
configure the controller as a follower. When the controller is used in follower mode, connect a 825 kΩ ±5%
resistor from the SS pin to the ground pin in parallel with the SS_EN capacitor. The follower controller operates
with 90° phase shift relative to the leader converter if their SYNC pins are tied together. The switching frequency
of the converter is equal to the frequency of output pulses.
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方程式 10 defines the nominal switching frequency of the converter configured as a leader (resistor RT between
the RT pin and VREF). On the UCC28951 there is an internal clock oscillator frequency which is twice as that of
the controller's output frequency.
æ
ç
ç
ç
ö
÷
÷
÷
2.5´103
RT
VREF - 2.5V
F
=
kHz
SW(nom)
æ
ç
è
ö
÷
ø
kW
+1´
ç
÷
ç
÷
V
è
ø
(10)
where
• RT is in kΩ
• VREF is in volts
• FSW(nom) is in kHz
This is also an empirical approximation and thus, there is no unit agreement. Assume for example, VREF = 5 V,
RT = 65 kΩ. Then the switching frequency FSW(nom) is going to be 92.6 kHz.
方程式 11 defines the nominal switching frequency of converter if the converter configured as a follower and the
resistor RT is connected between the RT pin and GND.
æ
ç
ç
ç
ç
è
ö
÷
÷
÷
÷
ø
2.5´103
RT
F
=
kHz
SW(nom)
æ
ö
kW
+1´
ç
÷
2.5V
V
è
ø
(11)
where
• RT is in kΩ
• FSW(nom) is in kHz
Notice that for VREF = 5 V, 方程式10 and 方程式11 yield the same results.
The plot in 图7-8 shows how FSW(nom) depends on the resistor RT value when the VREF = 5 V. As it is seen from
方程式 10 and 方程式 11, the switching frequency FSW(nom) is set to the same value for either leader or follower
configuration provided the same resistor value RT is used.
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1000
900
800
700
600
500
400
300
200
100
0
25
5
15
35 45 55 65 75 85 95 105 115 125
RT - Resistor - kΩ
图7-8. Converter Switching Frequency FSW(nom) Over Resistor RT Value
7.3.11 Slope Compensation (RSUM
)
Slope compensation prevents a sub-harmonic oscillation in the controller during in peak current mode (PCM)
control operation or during cycle-by-cycle current limit at duty cycles above 50% (some publications suggest it
may happen at D < 50%). Slope compensation in the controller adds an additional ramp signal to the CS signal
and is applied to:
• the PWM comparator in the case of peak current mode control
• the input of the cycle-by-cycle comparator
At low duty cycles and light loads, the slope compensation ramp reduces the noise sensitivity during peak
current mode control operation.
Placing a resistor from the RSUM pin to ground allows the controller to operate in PCM control. Connecting a
resistor from RSUM to VREF switches the controller to voltage mode control (VMC) with the internal PWM ramp.
In VMC the resistor at RSUM provides CS signal slope compensation for operation in cycle-by-cycle current limit.
That is, in VMC, the slope compensation is applied only to the cycle-by-cycle comparator while in PCM the slope
compensation is applied to both the PWM and cycle-by-cycle current limit comparators. The operation logic of
the slope compensation circuit is shown in 图7-9.
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COMP
4
+
Oscillator
0.85 V
VREF VCM
CLK
PCM
Ramp
Generator
VMC
RAMP
Cycle-by-Cycle ILIM
RSUM
Two Direction
Current Sense
Ramp
Summing
CS_SLOPECOMP
11
+
+
-
CS 15
2 V
Mode Select
GND PCM
7
GND
图7-9. The Operation Logic of Slope Compensation Circuit
Too much slope compensation reduces the benefits of PCM control. In the case of cycle-by-cycle current limit,
the average current limit becomes lower and this might reduce the start-up capability into large output
capacitances.
The optimum compensation ramp varies, depending on duty cycle, LOUT and LMAG. A good starting point in
selecting the amount of slope compensation is to set the slope compensation ramp to be half the inductor
current ramp downslope (inductor current ramp during the off time). The inductor current ramp downslope (as
seen at the CS pin input, and neglecting the effects of any filtering at the CS pin) is calculated in 方程式12:
V
L
R
OUT
CS
a1 × CT
m =
×
(12)
o
OUT
RAT
where
• VOUT is the output voltage of the converter
• LOUT is the output inductor value
• a1 is the transformer turns ratio (NP/NS)
• CTRAT is the current transformer ratio (IP/IS, typically 100:1)
Selection of LOUT, a1 and CTRAT are described later in this document. The total slope compensation is 0.5 m0.
Some of this ramp is due to magnetizing current in the transformer, the rest is added by an appropriately chosen
resistor from RSUM to ground.
The slope of the additional ramp, me, added to the CS signal by placing a resistor from RSUM to ground is
defined by 方程式13.
æ
ç
è
ö
÷
2.5
V
me =
0.5´RSUM ms
ø
(13)
where
• RSUM is in kΩ
• me is in V/μs
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If the resistor from the RSUM pin is connected to the VREF pin, then the controller operates in voltage mode
control, still having the slope compensation ramp added to the CS signal used for cycle-by-cycle current limit. In
this case the slope is defined by 方程式14.
æ
ç
è
ö
÷
ø
(VREF - 2.5V)
0.5´RSUM
V
me =
ms
(14)
where
• VREF is in volts
• RSUM is in kΩ
• me is in V/μs
These are empirically derived equations without units agreement. As an example, substituting VREF = 5 V and
RSUM = 40 kΩ, yields the result 0.125 V/μs. The related plot of me as a function of RSUM is shown in 图 7-10,
Because VREF = 5 V, the plots generated from 方程式13 and 方程式14 coincide.
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
5
20 40 60 80 100 120 140 160 180 200
Rsum - Resistor - kΩ
图7-10. Slope of the Added Ramp Over Resistor RSUM
备注
The recommended resistor range for RSUM is 10 kΩto 1 MΩ.
7.3.12 Dynamic SR ON/OFF Control (DCM Mode)
The voltage at the DCM pin provided by the resistor divider RDCMHI between VREF pin and DCM, and RDCM from
DCM pin to GND, sets the percentage of 2-V current limit threshold for the Current Sense pin, (CS). If the CS pin
voltage falls below the DCM pin threshold voltage, then the controller initiates the light load power saving mode,
and shuts down the synchronous rectifiers, OUTE and OUTF. If the CS pin voltage is higher than the DCM pin
threshold voltage, then the controller runs in CCM mode. Connecting the DCM pin to VREF makes the controller
run in DCM mode and shuts both Outputs OUTE and OUTF. Shorting the DCM pin to GND disables the DCM
feature and the controller runs in CCM mode under all conditions.
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VREF
1
20 mA
RDCM(hi)
PWM
R = 77 kW
CS
DCM_COMP
+
2-Cycle
Counter
15
12
R = 77 kW
DCM
0 = DCM
1 = CCM
C = 6.5 pF
RDCM
C = 6.5 pF
Other Blocks
图7-11. DCM Functional Block
Moving into
DCM Mode
0.8
VS(max)
0.6
VS(min)
0.4
0.2
TMIN Setting
Burst Mode
Area
0
0
1
2
3
4
5
6
7
8
9
10
Load Current - A
图7-12. Duty Cycle Change Over Load Current Change
A nominal 20-µA switched current source is used to create hysteresis. The current source is active only when
the system is in DCM Mode. Otherwise, it is inactive and does not affect the node voltage. Therefore, when in
the DCM region, the DCM threshold is the voltage divider plus ΔV explained in 方程式 15. When in the CCM
region, the threshold is the voltage set by the resistor divider. When the CS pin reaches the threshold set on the
DCM pin, the system waits to see two consecutive falling edge PWM cycles before switching from CCM to DCM
and vice-versa. The magnitude of the hysteresis is a function of the external resistor divider impedance. The
hysteresis can be calculated using 方程式15:
RDCMHI ´RDCM
DV = 2´10-5
RDCMHI + RDCM
(15)
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PWM
DCM Threshold
+ Hysteresis
CS
E
F
图7-13. Moving From DCM to CCM Mode
PWM
DCM Threshold
+ Hysteresis
CS
E
F
图7-14. Moving From CCM to DCM Mode
DCM must be used to prevent reverse current in the output inductor which could cause the synchronous FETS
to fail.
The controller must switch to DCM mode at a level where the output inductor current is positive. If the output
inductor current is negative when the controller switches to DCM mode then the synchronous FETs will see a
large VDS spike and may fail.
7.3.13 Current Sensing (CS)
The signal from the current sense pin is used for cycle-by-cycle current limit, peak-current mode control, light-
load efficiency management and setting the delay time for outputs OUTA, OUTB, OUTC, OUTD and delay time
for outputs OUTE, OUTF. Connect the current sense resistor RCS between CS and GND. Depending on layout,
to prevent a potential electrical noise interference, TI recommends pulling a small R-C filter between the RCS
resistor and the CS pin. There is a 200-Ω pulldown at the CS pin which is turned on after the PWM comparator
has tripped. This helps to reset the CS signal prior to the following switching cycle.
7.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
The cycle-by-cycle current limit provides peak current limiting on the primary side of the converter when the load
current exceeds its predetermined threshold. For peak current mode control, a certain leading edge blanking
time is needed to prevent the controller from false tripping due to switching noise. An internal 30-ns filter at the
CS input is provided. The total propagation delay TCS from CS pin to outputs is 100 ns. An external RC filter is
still needed if the power stage requires more blanking time. The 2.0-V ±3% cycle-by-cycle current limit threshold
is optimized for efficient current transformer based sensing. The duration when a converter operates at cycle-by-
cycle current limit depends on the value of soft-start capacitor and how severe the overcurrent condition is. This
is achieved by the internal discharge current IDS 方程式16 and 方程式17 at SS pin.
I
= −25 × 1 − D + 5 µA
(16)
DS leader
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I
= −25 × 1 − D µA
(17)
DS follower
The soft-start capacitor value also determines the so-called hiccup mode off-time duration. The behavior of the
converter during different modes of operation, along with related soft-start capacitor charge and discharge
currents are shown in 图7-15.
Cycle-by-Cycle ILIM
SS Pin (V)
Normal
Operation
Soft Start
.
OFF Time Before Restart
SS Clamp Voltage
Pull Up Threshold
4.65
25 mA
Soft Restart
3.70
3.60
Fast Pull Up
by 1 kW Switch
IDS = (-25 x (1-D)+5) mA
IHCC = 2.5 mA
ISS=25 mA
Output Enable
Threshold
0.55
0.00
Output Pulses (D)
图7-15. Timing Diagram of Soft-Start Voltage VSS
The largest discharge current of 20 µA is when the duty cycle is close to zero. This current sets the shortest
operation time during the cycle-by-cycle current limit and is defined in 方程式18 and 方程式19
C
× 4.65 V − 3.7 V
SS
T
T
=
(18)
(19)
CL on_leader
20 µA
C
× 4.65 V − 3.7 V
SS
=
CL on_follower
25 µA
Thus, if the soft-start capacitor CSS = 100 nF is selected, then the TCL(on) time is 5 ms.
To calculate the hiccup off time TCL(off) before the restart, use 方程式20 or 方程式21.
C
× 4.65 V − 3.7 V
SS
T
T
=
(20)
(21)
CL off_leader
2.5 µA
C
× 4.65 V − 3.7 V
SS
=
CL off_follower
2.5 µA
With the same soft-start capacitor value at 100 nF, the off-time before the restart is 122 ms. If the overcurrent
condition occurs before the soft-start capacitor voltage reaches the 3.7-V threshold during start-up, the controller
limits the current but the soft-start capacitor continues to be charged. As soon as the 3.7-V threshold is reached,
the soft-start voltage is quickly pulled up to the 4.65-V threshold by an internal 1-kΩ RDS(on) switch and the
cycle-by-cycle current limit duration timing starts by discharging the soft-start capacitor. Depending on specific
design requirements, the user can override this default behavior by applying external charge or discharge
currents to the soft-start capacitor. The whole cycle-by-cycle current limit and hiccup operation is shown in 图
7-15. In this example, the cycle-by-cycle current limit lasts about 5 ms followed by 122 ms of off-time.
Similarly to the overcurrent condition, the hiccup mode with the restart can be disabled by the user if a pullup
resistor of 261 k Ω is connected between the SS and VREF pins. The controller remains in the latch-off mode if
an overcurrent condition occurs. In this case, calculate an external soft-start capacitor value with the additional
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pullup current taken into account. The latch-off mode can be reset externally if the soft-start capacitor is forcibly
discharged below 0.55 V or the VDD voltage is lowered below the UVLO threshold.
7.3.15 Synchronization (SYNC)
The UCC28951 allows flexible configuration of converters operating in synchronized mode by connecting all
SYNC pins together and by configuration of the controllers as leader and/or followers. The controller configured
as leader (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency
equal to 2X the converter frequency FSW(nom) and 0.5 duty cycle. The controller configured as a follower (resistor
between RT and GND and 825-kΩresistor between SS_EN pin to GND) does not generate the synchronization
pulses. The follower controller synchronizes its own clock to the falling edge of the synchronization signal thus
operating 90° phase shifted versus the leader converter’s frequency FSW(nom)
.
The output inductor in a full bridge converter sees a switching frequency which is twice that seen by the
transformer. In the case of the UCC28951 this means that the output inductor operates at 2 × FSW(nom). This
means that the 90° phase shift between leader and follower controllers gives a 180° phase shift between the
currents in the output inductors and hence maximum ripple cancellation. For more information about
synchronizing more than two UCC28951 devices, see Synchronizing Three or More UCC28950 Phase-Shifted,
Full-Bridge Controllers (SLUA609).
If the synchronization feature is not used then the SYNC pin may be left floating, but connecting the SYNC pin to
GND through a 10-kΩ resistor will reduce noise pickup and switching frequency jitter.
• If any converter is configured as a follower, the SYNC frequency must be greater than or equal to 1.8 times
the converter frequency.
• follower converter does not start until at least one synchronization pulse has been received.
• If any or all converters are configured as followers, then each converter operates at its own frequency without
synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of
synchronization pulses at the follower converter, then the controller uses its own internal clock pulses to
maintain operation based on the RT value that is connected to GND in the follower converter.
• In leader mode, SYNC pulses start after SS pin passes its enable threshold which is 0.55 V.
• follower starts generating SS/EN voltage even though synchronization pulses have not been received.
• TI recommends that the SS on the leader controller starts before the SS on the follower controller; therefore
SS/EN pin on leader converter must reach its enable threshold voltage before SS/EN on the follower
converter starts for proper operation. On the same note, TI also recommends that the TMIN resistors on both
leader and follower are set at the same value.
CLK
SYNC_OUT
A
B
图7-16. SYNC_OUT (leader Mode) Timing Diagram
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SYNC_IN
CLK
A
B
图7-17. SYNC_IN (follower Mode) Timing Diagram
7.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
• All MOSFET control outputs have 0.2-A drive capability.
• The control outputs are configured as P-MOS and N-MOS totem poles with typical RDS(on) 20 Ωand 10 Ω,
accordingly.
• The control outputs are capable of charging 100-pF capacitor within 12 ns and discharge within 8 ns.
• The amplitude of output control pulses is equal to VDD
.
• Control outputs are designed to be used with external gate MOSFET/IGBT drivers.
• The design is optimized to prevent the latch-up of outputs and verified by extensive tests.
The UCC28951 controler has outputs OUTA, OUTB driving the active leg, initiating the duty cycle leg of power
MOSFETs in a phase-shifted full bridge power stage, and outputs OUTC, OUTD driving the passive leg,
completing the duty cycle leg, as it is shown in the typical timing diagram in 图 8-1. Outputs OUTE and OUTF
are optimized to drive the synchronous rectifier MOSFETs (see 图 8-3). These outputs have 200-mA peak-
current capabilities and are designed to drive relatively small capacitive loads like inputs of external MOSFET or
IGBT drivers. Recommended load capacitance should not exceed 100 pF. The amplitude of the output signal is
equal to the VDD voltage.
7.3.17 Supply Voltage (VDD)
Connect this pin to a bias supply in the range from 8 V to 17 V. Place high-quality, low ESR and ESL and at least
1-µF ceramic bypass capacitor CVDD from this pin to GND. TI recommends using a 10-Ω resistor in series from
the bias supply to the VDD pin to form an RC filter with the CVDD capacitor.
7.3.18 Ground (GND)
All signals are referenced to this node. TI recommends having a separate quiet analog plane connected in one
place to the power plane. The analog plane connects the components related to the pins VREF, EA+, EA-,
COMP, SS/EN, DELAB, DELCD, DELEF, TMIN, RT, RSUM. The power plane connects the components related
to the pins DCM, ADELEF, ADEL, CS, SYNC, OUTF, OUTE, OUTD, OUTC, OUTB, OUTA, and VDD. 图 7-18
shows an example of layout and ground planes connection.
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CREF
CVDD
R1
R2
1
2
3
4
5
6
7
8
9
VREF
EA+
GND 24
VDD 23
VDD
C1
R3
EA-
OUTA 22
OUTB 21
OUTC 20
OUTD 19
OUTE 18
OUTF 17
SYNC 16
CS 15
A
R4
R6
R5
VSENSE
COMP
SS/EN
DELAB
DELCD
DELEF
TMIN
B
C
D
E
C3
C2
CSS
RAB
ENABLE
RCD
REF
F
Power Plane
SYNC
RT(min)
Analog Plane
10 RT
RT
RAHI
RSUM
11 RSUM
12 DCM
ADEL 14
ADELEF 13
RA
RDCMHI
VREF
RAEFHI
Current Sense
RAEF
R7
RCS
RDCM
图7-18. Layout Recommendation for Analog and Power Planes
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7.4 Device Functional Modes
The UCC28951 offers many operational modes. These modes are described in detail in 节7.3.
• Current mode1. The UCC28951 controller operates in current mode control when the RSUM pin is connected
to GND through a resistor (RSUM) . The resistor sets the amount of slope compensation.
• Voltage mode1. The controller operates in voltage mode control when the RSUM pin is connected to VREF
through a resistor (RSUM). The chosen resistor value gives the correct amount of slope compensation for
operation in current limit mode (cycle-by-cycle current limit).
• DCM mode. The controller enters DCM mode when the signal at the CS pin falls below the level set by the
resistor at the DCM pin. The SR drives (OUTE and OUTF) turn off and secondary rectification occurs through
the body diodes of the SRs.
• Burst mode. The controller enters burst mode when the pulse width demanded by the feedback signal falls
below the width set by the resistor at the TMIN pin.
• Leader mode. This is the default operation mode of the controller and is used when there is only one
UCC28951 controller in the system. Connect the timing resistor (RT) from the RT pin to VREF. In a system
with more than one UCC28951 controller, configure one as the leader and the others as followers1.
• Follower mode. The follower controller operates with a 90° phase shift relative to the leader (providing their
SYNC pins are tied together). Connect the timing resistor (RT) from the RT pin to GND and connect an 825-
kΩ±5% resistor from the SS/EN pin to GND1.
• Synchronized mode. When a UC28950 controller is configured as a follower, its SYNC pin is used as an
input. The follower synchronizes its internal oscillator at 90° to the signal at its SYNC pin. The application
note, Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers, discusses how
multiple follower controllers may be synchronized to a single leader oscillator.
• Hiccup mode. This mode provides overload protection to the power circuit. The UCC28951 controller stops
switching after a certain time in current limit. It starts again (soft-start) after a delay time. The user can control
the time spent in current limit before switching is stopped and the delay time before the soft start happens.
• Current-limit mode. The UCC28951c ontroller provides cycle-by-cycle current limiting when the signal at the
CS pin reaches 2 V.
• Latch-off mode. Connect a resistor between the SS pin and VREF. The UCC28951 controller then latches off
when the controller enterscurrent-limit mode. 1
1
Current mode control and voltage mode control are mutually exclusive as are leader and follower modes.
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8 Application and Implementation
备注
以下应用部分中的信息不属于 TI 元件规格，TI 不担保其准确性和完整性。TI 的客户负责确定元件是否
适合其用途，以及验证和测试其设计实现以确认系统功能。
8.1 Application Information
The high efficiency of a phase-shifted full-bridge DC-DC converter using the UCC28951 is achieved by using
synchronous rectification, a control algorithm providing ZVS condition over the entire load current range,
accurate adaptive timing of the control signals between primary and secondary FETs and special operating
modes at light load. A simplified electrical diagram of this converter is shown in 图 8-3. The UCC28951controller
is located on the secondary side of converter, although it could be placed on the primary side as well. The
secondary side lication allows easy power system level communication and better handling of some transient
conditions that require fast direct control of the synchronous rectifier MOSFETs. The power stage includes
primary side MOSFETs, QA, QB, QC, QD and secondary side synchronous rectifier MOSFETs, QE and QF. For
example, for the 12-V output converters in server power supplies use of the center-tapped rectifier scheme with
L-C output filter is a popular choice.
To maintain high efficiency at different output power conditions, the converter operates in synchronous
rectification mode at mid and high output power levels, transitioning to diode rectifier mode at light load and then
into burst mode as the output power becomes even lower. All of these transitions are based on current sensing
on the primary side using a current sense transformer in this specific case.
The major waveforms of the phase-shifted converter during normal operation are shown in 图 8-1. The upper six
waveforms in 图 8-1 show the output drive signals of the controller. In normal mode, the outputs OUTE and
OUTF overlap during the part of the switching cycle when both rectifier MOSFETs are conducting and the
windings of the power transformer are shorted. Current, IPR, is the current flowing through the primary winding of
the power transformer. The bottom four waveforms show the drain-source voltages of rectifier MOSFETs, VDS_QE
and VDS_QF, the voltage at the output inductor, V LOUT, and the current through the output inductor, I LOUT
.
Proper timing between the primary switches and synchronous rectifier MOSFETs is critical to achieve highest
efficiency and reliable operation in this mode. The controller adjusts the turn OFF timing of the rectifier
MOSFETs as a function of load current to ensure minimum conduction time and reverse recovery losses of their
internal body diodes.
ZVS is an important feature of relatively high input voltage converters in reducing switching losses associated
with the internal parasitic capacitances of power switches and transformers. The controller ensures ZVS
conditions over the entire load current range by adjusting the delay time between the primary MOSFETs
switching in the same leg in accordance to the load variation. The controller also limits the minimum ON-time
pulse applied to the power transformer at light load, allowing the storage of sufficient energy in the inductive
components of the power stage for the ZVS transition.
As the load current reduces from full load down to the no-load condition, the controller selects the most efficient
power saving mode by moving from the normal operation mode to the discontinuous-current diode-rectification
mode and, eventually, at very light-load and at no-load condition, to the burst mode. These modes and related
output signals, OUTE, OUTF, driving the rectifier MOSFETs, are shown in 图8-2.
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T
SW(nom)
T
ABSET2
OUTA
OUTB
OUTC
T
ABSET1
T
SW(osc)
T
CDSET2
T
CDSET1
OUTD
I
PR
V
x(1-D) /D
OUT
OUT
V
I
LOUT
V
LOUT
I
OUT
图8-1. Phase-Shifted Converter Waveforms
OUTE
(CCM Mode)
OUTF
(CCM Mode)
OUTE and OUTF are disabled if VCS < VDCM
OUTE and OUTF are disabled if VCS < VDCM
OUTE
OUTF
Burst Mode at light load with TMIN maintaining ZVS
(The time scale is different versus above diagram)
Transformer
Winding
Magnetizing
Current
图8-2. Major Waveforms During Transitions Between Different Operating Modes
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It is necessary to prevent the reverse current flow through the synchronous rectifier MOSFETs and output
inductor at light load, during parallel operation and at some transient conditions. Such reverse current results in
circulating of some extra energy between the input voltage source and the load and, therefore, causes increased
losses and reduced efficiency. Another negative effect of such reverse current is the loss of ZVS condition. The
suggested control algorithm prevents reverse current flow, still maintaining most of the benefits of synchronous
rectification by switching off the drive signals of rectifier MOSFETs in a predetermined way. At some pre-
determined load current threshold, the controller disables outputs OUTE and OUTF by bringing them down to
zero.
Synchronous rectification using MOSFETs requires some electrical energy to drive the MOSFETs. There is a
condition below some light-load threshold when the MOSFET drive related losses exceed the saving provided by
the synchronous rectification. At such light load, it is best to disable the drive circuit and use the internal body
diodes of rectifier MOSFETs, or external diodes in parallel with the MOSFETs, for more efficient rectification. In
most practical cases, the drive circuit needs to be disabled close to DCM mode. This mode of operation is called
discontinuous-current diode-rectification mode.
At very light-load and no-load conditions, the duty cycle, demanded by the closed-feedback-loop control circuit
for output voltage regulation, can be very low. This level leads to the loss of ZVS condition and increased
switching losses. To avoid the loss of ZVS, the control circuit limits the minimum ON-time pulse applied to the
power transformer using resistor from TMIN pin to GND. Therefore, the only way to maintain regulation at very
light load and at no-load condition is to skip some pulses. The controller skips pulses in a controllable manner to
avoid saturation of the power transformer. Such operation is called burst mode. In Burst Mode there are always
an even number of pulses applied to the power transformer before the skipping off time. Thus, the flux in the
core of the power transformer always starts from the same point during the start of every burst of pulses.
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8.2 Typical Application
A typical application for the UCC28951 is a controller for a phase-shifted full-bridge converter that converts a 390-VDC input to a regulated 12-V output
using synchronous rectifiers to achieve high efficiency.
+
CT
VBIAS
VIN
CIN
CREF
R1
R2
RLF2
1
2
3
4
5
6
7
8
9
VREF
EA+
GND 24
VDD 23
VDD
œ
CVDD
R3
EA-
OUTA 22
OUTB 21
OUTC 20
OUTD 19
OUTE 18
OUTF 17
SYNC 16
CS 15
A
VDD
VDD
C1
R5
VSENSE
COMP
SS/EN
DELAB
DELCD
DELEF
TMIN
B
QA
QC
C2
A
C
R4
R6
C3
T1
NP
CSS
RAB
C
D
NS
NS
ENABLE
VDD
VDD
RCD
REF
E
QB
LOUT
QD
F
B
D
RTMIN
SYNC
VOUT
RAHI
RT
VREF
10 RT
+
RSUM
UCC27324
UCC27324
QF
11 RSUM
12 DCM
ADEL 14
ADELEF 13
RAEFHI
QE
RDCMHI
E
F
COUT
VREF
RA
œ
RAEF
DA
RLF1
CLF
RDCM
RCS
R7
VSENSE
图8-3. Typical Application
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8.2.1 Design Requirements
表8-1 lists the requirements for this application.
表8-1. UCC28951 Typical Application Design Requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
VIN
DC input voltage range
Maximum input current
370
390
410
2
V
A
IIN(max)
VIN= 370 VDC to 410 VDC
OUTPUT CHARACTERISTICS
VOUT
IOUT
Output voltage
VIN= 370 VDC to 410 VDC
11.4
12
12.6
50
V
Output current
VIN= 370 VDC to 410 VDC
A
Output voltage transient
Continuous output power
Load regulation
90% load step
600
mV
W
POUT
VIN= 370 VDC to 410 VDC
600
140
140
200
VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A
VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A
VIN = 370 VDC to 410 VDC, IOUT= 5 A to 50 A
mV
mV
mV
Line regulation
Output ripple voltage
SYSTEM
FSW
Switching Frequency
Full-load efficiency
100
kHz
VIN= 370 VDC to 410 VDC, POUT= 500 W
93%
94%
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8.2.2 Detailed Design Procedure
In high-power server applications to meet high-efficiency and green standards some power-supply designers
have found it easier to use a phase-shifted, full-bridge converter. This is because the phase-shifted, full-bridge
converter can obtain zero-voltage switching on the primary side of the converter, reducing switching losses, and
EMI and increasing overall efficiency.
This is a review of the design of a 600-W, phase-shifted, full-bridge converter for one of these power systems
using the UCC28951 device, which is based on typical values. In a production design, the values may need to
be modified for worst-case conditions. TI has provided a MathCAD Design Tool and an Excel Design Tool to
support the system designer. Both tools can be accessed in the Tools and Software tab of the UCC28951
product folder on TI.com, or can be downloaded through the following links: MathCAD Design Tool, Excel Design
Tool.
备注
The term fSW refers to the switching frequency applied to the power transformer. The output inductor
experiences a switching frequency that is 2 × fSW
.
8.2.2.1 Power Loss Budget
To meet the efficiency goal, a power loss budget must be set (see 方程式22).
æ
ç
è
ö
÷
ø
1- h
P
= POUT
´
» 45.2W
BUDGET
h
(22)
(23)
8.2.2.2 Preliminary Transformer Calculations (T1)
Transformer turns ratio (a1) is:
NP
a1=
NS
Estimate FET voltage drop (VRDSON) as: VRDSON = 0.3 V
Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will give
some room for dropout if a PFC front end is used (see 方程式24 and 方程式25).
NP
a1=
NS
(24)
V
- 2´ VRDSON ´D
)
VOUT + VRDSON
(
INMIN
MAX
a1=
» 21
(25)
Turn the ratio and round is to the nearest whole turn: a1 = 21
Calculate the typical duty cycle (DTYP) based on average input voltage in 方程式26.
V
+ VRDSON ´a1
)
(
OUT
DTYP
=
» 0.66
V - 2´ V
(
)
IN
RDSON
(26)
Output inductor peak-to-peak ripple current is set to 20% of the output current using 方程式27.
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POUT ´0.2
DILOUT
=
= 10A
VOUT
(27)
Take care in selecting the correct amount of magnetizing inductance (LMAG). 方程式 28 calculates the minimum
magnetizing inductance of the primary of the transformer (T1) to ensure the converter operates in current-mode
control. As LMAG reduces, the increasing magnetizing current becomes an increasing proportion of the signal at
the CS pin. If the magnetizing current increases enough, it can swamp out the current sense signal across RCS
and the converter will operate increasingly as if it were in voltage mode control rather than current mode.
V ´(1-DTYP
)
IN
LMAG
³
» 2.78mH
DILOUT ´0.5
´ 2´F
SW
a1
(28)
图 8-4 shows T1 primary current (IPRIMARY) and synchronous rectifiers QE (IQE) and QF (IQF) currents with
respect to the synchronous rectifier gate drive currents. IQE and IQF are the same as the secondary winding
currents of T1. Variable D is the duty cycle of the converter.
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IPP
IMP2
IMP2 » IPP - DILOUT / 2´a1
(
)
IPRIMARY
IMP
0A
D
On
QEg
Off
On
QFg
Off
IQE
0A
IQF
IPS
IMS
IMS2
IMS2 » IPS - DILOUT/2
0A
DILOUT/2
图8-4. T1 Primary and QE and QF FET Currents
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Calculate T1 secondary RMS current (ISRMS) in 方程式29 through 方程式31:
POUT DILOUT
+
IPS
=
» 55A
» 45A
VOUT
2
(29)
POUT DILOUT
-
IMS
=
VOUT
2
(30)
(31)
ΔILOUT
IMS2 = IPS
-
» 50A
2
Secondary RMS current (ISRMS1) when energy is being delivered to the secondary (see 方程式32):
2
é
ù
ú
û
I -I
(
)
D
æ
ö
PS
MS
MAX
ê
ISRMS1
=
IPS ´IMS
+
» 29.6A
ç
÷
2
3
è
ø
ê
ú
ë
(32)
Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are both
on (see 方程式33).
2
é
ù
ú
û
I -I
(
)
1-D
æ
ö
PS
MS2
MAX
ê
ISRMS2
=
IPS ´IMS2
+
» 20.3A
ç
÷
2
3
è
ø
ê
ú
ë
(33)
Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during freewheeling
period calculated in 方程式34. Refer to 图8-4.
DILOUT 1-D
MAX ö
æ
ç
ISRMS3
=
» 1.1A
÷
2
2´3
ø
è
(34)
(35)
Total secondary RMS current (ISRMS) is calculated in 方程式35:
2
2
2
ISRMS = ISRMS1 +ISRMS2 +ISRMS3 » 36.0A
Calculate T1 Primary RMS Current (IPRMS) using 方程式36 through 方程式40:
VINMIN ´DMAX
DILMAG
=
» 0.47A
L
MAG ´ 2´F
SW
(36)
æ
ç
è
ö
÷
ø
POUT
DILOUT
1
IPP
=
+
+ DILMAG » 3.3A
VOUT ´ h
2
a1
(37)
(38)
æ
ç
è
ö
÷
ø
POUT
DILOUT
1
IMP
=
-
+ DILMAG » 2.8A
VOUT ´ h
2
a1
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2
é
I
ù
ú
ú
û
I
-I
MP
(
)
PP
ê
I
=
D
(
´I
+
» 2.5A
)
PRMS1
MAX
PP MP
ê
3
ë
(39)
(40)
DI
1
æ
ö
LOUT
IMP2 = IPP -
» 3.0A
ç
÷
2
a1
è
ø
T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary (see 方程式41).
2
é
I
ù
ú
ú
û
I
-I
MP
(
)
PP
ê
I
=
D
(
´I
+
» 2.5A
)
PRMS1
MAX
PP MP
ê
3
ë
(41)
T1 Primary RMS (IPRMS2) current when the converter is free wheeling. This is calculated in 方程式42:
2
é
ù
ú
û
I -I
(
)
PP
MP2
ê
IPRMS2
=
1-D
(
I ´I
+
» 1.7A
)
ê PP
ú
MAX
MP2
3
ë
(42)
(43)
The total T1 primary RMS current (IPRMS) is calculated using 方程式43:
2
2
IPRMS = IPRMS1 +IPRMS2 » 3.1A
For this design, a Vitec™ transformer was selected for part number 75PR8107 with the following specifications:
• a1 = 21
• LMAG = 2.8 mH
• measured leakage inductance on the Primary (LLK) is 4 µH
• transformer Primary DC resistance (DCRP) is 0.215 Ω
• transformer Secondary DC resistance (DCRS) is 0.58 mΩ
• estimated transformer core losses (PT1) calculated in 方程式44 are twice the copper loss (which is an
estimate and the total losses may vary based on magnetic design)
P » 2´ I
(
T1
2 ´DCRP + 2´ISRMS2 ´DCRS » 7.0W
PRMS
)
(44)
(45)
Calculate remaining power budget using 方程式45:
P
= P
-P » 38.1W
BUDGET
BUDGET T1
8.2.2.3 QA, QB, QC, QD FET Selection
In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon are chosen
for QA..QD.
The FET drain to source on resistance is:
Rds(on)QA = 0.220W
(46)
The FET Specified COSS is:
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COSS _ QA _ SPEC = 780pF
(47)
The voltage across drain-to-source (VdsQA) where COSS was measured as a data sheet parameter:
VdsQA = 25V
(48)
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Calculate average Coss [2] using 方程式49:
VdsQA
COSS _ QA _ AVG = COSS _ QA _ SPEC
» 193pF
V
INMAX
(49)
(50)
(51)
(52)
(53)
The QA FET gate charge is:
QAg = 15nC
The voltage applied to FET gate to activate FET is:
Vg = 12V
Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg) using 方程式52:
P = IPRMS2 ìRDS(on)QA + 2ìQAg ì Vg ì fSW ö 2.1W
QA
Recalculate the power budget using 方程式53:
P
= P
- 4´PQA » 29.7W
BUDGET
BUDGET
8.2.2.4 Selecting LS
Calculating the value of the shim inductor (LS) is based on the amount of energy required to achieve zero
voltage switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch
node. 方程式 54 selects LS to achieve ZVS at 100% load down to 50% load based on the primary FET’s
average total COSS at the switch node.
备注
The actual parasitic capacitance at the switched node may differ from the estimate and LS may have
to be adjusted accordingly.
2
V
INMAX
L ³ 2´C
-LLK » 26mH
(
)
I
æ
PP
S
OSS _ QA _ AVG
ö2
DILOUT
2´a1
-
ç
÷
ø
2
è
(54)
For this design, a 26-µH Vitec inductor was chosen for LS, part number 60PR964. The shim inductor has the
following specifications:
LS = 26mH
(55)
The LS DC Resistance is:
DCRLS = 27mW
(56)
Estimate LS power loss (PLS) and readjust remaining power budget using 方程式57 through 方程式58:
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2
P = 2´IPRMS ´DCRLS » 0.5W
LS
(57)
(58)
P
= P
-P » 29.2W
BUDGET
BUDGET LS
8.2.2.5 Selecting Diodes DB and DC
There is a potential for high voltage ringing on the secondary rectifiers, caused by the difference in current
between the transformer and the shim inductor when the transformer comes out of freewheeling. Diodes DB and
DC provide a path for this current and prevent any ringing by clamping the transformer primary to the primary
side power rails. Normally these diodes do not dissipate much power, but must be sized to carry the full primary
current. The worse case power dissipated in these diodes is calculated using 方程式59:
P = 0.5´LS ´I2PRMS ´F
SW
(59)
Choose ultra-fast type diodes rated for the input voltage of the converter –VIN (410 VDC in this case).
The MURS360 diode accomodates this power level.
8.2.2.6 Output Inductor Selection (LOUT
)
Inductor LOUT is designed for 20% inductor ripple current (∆ILOUT) calculated in 方程式60 and 方程式61:
POUT ´0.2
600W ´0.2
DILOUT
=
=
» 10A
VOUT
12V
(60)
(61)
VOUT ì(1-DTYP
DILOUT ì 2ì fSW
)
LOUT
=
ö 2mH
Calculate output inductor RMS current (ILOUT_RMS) using 方程式62:
æ
ç
è
ö2
÷
2
POUT
VOUT
DI
LOUT ö
æ
ILOUT _RMS
=
+
= 50.1A
ç
÷
2 3
è
ø
ø
(62)
A 2-µH inductor from Vitec Electronics Corporation, part number 75PR8108, is suitable for this design. The
inductor has the following specifications:
LOUT = 2mH
(63)
The output inductor DC resistance is:
DCRLOUT = 750mW
(64)
Estimate output inductor losses (PLOUT) using 方程式 65 and recalculate the power budget using 方程式 66.
Note PLOUT is an estimate of inductor losses that is twice the copper loss. Note this may vary based on magnetic
manufactures. It is advisable to double check the magnetic loss with the magnetic manufacture.
2
= 2´ILOUT _RMS ´DCRLOUT » 3.8W
P
LOUT
(65)
(66)
P
= P
-P
» 25.4W
BUDGET
BUDGET
LOUT
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8.2.2.7 Output Capacitance (COUT
)
The output capacitor is selected based on holdup and transient (VTRAN) load requirements.
The time it takes LOUT to change 90% of its full load current is calculated in 方程式67:
L
OUT ´POUT ´0.9
VOUT
tHU
=
= 7.5ms
VOUT
(67)
During load transients most of the current will immediately go through the capacitors equivalent series resistance
(ESRCOUT). 方程式 68 and 方程式 69 are used to select ESRCOUT and COUT based on a 90% load step in
current. The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the output capacitance
(COUT) is selected for 10% of VTRAN
.
V
TRAN ´0.9
ESRCOUT
£
= 12mW
P
OUT ´0.9
VOUT
(68)
(69)
P
OUT ´0.9´ tHU
VOUT
TRAN ´0.1
COUT
³
» 5.6mF
V
Before selecting the output capacitor, the output capacitor RMS current (ICOUT_RMS) must be calculated using 方
程式70.
DILOUT
ICOUT _RMS
=
» 5.8A
3
(70)
To meet the design requirements five 1500-µF, aluminum electrolytic capacitors are chosen for the design from
United Chemi-Con™, part number EKY-160ELL152MJ30S. These capacitors have an ESR of 31 mΩ.
The number of output capacitors (n) is 5.
The total output capacitance is calculated using 方程式71:
COUT = 1500mF´n » 7500mF
(71)
The effective output capacitance ESR is calculated using 方程式72:
31mW
ESRCOUT
=
= 6.2mW
n
(72)
(73)
Calculate output capacitor loss (PCOUT) using 方程式73:
2
PCOUT = ICOUT _RMS ´ESRCOUT » 0.21W
Recalculate the remaining Power Budget using 方程式74:
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P
= P
-PCOUT » 25.2W
BUDGET
BUDGET
(74)
8.2.2.8 Select FETs QE and QF
Selecting FETs for a design is an iterative process. To meet the power requirements of this design, we select 75-
V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs have the following characteristics.
QEg = 152nC
(75)
Rds(on)QE = 3.2mW
(76)
Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), and
drain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage in
the design (VdsQE) that will be applied to the FET in the application.
The voltage across FET QE and QF when they are of isf:
2V
INMAX
VdsQE
=
= 39 V
a1
(77)
(78)
(79)
The voltage where FET COSS is specified and tested in the FET data sheet:
Vds _ spec = 25V
The specified output capacitance from FET data sheet is:
COSS _ SPEC = 1810pF
The average QE and QF COSS [2] is calculated using 方程式80:
Vds_SPEC
COSS_QE_ AVG = COSS_SPEC
» 1.9nF
VdsQE
(80)
(81)
The QE and QF RMS current are:
IQE _RMS = ISRMS = 36.0A
To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the gate
charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate charge at the
end of the miller plateau (QEMILLER_MAX) for the given VDS
.
The maximum gate charge at the end of the miller plateau is:
QEMILLER _MAX » 100nC
(82)
(83)
The minimum gate charge at the beginning of the miller plateau is:
QEMILLER _MIN » 52nC
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备注
The FETs in this design are driven with a UCC27324 Gate Driver IC, setup to drive 4-A (IP) of gate
drive current.
IP » 4A
(84)
Estimated FET Vds rise and fall time using 方程式85:
100nC - 52nC 48nC
=
tr » tf =
» 24ns
IP
2
4A
2
(85)
Estimate QE and QF FET Losses (PQE) using 方程式86:
P
2
P = IQE_RMS2 ìRds(on)QE
+
ì VdsQE t + t fSW + 2ìCOSS_QE_ AVG ì VdsQE fSW + 2ìQgQE ì VgQEfSW
OUT
(
)
QE
r
f
VOUT
(86)
PQE » 9.3W
(87)
(88)
Recalculate the power budget using 方程式88.
P
= P
- 2´PQE » 6.5W
BUDGET
BUDGET
8.2.2.9 Input Capacitance (CIN)
The input voltage in this design is 390 VDC, which is typically fed by the output of a PFC boost pre-regulator. It is
typical to select input capacitance based on holdup and ripple requirements.
备注
The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).
Calculate tank frequency using 方程式89:
1
fR =
2p LS ´(2´COSS _ QA _ AVG
)
(89)
(90)
Estimate the delay time using 方程式90:
2
tDELAY
=
» 314ns
f R´4
The effective duty cycle clamp (DCLAMP) is calculated in 方程式91:
≈
∆
«
’
1
DCLAMP
=
- tDELAY ì 2ì f = 94%
÷
SW
2ì fSW
◊
(91)
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VDROP is the minimum input voltage where the converter can still maintain output regulation (see 方程式92). The
converter’s input voltage would only drop down this low during a brownout or line-drop condition if this
converter was following a PFC pre-regulator.
æ
ç
è
ö
÷
ø
2´DCLAMP ´ VRDSON + a1´(VOUT + VRDSON
)
VDROP
=
= 276.2V
DCLAMP
(92)
CIN was calculated in 方程式93 based on one line cycle of holdup:
1
2´POUT
´
60Hz
CIN ³
» 364mF
2
V
2 - VDROP
(
)
IN
(93)
(94)
Calculate the high-frequency input capacitor RMS current (ICINRMS) using 方程式94.
P
2
OUT
I
=
I
−
= 1.8 A
× η
CINRMS
PRMS1
V
VIN min
To meet the input capacitance and RMS current requirements for this design, a 330-µF capacitor was chosen
from Panasonic part number EETHC2W331EA:
CIN = 330 µF
This capacitor has a high frequency (ESRCIN) of 150 mΩ and is measured with an impedance analyzer at 200
kHz. ESRCIN = 0.150 Ω
Estimate the CIN power dissipation (PCIN) using 方程式95:
2
PCIN = ICINRMS ´ESRCIN = 0.5W
(95)
And recalculate the remaining power budget using 方程式96:
P
= P
-PCIN » 6.0W
BUDGET
BUDGET
(96)
There is approximately 6.0 W that remains in the power budget for the current-sensing network, to bias the
control device, and for all resistors supporting the control device.
8.2.2.10 Current Sense Network (CT, RCS, R7, DA)
The CT chosen for this design has a turns ratio (CTRAT) of 100:1 in 方程式97:
IP
CTRAT
=
= 100
IS
(97)
(98)
Calculate nominal peak current (IP1) at VINMIN
:
The peak primary current is calculated using 方程式98:
æ
ç
è
ö
÷
ø
POUT
DILOUT
V
´DMAX
1
INMIN
I =
+
+
» 3.3A
P1
VOUT ´ h
2
a1 LMAG ´ 2´F
SW
The CS pin voltage where peak current limit will trip is:
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VP = 2V
(99)
Calculate current sense resistor (RCS) and leave 300 mV for slope compensation using 方程式 100. Include a
1.1 factor for margin:
VP - 0.3V
RCS
=
» 47W
IP1
´1.1
CTRAT
(100)
(101)
Select a standard resistor for RCS
:
RCS = 47W
Estimate the power loss for RCS using 方程式102:
æ
ç
è
ö2
÷
IPRMS1
CTRAT
P
=
´RCS » 0.03W
RCS
ø
(102)
Calculate maximum reverse voltage (VDA) on DA using 方程式103:
DCLAMP
P 1-DCLAMP
VDA = V
» 29.8V
(103)
(104)
(105)
Estimate the DA power loss (PDA) using 方程式104:
POUT ´0.6V
P
=
» 0.01W
DA
VINMIN ´ h´CTRAT
Calculate reset resistor R7:
Resistor R7 is used to reset the current sense transformer CT:
R7 = 100´RCS = 4.7kW
Resistor RLF1 and capacitor CLF form a low-pass filter for the current sense signal (Pin 15). For this design,
chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz, (which is appropriate for most
applications) but may be adjusted to suit individual layouts and EMI present in the design.
R
LF1 = 1kW
(106)
(107)
CLF = 330pF
1
fLFP
=
= 482kHz
2pf ´RLF1 ´CLF
(108)
The UCC28951 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency noise.
This pin needs at least 1 µF of high-frequency bypass capacitance (CREF).
CREF = 1mF
(109)
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The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (R1, R2), for this design
example, the error amplifier reference voltage (V1) will be set to 2.5 V. Select a standard resistor value for R1
and then calculate resistor value R2.
UCC28951 reference voltage:
VREF = 5V
(110)
Set voltage amplifier reference voltage:
V1= 2.5V
(111)
(112)
R1= 2.37kW
R1´ V - V1
(
)
REF
R2 =
= 2.37kW
V1
(113)
The voltage divider formed by resistor R3 and R4 are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).
Select a standard resistor for R3:
R3 = 2.37kW
(114)
(115)
(116)
Calculate R4 using 方程式115:
R3´ V - V1
(
)
OUT
R4 =
» 9kW
V1
Then choose a standard resistor for R4 using 方程式116:
R3´ V - V1
(
)
OUT
R4 =
» 9.09kW
V1
备注
TI recommends using an RCD clamp to protect the output synchronous FETs from overvoltage due to
switch node ringing.
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图8-5. Daughter Board Schematic
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8.2.2.10.1 Voltage Loop Compensation Recommendation
For best results in the voltage loop, TI recommends using a Type 2 or Type 3 compensation network (图 8-6). A
Type 2 compensation network does not require passive components CZ2 and RZ2. Type 1 compensation is not
versatile enough for a phase-shifted full bridge. When evaluating the COMP pin for best results, TI recommends
placing a 1-kΩresistor between the scope probe and the COMP pin of the UCC28951.
VOUT
VREF
EA+
EA-
+
CZ2
RI
R
1 kW
RD
CZ1
RZ2
RZ1
CP1
R
When evaluating COMP, for best results put
a 1-kW resistor between COMP and probe.
图8-6. Type 3 Compensation Evaluation
Compensating the feedback loop can be accomplished by properly selecting the feedback components (R5, C1
and C2). These components are placed as close as possible to pin 3 and 4 of the controller. A Type 2
compensation network is designed in this example.
Calculate load impedance at 10% load (RLOAD) :
2
VOUT
RLOAD
=
= 2.4W
POUT ´0.1
(117)
Approximate control to output transfer function (GCO(f)) as a function of frequency:
æ
ç
è
ö
÷
ø
DVOUT
DVC
RLOAD
RCS
1+ 2pj´ f ´ESRCOUT ´COUT
1+ 2pj´ f ´RLOAD ´COUT
1
GCO(f) »
= a1´CTRAT
´
´
´
æ
ç
è
ö2
÷
S(f)
S(f)
2p´ fPP
1+
+
2p´ fPP
ø
(118)
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Calculate double pole frequency of GCO(f):
F
SW
fPP
»
= 50kHz
2
(119)
(120)
Calculate angular velocity:
S(f) = 2p´ j´ f
Compensate the voltage loop with Type 2 feedback network. The following transfer function is the compensation
gain as a function of frequency (GC(f)):
DVC
2pj´ f ´R5´C2 +1
GC(f) =
=
2pj´ f ´C2´C1´R5
DVOUT
æ
ö
2pj´ f ´ C2 + C1 R4
+1
(
)
ç
è
÷
C2 + C1
ø
(121)
Calculate voltage loop feedback resistor (R5) based on the crossing the voltage loop (fC) over at a 10th of the
double pole frequency (fPP):
fPP
fC =
= 5kHz
10
(122)
(123)
R4
f
R5 =
» 27.9kW
æ
PP ö
GCO
ç
÷
10
è
ø
The standard resistor selcted for R5 is 27.4 kΩ.
Calculate the feedback capacitor (C2) to give added phase at crossover:
1
C2 =
» 5.8nF
fC
5
2´ p´R5´
(124)
The standard capacitance value (C2) selected for the design is 5.6 nF.
Put a pole at two times fC:
1
C1=
» 580pF
2´ p´R5´ fC ´ 2
(125)
(126)
The standard capacitance value (C1) selected for the design is 560 pF.
Use 方程式126 to calculate the loop gain as a function of frequency (TV(f)) in dB.
T dB(f) = 20log G (f)´G (f)
(
)
V
C
CO
Plot a theoretical loop gain and phase to graphically confirm loop stability. The theoretical loop gain crosses over
at roughly 3.7 kHz with a phase margin of greater than 90 degrees.
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80
60
40
20
0
180
135
90
45
0
-20
-40
-60
-80
-45
-90
-135
-180
TvdB(f)
&Tv(f)
100
1000
10000
100000
Frequency in Hz
图8-7. Loop Gain and Phase vs Frequency
备注
TI recommends confirming the loop stability of the final design with transient testing and/or a network
analyzer. Adjust the compensation (GC(f)) feedback as necessary.
V ´(1-DTYP
)
IN
LMAG
³
» 2.78mH
DILOUT ´0.5
´ 2´F
SW
a1
(127)
where
• loop gain (TVdB(f))
• loop phase (ΦTV(f))
To limit overshoot during the power up sequence, the UCC28951 has a soft-start function (SS, Pin 5). In this
application the soft-start time is 15 ms (tSS).
t
SS ´ 25mA
V1+ 0.55
CSS
=
» 123nF
(128)
The standard capacitor (CSS) selected for this design is 150 nF.
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This application presents a fixed delay approach to achieving ZVS from 100% load down to 50% load. Adaptive
delays can be generated by connecting the ADEL and ADELEF pins to the CS pin as shown in 图8-8 .
RAHI
CS 15
RAEFHI
ADEL 14
RA
RAEF
ADELEF 13
图8-8. Adaptive Delays
When the converter is operating below 50% load, the converter operates in valley switching. To achieve zero
voltage switching on switch node of QBd, the turn-on (tABSET) delays of FETs QA and QB must be initially set
based on the interaction of LS and the theoretical switch node capacitance. The following equations are used to
set tABSET initially.
Equate shim inductance to two times COSS capacitance using 方程式129:
1
2p´ fRLS =
2p´ fR ´(2´COSS _ QA _ AVG
)
(129)
(130)
Calculate tank frequency using 方程式130:
1
fR =
2p LS ´(2´COSS _ QA _ AVG
)
Set initial tABSET delay time and adjust as necessary.
备注
The 2.25 factor of the tABSET equation was derived from empirical test data and may vary based on
individual design differences.
2.25
tABSET
=
» 346ns
f R´4
(131)
The resistor divider formed by RA and RAHI programs the tABSET, tCDSET delay range of the controller. The
standard resistor value RAHI selected is 8.25 kΩ.
tABSET can be programmed between 30 ns to 1000 ns.
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The voltage at the ADEL input of the controller (VADEL) must be set with RA based on the following conditions:
• If tABSET > 155 ns, set VADEL = 0.2 V. tABSET can be programmed between 155 ns and 1000 ns.
• If tABSET ≤155 ns, set VADEL = 1.8 V. tABSET can be programmed between 29 ns and 155 ns.
Based on VADEL selection, calculate RA:
R
AHI ´ VADEL
RA =
» 344W
5V - VADEL
(132)
(133)
The closest standard resistor value for RA selected is 348 Ω.
Recalculate VADEL based on resistor divider selection:
5V ´RA
VADEL
=
= 0.202V
R
AHI + RA
Resistor RAB programs tABSET. Variable CS is the voltage at the CS pin with respect to ground and ratio KA was
calculated in 方程式5:
TABSET
RAB
=
´ 0.26 + CS´K ´1.3 » 30.6kW
A
(
)
5
(134)
The standard resistor value for RAB selected for the design is 30.1 kΩ.
备注
After a prototype oprational, fine tune tABSET during light-load operation to the peak and valley of the
resonance between LS and the switch node capacitance. In this design, the delay was set at 10%
load.
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Set t
at resonant tank Peak and Valley
tABSET = t 4 - t 3
ABSET
tABSET = t 1 - t 0
QB d
QA g
Miller Plateau
tMILLER = t 2 - t1
QB
g
Miller Plateau
tMILLER = t 5 - t 4
t0 t1 t2
t3 t4 t5
图8-9. tABSET to Achieve Valley Switching at Light Loads
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Initially, set the QC and QD turn-on delays (tCDSET) for the same delay as the QA and QB turn-on delays (Pin 6).
The following equations program the QC and QD turn-on delays (tCDSET) by properly selecting resistor RDELCD
(Pin 7).
tABSET = tCDSET
(135)
Resistor RCD programs tCDSET
:
TCDSET
RCD
=
´ 0.26 + CS´K ´1.3 » 30.6kW
A
(
)
5
(136)
The standard resistor RCD selected for this design is 30.1 kΩ.
备注
After a prototype operational, fine tune tCDSET during light-load operation. In this design, the CD node
was set to valley switch at roughly 10% load.. Obtaining ZVS at lighter loads with switch node QDd is
easier due to the reflected output current present in the primary of the transformer at FET QD and QC
during the turnoff or turnon period. This behavior is due to more peak current available to energize LS
before this transition, compared to the QA and QB turnoff and turnon period.
Set t
at resonant tank Peak and Valley
CDSET
tCDSET = t - t0
tCDSET = t - t3
1
4
QD
d
QC
g
Miller Plateau
tMILLER = t - t 1
2
QD g
Miller Plateau
tMILLER = t - t 4
5
t0 t1 t2
t3 t4 t5
图8-10. tCDSET to Achieve Valley Switching at Light Loads
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There is a programmable delay for the turnoff of FET QF after FET QA turnoff (tAFSET) and the turnoff of FET QE
after FET QB turnoff (tBESET). Set these delays to 50% of tABSET to ensure that the appropriate synchronous
rectifier turns off before the AB ZVS transition. If this delay is too large, it causes OUTE and OUTF not to overlap
correctly and creates excess body diode conduction on FETs QE and QF.
tAFSET = tBESET = tABSET ´0.5
(137)
The resistor divider formed by RAEF and RAEFHI programs the tAFSET and tBESET delay range of the controller. The
standard resistor value selected for RAEFHI is 8.25 kΩ.
备注
tAFSET and tBESET can be programmed between 32 ns to 1100 ns.
The voltage at the ADELEF pin of the controller (VADELEF) needs to be set with RAEF based on the following
conditions.
• If tAFSET < 170 ns set VADEL = 0.2 V, tABSET can be programmed between 32 ns and 170 ns.
• If tABSET > or = 170 ns set VADEL = 1.7 V, tABSET can be programmed between 170 ns and 1100 ns.
Based on VADELEF selection, calculate RAEF
:
R
AEFHI ´ VADELEF
RAEF
=
» 4.25kW
5V - VADELEF
(138)
The closest standard resistor value for RAEF is 4.22 kΩ.
Recalculate VADELEF based on resistor divider selection:
5V ´RAEF
VADELEF
=
= 1.692V
R
AEFHI + RAEF
(139)
(140)
The following equation was used to program tAFSET and tBESET by properly selecting resistor REF.
t
(
´0.5 - 4ns
2.65V - V
)´ (
´1.32 ´103
ADELEF
)
1
AFSET
REF
=
´
» 14.1kW
ns
5
1A
The standard resistor value selected for REF is 14 kΩ.
Resistor RTMIN programs the minimum on time (tMIN) that the UCC28951 (Pin 9) can demand before entering
burst mode. If the UCC28951 controller tries to demand a duty cycle on time of less than tMIN the power supply
goes into burst mode operation. For this design set the minimum on-time (tMIN) to 75 ns.
Set the minimum on-time by selecting RTMIN
:
tMIN
RTMIN
=
» 12.7kW
5.92
(141)
(142)
The standard resistor value for RTMIN is 13 kΩ.
A resistor from the RT pin to ground sets the converter switching frequency calculated in 方程式142.
Ω Hz
V
6
2.5 × 10
f
×
Ω
V
R
=
−
× V
− 2.5 V = 60 kΩ
REF
T
SW
2
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The standard resistor value selected for RT is 61.9 kΩ.
The UCC28951 provides slope compensation. The amount of slope compensation is set by the resistor RSUM
.
As suggested earlier, set the slope compensation ramp to be half the inductor current ramp downslope (inductor
current ramp during the off time), reflected through the main transformer and current sensing networks as
explained earlier in 节7.3.11.
Calculate required slope compensation ramp:
VOUT ìRCS
LOUT ì a1ì CTRAT
12 ì 47
mV
me = 0.5ì
= 0.5 ì
= 67
2 ì10-6 ì 21ì100
ms
(143)
The magnetizing current of the power transformer provides part of the slope compensation ramp. The slope of
this current is calculated using 方程式 144 where VINHU is the minimum voltage for VOUT holdup purposes. It is
the voltage at which the converter is operating at the maximum dudy cycle (DMAX) while maintaining VOUT
:
VINHU ´ RCS
260 ´ 47
mV
mMAG
=
=
» 44
2.76x10-3 ´100
LMAG ´ CTRAT
ms
(144)
Calculate the required compensating ramp:
mV
mV
mSUM = me - mMAG = (67 - 44)
= 23
ms
ms
(145)
The value for the resistor, RSUM, may be found from the graph in 图7-10, calculated from rearranged versions of
方程式 13, or calculated by 方程式 13, depending on whether the controller is operating in current mode or
voltage control mode. This design uses current mode control and 方程式146 is rearranged and evaluated:
2.5
2.5
RSUM
=
=
» 200kW
0.5 ´ 23x10-3
0.5 ´ mSUM
(146)
Confirm that the 300 mV allowed for the slope compensation ramp is sufficient when choosing RCS in 方程式
100.
mV
23
´ 0.7
mSUM ´ DMAX
2 ´ FSW
ms
DVSLOPE -COMP
=
=
= 80mV
2 ´100kHz
(147)
To increase efficiency at lighter loads the UCC28951 is programmed (Pin 12, DCM) under light-load conditions to
disable the synchronous FETs on the secondary side of the converter (QE and QF). This threshold is
programmed with resistor divider formed by RDCMHI and RDCM. This DCM threshold needs to be set at a level
before the inductor current goes discontinuous. 方程式 148 sets the level at which the synchronous rectifiers are
disabled at roughly 15% load current.
æ
ç
è
ö
÷
ø
POUT ´0.15 DILOUT
+
´R
CS
VOUT
2
VRCS
=
= 0.29V
a1´CTRAT
(148)
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The standard resistor value selected for RDCM is 1 kΩ.
Calculate resistor value RDCMHI
.
RDCM
V
- VRCS
(
)
REF
RDCMHI
=
» 16.3kW
VRCS
(149)
The standard resistor value for RDCMHI is 16.9 kΩ.
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8.2.3 Application Curves
Switch node QBd is valley switching and node QDd has achieved ZVS. Please refer to 图 8-13 and 图 8-14. It is
not uncommon for switch node QDd to obtain ZVS before QBd. This is because during the QDd switch node
voltage transition, the reflected output current provides immediate energy for the LC tank at the switch node.
Where at the QBd switch node transition the primary has been shorted out by the high-side or low-side FETs in
the H bridge. This transition is dependent on the energy stored in LS and LLK to provide energy for the LC tank
at switch node QBd making it take longer to achieve ZVS.
Valley Switching
QB
QD
d
d
Valley Switching
QD g
QBg
QB = off
QA= on
QD = on
QC = off
QD = off
QC = on
QB = on
0V
0V
QA/QB = off
tCDSET
tABSET
tD
Slight Delay after t
before Miller Plateau
tD
Slight Delay after t
before Miller Plateau
CDSET
ABSET
VIN = 390 V
IOUT = 5 A
VIN = 390 V
IOUT = 5 A
图8-12. Full-Bridge Gate Drives and Primary
图8-11. Full-Bridge Gate Drives and Primary
Switch Nodes (QDg QDd)
Switch Nodes (QBd and QDd)
Valley Switching
QB d
QD d
QDg
QBg
ZVS
0V
QD = off
QB = off
QD = on
QB = on
0V
0V
QC = on
QA = on
QC = off
QA/QB = off
tCDSET
tABSET
tD
tD
Slight Delay after t
Slight Delay after t
CDSET
ABSET
before Miller Plateau
before Miller Plateau
VIN = 390 V
IOUT = 10 A
VIN = 390 V
IOUT = 10 A
图8-14. Full-Bridge Gate Drives and Switch Nodes
图8-13. Full-Bridge Gate Drives and Switch Nodes
(QDg QDd)
(QBg QBd)
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ZVS Achieved
QD
QBd
d
QDg
ZVS
QBg
QB = off
QD = off
QC = on
QB = on
QD = on
0V
0V
QA = on
QA/QB = off
QC= off
tABSET
tCDSET
VIN = 390 V
IOUT = 25 A
VIN = 390 V
IOUT = 25 A
图8-15. Full-Bridge Gate Drives and Switch Nodes
图8-16. Full-Bridge Gate Drives and Switch Nodes
(QBg QBd)
(QDg QDd)
When the converter is running at 25 A, both switch nodes are operating into zero voltage switching (ZVS). It is
also worth mentioning that there is no evidence of the gate miller plateau during gate driver switching. This is
because the voltage across the drains and sources of FETs QA through QD transitioned earlier.
ZVS
QD d
QB d
QDg
ZVS
QBg
QB = off
QA = on
QD = off
QC = on
QB = on
QD = on
0V
0V
QA/QB = off
QC = off
tABSET
tCDSET
VIN = 390 V
IOUT = 50 A
VIN = 390 V
IOUT = 50 A
ZVS maintained from 50% to
100% output power
图8-17. Full-Bridge Gate Drives and Switch Nodes
(QBg QBd)
图8-18. Full-Bridge Gate Drives and Switch Nodes
(QDg QDd)
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9 Power Supply Recommendations
Operate the UCC28951 controller from a VDD rail within the limits given in the 节 6.3 section of this data sheet.
To avoid the possibility that the controller might stop switching, do not allow the VDD to fall into the UVLO_FTH
range. To minimize power dissipation in the controller, ensure that VDD is not unnecessarily high. Maintaining
VDD at 12 V is a good compromise between these competing constraints. The gate drive outputs from the
controller deliver large-current pulses into their loads. This indicates the need for a low-ESR decoupling
capacitor to be connected as directly as possible between the VDD and GND terminals.
TI recommends ceramic capacitors with stable dielectric characteristics over temperature, such as X7R. Avoid
capacitors which have a large drop in capacitance with applied DC voltage bias. For example, use a component
that has a low-voltage co-efficient of capacitance. The recommended decoupling capacitance is 1 μF, X7R, with
at least a 25-V rating with a 0.1-µF NPO capacitor in parallel.
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10 Layout
10.1 Layout Guidelines
To increase the reliability and robustness of the design, TI recommends the following layout guidelines:
• For the VREF pin: decouple this pin to GND with a good quality ceramic capacitor. A 1-µF, X7R, 25-V
capacitor is recommended. Keep VREF PCB tracks as far away as possible from sources of switching noise.
• For the EA+ pin: this is the noninverting input to the error amplifier. It is a high impedance pin and is
susceptible to noise pickup. Keep tracks from this pin as short as possible.
• For theEA–pin: this is the inverting input to the error amplifier. It is a high impedance pin and is susceptible
to noise pickup. Keep tracks from this pin as short as possible.
• For theCOMP pin: the error amplifier compensation network is normally connected to this pin. Keep tracks
from this pin as short as possible.
• For theSS/EN pin: keep tracks from this pin as short as possible. If the Enable signal is coming from a remote
source then avoid running it close to any source of high dv/dt (MOSFET Drain connections for example) and
add a simple RC filter at the SS/EN pin.
• For the DELAB, DELCD, DELEF, TMIN, RT, RSUM, DCM, ADELEF and ADEL pins: the components
connected to these pins are used to set important operating parameters. Keep these components close to the
IC and provide short, low impedance return connections to the GND pin.
• For the CS pin: this connection is arguably the most important single connection in the entire PSU system.
Avoid running the CS signal traces near to sources of high dv/dt. Provide a simple RC filter as close to the pin
as possible to help filter out leading edge noise spikes which occur at the beginning of each switching cycle.
• For the SYNC pin: this pin is essentially a digital I/O port. If it is unused, then it may be left open circuit or tied
to ground through a 1-kΩresistor. If Synchronisation is used, then route the incoming Synchronisation signal
as far away from noise sensitive input pins as possible.
• For the OUTA, OUTB, OUTC, OUTD, OUTE and OUTF pins: these are the gate drive output pins. They have
a high dv/dt rate associated with their rising and falling edges. Keep the tracks from these pins as far away
from noise sensitive input pins as possible. Ensure that the return currents from these outputs do not cause
voltage changes in the analog ground connections to noise sensitive input pins. Follow the layout
recommendation for analog and power ground planes in 图7-18.
• For the VDD pin: this pin must be decoupled to GND using ceramic capacitors as detailed in the 节9 section.
Keep this capacitor as close to the VDD and GND pins as possible.
• For the GND pin: this pin provides the ground reference to the controller. Use a ground plane to minimize the
impedance of the ground connection and to reduce noise pickup.
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10.2 Layout Example
VREF pin decoupled to GND (C1), close to the device
R28
C8
VDD decoupling as close to the
device as possible. (C6, C5)
R6
Top Side
R2
R1
R7
C1
C6 C5 R15
R9
U1
C3
R5
C4
OUTA through OUTE signals
routed as far as possible from
signal pins. (pins 17 through 22)
R12
R11
R13
R16
R24
C7
R14
R27
R22
RC filter close to CS pin.
(C7, R27, pin 15)
R17
R26
R25
R28
R23
Short tracks at EA+, EA-, COMP, SS/EN, DELAB, DELCD,
TMIN, RT, RSUM, DCM, ADELEF, and ADEL pins.
(pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14)
图10-1. Layout Example (Top Side)
Bottom Side
R29
C2
R3
R4
J1
R20
R8
R10
图10-2. Layout Example (Bottom Side)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
UCC28950 MathCAD Design Tool.
UCC28950 Excel Design Tool.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers (SLUA609)
• Making the Correct Choice: UCC28950-Q1 or UCC28951-Q1 (SLUA853)
• Gate Drive Outputs on the UCC28950 and UCC28951-Q1 During Burst Mode Operation (SLAU787)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
11.5 Trademarks
Vitec™ is a trademark of Vitec Electronics Corporation.
United Chemi-Con™ is a trademark of United Chemi-Con, Inc..
所有商标均为其各自所有者的财产。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC28951PWR
UCC28951PWT
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
24
24
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
UCC28951
UCC28951
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2021
OTHER QUALIFIED VERSIONS OF UCC28951 :
Automotive : UCC28951-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC28951PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 24
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
UCC28951PWR
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
B
13
0.30
24X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
24
1
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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