UCC2895 [TI]
BiCMOS Advanced Phase Shift PWM Controller; BiCMOS高级相移PWM控制器
| 型号： | UCC2895 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BiCMOS Advanced Phase Shift PWM Controller |
| 文件： | 总14页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UCC1895
UCC2895
UCC3895
available
BiCMOS Advanced Phase Shift PWM Controller
FEATURES
DESCRIPTION
• Programmable Output Turn-on Delay
The UCC3895 is a phase shift PWM controller that implements control of a
full-bridge power stage by phase shifting the switching of one half-bridge
with respect to the other. It allows constant frequency pulse-width modula-
tion in conjunction with resonant zero-voltage switching to provide high effi-
ciency at high frequencies. The part can be used either as a voltage mode
or current mode controller.
• Adaptive Delay Set
• Bidirectional Oscillator Synchronization
• Capability for Voltage Mode or Current
Mode Control
While the UCC3895 maintains the functionality of the UC3875/6/7/8 family
and UC3879, it improves on that controller family with additional features
such as enhanced control logic, adaptive delay set, and shutdown capabil-
ity. Since it is built in BCDMOS, it operates with dramatically less supply
current than it’s bipolar counterparts. The UCC3895 can operate with a
maximum clock frequency of 1MHz.
• Programmable Soft Start/Soft Stop
and Chip Disable via a Single Pin
• 0% to 100% Duty Cycle Control
• 7MHz Error Amplifier
• Operation to 1MHz
The UCC3895 and UCC2895 are offered in the 20 pin SOIC (DW) pack-
age, 20 pin PDIP (N) package, 20 pin TSSOP (PW) package, and 20 pin
PLCC (Q). The UCC1895 is offered in the 20 pin CDIP (J) package, and 20
pin CLCC package (L).
• Low Active Current Consumption
(5mA Typical @ 500kHz)
• Very Low Current Consumption
During Undervoltage Lock-out
(150mA typical)
SIMPLIFIED APPLICATION DIAGRAM
UCC3895
Q1
1
2
3
4
5
6
7
8
9
EAN
EAP 20
SS/DISB 19
OUTA 18
OUTB 17
PGND 16
VCC 15
VOUT
EAOUT
RAMP
REF
A
C
GND
SYNC
CT
VIN
VBIAS
OUTC 14
OUTD 13
CS 12
B
D
RT
DELAB
10 DELCD
ADS 11
UDG-98139
SLUS157B - DECEMBER 1999 - REVISED JANUARY 2001
UCC1895
UCC2895
UCC3895
CONNECTION DIAGRAMS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (IDD < 10mA) . . . . . . . . . . . . . . . . . . . . . . . 17V
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
REF current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15mA
OUT Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Analog inputs
DIL-20,c SOIC-20, TSSOP-20 (TOP VIEW)
J or N Package, DW Package, PW Package
EAN
EAOUT
RAMP
REF
1
2
3
4
5
6
7
8
9
20 EAP
(EAP, EAN, EAOUT, RAMP,
19 SS/DISB
18 OUTA
17 OUTB
16 PGND
15 VDD
14 OUTC
13 OUTD
12 CS
SYNC, ADS, CS, SS/DISB) . . . . . . . . . . . –0.3V to REF+0.3V
Power Dissipation at TA=+25°C (N Package). . . . . . . . . . . . 1W
Power Dissipation at TA=+25°C (D Package) . . . . . . . . 650mW
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature (soldering, 10 sec). . . . . . . . . . . . . . +300°C
GND
SYNC
CT
RT
TEMPERATURE & PACKAGE SELECTION
TABLE
DELAB
DELCD 10
11 ADS
TEMPERATURE
RANGE
PACKAGE
SUFFIX
UCC1895
UCC2895
UCC3895
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
J, L
DW, N, PW, Q
DW, N, PW, Q
PLCC-20, CLCC-20 (TOP VIEW)
Q Package, L Package
EAN
EAOUT
RAMP
ORDERING INFORMATION
EAP
SS/DISB
UCC 895
3
2
1
20 19
18
REF
GND
SYNC
CT
4
5
6
7
8
OUTA
17
16
15
14
OUTB
PGND
VDD
PACKAGE SUFFIX
TEMPERATURE RANGE
RT
OUTC
9
10 11 12 13
DELAB
DELCD
OUTD
CS
ADS
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kW, CT=220pF, RDELAB=10kW,
RDELCD=10kW, CREF=0.1mF, CVDD=1.0mF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for
UCC2895x, and –55°C to +125°C for UCC1895x.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
UVLO Section
Start Threshold
Stop Threshold
Hysteresis
10.2
8.2
11
9
11.8
9.8
V
V
V
1.0
2.0
3.0
Supply Current
Start-up Current
IDD Active
VDD = 8V
150
5
250
6
mA
mA
V
VDD Clamp Voltage
IDD = 10mA
16.5
17.5
18.5
2
UCC1895
UCC2895
UCC3895
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kW, CT=220pF, RDELAB=10kW,
RDELCD=10kW, CREF=0.1mF, CVDD=1.0mF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for
UCC2895x, and –55°C to +125°C for UCC1895x.
PARAMETER
Voltage Reference Section
Output Voltage
TEST CONDITIONS
MIN
TYP
MAX UNITS
TJ = 25°C
4.94
4.85
5.00
5
5.06
5.15
V
V
10V < VDD < 17.5V, 0mA < IREF < 5mA,
Temperature
Short Circuit Current
Error Amplifier Section
Common Mode Input Voltage Range
Offset Voltage
REF = 0V, TJ = 25°C
10
20
mA
–0.1
–7
3.6
7
V
mV
mA
Input Bias Current (EAP, EAN)
EAOUT VOH
–1
1
EAP–EAN = 500mV, IEAOUT= –0.5mA
EAP–EAN = –500mV, IEAOUT= 0.5mA
EAP–EAN = 500mV, EAOUT= 2.5V
4.0
0
4.5
0.2
1.5
4.5
85
5.0
0.4
V
EAOUT VOL
V
EAOUT Source Current
EAOUT Sink Current
Open Loop DC Gain
Unity Gain Bandwidth
Slew Rate
1.0
2.5
75
mA
mA
dB
EAP–EAN = –500mV, EAOUT= 2.5V, (Note 4)
(Note 3)
5.0
1.5
7.0
2.2
MHz
V/ms
EAN from 1V to 0V, EAP = 500mV,
EAOUT from 0.5V to 3.0V, (Note 3)
No Load Comparator Turn-Off Threshold
No Load Comparator Turn-On Threshold
No Load Comparator Hysteresis
Oscillator Section
0.45
0.55
0.50
0.60
0.55
0.69
V
V
V
0.035 0.100 0.165
Frequency
TJ = 25°C
473
500
2.5
2.10
1.90
4.5
0.5
85
527
5
kHz
%
V
Total Variation
Line, Temperature (Note 3)
SYNC VIH
2.05
1.85
4.1
2.25
1.95
5.0
1.0
135
3.1
2.50
0.4
0.6
SYNC VIL
V
SYNC VOH
ISYNC = –400mA, CT = 2.6V
V
SYNC VOL
ISYNC = 100mA, CT = 0V
0.0
V
SYNC Output Pulse Width
RT Voltage
SYNC Load = 3.9kW and 30pF in parallel
ns
V
2.9
2.25
0.0
3
CT Peak Voltage
2.35
0.2
0.2
V
CT Valley Voltage
UCC2895, UCC3895
UCC1895
V
CT Valley Voltage
0.0
V
PWM Comparator Section
EAOUT to RAMP Input Offset Voltage
RAMP = 0V, DELAB = DELCD = REF
RAMP = 0V, EAOUT = 650mV (Note 1)
0.72
0.00
0.85
0.85
1.05
1.40
V
Minimum Phase Shift
%
(OUTA to OUTC, OUTB to OUTD)
RAMP to OUTC/OUTD Delay
RAMP from 0V to 2.5V, EAOUT = 1.2V,
DELAB = DELCD = REF (Note 2)
70
19
120
5
ns
RAMP Bias Current
RAMP Sink Current
Current Sense Section
CS Bias Current
RAMP < 5V, CT < 2.2V
RAMP = 5V, CT < 2.6V
–5
12
mA
mA
0 < CS , 2.5V, 0 < ADS < 2.5V
–4.5
1.90
2.4
20
2.10
2.6
mA
V
Peak Current Threshold
Overcurrent Threshold
CS to Output Delay
2.00
2.5
75
V
CS from 0 to 2.3V, DELAB = DELCD = REF
3
110
ns
UCC1895
UCC2895
UCC3895
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82kW, CT=220pF, RDELAB=10kW,
RDELCD=10kW, CREF=0.1mF, CVDD=1.0mF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for
UCC2895x, and –55°C to +125°C for UCC1895x.
PARAMETER
Soft Start/Shutdown Section
Soft Start Source Current
TEST CONDITIONS
MIN
TYP
MAX UNITS
SS/DISB = 3.0V, CS < 1.9V
–40
325
0.44
–35
350
0.50
–30
375
0.56
mA
mA
V
Soft Start Sink Current
SS/DISB = 3.0V, CS > 2.6V
Soft Start/Disable Comparator Threshold
Delay Set Section
DELAB/DELCD Output Voltage
ADS = CS = 0V
0.45
1.9
0.50
2.0
0.55
2.1
600
20
V
V
ADS = 0V, CS = 2.0V
Output Delay
ADS Bias Current
Output Section
VOH (all outputs)
VOL (all outputs)
Rise Time
ADS = CS = 0V (Notes 2 and 3)
0V < ADS < 2.5V, 0V < CS < 2.5V
450
–20
525
ns
mA
IOUT = –10mA, VDD to Output
IOUT = 10mA
250
150
20
400
250
35
mV
mV
ns
CLOAD = 100pF, (Note 3)
CLOAD = 100pF, (Note 3)
Fall Time
20
35
ns
t
PERIOD
t
t
f(OUTA) − tf(OUTC)
Φ = 200 •
Φ = 200 •
tPERIOD
f(OUTB) − tf(OUTD)
OUTA
OUTC
tPERIOD
t
= t
- t
DELAY
f(OUTA) f(OUTC)
OUTA
- t
t
= t
DELAY
f(OUTA) r(OUTB)
OUTB
4
UCC1895
UCC2895
UCC3895
PIN DESCRIPTIONS
ADS: Adaptive Delay Set. This function sets the ratio be- DELAB, DELCD: Delay Programming Between
tween the maximum and minimum programmed output Complementary Outputs. DELAB programs the dead
delay dead time. When the ADS pin is directly connected time between switching of OUTA and OUTB, and DELCD
to the CS pin, no delay modulation occurs. The maximum programs the dead time between OUTC and OUTD. This
delay modulation occurs when ADS is grounded. In this delay is introduced between complementary outputs in
case, delay time is four times longer when CS = 0 than the same leg of the external bridge. The UCC3895 allows
when CS = 2.0V (the Peak Current threshold), ADS the user to select the delay, in which the resonant
changes the output voltage on the delay pins DELAB and switching of the external power stages takes place.
DELCD by the following formula:
Separate delays are provided for the two half-bridges to
accommodate differences in resonant capacitor charging
currents. The delay in each stage is set according to the
following formula:
(
)
VDEL =[0.75 • VCS − VADS ]+0.5V
where VCS and VADS are in Volts. ADS must be limited to
between 0V and 2.5V and must be less than or equal to
CS. DELAB and DELCD also will be clamped to a mini-
mum of 0.5V.
(25 • 10−12 )• RDEL
tDELAY
=
+ 25ns
VDEL
where VDEL is in Volts, and RDEL is in Ohms and tDELAY
is in seconds. DELAB and DELCD can source about
1mA maximum. Choose the delay resistors so that this
maximum is not exceeded. Programmable output delay
can be defeated by tying DELAB and/or DELCD to REF.
For an optimum performance keep stray capacitance on
these pins at <10pF.
EAOUT: Error Amplifier Output. It is also connected inter-
nally to the non-inverting input of the PWM comparator
and the no-load comparator. EAOUT is internally
clamped to the soft start voltage. The no-load comparator
shuts down the output stages when EAOUT falls below
500mV, and allows the outputs to turn-on again when
EAOUT rises above 600mV.
EAP: The non-inverting input to the error amplifier.
EAN: The inverting input to the error amplifier.
CT: Oscillator Timing Capacitor. (Refer to Fig. 1, Oscilla-
tor Block Diagram) The UCC3895’s oscillator charges CT
via a programmed current. The waveform on CT is a
sawtooth, with a peak voltage of 2.35V. The approximate
oscillator period is calculated by the following formula:
GND: Chip ground for all circuits except the output
stages.
OUTA, OUTB, OUTC, OUTD: The 4 outputs are 100mA
complementary MOS drivers, and are optimized to drive
FET driver circuits. OUTA and OUTB are fully
complementary, (assuming no programmed delay). They
operate near 50% duty cycle and one-half the oscillating
frequency. OUTA and OUTB are intended to drive one
half-bridge circuit in an external power stage. OUTC and
OUTD will drive the other half-bridge and will have the
same characteristics as OUTA and OUTB. OUTC is
phase shifted with respect to OUTA, and OUTD is phase
shifted with respect to OUTB. Note that changing the
phase relationship of OUTC and OUTD with respect to
OUTA and OUTB requires other than the nominal 50%
duty ratio on OUTC and OUTD during those transients.
5 • RT • CT
tOSC
=
+120ns
48
where CT is in Farads, and RT is in Ohms and tOSC is in
seconds. CT can range from 100pF to 880pF. Please
note that a large CT and a small RT combination will re-
sult in extended fall times on the CT waveform. The in-
creased fall time will increase the SYNC pulse width,
hence limiting the maximum phase shift between OUTA,
OUTB and OUTC, OUTD outputs, which limits the maxi-
mum duty cycle of the converter.
CS: Current Sense. This is the inverting input of the Cur-
rent Sense comparator and the non-inverting input of the
Over-current comparator, and the ADS amplifier. The cur-
rent sense signal is used for cycle-by-cycle current limit-
ing in peak current mode control, and for overcurrent
protection in all cases with a secondary threshold for out-
put shutdown. An output disable initiated by an
overcurrent fault also results in a restart cycle, called
“soft stop”, with full soft start.
PGND: Output Stage Ground. To keep output switching
noise from critical analog circuits, the UCC3895 has 2
different ground connections. PGND is the ground
connection for the high-current output stages. Both GND
and PGND must be electrically tied together closely near
the IC. Also, since PGND carries high current, board
traces must be low impedance.
5
UCC1895
UCC2895
UCC3895
PIN DESCRIPTIONS (cont.)
After a fault or disable condition has
passed, VDD is above the start threshold, and/or
SS/DISB falls below 0.5V during a soft stop, SS/DISB will
switch to a soft start mode. The pin will now source
RAMP: The Inverting Input of the PWM Comparator. This
pin receives either the CT waveform in voltage and aver-
age current mode controls, or the current signal (plus
slope compensation) in peak current mode control. An in-
ternal discharge transistor is provided on RAMP, which is
triggered during the oscillator dead time.
current, equal to IRT
.
A user-selected capacitor on
SS/DISB determines the soft start (and soft-start) time. In
addition, a resistor in parallel with the capacitor may be
used, limiting the maximum voltage on SS/DISB. Note
that SS/DISB will actively clamp the EAOUT pin voltage
to approximately the SS/DISB pin voltage during both
soft start, soft stop, and disable conditions.
RT: Oscillator Timing Resistor. (Refer to Fig. 1, Oscillator
Block Diagram) The oscillator in the UCC3895 operates
by charging an external timing capacitor, CT, with a fixed
current programmed by RT. RT current is calculated as
follows:
SYNC: Oscillator Synchronization. (Refer to Fig. 1, Oscil-
lator Block Diagram) This pin is bidirectional. When used
as an output, SYNC can be used as a clock, which is the
same as the chip’s internal clock. When used as an in-
put, SYNC will override the chip’s internal oscillator and
act as it’s clock signal. This bidirectional feature allows
synchronization of multiple power supplies. The SYNC
signal will also internally discharge the CT capacitor and
any filter capacitors that are present on the RAMP pin.
The internal SYNC circuitry is level sensitive, with an in-
put low threshold of 1.9V, and an input high threshold of
2.1V. A resistor as small as 3.9kW may be tied between
SYNC and GND to reduce the sync pulse width.
3.0 V
IRT
=
RT
where RT is in Ohms and IRT is in Amperes. RT can
range from 40kW to 120kW Soft start charging and dis-
charging current are also programmed by IRT
.
SS/DISB: Soft Start/Disable. This pin combines the two
independent functions.
: A rapid shutdown of the chip is
accomplished by any one of the following: externally
forcing SS/DISB below 0.5V, externally forcing REF
below 4V, VDD dropping below the UNLO threshold, or an
overcurrent fault is sensed (CS = 2.5V).
VDD: Power Supply. VDD must be bypassed with a mini-
mum of a 1.0mF low ESR, low ESL capacitor to ground.
In the case of REF being pulled below 4V or an UVLO
condition, SS/DISB is actively pulled to ground via an
internal MOSFET switch. If an overcurrent is sensed,
SS/DISB will sink a current of (10 • IRT) until SS/DISB
falls below 0.5V.
REF: 5V, ±1.2% voltage reference. The reference
supplies power to internal circuitry, and can also supply
up to 5mA to external loads. The reference is shut down
during undervoltage lock-out but is operational during all
other disable modes. For best performance, bypass with
a 0.1mF low ESR, low ESL capacitor to ground.
Note that if SS/DISB is externally forced below 0.5V the
pin will start to source current equal to IRT. Also note that
the only time the part switches into the low IDD current
mode is when the part is in undervoltage lockout.
APPLICATION INFORMATION
Programming DELAB, DELCD, and the Adaptive Delay Set
The UCC3895 allows the user to set the delay between
switch commands within each leg of the full bridge power
circuit according to the following formula from the data
sheet:
UCC3895
CS 12
(25 • 10−12 )• RDEL
9
DELAB
tDELAY
=
+ 25nsec
VDEL
R
DELAB
10 DELCD
ADS 11
For this equation VDEL is determined in conjunction with
the desire to utilize (or not utilize) the adaptive delay set
feature from the following formula:
R
DELCD
(
)
VDEL =[0.75 • VCS − VADS ]+0.5V
The following diagram illustrates the resistors needed to
program the delay periods and the adaptive delay set
function.
6
UCC1895
UCC2895
UCC3895
APPLICATION INFORMATION (CONT.)
The Adaptive Delay Set feature (ADS) allows the user to ing the UC3879. Implementing this adaptive feature is
vary the delay times between switch commands within simplified in the UCC3895 controller, giving the user the
each of the converter’s two legs. The delay time modula- ability to tailor the delay times to suit a particular applica-
tion is implemented by connecting ADS (pin 11) to CS, tion with a minimum of external parts.
GND, or a resistive divider from CS to GND to set VADS
.
From the equation for VDEL above, if ADS is tied to GND
then VDEL rises in direct proportion to VCS, causing a de-
crease in tDELAY as the load increases. In this condition
the maximum value of VDEL is 2V. If ADS is connected to
a resistive divider between CS and GND the term
A = VADS/VCS RDELAY = 10kW
A=1.0
A=0.8
500
400
300
200
(VCS-VDS) becomes smaller, reducing the level of VDEL
.
This will decrease the amount of delay modulation. In the
limit of ADS tied to CS, VDEL=0.5V and no delay modula-
tion occurs. In the case with maximum delay modulation
(ADS=GND), when the circuit goes from light load to
heavy load the variation of VDEL is from 0.5V to 2V. This
causes the delay times to vary by a 4:1 ratio as the load
is changed.
A=0.6
A=0.4
A=0.2
A=0.1
100
0
0.5
1.0
1.5
2.0
2.5
CURRENT SENSE VOLTAGE (V)
The ability to program an adaptive delay is a desirable
feature because the optimum delay time is a function of
the current flowing in the primary winding of the trans-
former, and can change by a factor of 10:1 or more as
circuit loading changes. Reference [1] delves into the
many interrelated factors for choosing the optimum delay
times for the most efficient power conversion, and illus-
trates an external circuit to enable adaptive delay set us-
[1]
L. Balogh,
Unitrode Power
Supply Design Seminar Manual, Unitrode Corporation,
1996, Topic 2.
CLOCK
RAMP
&
COMP
PWM
SIGNAL
OUTPUT A
OUTPUT B
OUTPUT C
OUTPUT D
UDG-98138
7
UCC1895
UCC2895
UCC3895
APPLICATION INFORMATION (cont.)
IRT
Q
RT
CT
VDD
8
7
15
S
R
D
Q
Q
8(IRT
)
OSC
Q
OUTA
DELAB
OUTB
18
9
S
R
DELAY A
DELAY B
D
Q
SYNC
RAMP
6
3
Q
PWM
17
COMPARATOR
+
0.8 V
EAOUT
EAP
OUTC
2
20
1
14
DELAY C
DELAY D
D
Q
Q
S
R
ERROR
AMP
NO LOAD
COMPARATOR
10 DELCD
+
+
OUTD
13
EAN
CURRENT SENSE
COMPARATOR
+
0.5 V / 0.6 V
2 V
16 PGND
11 ADS
CS
12
OVER CURRENT
ADAPTIVE DELAY
SET AMPLIFIER
COMPARATOR
+
2.5 V
+
0.5V
Q
Q
S
R
UVLO COMPARATOR
+
REF
IRT
11 V / 9 V
DISABLE
REF
4
COMPARATOR
REF
HI=ON
HI=ON
0.5 V
REFERENCE OK
COMPARATOR
SS
19
+
+
4 V
GND
5
10(IRT
)
UDG-98140
8
UCC1895
UCC2895
UCC3895
CIRCUIT DESCRIPTION
REF
V
REF
8IRT
RT
RT
IRT
CT
2.5 V
CLOCK
S
R
Q
+
+
CT
0.2 V
SYNC
CLOCK
UDG-98141
REF
0.5 V
TO DELAY A
AND DELAY B
BLOCKS
75 kΩ
+
100 kΩ
CS
DELAB
+
100 kΩ
ADS
75 kΩ
REF
TO DELAY C
AND DELAY D
BLOCKS
DELCD
+
UDG-98142
9
UCC1895
UCC2895
UCC3895
CIRCUIT DESCRIPTION (cont.)
V
REF
BUSSED CURRENT
FROM ADS CIRCUIT
3.5V
DELAB/CD
FROM PAD
DELAYED
CLOCK
SIGNAL
2.5V
CLOCK
UDG-98143
TYPICAL CHARACTERISTIC
Vcs=0V
Vcs=2V
GAIN (dB)
PHASE MARGIN (°C)
2000
1800
1600
1400
1200
1000
800
100
80
60
40
20
0
200
160
120
80
600
400
40
200
0
0
0
10
20
30
40
1
100
10000
1000000
RDEL (kW)
FREQUENCY (Hz)
1
RT=47K
RT=62k
RT=82k
RT=100k
1600
1400
1200
1000
800
600
400
200
0
0.95
0.9
0.85
0.8
-60
-40
-20
0
20
40
60
80
100 120
100
1000
TEMPERATURE (°C)
CT (pF)
10
UCC1895
UCC2895
UCC3895
TYPICAL CHARACTERISTIC (cont.)
Vdd=10V
Vdd=12V
Vdd=15V
Vdd=17V
Vdd=10V
Vdd=12V
Vdd=15V
Vdd=17V
13
12
11
10
9
9
8
7
6
5
4
8
7
6
5
4
0
400
800
1200
1600
0
400
800
1200
1600
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (kHz)
11
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
UCC1895J
UCC1895L
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
J
20
20
20
20
20
20
20
20
20
20
20
20
20
1
None
None
None
None
None
None
None
None
None
None
None
None
A42 SNPB
Level-NC-NC-NC
LCCC
SOIC
FK
1
POST-PLATE Level-NC-NC-NC
UCC2895DW
UCC2895DWTR
UCC2895N
DW
DW
N
25
CU SNPB
CU SNPB
CU SNPB
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
Level-NA-NA-NA
SOIC
2000
20
PDIP
UCC2895PW
TSSOP
TSSOP
TSSOP
PLCC
PLCC
SOIC
PW
PW
PW
FN
70
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
UCC2895PWTR
UCC2895PWTRG4
UCC2895Q
2000
2000
46
Call TI
Call TI
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
UCC2895QTR
UCC3895DW
UCC3895DWTR
UCC3895DWTRG4
FN
1000
25
DW
DW
DW
SOIC
2000
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
UCC3895N
UCC3895PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
N
20
20
20
20
20
70
None
None
None
CU SNPB
Level-NA-NA-NA
TSSOP
TSSOP
TSSOP
PW
PW
PW
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
UCC3895PWTR
UCC3895PWTRG4
2000
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3895Q
ACTIVE
ACTIVE
PLCC
PLCC
FN
FN
20
20
46
None
None
CU SNPB
CU SNPB
Level-2-220C-1 YEAR
Level-2-220C-1 YEAR
UCC3895QTR
1000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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