UCC28C43DGK [TI]
BICMOS LOW POWER CURRENT MODE PWM CONTROLLER; BiCMOS低功耗电流模式PWM控制器型号: | UCC28C43DGK |
厂家: | TEXAS INSTRUMENTS |
描述: | BICMOS LOW POWER CURRENT MODE PWM CONTROLLER |
文件: | 总19页 (文件大小:295K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
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FEATURES
DESCRIPTION
D
Enhanced Replacement for UC3842A Family
With Pin-to-Pin Compatibility
UCC38C4x family is a high-performance current-
mode PWM controller. It is an enhanced BiCMOS
version with pin-for-pin compatibility to the
industry standard UC384xA family and UC384x
family of PWM controllers. In addition, lower
startup voltage versions of 7 V are offered as
UCC38C40 and UCC38C41.
D
D
D
D
1-MHz Operation
50-µA Standby Current, 100-µA Maximum
Low Operating Current of 2.3 mA at 52 kHz
Fast 35-ns Cycle-by-Cycle Overcurrent
Limiting
Providing necessary features to control fixed
frequency, peak current-mode power supplies,
this family offers the following performance
advantages. The device offers high-frequency
operation up to 1 MHz with low start-up and
operating currents, thus minimizing start-up loss
and low operating power consumption for
improved efficiency. The device also features a
very fast current-sense-to-output delay time of
35 ns and a 1 A peak output current capability
with improved rise and fall times for driving large
external MOSFETs directly.
D
1-A Peak Output Current
D
Rail-to-Rail Output Swings with 25-ns Rise
and 20-ns Fall Times
D
D
D
D
1% Initial Trimmed 2.5-V Error Amplifier
Reference
Trimmed Oscillator Discharge Current
New Under Voltage Lockout Versions
MSOP-8 Package Minimizes Board Space
APPLICATIONS
D
D
D
Switch-Mode Power Supplies
The UCC38C4x family is offered in 8-pin
packages, MSOP (DGK), SOIC (D) and PDIP (P).
dc-to-dc Converters
Board Mount Power Modules
FUNCTIONAL BLOCK DIAGRAM
5.0 V
VREF
8
VREF
7
5
VDD
GND
UVLO
+
VREF
GOOD LOGIC
RT/CT
4
OSC
(NOTE)
T
6
OUT
2.5 V
ERROR AMP
2R
+
S
R
Q
FB
COMP
CS
2
1
3
R
1V
Q
Note: Toggle flip−flop used only in UCC38C41, UCC38C44, and UCC38C45.
UDG−99139
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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ꢠ ꢤ ꢡ ꢠꢋ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ
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1
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
recommended operating conditions
MIN
MAX
18
UNIT
V
Input voltage, V
DD
Output voltage range, V
OUT
18
V
W
Average output current, I
OUT
200
−20
150
mA
mA
°C
W
Reference output current, I
OUT(ref)
W
Operating junction temperature, T
−55
J
¶
It is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.
}w
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
(MAX ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Output current, I
peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
OUT
Output energy, capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 µJ
Voltage rating (COMP, CS, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.3 V
(OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 20 V
(RT/CT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.3 V
(VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Error amplifier output sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Total Power Dissipation at T = 25°C: D package (θjc = 22 °C/W, θja = 40 − 70 °C/W) . . . . . . . . . . 650 mW
A
DGK package (θjc = 41 °C/W, θja = 238 − 269 °C/W . . . . . . 350 mW
P package (θjc = 50 °C/W, θja = 110 °C/W . . . . . . . . . . . . . . 850 mW
J
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature range T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground. Currents are positive into and negative out of the specified terminals. Consult the Packaging Section of
the Databook for thermal limitations and considerations of the package.
‡
§
AVAILABLE OPTIONS
SOIC−8
SMALL OUTLINE
(D){
PDIP−8
PLASTIC DIP
(P)
MSOP−8
SMALL OUTLINE
(DGK){
MAXIMUM
DUTY CYCLE
UVLO
ON/OFF
T
A
14.5V / 9.0V
8.4V / 7.6V
7.0V / 6.6V
14.5V / 9.0V
8.4V / 7.6V
7.0V / 6.6V
14.5V / 9.0V
8.4V / 7.6V
7.0V / 6.6V
14.5V / 9.0V
8.4V / 7.6V
7.0V / 6.6V
UCC28C42D
UCC28C43D
UCC28C40D
UCC28C44D
UCC28C45D
UCC28C41D
UCC38C42D
UCC38C43D
UCC38C40D
UCC38C44D
UCC38C45D
UCC38C41D
UCC28C42P
UCC28C43P
UCC28C40P
UCC28C44P
UCC28C45P
UCC28C41P
UCC38C42P
UCC38C43P
UCC38C40P
UCC38C44P
UCC38C45P
UCC38C41P
UCC28C42DGK
UCC28C43DGK
UCC28C40DGK
UCC28C44DGK
UCC28C45DGK
UCC28C41DGK
UCC38C42DGK
UCC38C43DGK
UCC38C40DGK
UCC38C44DGK
UCC38C45DGK
UCC38C41DGK
100%
50%
−40°C to 105°C
100%
50%
0°C to 70°C
†
D (SOIC−8) and DGK (MSOP−8) packages are available taped and reeled. Add R suffix to device type (e.g.
UCC28C42DR) to order quantities of 2500 devices per reel. Tube quantities are 75 for D packages (SOIC−8) and
80 for DGK package (MSOP−8), and 50 for P package (PDIP-8).
2
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ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢂ ꢃꢁ ꢄꢉ
ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢅ ꢆ ꢀ ꢁꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢈ ꢃꢁ ꢄꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
electrical characteristics V
= 15 V (See Note 1), R = 10 kΩ, C = 3.3 nF, C
= 0.1µF and no load
DD
T
T
A
VDD
on the outputs, T = −40°C to 105°C for the UCC28C4x and T = 0°C to 70°C for the UCC38C4x,
A
T = T (unless otherwise noted)
A
J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Section
Output voltage, initial accuracy
Line regulation
T
= 25°C
I
= 1mA
4.9
5.0
5.1
20
V
mV
mV
mV/°C
V
A
OUT
V
= 12 V to 18 V
0.2
3
DD
Load regulation
1mA to 20mA
See Note 2
25
Temperature stability
Total output variation
Output noise voltage
Long term stability
Output short circuit
Oscillator Section
Initial accuracy
0.2
0.4
5.18
See Note 2
4.82
10 Hz to 10 kHz,
1000 hours,
T
A
= 25°C,
See Note 2
See Note 2
50
5
µV
T
A
= 125°C,
25
mV
mA
–30
–45
–55
T
A
= 25°C,
See Note 3
See Note 2
50.5
53
0.2%
1%
55
1.0%
2.5%
kHz
Voltage stability
V
= 12 V to 18 V
DD
Temperature stability
Amplitude
T
MIN
to T ,
MAX
RT/CT Pin peak-to-peak
1.9
V
T
= 25°C,
RT/CT = 2 V,
See Note 4
See Note 4
7.7
7.2
8.4
9.0
9.5
mA
mA
A
Discharge current
RT/CT = 2 V,
8.4
Error Amplifier Section
Feedback input voltage, initial accuracy
Feedback input voltage, total variation
Input bias current
V
V
V
V
= 2.5 V,
= 2.5 V,
T
= 25°C
2.475
2.45
2.500
2.50
–0.1
90
2.525
2.55
–2.0
V
V
COMP
A
COMP
= 5.0 V
µA
dB
MHz
dB
mA
mA
V
FB
Open-loop voltage gain (A
Unity gain bandwidth
)
= 2 V to 4 V
65
1.0
60
VOL
OUT
See Note 2
1.5
Power supply rejection ratio (PSRR)
Output sink current
V
DD
V
FB
V
FB
V
FB
V
FB
= 12 V to 18 V
= 2.7 V,
V
V
= 1.1 V
2
14
–1.0
6.8
COMP
Output source current
High-level output voltage (VOH)
Low-level output voltage (VOL)
Current Sense Section
Gain
= 2.3 V,
= 5V
–0.5
5
COMP
= 2.7 V,
R
R
= 15 k to GND
= 15 k to VREF
LOAD
LOAD
= 2.7 V,
0.1
1.1
V
See Note 5, 6
V < 2.4 V
2.85
0.9
3.00
1.0
3.15
1.1
V/V
V
Maximum input signal
Power supply rejection ratio (PSRR)
Input bias current
FB
VDD = 12 V to 18 V, See Note 2, 5
70
dB
µA
ns
V
–0.1
35
–2.0
70
CS to output delay
COMP to CS offset
V
= 0 V
1.15
CS
above the start threshold before setting at 15 V.
NOTE: 1. Adjust V
DD
NOTE: 2. Ensured by design. Not production tested.
NOTE: 3. Output frequencies of the UCC38C41, UCC38C44 and the UCC38C45 are half the oscillator frequency.
NOTE: 4. Oscillator discharge current is measured with R = 10 kΩ to V
T
REF.
NOTE: 5. Parameter measured at trip point of latch with V
= 0 V.
FB
DV
COM
NOTE: 6. Gain is defined as ACS +
, 0V ¬ V
¬ 900mV
CS
DV
CS
3
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
electrical characteristics V
= 15 V (See Note 1), R = 10 kΩ, C = 3.3 nF, C
= 0.1µF and no load
DD
T
T
A
VDD
on the outputs, T = −40°C to 105°C for the UCC28C4x and T = 0°C to 70°C for the UCC38C4x,
A
T = T (unless otherwise noted)
A
J
PARAMETER
Output Section
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
V
low (R
pull-down)
pull-up)
I
I
= 200 mA
5.5
15
25
50
40
OUT
DS(on)
SINK
Ω
high (R
= 200 mA
10
25
20
OUT
DS(on)
SOURCE
Rise tIme
Fall time
T
= 25°C,
= 25°C,
C
= 1 nF
= 1 nF
A
LOAD
C
LOAD
ns
T
A
Undervoltage Lockout Section
UCC38C42, UCC38C44
UCC38C43, UCC38C45
UCC38C40, UCC38C41
UCC38C42, UCC38C44
UCC38C43, UCC38C45
UCC38C40, UCC38C41
13.5
14.5
8.4
7.0
9
15.5
9.0
7.5
10
7.8
6.5
8
Start threshold
V
7.0
6.1
7.6
6.6
8.2
7.1
Minimum operating voltage
PWM Section
UCC38C42, UCC38C43, UCC38C40, V
UCC38C44, UCC38C45, UCC38C41, V
< 2.4 V
< 2.4 V
94%
47%
96%
48%
FB
Maximum duty cycle
FB
Minimum duty cycle
V
FB
> 2.6 V
0%
Current Supply Section
Start-up current (I
)
V
V
= Undervoltage lockout start threshold (−0.5 V)
50
100
3.0
µA
START-UP
DD
Operating supply current (I
)
= V
CS
= 0 V
2.3
mA
DD
FB
NOTE 1: Adjust V
DD
above the start threshold before setting at 15 V.
PDIP (P) or SOIC (D) PACKAGE
(TOP VIEW)
MSOP (DGK) PACKAGE
(TOP VIEW)
COMP
FB
VREF
VDD
OUT
GND
8
7
6
5
1
2
3
4
COMP
FB
VREF
VDD
OUT
GND
1
2
3
4
8
7
6
5
CS
CS
RT/CT
RT/CT
4
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ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢂ ꢃꢁ ꢄꢉ
ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢅ ꢆ ꢀ ꢁꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢈ ꢃꢁ ꢄꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
pin assignments
COMP: This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is
frequently used as a control port by utilizing a secondary-side error amplifier to send an error signal across the
secondary-primary isolation boundary through an opto-isolator.
CS: The current sense pin is the non-inverting input to the PWM comparator. This is compared to a signal
proportional to the error amplifier output voltage. A voltage ramp can be applied to this pin to run the device with
a voltage mode control configuration.
FB: This pin is the inverting input to the error amplifier. The non-inverting input to the error amplifier is internally
trimmed to 2.5 V 1%.
GND: Ground return pin for the output driver stage and the logic level controller section.
OUT: The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the
UCC38C40, UCC38C42 and UCC38C43 is the same frequency as the oscillator, and can operate near 100%
duty cycle. In the UCC38C41, UCC38C44 and the UCC38C45, the frequency of OUT is one-half that of the
oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%.
RT/CT: Timing resistor and timing capacitor. The timing capacitor should be connected to the device ground
using minimal trace length.
VDD: Power supply pin for the device. This pin should be bypassed with a 0.1-µF capacitor with minimal trace
lengths. Additional capacitance may be needed to provide hold up power to the device during startup.
VREF: 5-V reference. For stability, the reference should be bypassed with a 0.1-µF capacitor to ground using
the minimal trace length possible.
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
This device is a pin-for-pin replacement of the bipolar UC3842 family of controllers, the industry standard PWM
controller for single-ended converters. Familiarity with this controller family is assumed.
The UCC28C4x/UCC38C4x series is an enhanced replacement with pin-to-pin compatibility to the bipolar
UC284x/UC384x and UC284xA/UC384xA families. The new series offers improved performance when
compared to older bipolar devices and other competitive BiCMOS devices with similar functionality. Note that
these improvements discussed below generally consist of tighter specification limits that are a subset of the
older product ratings, maintaining drop-in capability. In new designs these improvements can be utilized to
reduce the component count or enhance circuit performance when compared to the previously available
devices.
advantages
This device increases the total circuit efficiency whether operating off-line or in dc input circuits. In off-line
applications the low start-up current of this device reduces steady state power dissipation in the startup resistor,
and the low operating current maximizes efficiency while running. The low running current also provides an
efficiency boost in battery operated supplies.
low voltage operation
Two members of the UCC38C4x family are intended for applications that require a lower start-up voltage than
the original family members. The UCC38C40 and UCC38C41 have a turn-on voltage of 7.0 V typical and exhibit
hysteresis of 0.4 V for a turn-off voltage of 6.6 V. This reduced start-up voltage enables use in systems with lower
voltages, such as 12-V battery systems which are nearly discharged.
high speed operation
The BiCMOS design allows operation at high frequencies that were not feasible in the predecessor bipolar
devices. First, the output stage has been redesigned to drive the external power switch in approximately half
the time of the earlier devices. Second, the internal oscillator is more robust with less variation as frequency
increases. In addition, the current sense to output delay has been reduced by a factor of three, to 45ns typical.
These features combine to provide a device capable of reliable high frequency operation.
The UCC38C4x family oscillator is true to the curves of the original bipolar devices at lower frequencies yet
extends the frequency programmability range to at least 1MHz. This allows the device to offer pin to pin
capability where required yet capable of extending the operational range to the higher frequencies typical of
latest applications. When the original UC3842 was released in 1984 most switching supplies operated between
20kHz and 100kHz. Today, the UCC38C4x can be used in designs cover a span roughly ten times higher than
those numbers.
start/run current improvements
The start−up current is only 60 µA typical, a significant reduction from the bipolar device’s ratings of 300uA
(UC384xA). For operation over the temperature range of −40 to 85°C the UCC28C4x devices offer a maximum
startup current of 100 µA, an improvement over competitive BiCMOS devices. This allows the power supply
designer to further optimize the selection of the startup resistor value to provide a more efficient design. In
applications where low component cost overrides maximum efficiency the low run current of 2.3 mA, typical,
may allow the control device to run directly through the single resistor to (+) rail, rather than needing a bootstrap
winding on the power transformer, along with a rectifier. The start/run resistor for this case must also pass
enough current to allow driving the primary switching MOSFET, which may be a few milliamps in small devices.
6
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ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢂ ꢃꢁ ꢄꢉ
ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢅ ꢆ ꢀ ꢁꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢈ ꢃꢁ ꢄꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
1% initial reference voltage
The BiCMOS internal reference of 2.5 V has an enhanced design and utilizes production trim to allow initial
accuracy of 1% at room temperature and 2% over the full temperature range. This can be used to eliminate
an external reference in applications that do not require the extreme accuracy afforded by the additional device.
This is very useful for nonisolated dc-to-dc applications where the control device is referenced to the same
common as the output. It is also applicable in offline designs that regulate on the primary side of the isolation
boundary by looking at a primary bias winding, or perhaps from a winding on the output inductor of a
buck-derived circuit.
reduced discharge current variation
The original UC3842 oscillator did not have trimmed discharged current, and the parameter was not specified
on the datasheet. Since many customers attempted to use the discharge current to set a crude deadtime limit
the UC3842A family was released with a trimmed discharge current specified at 25°C. The
UCC28C4x/UCC38C4x series now offers even tighter control of this parameter, with approximately 3%
accuracy at 25°C, and less than 10% variation over temperature using the UCC28C4x devices. This level of
accuracy can enable a meaningful limit to be programmed, a feature not currently seen in competitive BiCMOS
devices. The improved oscillator and reference also contribute to decreased variation in the peak to peak
variation in the oscillator waveform, which is often used as the basis for slope compensation for the complete
power system.
soft-start
The following diagram provides a typical soft-start circuit for use with the UCC38C42. The values of R and C
should be selected to bring the COMP pin up at a controlled rate, limiting the peak current supplied by the power
stage. After the soft-start interval is complete the capacitor continues to charge to V
the PNP transistor from circuit considerations.
, effectively removing
REF
The optional diode in parallel with the resistor forces a soft-start each time the PWM goes through UVLO and
the reference (V ) goes low. Without the diode,the capacitor otherwise remains charged during a brief loss
REF
of supply or brown-out, and no soft-start is enabled upon reapplication of VIN.
8
1
V
REF
UCC38C42
COMP
GND
5
Figure 1
UDG−01072
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
oscillator synchronization
The UCC38C4x oscillator has the same synchronization characteristics as the original bipolar devices. Thus,
the information in the Application Note U−100A, UC3842/3/4/5 Provides Low-Cost Current-Mode Control, (TI
Literature No. SLUA143) still applies. The application note describes how a small resistor from the timing
capacitor-to-ground can offer an insertion point for synchronization to an external clock, (see Figures 2 and 3).
Figure 2 shows how the UCC38C42 can be synchronized to an external clock source. This allows precise
control of frequency and dead time with a digital pulse train.
8
4
V
REF
R
T
SYNCHRONIZATION
CIRCUIT INPUT
R / C
T
T
C
T
UCC38C42
PWM
W
24
UDG−01069
Figure 2. Oscillator Synchronization Circuit
UPPER THRESHOLD
LOWER THRESHOLD
CLOCK
INPUT
LOW
HIGH
OFF .
LOW
ON .
PWM
OUT
ON .
OUTPUT A
VCT (ANALOG)
UPPER THRESHOLD
VCT
LOWER THRESHOLD
VSYNC (DIGITAL)
COMBINED
UDG−01070
Figure 3. Synchronization to an External Clock
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ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢂ ꢃꢁ ꢄꢉ
ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢅ ꢆ ꢀ ꢁꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢈ ꢃꢁ ꢄꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
precautions
The absolute maximum supply voltage is 20 V, including any transients that may be present. If this voltage is
exceeded, device damage is likely. This is in contrast to the predecessor bipolar devices, which could survive
up to 30 V. Thus, the supply pin should be decoupled as close to the ground pin as possible. Also, since no clamp
is included in the device, the supply pin should be protected from external sources which could exceed the 20 V
level.
Careful layout of the printed board has always been a necessity for high frequency power supplies. As the device
switching speeds and operating frequencies increase the layout of the converter becomes increasingly
important.
This 8-pin device has only a single ground for the logic and power connections. This forces the gate drive current
pulses to flow through the same ground that the control circuit uses for reference. Thus, the interconnect
inductance should be minimized as much as possible. One implication is to place the device (gate driver)
circuitry close to the MOSFET it is driving. Note that this can conflict with the need for the error amplifier and
the feedback path to be away from the noise generating components.
circuit applications
Figure 4 shows a typical off-line application.
D50
F1
12 V
OUT
T1
R10
C52
C55
C3
D2
C12
AC INPUT
100 Vac − 240 Vac
EMI FILTER
+
R56
BR1
L50
R11
D51
REQUIRED
C1A
C18
5 V
R12
OUT
RT1
C53
C54
D6
R55
C5
SEC
COMMON
R6
R50
UCC38C44
R16
1
2
3
4
COMP REF
8
7
6
5
IC2
Q1
IC2
FB
CS
VCC
OUT
R53
C50
R52
C13
C51
R50
RT/CT GND
K
IC3
A
R
R54
UDG−01071
Figure 4. Typical Off-Line Application
Figure 5 shows the forward converter with synchronous rectification. This application provides 48 V to 3.3 V at
10 A with over 85% efficiency and uses the UCC38C42 as the secondary-side controller and UCC3961 as the
primary-side startup control device.
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
+
+
+
+
Figure 5. Forward Converter with Synchronous Rectification Using the UCC38C42
as the Secondary-Side Controller
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ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢂ ꢃꢁ ꢄꢉ
ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢅ ꢆ ꢀ ꢁꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢈ ꢃꢁ ꢄꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
OSCILLATOR DISCHARGE CURRENT
vs
vs
TIMING RESISTANCE AND CAPACITANCE
TEMPERATURE
9.5
9.0
8.5
10 M
1 M
CT = 220 pF
CT = 470 pF
CT = 1 nF
100 k
10 k
1 k
8.0
7.5
7.0
CT = 4.7 nF
CT = 2.2 nF
1 k
10 k
100 k
−50
−25
0
25
50
75
100
125
T
J
− Temperature − °C
R
− Timing Resistance − W
T
Figure 6
Figure 7
COMP to CS OFFSET VOLTAGE (with CS = 0)
ERROR AMPLIFIER
FREQUENCY RESPONSE
vs
TEMPERATURE
100
1.8
200
180
1.6
1.4
90
80
70
60
50
40
30
20
10
0
160
140
GAIN
1.2
1.0
0.8
0.6
0.4
0.2
0.0
120
100
80
60
40
PHASE
MARGIN
20
0
1
10
100
1 k 10 k 100 k 1 M 10 M
−50
−25
0
25
50
75
100
125
f − Frequency − Hz
T
J
− Temperature − °C
Figure 8
Figure 9
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
REFERENCE VOLTAGE
vs
ERROR AMPLIFIER REFERENCE VOLTAGE
vs
TEMPERATURE
TEMPERATURE
2.55
2.54
5.05
5.04
5.03
5.02
5.01
2.53
2.52
2.51
2.50
2.49
5.00
4.99
4.98
4.97
4.96
4.95
2.48
2.47
2.46
2.45
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T
J
− Temperature − °C
T
J
− Temperature − °C
Figure 11
Figure 10
REFERENCE SHORT-CIRCUIT CURRENT
ERROR AMPLIFIER INPUT BIAS CURRENT
vs
vs
TEMPERATURE
TEMPERATURE
200
−35
−37
−39
−41
−43
−45
−47
−49
−51
−53
−55
150
100
50
0
−50
−100
−150
−200
−50
−25
0
25
− Temperature − °C
J
50
75
100
125
−50
−25
0
T
25
50
75
100
125
T
− Temperature − °C
J
Figure 13
Figure 12
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ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢂ ꢃꢁ ꢄꢉ
ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢅ ꢆ ꢀ ꢁꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢈ ꢃꢁ ꢄꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
UNDERVOLTAGE LOCKOUT
UNDERVOLTAGE LOCKOUT
vs
vs
TEMPERATURE (UCC38C43 & UCC38C45)
TEMPERATURE (UCC38C42 & UCC38C44)
16
9.0
8.8
UVLO
ON
15
14
13
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
UVLO
ON
12
11
UVLO
OFF
10
9
8
UVLO
OFF
7
6
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T
J
− Temperature − °C
T
J
− Temperature − °C
Figure 14
Figure 15
UNDERVOLTAGE LOCKOUT
vs
TEMPERATURE (UCC38C40 & UCC38C41)
7.3
7.2
UVLO
ON
7.1
7.0
6.9
6.8
6.7
6.6
6.5
6.4
UVLO
OFF
6.3
−50
−25
0
25
50
75
100
125
T
J
− Temperature − °C
Figure 16
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT
vs
OSCILLATOR FREQUENCY
3.0
2.9
25
20
15
10
1-nF LOAD
2.8
2.7
2.6
2.5
2.4
NO LOAD
NO LOAD
2.3
2.2
5
0
2.1
2.0
−50
−25
0
25
50
75
100
125
0 k
200 k
400 k
600 k
800 k
1 M
f − Frequency − Hz
T
J
− Temperature − °C
Figure 17
Figure 18
OUTPUT RISE TIME AND FALL TIME
MAXIMUM DUTY CYCLE
vs
vs
TEMPERATURE
OSCILLATOR FREQUENCY
40
100
10% to 90%
V
DD
= 12 V
35
CT = 220 pF
tr
90
80
(1 nF)
30
25
20
tf
(1 nF)
70
60
CT = 1 nF
15
10
50
0
500
1000
1500
−50
−25
0
25
50
75
100
125
2000
2500
T
J
− Temperature − °C
f − Frequency − kHz
Figure 19
Figure 20
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ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢂ ꢃꢁ ꢄꢉ
ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢅ ꢆ ꢀ ꢁꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢂ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁ ꢁꢈ ꢃꢁ ꢄꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
MAXIMUM DUTY CYCLE
vs
MAXIMUM DUTY CYCLE
vs
TEMPERATURE
TEMPERATURE
100
98
96
94
92
90
50
UCC38C40
UCC38C42
UCC38C43
UCC38C41
UCC38C44
UCC38C45
49
48
47
46
45
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
T
J
− Temperature − °C
T
J
− Temperature − °C
Figure 21
Figure 22
CURRENT SENSE THRESHOLD VOLTAGE
CS TO OUT DELAY TIME
vs
vs
TEMPERATURE
TEMPERATURE
1.10
70
65
60
55
50
45
40
35
30
1.05
1.00
0.95
0.90
−50
−25
0
25
50
75
100
125
−50
−25
0
T
25
50
75
100
125
T
J
− Temperature − °C
− Temperature − °C
J
Figure 23
Figure 24
15
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ꢀ
ꢁꢁ
ꢂ
ꢃ
ꢁ
ꢄꢅ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃ
ꢁ
ꢄ
ꢇ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃ
ꢁ
ꢄ
ꢂ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃꢁ
ꢄ
ꢈ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃꢁ
ꢄ
ꢄ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃꢁ
ꢄ
ꢉ
ꢀ
ꢁꢁ
ꢈ
ꢃ
ꢁ
ꢄꢅ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃ
ꢁ
ꢄ
ꢇ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃ
ꢁ
ꢄ
ꢂ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃ
ꢁ
ꢄ
ꢈ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃꢁ
ꢄ
ꢄ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃꢁ
ꢄ
ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
MECHANICAL DATA
D (SOIC)
PLASTIC SMALL-OUTLINE PACKAGE
Note: UCC38C4x is offered in an 8-pin package ONLY.
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°−ā8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
16
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ꢀ
ꢁ
ꢁ
ꢂ
ꢃ
ꢁ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃꢁ
ꢄ
ꢇ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃꢁ
ꢄ
ꢂ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃꢁ
ꢄ
ꢈ
ꢆ
ꢀ
ꢁ
ꢁ
ꢂ
ꢃꢁ
ꢄ
ꢄ
ꢆ
ꢀ
ꢁ
ꢁꢂ
ꢃ
ꢁ
ꢄ
ꢉ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃ
ꢁ
ꢄ
ꢅ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃ
ꢁ
ꢄ
ꢇ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃꢁ
ꢄ
ꢂ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃꢁ
ꢄ
ꢈ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃ
ꢁ
ꢄ
ꢄ
ꢆ
ꢀ
ꢁ
ꢁ
ꢈ
ꢃ
ꢁ
ꢄ
ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
M
0,65
8
0,25
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°−ā6°
1
4
0,69
3,05
2,95
0,41
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073329/B 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
17
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ꢀ ꢁꢁꢂ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢈ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢂ ꢃꢁ ꢄ ꢉ
ꢀ ꢁꢁꢈ ꢃ ꢁ ꢄꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢁꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢂ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢁꢄ ꢈ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢄ ꢆ ꢀꢁꢁ ꢈ ꢃꢁ ꢄ ꢉ
SLUS458C − AUGUST 2001 − REVISED SEPTEMBER 2003
MECHANICAL DATA
P (PDIP)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.430 (10,92)
MAX
0.010 (0,25)
M
0.015 (0,38)
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
18
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