UCC28C57HQDRQ1_技术文档

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

UCC28C5x-Q1 适用于Si 和SiC MOSFET 的汽车类低功耗、电流模式、高性能

PWM 控制器

1 特性

3 说明

• 支持Si 和SiC MOSFET 应用的欠压锁定选项

• 30V VDD 绝对最大电压

• 1MHz 最大固定频率工作

• 50μA 启动电流，最大值75μA

• 低工作电流：1.3mA（f_OSC= 52kHz）

• 高工作T_J：150°C（最大值）

• 35ns 快速逐周期过流限制

• 峰值驱动电流为±1A

UCC28C5x-Q1 系列器件为高性能电流模式PWM 控制

器，可用于驱动各种应用中的 Si 和 SiC MOSFET。

UCC28C5x-Q1 系列是 UCC28C4x-Q1 的更高效、更

稳健的版本。

除持续支持 Si MOSFET 的现有 UVLO 阈值

(UCC28C50-55-Q1) 外，UCC28C5x-Q1 系列还具有

可确保 SiC MOSFET 可靠运行的新 UVLO 阈值

(UCC28C56-59-Q1)。

• 轨到轨输出：

VDD 绝对最大额定电压从 20V 增加至 30V，便于以理

想方式驱动 20Vgs、18Vgs 或15Vgs SiC MOSFET 的

栅极，同时可无需使用外部LDO。

– 25ns 上升时间

– 20ns 下降时间

• 精度为±1% 的2.5V 误差放大器基准

• 与UCC28C4x-Q1 引脚对引脚兼容的可直接替代产

品

器件性能改进

UCC28C4x-Q1 UCC28C5x-Q1

参数

52kHz 时的电源电流

启动电流（上限值）

VDD 绝对上限值

• 提供功能安全

2.3mA

100µA

20V

1.3mA

75µA

– 可帮助进行功能安全系统设计的文档

• 具有符合AEC-Q100 标准的下列特性

30V

– 器件温度等级1：-40°C 至125°C

– 器件HBM 分类等级2：±2kV

– 器件CDM 分类等级C4B：750 V

±2%

±1%

基准电压精度

Si FET 的UVLO 和D_MAX

SiC FET 的UVLO 和D_MAX

6 个选项

none

6 个选项

2 应用

1. 如需了解所有可用封装，请参阅数据表末尾的可订

购产品附录。

• 牵引逆变器高压转低压备用电源

• OBC 和直流/直流转换器隔离式偏置电源

• HVAC 压缩机高压隔离式电源

• 交流和直流EV 充电设备中的单端直流转换器

D_CLAMP

C_SNUB

R_SNUB

D_OUT

V

IN

V_OUT

N_S

C

IN

N_P

N_A

R_START

C_OUT

C_SS

D_BIAS

R_VDD

R_SS

C_VDD

1

2

3

4

COMP

FB

VREF

VDD

OUT

GND

8

7

6

5

R_COMPp

C_COMPp

R_G

CS

R_RT

Q_SW

R_CS

RT/CT

R_BLEEDER

D_ZC_VDDbpC_VREF

C_CT

C_RAMP

R_CSF

R_DIS

R_RAMP

R_FBU

C_CSF

R_FBB

图3-1. 典型汽车应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

Table of Contents

8.4 Device Functional Modes..........................................25

9 Application and Implementation..................................26

9.1 Application Information............................................. 26

9.2 Typical Application.................................................... 26

9.3 PCB Layout Recommendations ........................... 41

9.4 Power Supply Recommendations.............................47

10 Device and Documentation Support..........................48

10.1 Device Support....................................................... 48

10.2 Documentation Support.......................................... 48

10.3 Related Links.......................................................... 48

10.4 支持资源..................................................................48

10.5 Trademarks.............................................................48

10.6 静电放电警告.......................................................... 48

10.7 术语表..................................................................... 48

11 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 5

7.1 Absolute Maximum Ratings........................................ 5

7.2 ESD Ratings............................................................... 5

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................6

7.5 Electrical Characteristics.............................................7

7.6 Typical Characteristics................................................9

8 Detailed Description......................................................13

8.1 Overview...................................................................13

8.2 Functional Block Diagram.........................................14

8.3 Feature Description...................................................14

Information.................................................................... 48

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (February 2023) to Revision C (March 2023)

Page

• UCC28C58-Q1 器件的初始发行版..................................................................................................................... 1

• Updated Available Options Table........................................................................................................................3

• Added Link to Technical Support ..................................................................................................................... 48

Changes from Revision A (October 2022) to Revision B (February 2023)

Page

• UCC28C55-Q1、UCC28C56L-Q1、UCC28C57L-Q1 和UCC28C57H-Q1 器件的初始发行版.........................1

Changes from Revision * (June 2022) to Revision A (October 2022)

Page

• UCC28C59-Q1 器件的初始发行版..................................................................................................................... 1

• Updated Available Options Table........................................................................................................................3

• Updated Electrical Characteristics section ........................................................................................................ 7

• Updated Typical Characteristics section ............................................................................................................9

• Updated Application Information section ......................................................................................................... 26

2

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

5 Device Comparison Table

UVLO

MAXIMUM

DUTY

CYCLE

TURN ON AT 14.5 V

TURN OFF AT 9 V

SUITABLE FOR OFF-LINE

APPLICATIONS

TURN ON AT 8.4 V

TURN OFF AT 7.6 V

SUITABLE FOR DC/DC

APPLICATIONS

TURN ON AT 7 V

TURN OFF AT 6.6 V

SUITABLE FOR BATTERY

APPLICATIONS

TEMPERATURE (T_A)

UCC28C52QDRQ1

UCC28C54QDRQ1

UCC28C53QDRQ1

UCC28C55QDRQ1

UCC28C50QDRQ1

UCC28C51QDRQ1

100%

50%

–40°C to 125°C

UVLO

TURN ON AT 18.8 V TURN

OFF AT 14.5V

TURN ON AT 16 V TURN

OFF AT 12.5V

MAXIMUM

DUTY

CYCLE

TURN ON AT 18.8 V

TURN OFF AT 15.5V

Suitable for HV applications

using GEN-I SiC MOSFET

TEMPERATURE (T_A)

Suitable for HV applications Suitable for HV applications

using GEN-II SiC MOSFET using GEN-III SiC MOSFET

UCC28C56HQDRQ1

UCC28C57HQDRQ1

UCC28C56LQDRQ1

UCC28C57LQDRQ1

UCC28C58QDRQ1

UCC28C59QDRQ1

100%

50%

–40°C to 125°C

BODY SIZE (NOM)

4.90 mm × 3.91 mm

Device Information1

PART NUMBER

PACKAGE

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1

UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1

UCC28C56H-Q1, UCC28C56L-Q1

SOIC (8)

UCC28C57H-Q1, UCC28C57L-Q1

UCC28C58-Q1, UCC28C59-Q1

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

6 Pin Configuration and Functions

COMP

FB

1

2

3

4

8

7

6

5

VREF

VDD

OUT

GND

CS

RT/CT

Not to scale

图6-1. D Package 8-Pin SOIC Top View

表6-1. Pin Functions

I/O

DESCRIPTION

NAME

NO.

This pin provides the output of the error amplifier for compensation. In addition, the COMP pin is frequently

used as a control port, by utilizing a secondary-side error amplifier to send an error signal across the

secondary-primary isolation boundary through an opto-isolator. The error amplifier is internally current limited

so the user can command zero duty cycle by externally forcing COMP to GND.

COMP

1

O

Primary-side current sense pin. The current sense pin is the noninverting input to the PWM comparator.

Connect to current sensing resistor. This signal is compared to a signal proportional to the error amplifier

output voltage. The PWM uses this to terminate the OUT switch conduction. A voltage ramp can be applied to

this pin to run the device with a voltage mode control configuration.

CS

3

I

This pin is the inverting input to the error amplifier. FB is used to control the power converter voltage-feedback

loop for stability. The noninverting input to the error amplifier is internally trimmed to 2.5 V ±1%.

FB

2

5

I

GND

Ground return pin for the output driver stage and the logic level controller section.

—

The output of the on-chip drive stage. OUT is intended to directly drive a MOSFET. The OUT pin in the

UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L-Q1, and UCC28C58-Q1 is the same

frequency as the oscillator, and can operate near 100% duty cycle. In the UCC28C51-Q1, UCC28C54-Q1,

UCC28C55-Q1, UCC28C57H/L-Q1, and UCC28C59-Q1, the frequency of OUT is one-half that of the

oscillator due to an internal T flipflop. This limits the maximum duty cycle to < 50%. Peak currents of up to 1 A

are sourced and sunk by this pin. OUT is actively held low when VDD is below the turn-on threshold.

OUT

6

O

Fixed frequency oscillator set point. Connect timing resistor (R_RT) to VREF and timing capacitor (C_CT) to GND

from this pin to set the switching frequency. For best performance, keep the timing capacitor lead to the device

GND as short and direct as possible. If possible, use separate ground traces for the timing capacitor and all

other functions. The switching frequency (fSW) of the UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1,

UCC28C56H/L and UCC28C58 gate drive is equal to fOSC; the switching frequency of the UCC28C51-Q1,

RT/CT

4

I/O

UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and UCC28C59-Q1 is equal to half of the f_OSC

.

Analog controller bias input that provides power to the device. Total VDD current is the sum of the quiescent

VDD current and the average OUT current. A bypass capacitor, typically 0.1 µF, connected directly to GND

with minimal trace length, is required on this pin. Additional capacitance at least 10 times greater than the gate

capacitance of the main switching FET used in the design and 10 times greater than the capacitance on the

VREF pin are also required on VDD.

VDD

7

8

I

5-V reference voltage. VREF is used to provide charging current to the oscillator timing capacitor through the

timing resistor. It is important for reference stability that VREF is bypassed to GND with a ceramic capacitor

connected as close to the pin as possible. A minimum value of 0.1 µF ceramic is required. Additional VREF

bypassing is required for external loads on VREF. No external voltage higher than specified VREF is allowed

to superimposed to VREF pin Since VREF is an ouput.

VREF

O

4

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

MAX

30

UNIT

V

Input voltage

VDD

I_VDD

Input current

30

mA

A

Output drive current (peak)

Output energy (capacitive load), E_OUT

Analog input voltage

±1

5

µJ

COMP, CS, FB, RT/CT

OUT

6.3

30

–0.3

V

Output driver voltage

Reference voltage

VREF

7

Error amplifier output sink current

Total power dissipation at T_A= 25°C

Lead temperature (soldering, 10 s), T_LEAD

Operating junction temperature, T_J

Storage temperature, T_stg

COMP

10

mA

°C/W

°C

D package

72.3

300

150

°C

–40

–65

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under 节7.3.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND pin. Currents are positive into and negative out of the specified terminals.

7.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per AEC Q100-011 节7.2

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

V

V_VDD

Input voltage

28

V_OUT

Output driver voltage

Average output driver current⁽¹⁾

Reference output current⁽¹⁾

V

I_OUT

200

–20

mA

I_OUT(VREF)

T_J

Operating junction temperature⁽¹⁾

Operating ambient temperature⁽¹⁾

UCC28C5x-Q1

150

125

°C

–40

T_A

(1) TI recommends against operating the device under conditions beyond those specified in this table for extended periods of time.

7.4 Thermal Information

UCC28C5x-Q1

THERMAL METRIC⁽¹⁾

UNIT

D (SOIC) 8 PINS

R_θJA

Junction-to-ambient thermal resistance

128.9

71.7

72.3

23.4

71.5

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

R_θJB

ψ_JT

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor anddevicePackage Thermal Metrics

application report.

6

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

7.5 Electrical Characteristics

V_VDD= 20 V ⁽¹⁾(for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1), V_VDD= 15 V⁽¹⁾(for the rest), R_RT= 10 kΩ,

C_CT= 3.3 nF, C_VDD= 0.1 µF and no load on the outputs, T_J= –40°C to 150°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

REFERENCE

V_VREF

VREF voltage, initial accuracy

Line regulation

I_OUT= 1 mA

4.95

5

0.2

3

5.05

20

V

V_VDD= 12 V to 25 V

1 mA to 20 mA

mV

Load regulation

25

Temperature stability

Total output variation

VREF noise voltage

See ⁽²⁾

0.2

0.4 mV/°C

See ⁽²⁾

4.82

30

5.18

V

10 Hz to 10 kHz, T_J= 25°C, see ⁽²⁾

1000 hours, T_J= 150°C, see ⁽²⁾

50

5

µV

mV

mA

Long term stability

25

55

I_VREF

Output short circuit (source current)

45

OSCILLATOR

T_J= 25°C, see ⁽³⁾

50.5

53

55 kHz

57 kHz

1%

f_OSCInitial accuracy

T_J= Full Range, see ⁽³⁾

Voltage stability

Temperature stability

Amplitude

0.2%

12 V ≤V_VDD≤25 V

T_J(MIN)to T_J(MAX), see ⁽²⁾

RT/CT pin peak-to-peak voltage

T_J= 25°C, V_RT/CT= 2 V, see ⁽⁴⁾

T_J= Full Range, V_RT/CT= 2 V, see ⁽⁴⁾

1% 2.5%

1.9

8.4

V

Discharge current

7.7

7.2

9

mA

9.5

ERROR AMPLIFIER

V_FB

Feedback input voltage, initial accuracy T_J= 25°C, V_COMP= 2.5 V

2.475

2.45

2.5 2.525

V

Feedback input voltage, total variation T_J= Full Range, V_COMP= 2.5 V

2.5

0.1

90

2.55

2

I_FB

Input bias current

V_FB= 5 V, (sourcing current)

µA

dB

A_VOL

Open-loop voltage gain

Unity gain bandwidth

Power supply rejection ratio

Output sink current

65

1

2 V ≤V_OUT≤4 V

See ⁽²⁾

1.5

MHz

dB

PSRR

60

2

12 V ≤V_VDD≤25 V

V_FB= 2.7 V, V_COMP= 1.1 V

V_FB= 2.3 V, V_COMP= 5 V, (sourcing current)

14

1

mA

Output source current

0.5

V_REF

–

VOH

VOL

High-level COMP voltage

Low-level COMP voltage

V

V_FB= 2.7 V, R_COMP= 15 kΩCOMP to GND

V_FB= 2.7 V, R_COMP= 15 kΩCOMP to VREF

0.2

0.1

1.1

CURRENT SENSE

T_J= 25°C, See ⁽⁵⁾

T_J= Full Range, See ⁽⁵⁾

V_FB< 2.4 V

2.85

2.75

0.9

3

3.15

1.1

V/V

V

A_CS

Gain

V_CS

PSRR

I_CS

Maximum input signal

1

Power supply rejection ratio

Input bias current (source current)

CS to output delay

V_VDD= 12 V to 25 V^{(2) (5)}

70

dB

µA

ns

V

0.1

35

2

t_D

70

COMP to CS offset

V_CS= 0 V

1.15

OUTPUT

V_OUT(low)R_DS(on)pulldown

V_OUT(high)R_DS(on)pullup

I_SINK= 200 mA

5.5

10

25

20

15

25

50

40

Ω

ns

I_SOURCE= 200 mA

T_J= 25°C, C_OUT= 1 nF

t_RISE

t_FALL

Rise tIme

Fall tIme

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

V_VDD= 20 V ⁽¹⁾(for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1), V_VDD= 15 V⁽¹⁾(for the rest), R_RT= 10 kΩ,

C_CT= 3.3 nF, C_VDD= 0.1 µF and no load on the outputs, T_J= –40°C to 150°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

UNDERVOLTAGE LOCKOUT

UCC28C52-Q1, UCC28C54-Q1

UCC28C53-Q1, UCC28C55-Q1

UCC28C50-Q1, UCC28C51-Q1

13.5

7.8

14.5

8.4

7

15.5

9

6.5

7.5

VDD_ON

Start threshold⁽⁶⁾

V

UCC28C56H-Q1, UCC28C57H-Q1

UCC28C56L-Q1, UCC28C57L-Q1

UCC28C58-Q1, UCC28C59-Q1

17.6

14.8

18.8

16

20

17.2

UCC28C52-Q1, UCC28C54-Q1

UCC28C53-Q1, UCC28C55-Q1

UCC28C50-Q1, UCC28C51-Q1

8

7

9

7.6

6.6

10

8.2

7.1

6.1

VDD_OFFMinimum operating voltage ⁽⁶⁾

V

UCC28C56H-Q1, UCC28C57H-Q1

UCC28C56L-Q1, UCC28C57L-Q1

UCC28C58-Q1, UCC28C59-Q1

UCC28C52-Q1, UCC28C54-Q1

UCC28C53-Q1, UCC28C55-Q1

UCC28C51-Q1, UCC28C50-Q1

UCC28C56H-Q1, UCC28C57H-Q1

UCC28C56L-Q1, UCC28C57L-Q1

UCC28C58-Q1, UCC28C59-Q1

15

13.95

12

15.5

14.5

12.5

5.5

16

15

13

5.4

0.8

0.9

0.4

0.5

V

(6)

VDD_HystVDD_ON- VDD_OFF

2.6

3.3

3.65

2.8

4.3

3.5

PWM

UCC28C52-Q1, UCC28C53-Q1, UCC28C50-Q1,

V_FB< 2.4 V

94%

47%

96%

48%

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C58-

Q1, V_FB< 2.4 V

D_MAX

Maximum duty cycle

Minimum duty cycle

UCC28C54-Q1, UCC28C55-Q1, UCC28C51-Q1,

V_FB< 2.4 V

UCC28C57H-Q1, UCC28C57L-Q1, UCC28C59-

Q1, V_FB< 2.4 V

D_MIN

V_FB> 2.6 V

0%

CURRENT SUPPLY

I_START-UPStart-up current

50

75

2

µA

V_VDD= VDD_ON–0.5 V

I_VDD

Operating supply current

V_FB= V_CS= 0 V

1.3

mA

(1) Adjust V_VDDabove the start threshold before setting at 20 V for UCC28C56H/L-Q1, UCC28C57H/L-Q1 and UCC28C58/9-Q1, and 15.5

V for the rest family.

(2) Ensured by design. Not production tested.

(3) Output frequencies of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1, and the UCC28C59-Q1 are half the

oscillator frequency.

(4) Oscillator discharge current is measured with R_RT= 10 kΩto VREF.

(5) Parameter measured at trip point of latch with V_FB= 0 V. Gain is defined as A_CS= ΔV_COMP/ ΔV_CS, 0 V ≤V_CS≤900 mV.

(6) VDD_ON, VDD_OFF, and V_REFare tracking each other in the same direction, e.g., min VDD_OFFis due to min VDD_ON

.

8

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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7.6 Typical Characteristics

9.5

9

1000

Group 1, VDD = 12 V

Group 2, VDD = 20 V

100

8.5

8

10

220 pF

470 pF

7.5

1 nF

2.2 nF

4.7 nF

1

7

-50

-25

0

25

50

75

100

125

1

10

R_RTTiming Resistance (kW)

100

Temperature (C)

D001

Group 1: UCC28C50-Q1 to UCC28C55-Q1

Group 2: UCC28C56H-Q1 to UCC28C59-Q1

图7-1. Oscillator Frequency vs Timing Resistance

and Capacitance

图7-2. Oscillator Discharge Current vs

Temperature

100

1.8

1.6

1.4

1.2

1

200

180

Group 1, VDD = 12 V

Group 2, VDD = 20 V

90

80

70

60

50

40

30

20

10

0

160

140

GAIN

120

100

80

0.8

0.6

0.4

0.2

0

60

40

PHASE

MARGIN

-50

-25

0

25

50

75

100

125

20

0

Temperature (C)

V_CS= 0

1

10

100

1 k 10 k 100 k 1 M 10 M

f -- Frequency -- Hz

Group 1: UCC28C50-Q1 to UCC28C55-Q1

Group 2: UCC28C56H-Q1 to UCC28C59-Q1

图7-3. Error Amplifier Frequency Response

图7-4. COMP to CS Offset Voltage vs Temperature

5.05

2.55

Group 1, VDD = 12 V

Group 2, VDD = 20 V

Group 1, VDD = 12 V

Group 2, VDD = 20 V

5.04

2.54

5.03

5.02

5.01

5

2.53

2.52

2.51

2.5

4.99

4.98

4.97

4.96

4.95

2.49

2.48

2.47

2.46

2.45

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (C)

Group 1: UCC28C50-Q1 to UCC28C55-Q1

Group 2: UCC28C56H-Q1 to UCC28C59-Q1

Group 1: UCC28C50-Q1 to UCC28C55-Q1

Group 2: UCC28C56H-Q1 to UCC28C59-Q1

图7-5. Reference Voltage vs Temperature

图7-6. Error Amplifier Reference Voltage vs

Temperature

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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200

-35

Group 1, VDD = 12 V

Group 2, VDD = 20 V

-37

150

-39

100

-41

-43

50

-45

0

-47

-49

--50

-51

--100

-53

-55

-50

--150

-25

0

25

50

75

100

125

Temperature (C)

--200

--50

--25

0

25 50

Temperature (°C)

75

100

125

Group 1: UCC28C50-Q1 to UCC28C55-Q1

Group 2: UCC28C56H-Q1 to UCC28C59-Q1

图7-8. Error Amplifier Input Bias Current vs

图7-7. Reference Short-Circuit Current vs

Temperature

16

15

14

9.0

UVLO

8.8

ON

8.6

8.4

13

UVLO

ON

12

11

8.2

8.0

7.8

UVLO

OFF

10

9

7.6

7.4

8

UVLO

OFF

7

7.2

6

7.0

--50

--25

0

25

50

75

100

125

--50

--25

0

25 50

Temperature (°C)

75

100

125

Temperature (°C)

UCC28C52-Q1 and UCC28C54-Q1

UCC28C53-Q1 and UCC28C55-Q1

图7-9. Undervoltage Lockout vs Temperature

图7-10. Undervoltage Lockout vs Temperature

7.3

7.2

UVLO

ON

7.1

7.0

6.9

6.8

6.7

6.6

6.5

UVLO

OFF

6.4

6.3

UCC28C56H-Q1 and UCC28C57H-Q1

--50

--25

0

25

50

75

100

125

Temperature (°C)

图7-12. Undervoltage Lockout vs Temperature

UCC28C50-Q1 and UCC28C51-Q1

图7-11. Undervoltage Lockout vs Temperature

10

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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19

18

17

16

15

14

13

12

11

UVLO_ON

UVLO_OFF

10

9

-50

-25

0

25

50

75

100

125

Temperature (C)

UCC28C56L-Q1 and UCC28C57L-Q1

UCC28C58-Q1 and UCC28C59-Q1

图7-13. Undervoltage Lockout vs Temperature

图7-14. Undervoltage Lockout vs Temperature

14

2.1

Group 1 (No Load, V_DD= 12 V)

Group 2 (No Load, V_DD= 20 V)

2

12

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1-nF Load

10

8

6

4

No Load

2

0

200

400

600

800

1000

1200

-50

-25

0

25

50

75

100

125

Frequency (kHz)

Temperature (C)

Group 1: UCC28C50-Q1 to UCC28C55-Q1

Group 2: UCC28C56H-Q1 to UCC28C59-Q1

图7-15. Supply Current vs Oscillator Frequency

图7-16. Supply Current vs Temperature

40

100

CT = 220 pF

35

tr

(1 nF)

90

30

80

tf

(1 nF)

25

70

CT = 1 nF

20

60

50

15

10

0

500

1000

1500

2000

--50

--25

0

25

50

75

100

125

2500

f -- Frequency -- kHz

T

J

-- Temperature -- °C

图7-18. Maximum Duty Cycle vs Oscillator

图7-17. Output Rise Time and Fall Time vs

Frequency

Temperature

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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100

50

98

96

94

92

90

49

48

47

46

45

--50

--25

0

25

50

75

100

125

--50

--25

0

25

50

75

100

125

Temperature (°C)

UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1,

UCC28C56H/L-Q1, and UCC28C58-Q1

UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C57H/L-Q1, and UCC28C59-Q1

图7-19. Maximum Duty Cycle vs Temperature

图7-20. Maximum Duty Cycle vs Temperature

1.05

Group 1, VDD = 12 V

Group 2, VDD = 20 V

1.03

1.01

0.99

0.97

0.95

-50

-25

0

25

50

75

100

125

Temperature (C)

Group 1: UCC28C50-Q1 to UCC28C55-Q1

Group 2: UCC28C56H-Q1 to UCC28C59-Q1

图7-21. Current Sense Threshold Voltage vs

Temperature

图7-22. Current Sense to Output Delay Time vs

Temperature

12

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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8 Detailed Description

8.1 Overview

The UCC28C5x-Q1 series of control integrated circuits provide the features necessary to implement AC-DC or

DC‑to-DC fixed-frequency current-mode control schemes with a minimum number of external components.

Protection circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits

include a start-up current of less than 75 µA, a precision reference trimmed for accuracy at the error amplifier

input, logic to ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-

limit control, and an output stage designed to source or sink high-peak current. The output stage, suitable for

driving N-channel MOSFETs, is low when it is in the OFF state. The oscillator contains a trimmed discharge

current that enables accurate programming of the maximum duty cycle and dead time limit, making this device

suitable for high-speed applications.

Major differences between members of this series are the UVLO thresholds, acceptable ambient temperature

range, and maximum duty cycle and frequency. Typical UVLO thresholds of 14.5 V (ON) and 9 V (OFF) on the

UCC28C52-Q1 and UCC28C54-Q1 devices make them ideally suited to off-line AC-DC applications. The

corresponding typical thresholds for the UCC28C53-Q1 and UCC28C55-Q1 devices are 8.4-V (ON) and 7.6-V

(OFF), making them ideal for use with regulated input voltages used in DC-DC applications. The UCC28C50-Q1

and UCC28C51-Q1 feature a start-up threshold of 7 V and a turnoff threshold of 6.6 V (OFF), which makes them

suitable for battery- powered applications. The UCC28C56H/L-Q1, UCC28C57H/L-Q1, UCC28C58-Q1 and

UCC28C59-Q1 operate with higher start-up thresholds for them suitably to work with SiC MOSFETs which often

being used in high-voltage and high-power traction inverter applications. The UCC28C56H-Q1 and

UCC28C57H-Q1 are with a start-up threshold 18.8-V (ON) and 15.5-V (OFF). The UCC28C56L-Q1 and

UCC28C57L-Q1 are with a start-up threshold 18.8-V (ON) and 14.5-V (OFF). The UCC28C58-Q1 and

UCC28C59-Q1 are with a start-up threshold 16-V (ON) and 12.5-V (OFF). The UCC28C50-Q1, UCC28C52-Q1,

UCC28C53-Q1, UCC28C56H/L-Q1 and UCC28C58-Q1 devices operate to duty cycles approaching 100%. The

UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1 and UCC28C59-Q1 obtain a duty cycle

from 0% to 50% by the addition of an internal toggle flip-flop, which blanks the output off every other clock cycle.

The UCC28C5x series is specified for operation from –40°C to 125°C. The switching frequency (fSW) of the

UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C56H/L-Q1 and UCC28C58-Q1 gate drive is equal to

fOSC; the switching frequency of the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1 and

UCC28C59-Q1 is equal to half of the f_OSC

.

The UCC28C5x-Q1 series are an enhanced replacement with pin-to-pin compatibility to the BiCMOS

UCC28C4x- Q1 families. The new series offers improved performance when compared to older bipolar devices

and other competitive BiCMOS devices with similar functionality. These improvements generally consist of

tighter specification limits that are a subset of the older product ratings, maintaining drop-in capability. In new

designs, these improvements can reduce the component count or enhance circuit performance when compared

to the previously available devices.

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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8.2 Functional Block Diagram

VDD

UVLO

EN

5V

VREF

VREF Good

Logic

RT/CT

Osc

OUT

GND

T

( NOTE)

2.5V

S

R

2R

+

E/A

PWM

Latch

FB

COMP

CS

R

1V

PWM

Comparator

Toggle flip-flop used only in UCC28C51-Q1, UCC28C54-Q1, UCC8C55-Q1, UCC28C57H/L-Q1, and UCC28C59-Q1

8.3 Feature Description

The BiCMOS design allows operation at high frequencies that were not feasible in the predecessor bipolar

devices. First, the output stage has been redesigned to drive the external power switch in approximately half the

time of the earlier devices. Second, the internal oscillator is more robust, with less variation as frequency

increases. This faster oscillator makes this device suitable for high speed applications and the trimmed

discharge current enables precise programming of the maximum duty cycle and dead-time limit. In addition, the

current sense to output delay is kept the same 45 ns (typical) as the UCC28C4x-Q1. Such a delay time in the

current sense results in superior overload protection at the power switch. The reduced start-up current of this

device minimizes steady state power dissipation in the startup resistor, and the low operating current maximizes

efficiency while running, increasing the total circuit efficiency, whether operating off-line, DC input, or battery

operated circuits. These features combine to provide a device capable of reliable, high-frequency operation.

表8-1. Key Parameters

PARAMETER

UCC28C4x-Q1

UCC28C5x-Q1

1.3 mA

Supply current at 52 kHz

Start-up current

2.3 mA

100 µA

75 µA

V_DDabsolute maximum

Reference voltage accuracy

20 V

30 V

± 2%

± 1%

UVLO and D_MAXfor Si MOSFET

UVLO and D_MAXfor SiC MOSFET

6 options

no options

6 options

14

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.3.1 Detailed Pin Description

8.3.1.1 COMP

The error amplifier in the UCC28C5x-Q1 family has a unity-gain bandwidth about 1 MHz. The COMP terminal

can both source and sink current. The error amplifier is internally current-limited, so that one can command zero

duty cycle by externally forcing COMP to GND.

8.3.1.2 FB

FB is the inverting input of the error amplifier. The noninverting input to the error amplifier is internally trimmed to

2.5 V ± 1%. FB is used to control the power converter voltage-feedback loop for stability. For best stability, keep

FB lead length as short as possible and FB stray capacitance as small as possible.

8.3.1.3 CS

The UCC28C5x-Q1 current sense input connects directly to the PWM comparator. Connect CS to the MOSFET

source current sense resistor. The PWM uses this signal to terminate the OUT switch conduction. A voltage

ramp can be applied to this pin to run the device with a voltage mode control configuration or to add slope

compensation. To prevent false triggering due to leading edge noises, an RC current sense filter may be

required. The gain of the current sense amplifier is typically 3 V/V.

8.3.1.4 RT/CT

RT/CT is the oscillator timing pin. For fixed frequency operation, set the timing capacitor charging current by

connecting a resistor from VREF to RT/CT. Set the frequency by connecting timing capacitor from RT/CT to

GND. For the best performance, keep the timing capacitor lead to GND as short and direct as possible. If

possible, use separate ground traces for the timing capacitor and all other functions.

The UCC28C5x-Q1’s oscillator allows for operation to 1 MHz. The device uses an external resistor to set the

charging current for the external capacitor, which determines the oscillator frequency. TI recommends timing

resistor values from 1 kΩ to 100 kΩ and timing capacitor values from 220 pF to 4.7 nF. The UCC28C5x-Q1

oscillator is true to the curves of the original bipolar devices at lower frequencies, yet extends the frequency

programmability range to at least 1 MHz. This allows the device to offer pin-to-pin capability where required, yet

capable of extending the operational range to the higher frequencies. See 图 7-1 for component values for

setting the oscillator frequency.

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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8.3.1.5 GND

GND is the signal and power returning ground. TI recommends separating the signal return path and the high

current gate driver path so that the signal is not affected by the switching current.

8.3.1.6 OUT

The high-current output stage of the UCC28C5x-Q1 to drive the external power switch has been kept the same

as the earlier devices UCC28C4x-Q1. To drive a power MOSFET directly, the totem-pole OUT driver sinks or

source up to 1 A peak of current. The OUT of the UCC28C50-Q1, UCC28C52-Q1, UCC28C53-Q1,

UCC28C56H/L-Q1 and UCC28C58-Q1 devices switch at the same frequency as the oscillator and can operate

near 100% duty cycle. In the UCC28C51-Q1, UCC28C54-Q1, and UCC28C55-Q1, UCC28C57H/L-Q1 and

UCC28C59-Q1, the switching frequency of OUT is one-half that of the oscillator due to an internal T flip-flop.

This limits the maximum duty cycle in the UCC28C51-Q1, UCC28C54-Q1, UCC28C55-Q1, UCC28C57H/L-Q1

and UCC28C59-Q1 to < 50%.

The UCC28C5x-Q1 family houses unique totem pole drivers exhibiting a 10-Ωimpedance to the upper rail and a

5.5-Ω impedance to ground, typically. This reduced impedance on the low-side switch helps minimize turn-off

losses at the power MOSFET, whereas the higher turn-on impedance of the high-side is intended to better match

the reverse recovery characteristics of many high-speed output rectifiers. Transition times, rising and falling

edges, are typically 25 nanoseconds and 20 nanoseconds, respectively, for a 10% to 90% change in voltage.

A low impedance MOS structure in parallel with a bipolar transistor, or BiCMOS construction, comprises the

totem-pole output structure. This more efficient utilization of silicon delivers the high peak current required along

with sharp transitions and full rail-to-rail voltage swings. Furthermore, the output stage is self-biasing, active low

during under-voltage lockout type. With no VDD supply voltage present, the output actively pulls low if an

attempt is made to pull the output high. This condition frequently occurs at initial power-up with a power

MOSFET as the driver load.

16

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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8.3.1.7 VDD

VDD is the power input connection for this device. In normal operation, power VDD through a current limiting

resistor. The absolute maximum supply voltage is 30 V, extended from 20 V of UCC28C5x-Q1 to facilitate more

designs and applications. The 30-V voltage, including any transients that may be present, cannot be exceeded,

device damage is likely if otherwise. Hence UCC28C5x devices match the predecessor bipolar devices, which

could survive up to 30 V on the input bias pin. But still, no internal clamp is included in the device, the VDD pin

must be protected from external sources which could exceed the 30 V level. If containing the start-up and

bootstrap supply voltage from the auxiliary winding N_Abelow 30 V under all line and load conditions can not be

achieved, use a zener protection diode from VDD to GND. Depending on the impedance and arrangement of the

bootstrap supply, this may require adding a resistor, R_VDD, in series with the auxiliary winding to limit the current

into the zener as shown in 图 8-1. Insure that over all tolerances and temperatures, the minimum zener voltage

is higher than the highest UVLO upper turn-on threshold. To ensure against noise related problems, filter VDD

with a ceramic bypass capacitor to GND. The VDD pin must be decoupled as close to the GND pin as possible.

N_P

N_A

N_S

R_START

D_BIAS

To

Input

R_VDD

VDD

GND

OUT

C_VCC

C_VDDbp

0.1 mF

D_ZCLAMP

R_CS

图8-1. VDD Protection

Although nominal VDD operating current is only 1.3 mA, the total supply current is higher, depending on the OUT

current. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the

operating frequency and the MOSFET gate charge (Q_g), average OUT current can be calculated from 方程式1.

I_OUT= Q_g× f_SW

(1)

8.3.1.8 VREF

VREF is the voltage reference for the error amplifier and also for many other internal circuits in the device. The

5-V reference tolerance is ±1% for the UCC28C5x-Q1 family. The high-speed switching logic uses VREF as the

logic power supply. The reference voltage is divided down internally to 2.5 V ±1% and connected to the error

amplifier's noninverting input for accurate output voltage regulation. The reference voltage sets the internal bias

currents and thresholds for functions such as the oscillator upper and lower thresholds along with the

overcurrent limiting threshold. The output short-circuit current is 55 mA (maximum). To avoid device over-heating

and damage, do not pull VREF to ground as a means to terminate switching. For reference stability and to

prevent noise problems with high-speed switching transients, bypass VREF to GND with a ceramic capacitor

close to thedevicepackage. A minimum of 0.1-µF ceramic capacitor is required. Additional VREF bypassing is

required for external loads on the reference. An electrolytic capacitor may also be used in addition to the ceramic

capacitor.

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.3.2 Undervoltage Lockout

Six sets of UVLO thresholds are available with turn-on and turnoff thresholds of: (14.5 V and 9 V), (8.4 V and 7.6

V), (7 V and 6.6 V), (18.8 V and 15.5 V), (18.8 V and 14.5V) and (16 V and 12.5V), respectively. The first set is

primarily intended for off-line and 48-V distributed power applications, where the wider hysteresis allows for

lower frequency operation and longer soft-starting time of the converter. The second set of UVLO option is ideal

for high frequency DC-DC converters typically running from a 12-VDC input. The third set is for battery powered

and portable applications. The fourth to sixth UVLO sets are to drive SiC MOSFETs in High Voltage applications.

表8-2 shows the maximum duty cycle and UVLO thresholds by device.

表8-2. UVLO Options

MAXIMUM DUTY CYCLE

UVLO ON

14.5 V

8.4 V

UVLO OFF

PART NUMBER

UCC28C52-Q1

UCC28C53-Q1

UCC28C50-Q1

100%

9 V

7.6 V

7 V

6.6 V

100%

18.8 V

16 V

15.5 V

14.5 V

12.5 V

UCC28C56H-Q1

UCC28C56L-Q1

UCC28C58-Q1

50%

14.5 V

8.4 V

7 V

9 V

UCC28C54-Q1

UCC28C55-Q1

UCC28C51-Q1

7.6 V

6.6 V

50%

18.8 V

16 V

15.5 V

14.5 V

12.5 V

UCC28C57H-Q1

UCC28C57L-Q1

UCC28C59-Q1

During UVLO the device draws less than 75 µA of supply current. Once crossing the turn-on threshold the

device supply current increases to a maximum of 2 mA, typically 1.3 mA. This low start-up current allows the

power supply designer to optimize the selection of the start-up resistor value to provide a more efficient design.

In applications where low component cost overrides maximum efficiency, the low run current of 1.3 mA (typical)

allows the control device to run directly through the single resistor to (+) rail, rather than requiring a bootstrap

winding on the power transformer, along with a rectifier. The start and run resistor for this case must also pass

enough current to allow driving the primary switching MOSFET, which may be a few milliamps in small devices.

< 2

< 0.075

V

ON

OFF

Operating Voltage (V)

图8-2. UVLO ON and OFF Profile

18

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.3.3 ±1% Internal Reference Voltage

The BiCMOS internal reference of 2.5 V has an enhanced design, and uses production trim to allow initial

accuracy of ±1% at room temperature and ±2% over the full temperature range. This can be used to eliminate an

external reference in applications that do not require the extreme accuracy afforded by the additional device.

This is useful for non-isolated DC-DC applications, where the control device is referenced to the same common

as the output. It is also applicable in off-line designs that regulate on the primary side of the isolation boundary

by looking at a primary bias winding, or from a winding on the output inductor of a buck-derived circuit.

8.3.4 Current Sense and Overcurrent Limit

An external series resistor (R_CS) senses the current and converts this current into a voltage that becomes the

input to the CS pin. The CS pin is the noninverting input to the PWM comparator. The CS input is compared to a

signal proportional to the error amplifier output voltage; the gain of the current sense amplifier is typically 3 V/V.

The peak I_SENSEcurrent is determined using 方程式2

V_CS

I_SENSE

=

R_CS

(2)

The typical value for V_CSis 1 V. A small RC filter (R_CSFand C_CSF) may be required to suppress switch transients

caused by the reverse recovery of a secondary side diode or equivalent capacitive loading in addition to parasitic

circuit impedances. The time constant of this filter should be considerably less than the switching period of the

converter.

Error

Amplifier

2 R

COM

P

R

1 V

PWM

Comparat

or

I_SENS

E

R_CSF

CS

C_CSF

R_CS

GND

图8-3. Current-Sense Circuit Schematic

Cycle-by-cycle pulse width modulation performed at the PWM comparator essentially compares the error

amplifier output to the current sense input. This is not a direct volt-to-volt comparison, as the error amplifier

output network incorporates two diodes in series with a resistive divider network before connecting to the PWM

comparator. The two-diode drop adds an offset voltage that enables zero duty cycle to be achieved with a low

amplifier output. The 2R/R resistive divider facilitates the use of a wider error amplifier output swing that can be

more symmetrically centered on the 2.5-V noninverting input voltage.

The 1-V zener diode associated with the PWM comparator’s input from the error amplifier is not an actual

diode in the device’s design, but an indication that the maximum current sense input amplitude is 1 V (typical).

When this threshold is reached, regardless of the error amplifier output voltage, cycle-by-cycle current limiting

occurs, and the output pulse width is terminated within 35 ns (typical). The minimum value for this current limit

threshold is 0.9 V with a 1.1-V maximum. In addition to the tolerance of this parameter, the accuracy of the

current sense resistor, or current sense circuitry, must be taken into account. It is advised to factor in the worst

case of primary and secondary currents when sizing the ratings and worst-case conditions in all power

semiconductors and magnetic components.

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.3.5 Reduced-Discharge Current Variation

The UCC28C5x-Q1 oscillator design incorporates a trimmed discharge current to accurately program maximum

duty cycle and operating frequency. In its basic operation, a timing capacitor (C_CT) is charged by a current

source, formed by the timing resistor (R_RT) connected to the device’s reference voltage (VREF). The oscillator

design incorporates comparators to monitor the amplitude of the timing capacitor’s voltage. The exponentially

shaped waveform charges up to a specific amplitude representing the oscillator’s upper threshold of 2.5 V.

Once reached, an internal current sink to ground is turned on and the capacitor begins discharging. This

discharge continues until the oscillator’s lower threshold has reached 0.7 V at which point the current sink is

turned off. Next, the timing capacitor starts charging again and a new switching cycle begins.

VDD_ON

VDD_OFF

VREF

R_RT

C_CT

RT/CT

GND

t_ON

t_PERIOD

t_OFF

8.4 mA

图8-4. Oscillator Circuit

While the device is discharging the timing capacitor, resistor R_RTis also still trying to charge C_CT. It is the exact

ratio of these two currents, the discharging versus the charging current, which specifies the maximum duty cycle.

During the discharge time of C_CT, the device’s output is always off. This represents an ensured minimum off

time of the switch, commonly referred to as dead-time. To program an accurate maximum duty cycle, use the

information provided in 图 7-18 for maximum duty cycle versus oscillator frequency. Any number of maximum

duty cycles can be programmed for a given frequency by adjusting the values of R_RTand C_CT. Once R_RTis

selected, the oscillator timing capacitor can be found using the curves in 图 7-1. However, because resistors are

available in more precise increments, typically 1%, and capacitors are only available in 5% accuracy, it might be

more practical to select the closest capacitor value first and then calculate the timing resistor value next.

20

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.3.6 Oscillator Synchronization

Synchronization is best achieved by forcing the timing capacitor voltage above the oscillator's internal upper

threshold. A small resistor is placed in series with C_CTto GND. This resistor serves as the input for the sync

pulse which raises the C_CTvoltage above the oscillator’s internal upper threshold. The PWM is allowed to run

at the frequency set by R_RTand C_CTuntil the sync pulse appears. This scheme offers several advantages

including having the local ramp available for slope compensation. The UCC28C5x-Q1 oscillator must be set to a

lower frequency than the sync pulse stream, typically 20 percent with a 0.5-V pulse applied across the resistor.

VREF

R_RT

C_CT+ SYNC

C_CT

RT/CT

GND

SYNC

50

C_CT

图8-5. Oscillator Synchronization Circuit

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.3.7 Soft Start

Soft start is the technique to gradually power up the converter in a well-controlled fashion by slowly increasing

the effective duty cycle starting at zero and gradually rising. Following start-up of the PWM, the error amplifier

inverting input is low, commanding the error amplifier’s output to go high. The output stage of the amplifier can

source 1 mA typically, which is enough to drive most high impedance compensation networks, but not enough

for driving large loads quickly. Soft start is achieved by charging a fairly large value, >1-µF, capacitor (C_SS

)

connected to the error amplifier output through a PNP transistor as shown in 图8-6

VREF

R_SS

COMP

Z_F

+

2N2907

C_SS

FB

Z_I

To VOUT

图8-6. Soft-Start Implementation

The limited charging current of the amplifier into the capacitor translates into a dv/dt limitation on the error

amplifier output. This directly corresponds to some maximum rate of change of primary current in a current mode

controlled system as one of the PWM comparator’s inputs gradually rises. The values of R_SSand C_SSmust be

selected to bring the COMP pin up at a controlled rate, limiting the peak current supplied by the power stage.

After the soft-start interval is complete, the capacitor continues to charge to VREF, effectively removing the PNP

transistor from the circuit consideration. Soft start performs a different, frequently preferred function in current

mode controlled systems than it does in voltage mode control. In current mode, soft start controls the rising of

the peak switch current. In voltage mode control, soft start gradually widens the duty cycle, regardless of the

primary current or rate of ramp-up.

The purpose of the resistor R_SSand diode is to take the soft-start capacitor out of the error amplifier’s path

during normal operation, once soft start is complete and the capacitor is fully charged. The optional diode in

parallel with the resistor forces a soft start each time the PWM goes through UVLO condition that forces VREF to

go low. Without the diode, the capacitor remains charged during a brief loss of supply or brown-out, and no soft

start is enabled upon re-application of VDD.

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.3.8 Enable and Disable

There are a few ways to enable or disable the UCC28C5x-Q1 devices, depending on which type of restart is

required. The two basic techniques use external transistors to either pull the error amplifier output low (< 2 V_BE

)

or pull the current sense input high (> 1.1 V). Application of the disable signal causes the output of the PWM

comparator to be high. The PWM latch is reset dominant so that the output remains low until the next clock cycle

after the shutdown condition at the COMP or CS pin is removed. Another choice for restart without a soft start is

to pull the current sense input above the cycle-by-cycle current limiting threshold. A logic level P-channel FET

from the reference voltage to the current sense input can be used.

COMP

DISABLE

图8-7. Disable Circuit

8.3.9 Slope Compensation

With current mode control, slope compensation is required to stabilize the overall loop with duty cycles

exceeding 50%. Although not required, slope compensation also improves stability in applications using below a

50% maximum duty cycle. Slope compensation is introduced by injecting a portion of the oscillator waveform to

the actual sensed primary current. The two signals are summed together at the current sense input (CS)

connection at the filter capacitor. To minimize loading on the oscillator, it is best to buffer the timing capacitor

waveform with a small transistor whose collector is connected to the reference voltage.

VREF

0.1 µF

R_RT

RT/CT

CS

C_CT

R_RAMP

R_CSF

I_SENSE

R_CS

C_CSF

图8-8. Slope Compensation Circuit

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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8.3.10 Voltage Mode

In certain applications, voltage mode control may be a preferred control strategy for a variety of reasons. Voltage

mode control is easily executable with any current mode controller, especially the UCC28C5x-Q1 family

members. Implementation requires generating a 0-V to 0.9-V sawtooth shaped signal to input to the current

sense pin (CS) which is also one input to the PWM comparator. This is compared to the divided down error

amplifier output voltage at the other input of the PWM comparator. As the error amplifier output is varied, it

intersects the sawtooth waveform at different points in time, thereby generating different pulse widths. This is a

straightforward method of linearly generating a pulse whose width is proportional to the error voltage.

Implementation of voltage mode control is possible by using a fraction of the oscillator timing capacitor (C_CT

)

waveform. This can be divided down and fed to the current sense pin as shown in 图 8-9. The oscillator timing

components must be selected to approximate as close to a linear sawtooth waveform as possible. Although

exponentially charged, large values of timing resistance and small values of timing capacitance help

approximate a more linear shaped waveform. A small transistor is used to buffer the oscillator timing

components from the loading of the resistive divider network.

VREF

R_RT

2N2222

RT/CT

CS

C_CT

图8-9. Current Mode PWM Used as a Voltage Mode PWM

24

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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8.4 Device Functional Modes

8.4.1 Normal Operation

During normal operating mode, the controller can be used in peak current mode or voltage mode control. When

the converter is operating in peak current mode, the controller regulates the converter's peak current and duty

cycle. When used in voltage mode control, the controller regulates the power converter's duty cycle. The

regulation of the system's peak current and duty cycle can be achieved with the use of the integrated error

amplifier and external feedback circuitry.

8.4.2 UVLO Mode

During the system start-up, VDD voltage starts to rise from 0 V. Before the VDD voltage reaches its

corresponding turnon threshold, thedeviceis operating in UVLO mode. In this mode, the VREF pin voltage is not

generated. When VDD is above 1 V and below the turnon threshold, the VREF pin is actively pulled low. This

way, VREF can be used as a logic signal to indicate UVLO mode. If the bias voltage to VDD drops below the

UVLO-OFF threshold, the PWM switching stops and VREF returns to 0 V. The device can be restarted by

applying a voltage greater than the UVLO-ON threshold to the VDD pin.

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The UCC28C5x-Q1 controllers are peak current mode pulse width modulators. These controllers have an

integrated error amplifier and can be used in isolated or nonisolated power supply designs. There is an on-chip

gate driver capable of delivering 1 A of peak current. This is a high-speed PWM capable of operating at

switching frequencies up to 1 MHz. 图9-1 shows a typical high-voltage input application with UCC28C56H-Q1.

9.2 Typical Application

A typical application for the UCC28C56H-Q1 in an 800-V_TYPflyback converter utilizing a single 1700-V SiC

MOSFET is shown in 图 9-1. The UCC28C56H-Q1 uses an inner current control loop that contains a small

current sense resistor which senses the primary inductor current ramp. This current sense resistor transforms

the inductor current waveform to a voltage signal that is input to the PWM comparator. This inner loop

determines the response to input voltage changes. An outer voltage control loop involves comparing a portion of

the output voltage to a reference voltage at the input to an error amplifier. The bandwidth of the outer voltage

control loop determines the response to load changes.

VIN

C4

1.5pF

C1

0.22uF

C2

0.22uF

C3

0.22uF

D1

160V

1

Q1

HV_GND

D2

130V

HV Clamp

R1

1.0M

D3

160V

D4

130V

1

Q2

D5

22V

R2

62

R28

62

HV Startup for VDD

C5

1000pF

D6

130V

R3

1.0M

R4

100

T1

R5

1.00k

Lpri=550 µH

Npri:Nsec=10.2:1

Npri:Naux=8.5:1

HV_GND

D8

130V

D7

1.6kV

9

8

1

D9

18V

1

Vout

2

C6

R7

3

HV_GND

D10

18V

+

SW

R6

10.0k

3

4

6

11

10

C9

1000uF

C10

1000uF

D11

D12

60V

Disable HV

Startup

200V

R10

0

NC

C17

R9

10.0k

330nF

HV_GND

VDD

AUX

Iso_GND

1

2

7

12

Q3

NC

1

Q4

D13

Iso_GND

Soft Start

C12

22uF

C13

4.7uF

C11

47nF

200V

5

D14

40V

AUX Supply

R13

20.0k

C7

10uF

C8

10uF

R8

100k

HV_GND

U1

UCC28C56H-Q1

R12

40.2k

C14

C24

2200pF 2200pF

VREF

5V

8

4

2

1

3

7

6

5

R11

10.0

VREF

RT/CT

FB

VDD

OUT

GND

Iso_GND

RT/CT

FB

R14

39.2

Q5

2.5V

OUT

Gate_FET

1

HV_GND

Iso_GND

C16

100nF

C15

1000pF

COMP

C18

1uF

COMP

CS

R15

44.2k

Gate Drive

R17

2.55k

1

C19

22nF

Q6

HV_GND

R16

127

C20

100pF

HV_GND

VREF

Q7

R18

324k

R19

20.0k

HV_GND

Voltage

Feedback

1

R21

1.00k

Slope Compensation

Current Filtering

CS

Rsense

R22

4.02k

C21

2.2µF

C22

100pF

R20

3.48k

Current

Sensing

R23

15.0k

C23

22pF

R24

0.91

R25

0.91

R26

2.00k

1

Q8

HV_GND

R27

127

Leading Edge

Blanking

HV_GND

图9-1. Typical Flyback Application Schematic

26

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English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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9.2.1 Design Requirements

表9-1 shows a typical set of performance requirements for a high-voltage flyback converter capable of delivering

15 V output from a 40 V to 1000 V DC input. From 125 V to 1000 V input, the converter can deliver 40 W. From

40 V to 125 V input, the converter is derated to deliver 20 W. To minimize the transformer size and reduce

losses, the power stage is designed such that it operates in discontinuous conduction mode (DCM) at high input

voltage and very near transition mode at low input voltage. In DCM mode (i.e. relatively high input voltage) the

magnetizing current is reset to zero before the start of the next PWM cycle. Compared to continuous conduction

mode (CCM), DCM provides the advantage of very low turn-on switching losses, even at high V_IN, because the

current always starts from 0A. Also, in DCM mode, the output rectifier current decays to zero before the next

switching event. Therefore, DCM eliminates the reverse recovery losses of the output rectifier, unlike CCM.

The peak power of the converter is designed to support 48 W, 120 % higher than the nominal 40 W.

表9-1. Design Parameters

PARAMETER

V_IN

OPERATING CONDITIONS

MIN

40

NOM

800

15

MAX

1000

16

UNIT

V_DC

A

Input Voltage

V_OUT

Output Voltage

14

0.2 A ≤I_OUT≤I_{OUT_FL}

125 V ≤V_IN≤1000 V

40 V ≤V_IN< 125 V

I_{OUT_FL}

Full-Load Output Current

2.7

1.3

A

f_SW

Switching Frequency

Duty Cycle at V_{IN_MIN}

Output Voltage Ripple

42.5

80

kHz

%

D_{VIN_MIN}

V_RIPPLE

0.5

V_PP

9.2.2 Detailed Design Procedure

This procedure outlines the steps to design a discontinuous current mode (DCM) flyback converter utilizing the

UCC28C56H-Q1. However, it could be adopted for any of the controllers in the UCC28C5x family and other

input/output voltages. See 图9-1 for component reference designators referred to in the design procedure.

9.2.2.1 Primary-to-Secondary Turns Ratio of the Flyback Transformer (NPS)

To start, we need to estimate the forward voltage (V_F) of the output Schottky diode and the on-time of the

MOSFET (t_{ON_EST}

)

V

= 0.5V

(3)

(4)

F

D

VIN_MIN

0.80

t

=

= 18.8 µs

42.5 kHz

ON_EST

f

SW

Next, estimate the transformer primary-to-secondary turns ratio

V

× t

ON_EST

40 V × 18.8 µs

− 18.8 µs 15 V + 0.5 V

IN_MIN

N

=

= 10.3

(5)

(6)

PS

1

×

− t

×

V

+ V

ON_EST

OUT F

42.5 kHz

f

SW

Calculate the reverse withstand voltage of output rectifier diode during t_{ON_EST}

V

IN_MAX

1000 V

V

= V

+

= 15 V +

= 112 V

10.3

SEC_REV

OUT

N

PS

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English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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Calculate the (expected) drain-to-source voltage of the MOSFET during the off time

V

= V

+ V

+ V × N = 1000 V + 15 V + 0.5 V × 10.3 = 1160 V

(7)

DS_OFF

IN_MAX

OUT

F

PS

The switching MOSFET and output rectifier generally experience voltage ringing due to transformer leakage and

parasitic capacitance. Based on V_{SEC_REV}, a 200V-rated Schottky diode is chosen, so the secondary RC

snubber can damp the voltage spike and ringing with reduced snubber power loss. Based on V_{DS_OFF}, a 1.7kV-

rated SiC MOSFET is chosen, so a higher breakdown voltage of the primary TVS diode clamping circuit can

clamp the switching voltage stress caused by the transformer leakage with reduced clamping power loss. If

V_{DS_OFF}is too high, the turns ratio can be reduced by decreasing D_{VIN_MIN}, but V_{SEC_REV}will increase. Deciding

which component voltage is more critical and iterate again if necessary.

9.2.2.2 Primary Magnetizing Inductance of the Flyback Transformer (LM)

Calculate the maximum primary magnetizing inductance (L_{M_CRIT}) to maintain DCM operation at full load and

minimum input voltage using the following equation

V

× D

× 1 − D

× N

VIN_MIN PS

40 V × 0.80 × 1 − 0.80 × 10.3

2 × 42.5 kHz × 1.3 A

IN_MIN

VIN_MIN

2 × f

L

=

= 597 µH

(8)

M_CRIT

× I

SW

OUT

To account for the inductance variance, a typical L_Mof 550 µH is used in the following calculation. P_{O_MAX}occurs

when the CS-pin voltage reaches at 1 V. P_{O_MAX}determines the maximum output power of the flyback converter,

set 120% larger than the full-load output power of 40 W. Then, the maximum peak magnetizing current (I_{M_MAX}

can be calculated as

)

2 × P

O_MAX

2 × 40 W × 120 %

550 µH × 42.5 kHz × 0.85

I

=

= 2.2 A

(9)

M_MAX

L

× f

× η

M

SW

9.2.2.3 Number of Turns of the Flyback Transformer Windings

The turns number of primary winding (N_P) and the cross-section area of transformer core (A_E) is chosen to

ensure the maximum flux density (B_MAX) of transformer core is lower than the saturation flux density (B_SAT) at

highest core temperature. In this example, the EFD30 core size with A_Eof 0.69 cm²is used.

L

× I

550 µH × 2.2 A

M

B

M_MAX

× A

N

=

≈ 51 turns

(10)

P

2

MAX

E

0.34 T × 0.69 cm

The number of turns of the secondary winding (N_S) can be calculated with N_PS, calculated previously. N_Sand N_P

are adjusted to the nearest suitable integers. Therefore, the new N_PSis changed from 10.3 to 10.2 for practical

integer turns.

N

P

51

10.2

N =

=

= 5 turns

(11)

S

N

PS

The turns number of auxiliary winding (N_AUX) needs to consider the targeted rectified auxiliary winding voltage

(V_AUX) and the forward voltage of the rectifier diode (V_{F_DAUX}), since V_AUXdetermines the gate driver voltage on

the SiC MOSFET which strongly affects its optimal R_{DS_ON}

.

V

+ V

× N

AUX

F_DAUX

+ V

18 V + 0.5 V × 5

15 V + 0.5 V

S

N

=

≈ 6 turns

(12)

AUX

V

OUT

F

28

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English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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9.2.2.4 Current Sense Resistors (R24, R25) and Current Limiting

An external series resistor (R_CS) senses the current and converts this current into a voltage that becomes the

input to the CS pin. The CS pin is the noninverting input to the PWM comparator. The CS input is compared to a

signal proportional to the error amplifier output voltage. Calculate the current sense resistor based on the 2.2-A

peak magnetizing current at P_{O_MAX}of 48 W.

V

CS_MAX

1 V

2.2 A

R

=

= 0.455 Ω

(13)

CS

I

M_MAX

For any input voltage, if the output is shorted to ground or the output voltage ramps up quickly during soft-start,

the controller duty cycle can easily reach the maximum duty cycle (D_MAX), so the power rating of the R_CS

resistor(s) must maintain adequate design margin to support those transient events.

D

MAX

3

I

= I

×

= 1.24 A

(14)

(15)

PRI_RMS_MAX

M_MAX

2

P

= I

× R = 0.7 W

RCS

RMS_MAX CS

The applications schematic shows two 0.91-Ω resistors that are 2010 size in parallel, R24 and R25, for a

combined resistance of 0.455 Ω. Each can handle 0.55 W at 105°C ambient and 1 W below 70°C ambient. For a

traction inverter at 105°C ambient, the two paralleled resistors can handle the worst case and offer enough

margin from resistor mismatch.

9.2.2.5 Primary Clamp Circuit (D7, D1, D3, R2, R28) to Limit Voltage Stress

At turn-off a high voltage spike appears on the MOSFET due to the transformer’s leakage inductance. This

voltage spike can exceed the MOSFETs maximum V_DSrating, leading to failure of the device. Therefore, a

clamping circuit is required. There are two types of clamping circuits: the RCD clamp and the diode-zener (or

TVS) clamp. The TVS clamp provides better light-load efficiency and lower input power at no load than the RCD

clamp because the TVS may not activated at lighter output load. The RCD clamp offers additional damping of

parasitic ringing and improved EMI. The TVS diode clamp is used in this design example. The series resistor

(R_CLAMP), R2 // R8 in the schematic, creates a snubber effect for the TVS diode clamp for improved EMI, but the

voltage stress on V_DSis increased.

The total clamping voltage (V_CLAMP) is designed to meet the 90% derating of the primary MOSFET at V_{IN_MAX}

.

V_CLAMPalso needs to be higher than the reflected voltage on primary to limit the clamping loss. Two TVS diodes,

D1 and D3, are connected in series to share the high clamping loss at full load. In the schematic, each 160-V

clamp diode exhibits about 200 V at peak current, so the equivalent V_CLAMPis around 400V.

The maximum and minimum clamp voltages can be calculated with the following equations.

V

< V

× 90% − V

− I

× R = 1.7 kV × 0.9 − 1 kV − 2.2 A × 31 Ω = 461 V

CLAMP

(16)

CLAMP_MAX

DS_MAX

IN

MAX

M_MAX

> V

+ V × N = 15 V + 0.5 V × 10.2 = 158 V

(17)

CLAMP_MIN

OUT

F

PS

The voltage rating of the series rectifier diode (D7) needs to be higher than 1.4 kV, which is the summation of

1000 V_{IN_MAX}and 400 V_CLAMP, so a 1.6 kV device is chosen assuming 90% derating. Instead of an ultra-fast

type, the slow-recovery P/N junction diode should be considered, so that the reverse recovery could help to

damp the high-frequency ringing after clamping and also recycle partial leakage energy to secondary side for

increased converter efficiency.

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English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

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9.2.2.6 Primary-Side Current Stress and Input Capacitor Selection

The input capacitors must be rated for the maximum input voltage, limit the input voltage ripple, and support the

required RMS current. The primary peak current (I_{M_VIN}) and duty cycle (D_VIN) at any input voltage (V_IN) can be

derived with the following equations

2 × P

O

I

=

(18)

(19)

M_VIN

L

× f

× η

M

SW

I

× L

M

D

=

f

VIN

SW

V

IN

The minimum input capacitance (C_{IN_MIN}) and RMS current (I_{CIN_RMS}) they must support can be estimated with

the following

I

× D

VIN

M

C

=

(20)

(21)

IN_MIN

2 × f

× V

SW

IN_RIPPLE

2

I

× D

VIN

P

M

O

× η

I

=

−

V

CIN_RMS

3

IN

Assuming 30% input voltage ripple for both 20 W at 40-V and 40 W at 125-V, the required minimum input

capacitance is calculated for each case based on the above equations. C_{IN_MIN}at 40-V input is 1.15 µF, while

C_{IN_MIN}at 125-V input is only 0.24 µF.

Low voltage operation requires almost 5x more input capacitance to produce the same percentage of input

voltage ripple. If the input of auxiliary power supply is tapped to the input of the system power converters, such

as the back-up power supply of traction inverters, the input capacitance of the power converters may be

sufficient to meet the C_{IN_MIN}requirement at 40-V input. Therefore, the design example only parallels 2-3 high-

voltage film capacitors near the regulator for high frequency decoupling.

9.2.2.7 Secondary-Side Current Stress and Output Capacitor Selection

Similar to the input capacitors, the output capacitors must limit the voltage ripple and support an RMS current.

However, for DCM operation, the high peak secondary current results in a relatively substantial RMS current in

the output capacitors, usually requiring multiple capacitors in parallel.

First, estimate the maximum ESR of the output capacitors (R_{ESR_MAX}) based on the output ripple requirement

and highest secondary peak current at full load (I_{SEC_PEAK}). When an electrolytic capacitor is used, the output

ripple magnitude is mainly determined by the ESR ripple. Paralleling the two output capacitors, C9 and C10,

reduces the total ESR less than R_{ESR_MAX}

.

2 × 40 W

I

= N

= 20.5 A

× f × η

SW

(22)

(23)

SEC_PEAK

PS

L

M

V

OUT_RIPPLE

0.5 V

R

=

= 24 mΩ

20.5 A

ESR_MAX

I

SEC_PEAK

Next, calculate the minimum required output capacitance to meet the output voltage ripple requirement

assuming full-load and 90% of R_{ESR_MAX}

I

× 1 − D

VIN

OUT

C

≥

= 1196 µF

(24)

OUT

V

− I

SEC_PEAK

× 90% × R

ESR_MAX

× f

SW

OUT_RIPPLE

30

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Finally, calculate the RMS current the output capacitors must withstand at full load (I_{COUT_RMS}), considering the

demagnetizing time (i.e. duty cycle (D_DEMAG)) during DCM operation. Note that paralleling two or more output

capacitors, C9 and C10, shares the total RMS current and also reduces the power loss contributed by the ESR.

I

× L

M

M_FL

D

=

× f

= 0.297

(25)

(26)

DEMAG

SW

V

+ V × N

OUT

F

PS

2

I

× D

SEC_PEAK

DEMAG

2

I

=

− I

= 6.45 A

COUT_RMS

OUT

3

9.2.2.8 VDD Capacitors (C12, C18)

During high-voltage (HV) startup from V_IN, capacitor C12 must hold the VDD voltage above the UVLO turn-off

threshold until the AUX voltage rises high enough to forward bias D12. If the value of C12 is not high enough the

VDD voltage will decay below the UVLO turn-off threshold and the converter will prematurely stop switching. The

controller will continuously cycle on-and-off as the VDD voltage transitions between UVLO turn-on and UVLO

turn-off. One of the most common issues seen with new designs is the VDD capacitor value is too low and

“there's no output voltage”or "it's not starting" is reported.

First, estimate a total HV soft start time, t_SS. This estimate must include: (1) time for the COMP voltage to rise

from 0 V to the PWM switching threshold (COMP to CS offset, 1.15 V_TYP), and (2) time for the AUX voltage (on

C13) to rise from 0 V until it forward biases D12. Typical values are 1-2 ms for the COMP rise time and 10-14 ms

for the AUX rise time. Calculate the VDD capacitor value with the following equation

I

+ 1.25 × f

× Q

× t

SS

VDD_MAX

VDD

SW GATE

C

>

(27)

VDD

− VDD

OFF

ON

Using I_{VDD_MAX}= 2 mA, f_SW= 42.5 kHz, Q_GATE= 11 nC, t_SS= 14 ms (2ms + 12ms),

VDD_ON= 17.6 V, and VDD_OFF= 14.5 V results in

C

> 11.7 µF

(28)

VDD

Allowing ±20% initial capacitor tolerance and another 20% for endurance (life, temperature, etc.) means the VDD

bulk capacitor must be at least 19.5 µF. Select the next higher standard capacitor value, 22 µF. This capacitor

should be rated to at least the ABS MAX voltage of the VDD pin, 30 V.

The electrolytic bulk capacitor (C12) should be located relatively close to the VDD pin. On the other hand, the

high-frequency bypass capacitor, C18, must be a ceramic type and be physically placed and grounded as close

as possible to the VDD pin. A 1.0 μF, X7R capacitor is recommended for the high-frequency decoupling. To

offset the effects of DC-bias, this capacitor must be rated to about 2x the expected VDD voltage (≥35V)

9.2.2.9 Gate Drive Network (R14, R16, Q6)

When the primary MOSFET turns on in DCM operation, its current starts from 0A and ramps up to a peak value

each PWM cycle. Therefore, to reduce gate drive losses and increase overall efficiency, it is desirable to turn the

MOSFET on relatively slowly when its current (and losses) are low. On the other hand, when the current ramps

up to its peak the MOSFET must be turned off quickly to limit its losses, which also helps increase efficiency.

R14 is the gate driver resistor controlling the turn-on time of the MOSFET (Q5). The optional PNP pull-down

transistor (Q6) is used to turn the MOSFET off as quickly as possible, when the MOSFET is far away from the

controller gate driver pin.

The selection of R14 resistor value must be done in conjunction with EMI compliance testing and efficiency

testing. Using a larger resistor value for R14 slows down the turn-on of the MOSFET. A slower switching speed

reduces EMI but also increases the switching loss. A tradeoff between switching loss and EMI performance must

be carefully performed. For this design, efficiency was measured for a range of values for R14. Efficiency

peaked with a value of 39‑Ωfor R14.

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English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

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9.2.2.10 VREF Capacitor (C18)

The precision 5-V internal reference performs several important functions. The reference voltage is divided down

internally to 2.5 V and connected to the error amplifier’s noninverting input for accurate output voltage

regulation. Other duties of the reference voltage are to set internal bias currents and thresholds for functions

such as the VDD Start and Stop thresholds, and the oscillator upper and lower voltage thresholds. Therefore,

the reference voltage must be bypassed with a ceramic capacitor. A 1.0-µF, 25-V ceramic capacitor was

selected for this converter. Placement of this capacitor on the physical printed-circuit board layout must be as

close as possible to the respective VREF and GND pins.

9.2.2.11 RT/CT Components (R12, C15)

The internal oscillator uses a timing capacitor (C15) and a timing resistor (R12) to program the oscillator

frequency. The operating frequency can be programmed based the curves in Figure 7-1, where the timing

resistor is found once the timing capacitor is selected. It is best for the timing capacitor to have a flat temperature

coefficient, typical of most COG or NPO type capacitors. For this converter, 40.2 kΩand 1000 pF were selected

for R12 and C15 to operate at 42.5-kHz switching.

9.2.2.12 HV Start-Up Circuitry for VDD (Q1, Q2, D2, D4, D6, D8, R5)

The HV Startup circuit utilizes two 600-V depletion mode MOSFETs (Q1, Q2). The depletion mode MOSFET

conducts when no gate voltage is applied and begins to turn off as the V_GSvoltage becomes more and more

negative. It is completely off when V_GSis below the turn-off threshold. The characteristics of the depletion mode

FET make it well suited to implementing a current source for high-voltage startup. It is difficult to find a low-cost

and small-size depletion MOSFET with 1.2-kV rating, but there are wide variety of selection in 600-V to 800-V

domain. Therefore, the stacked depletion MOSFET configuration with the proposed gate clamp circuit will evenly

distribute the voltage stress from the 1-kV input voltage.

First, let’s look at the operation of Q1. Notice the four 130-V Zener diodes; D2, D4, D6 and D8. Their combined

Zener voltage is 520 V. Next, think of R1 as a pull-up resistor to V_INthat simply provides current to the Zener

diodes. With that in mind, it’s obvious that these diodes will be off if V_IN< 520 V. Now, as V_INrises above 520

V, the voltage at the source of Q1 will be clamped slightly above 520 V, let’s say 521 V. In effect Q1 is biased

such that the maximum voltage presented to Q2 is limited to 521 V. The V_DSvoltage of Q1 is V_IN– 520 V. At

1000 V_IN, the V_DSof Q2 will be 521 V and V_DSof Q1 will be 479 V.

Next, let’s look at the operation of Q2. For now, let’s say D5 is a 22-V “safety” clamp to limit the maximum

value of VDD in the event Q3 does not turn on. So, for normal operation it’s practical to assume D5 is off.

When VDD < V_{DD_ON}, Q3 is also off because the controller has not been powered up yet and VREF = 0 V. R3 is

a pull-up resistor (similar to R1 for Q1) that biases D9 on in the forward direction during HV startup. The majority

of current flows from the source of Q2 through R5 and charges the 22-µF capacitor on VDD (C12). We can use

KVL around the loop formed by R3, D9, and R5 and solve for the current through R5.

V

+ V

GS

F D9

R5

I

=

(29)

R5

Typical values for V_{F_D9}and V_GS=V_{TH_Q2}are 0.3 V and 1.0 V, respectively. With this information we can solve for

I_R5

0.3V + 1.0V

I

=

= 1.3 mA

(30)

R5

1kΩ

Notice this current does not depend on V_INso it will be constant over the entire range of V_IN.

If a soft start time requirement is provided (t_SS,MAX) the maximum value of R5 (R5_MAX) can be calculated.

V

+ V

+ I

TH_Q2

× VDD

F_D9

R5

=

(31)

MAX

C

VDD

t

ON

SU_UCC28C5x

SS, MAX

32

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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Q3 functions as a simple switch controlled by VREF from the controller to shut down the HV startup circuit.

When Q3 turns on zener diode D9 is reverse biased and clamps the V_GSvoltage of Q2 to about ‒18 V. Shutting

down the HV startup circuit when it is not needed reduces power and improves efficiency.

This HV startup circuit is presented in detail and compared to traditional NPN-based HV startup circuit in “High-

Density 40W Auxiliary Power Supply Utilizing a SiC MOSFET for 800-V Traction Inverters”, SLUAAL3.

9.2.2.13 Desensitization to CS-pin Noise by RC Filtering, Leading-Edge Blanking, and Slope

Compensation

High-voltage and fast switching leads to a high dv/dt switching node, which generates a fair amount of noise.

During PCB layout, the switching node must be kept away from quiet areas, such as the current sense circuitry,

voltage feedback circuitry, and loop compensation components to reduce noise coupling.

It’s common knowledge that each time the MOSFET turns on a spike appears on the current sense resistor for

a very short time. This spike can cause the MOSFET to turn off early if precautions are not taken. Figure 9

shows several important sub-circuits required for reliable operation. First, and most important, R21 and C22 form

a low pass filter between the (noisy) R_SENSEnode and the CS pin. The low pass filter can attenuate most of the

noise spike but too much filtering will delay the current information too. Second, Q6 and the components

connected to its base are leading-edge blanking. This AC-coupled transistor pulls down on the CS voltage each

time the MOSFET is turned on. The amount of leading-edge blanking is determined by C23, R26, and R27.

At duty cycles above 50 %, current mode control has a subharmonic oscillation phenomenon unless slope

compensation is added. In Figure 9, R22 injects a small amount of voltage ramp to the CS pin. The voltage ramp

for slope compensation is formed by passing the RT/CT voltage through an emitter-follower formed by Q7 and

R23. The emitter follower buffers the RT/CT circuit so the switching frequency will not be changed. C21 ac-

couples the output of the emitter follower to the CS pin (via R22). AC-coupling the slope compensation ramp is

preferred because it avoids adding a DC bias at the CS pin, which would effectively reduce the current limit

threshold. Lastly, C21 should be large enough to pass the slope compensation ramp. Making C21 too small

results in a transient negative voltage at the CS pin when the RT/CT waveform resets, making very small on-

times of the MOSFET impossible. The extra benefit of the slope-compensation signal is to create more noise

margin to the leading-edge spike on CS pin from prematurely turning off primary MOSFET.

U1

UCC28C56H-Q1

R12

40.2k

VREF

8

4

2

1

3

7

6

VREF

RT/CT

FB

VDD

OUT

GND

RT/CT

OUT

C16

100nF

C15

1000pF

VREF

COMP

CS

5

HV_GND

1

HV_GND

Q7

R21

1.00k

Slope Compensation

Current Filtering

CS

Rsense

R22

C21

2.2µF

4.02k

C22

100pF

R23

15.0k

C23

22pF

R26

2.00k

1

Q8

HV_GND

R27

127

Leading Edge

Blanking

HV_GND

图9-2. Figure TBD: Current Filtering, Leading-Edge Blanking, and Slope Compensation

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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9.2.2.14 Voltage Feedback Compensation

Feedback compensation, also called closed-loop control, can reduce or eliminate steady state error, reduce the

sensitivity of the system to parametric changes, change the gain or phase of a system over some desired

frequency range, reduce the effects of small signal load disturbances and noise on system performance, and

create a stable system from an unstable system. A peak current mode flyback uses an outer voltage feedback

loop to stabilize the converter. To adequately compensate the voltage loop, the open-loop parameters of the

power stage must be determined.

9.2.2.14.1 Power Stage Gain, Poles, and Zeroes

The typical power stage of the DCM flyback has a single zero and a single pole. The zero is created by the ESR

of the output capacitors and the output capacitance. The pole is created by the load resistance and the output

capacitance. When the load changes the pole shifts in frequency as 1/RLOAD. The power stage will introduce

the most phase loss when the load is relatively low and RLOAD is high. Therefore, it is best to stabilize the

system and check the stability margins at low VIN, high VIN, light-load, and maximum load.

Start by calculating the location of the power-stage zero

1

f

=

= 4.8 kHz

(32)

ZERO

2 × π × C

× ESR

COUT

2 × π × 2000µF × 16.5mΩ

OUT

Next, calculate the pole location with about 120 % of maximum load, 3.24 A load (R_LOAD= 4.6 Ω)

1

f

=

= 17 Hz

(33)

POLE

2 × π × C

× R

LOAD

2 × π × 2000µF × 4.6Ω

OUT

In this application, the feedback voltage is formed from an auxiliary winding. This feedback path contains a 22-

µF capacitor (C12) and a 4.7-µF capacitor (C13) that introduce another (atypical) low frequency pole. The pole is

formed by the total capacitance (C12+C13) and the equivalent load current of the regulator. The equivalent load

of the regulator is the sum of the operating supply current (IVDD, 1.3 mATYP) and the gate drive current to the

MOSFET (Q_Gx f_SW, 11 nC x 42.5 kHz = 0.47 mA). The VDD voltage is typically 18.6 V, so the equivalent

resistance can be modelled as 18.6 V / 1.77 mA = 10.5 kΩ.

The following figure shows the frequency response of the plant characteristic (a.k.a. COMP-to-output response).

It compares the DCM flyback both with and without the pole formed by AUX components, 22 µF + 4.7 µF / 10.5

kΩ. Notice the response with the AUX components is ~15dB lower with an additional 45 deg of phase loss at 1.0

kHz.

20

0

DCM Flyback

-15 dB diff at

1 kHz

-20

DCM Flyback w/ AUX Components

-40

0

DCM Flyback

-45

-90

-45 deg diff at

1 kHz

DCM Flyback w/ AUX Components

400 600 800 1k 2k

-135

1

2

4

6

8

10

20

40

60 80 100

200

4k

6k 8k 10k

1kHertz/div

freq/Hertz

图9-3. Comparison of DCM Flyback Plant with and without AUX Components

34

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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9.2.2.14.2 Compensation Components

To compensate a peak-current-mode controller it’s very common to use a Type-II compensator. The Type-II

compensator introduces a pole at DC, a relatively low frequency zero (f_Z,COMP), and a higher frequency pole

(f_P,COMP). The pole at DC forces the system to have high gain at very low frequency and zero stead-state error.

VAUX

R17

R18

C19

R19

R20

FB

-

COMP

OUT

+

0

VREF

图9-4. Type-II Compensation with an Error Amplifier

The low frequency zero is formed by R18 and C19

1

f

=

(34)

(35)

(36)

Z, COMP

2 × π × C19 × R18

The higher frequency pole is formed by R18 and C20

1

f

=

P, COMP

2 × π × C20 × R18

The mid-frequency gain of the compensator is given by

R18

G

=

COMP

R17 + R19

First, select a crossover frequency, 625 Hz. Then, use the frequency response of the plant (control-to-output) at

low input voltage to determine how much gain the compensator must add to increase the crossover to the

desired bandwidth. In 图 9-5 the plant is measured to be -23.3 dB at 625 Hz. Therefore, the error amplifier must

have a mid-frequency gain of 14.6 V/V.

105.49356

622.655752

-517.162193

80

60

40

20

0

-20

-40

-23 dB at 625 Hz

1

2

4

6

8

10

20

40

60 80 100

200

400 600 800 1k

REF

2k

4k

6k 8k 10k

20k

A

freq/Hertz

2kHertz/div

图9-5. Measuring the plant gain at the desired crossover frequency: -23 dB at 625 Hz

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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Choose (R17+R19) = 22.5 kΩ, and solve for R18

R18 = G

× R17 + R19 = 14.6 V/V × 22.5kΩ = 328kΩ

(37)

COMP

Select a standard value for R18, like 324 kΩ.

Now that we know R18, it’s fairly straightforward to set f_Z,COMP= f_POLEand solve for C19

1

f

= f

=

= 17 Hz

(38)

(39)

Z, COMP

POLE

2 × π × C19 × 324kΩ

C19 = 28nF

Likewise, set f_P,COMP= f_ZEROand solve the following for C20

1

f

= f

=

= 4.8 kHz

(40)

(41)

P, COMP

ZERO

2 × π × C20 × 324kΩ

C20 = 102pF

Finally, choose standard capacitor values, C19 = 22 nF and C20 = 100 pF. Notice that a slightly lower value was

used for C19 than calculated. This was done to have a faster “reset” time during after a load transient

response. If the complete loop is found to have too little phase margin then C19 can be increased at the cost of

slower reset time.

9.2.2.14.3 Bode Plots and Stability Margins

It’s important to simulate (or measure) the stability margins at low V_INand high V_INat both light load and heavy

load. 图 9-6 to 图 9-9 show the simulated bandwidth, gain margin, and phase margin for this design at 40 V_IN

and 800 V_INat both light load and full load. The phase margin is always above 55 deg and the gain margin is

>20 dB.

36

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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9.2.2.14.4 Stability Measurements

80

60

40

20

0

80

60

40

20

0

820 Hz BW

500 Hz BW

-20

>22 dB GM

>30 dB GM

-40

180

135

90

135

90

71 deg PM

74 deg PM

45

0

-45

-90

-135

-180

-45

-90

-135

-180

1

2

4

6

8

10

20

40

60 80 100

200

400

600 800 1k

REF

2k

4k

6k 8k 10k

20k

A

1

freq/Hertz

2

4

6

8

10

20

40

60 80 100

200

400

600 800 1k

REF

2k

4k

6k 8k 10k

20k

A

freq/Hertz

2kHertz/div

500 Hz Bandwidth

820 Hz Bandwidth

Phase Margin = 74 deg

Gain Margin > 30 dB

Phase Margin = 71 deg

Gain Margin > 22 dB

图9-6. 40 V_IN, Light Load (500 mA)

图9-7. 40 V_IN, Maximum Load (1.33 A)

80

60

40

20

0

80

60

40

20

0

640 Hz BW

845 Hz BW

-20

>28 dB GM

>29 dB GM

-40

180

135

90

135

90

79 deg PM

56 deg PM

45

0

-45

-90

-135

-180

-45

-90

-135

-180

1

2

4

6

8

10

20

40

60 80 100

200

400

600 800 1k

REF

2k

4k

6k 8k 10k

20k

A

1

freq/Hertz

2

4

6

8

10

20

40

60 80 100

200

400

600 800 1k

REF

2k

4k

6k 8k 10k

20k

A

freq/Hertz

2kHertz/div

640 Hz Bandwidth

845 Hz Bandwidth

Phase Margin = 79 deg

Gain Margin > 28 dB

Phase Margin = 56 deg

Gain Margin > 29 dB

图9-8. 800 V_IN, Light Load (500 mA)

图9-9. 800 V_IN, Maximum Load (2.7 A)

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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9.2.3 Application Curves

V_INapplied to V_OUTready in 266 ms

CH1: V_INat 10 V/DIV

V_INapplied to V_OUTready in 224 ms

CH1: V_INat 200 V/DIV

CH2: VDD at 4 V/DIV

CH3: COMP at 2 V/DIV

CH4: VOUT at 4 V/DIV via differential probe

图9-10. HV Startup at 50 V_IN, 20 W

图9-11. HV Startup at 800 V_IN, 40 W

V_DDcapacitor hold-up time = 8.9 ms

V_OUTrise time = 9.1 ms

V_DDcapacitor hold-up time = 12.6 ms

V_OUTrise time = 17.2 ms

CH2: VDD at 4 V/DIV

CH3: COMP at 2V/DIV

CH4: V_OUTat 4 V/DIV via differential probe

图9-13. V_OUTSoft Starting at 800 V_IN, 40 W

图9-12. V_OUTSoft Starting at 50 V_IN, 20 W

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

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Soft Start Overshoot = 1.2 %

Soft Start Overshoot = 2.4 %

CH4: V_OUTat 1 V/DIV via differential probe

图9-14. V_OUTOvershoot at 50 V_IN, 20W

图9-15. V_OUTOvershoot at 800 V_IN, 40 W

Output Voltage Ripple = 298 mV_PP

Output Voltage Ripple = 388 mV_PP

CH4: V_OUTat 200 mV/DIV via differential probe

图9-16. Output Voltage Ripple at 50 V_IN, 20W

图9-17. Output Voltage Ripple at 800 V_IN, 40 W

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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f_SW= 42.6 kHz, t_ON= 16.3 us, Duty Cycle = 69 %

CH1: VGATE at 5 V/DIV

f_SW= 42.3 kHz, t_ON= 1.4 us, Duty Cycle = 5.9 %

CH1: VGATE at 5 V/DIV

CH2: RT/CT at 500 mV/DIV

CH3: COMP at 400 mV/DIV

CH2: RT/CT at 500 mV/DIV

CH3: COMP at 400 mV/DIV

图9-18. PWM Switching at 50 V_IN, 20 W

图9-19. PWM Switching at 800 V_IN, 40 W

250 mA to 2.7 A to 250 mA

V_MAX= 16.1 V, V_MIN= 15.1V, dV = 1.0 V

CH1: COMP at 50 mV/DIV

250 mA to 1.3 A to 250 mA

V_MAX= 16.1 V, V_MIN= 15.4 V, dV = 0.7 V

CH1: COMP at 50 mV/DIV

CH2: I_LOAD at 800 mA/DIV

CH2: I_LOAD at 500 mA/DIV

CH4: V_OUTat 600 mV/DIV via differential probe

图9-21. Load Transient at 800 V_IN, 2.5 A Step

图9-20. Load Transient at 800 V_IN, 1 A Step Change

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UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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9.3 PCB Layout Recommendations

In general, try to keep all high current loop areas as small as possible. Keep all traces with high current and high

frequency away from other traces in the design. If necessary, high frequency/high current traces should be

perpendicular to signal traces, not parallel to them. Shielding signal traces with ground planes can help reduce

noise pick up. Always consider appropriate clearances between the high-voltage connections and any low

voltage nets.

In order to increase the reliability and robustness of the design TI recommends the following PCB layout

guidelines.

9.3.1 PCB Layout Routing Examples

1) The power ground should not disturb (i.e. mix with) the signal ground. The signal ground includes the small

R’s and C’s around the controller (for COMP, FB, RT/CT, CS) and the controller ground pin. The power

ground includes the input capacitors, current sense resistors, return for the Y-capacitor, and gate drive return via

the PNP transistor Q6.

图9-22. Top Layer: Signal Grounds, Power Grounds, and their Connection to a Single-Point Ground

图9-23. Bottom Layer: Signal Grounds, Power Grounds, and their Connection to a Single-Point Ground

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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2) The primary-side power loop must be minimized. Use relatively wide traces. This loop includes the input

capacitors (C2, C3), transformer primary winding (T1 pins 1, 3), switching MOSFET (Q5), and sense resistors

(R24, R25). Do not use vias in this path.

图9-24. Primary-Side Power Loop Routing

3) The secondary-side power loop should be minimized. Use copper pours or very wide traces. This loop

includes the output capacitors (C9, C10), transformer secondary winding (T1 pins 8/9, 10/11), and output rectifier

diode (D11). If interconnection between layers is required use multiple vias to handle the high peak currents.

图9-25. Secondary-Side Power Loop Routing

42

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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4) The AUX feedback loop should be minimized. This loop includes components C13, D13, and the transformer

AUX winding (T1 pins 6, 5).

图9-26. AUX Feedback Loop Routing

5) The loop of the high-voltage clamp must be minimized. This loop includes D1, D3, R2//R28, and D7. All these

components should be on the same layer.

图9-27. High-Voltage Clamp Loop Routing

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

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6) The Y-type capacitor from the isolation ground to the power ground (C14, C24) should route back to the single

point ground without disturbing the signal ground around the controller.

图9-28. Y-Capacitor Ground Routing

7) The trace from the OUT pin (U1 pin 6) to the gate of the switching MOSFET (Q5-1) must be as short as

possible and relatively wide. Do not use vias in this path.

图9-29. Gate Drive (OUT) Trace Routing

44

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

8) The collector of the PNP gate pull-down transistor (Q6 pin 3) should route directly back to the single point

ground without disturbing the signal ground around the controller.

图9-30. Gate Pull-Down PNP Transistor Collector Routing

9) The connection from the current sense resistors (R24/R25) to the low-pass filter (R21, C22) and on to the CS

pin must be direct and it must avoid noisy signals. For example, do not route this trace near the MOSFET gate

drive or SW node.

图9-31. Current Sense Trace Routing

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

10) The loop formed by the R-C snubber (R4, C5) around the output rectifier diode (D11) should be minimized.

Do not use vias in this path.

11) The VDD pin must have a ceramic capacitor (C18) located as close as possible.

12) The VREF pin must have a ceramic capacitor (C16) located as close as possible.

13) The compensation components (R18, C19, C20) must be located near the COMP pin.

14) The feedback divider components (R17, R19, R20) must be located near the FB pin.

15) The frequency setting components (R12, C15) must be located near the RT/CT pin.

46

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

9.4 Power Supply Recommendations

The absolute maximum supply voltage is 30 V, including any transients that may be present. If this voltage is

exceeded, device damage is likely. Thus, the supply pin must be decoupled as close to the GND pin as possible.

Also, because no clamp is included in the device, the supply pin must be protected from external sources which

could exceed the 30-V level.

To prevent false triggering due to leading edge noises, an RC current sense filter may be required on CS. Keep

the time constant of the RC filter well below the minimum on-time pulse width.

To prevent noise problems with high-speed switching transients, bypass VREF to ground with a ceramic

capacitor close to the device package. A minimum of 0.1-µF ceramic capacitor is required. Additional VREF

bypassing is required for external loads on the reference. An electrolytic capacitor may also be used in addition

to the ceramic capacitor.

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Product Folder Links: UCC28C50-Q1 UCC28C51-Q1 UCC28C52-Q1 UCC28C53-Q1 UCC28C54-Q1

UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

UCC28C50-Q1, UCC28C51-Q1, UCC28C52-Q1, UCC28C53-Q1, UCC28C54-Q1, UCC28C55-Q1,

UCC28C56H-Q1, UCC28C56L-Q1, UCC28C57H-Q1, UCC28C57L-Q1, UCC28C58-Q1, UCC28C59-Q1

ZHCSQ75C –JUNE 2022 –REVISED MARCH 2023

www.ti.com.cn

10 Device and Documentation Support

10.1 Device Support

10.1.1 Development Support

10.2 Documentation Support

10.2.1 Related Documentation

(UCC28C5x-Q1 Technical Documents)

10.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

表10-1. Related Links (to be updated)

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

UCC28C50-Q1

UCC28C51-Q1

UCC28C52-Q1

UCC28C53-Q1

UCC28C54-Q1

UCC28C55-Q1

Click here

10.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

10.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

10.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

10.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

48

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UCC28C55-Q1 UCC28C56H-Q1 UCC28C56L-Q1 UCC28C57H-Q1 UCC28C57L-Q1 UCC28C58-Q1

UCC28C59-Q1

English Data Sheet: SLUSEV2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC28C57HQDRQ1
厂家：	TEXAS INSTRUMENTS
描述：	汽车类 30V 低功耗电流模式 PWM 控制器，适用于 SiC，18.8V/15.5V UVLO，50% 占空比 \| D \| 8 \| -40 to 150 控制器
文件：	总54页 (文件大小：2568K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC28C57HQDRQ1 [TI]

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UCC28C59DR

UCC28C59QDRQ1

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