UCC2975_15 [TI]
MULTI-TOPOLOGY PIEZOELECTRIC TRANSFORMER CONTROLLER;
| 型号： | UCC2975_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MULTI-TOPOLOGY PIEZOELECTRIC TRANSFORMER CONTROLLER |
| 文件： | 总28页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢂꢃ ꢄꢄ
ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
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FEATURES
DESCRIPTION
D
3-V to 13.5-V Operation
Liquid crystal display (LCD) enclosures and cold
D
Supports Flyback (UCC3975), Half-Bridge
(UCC3976), and Push-Pull (UCC3977)
Topologies
cathode fluorescent lamps (CCFLs) used in
notebook computer and portable electronics
displays are becoming increasingly narrow,
generating the need for a low profile CCFL power
supply. Recent advances in single- and
multi-layered piezoelectric ceramic transformers
(PZT) have enabled the development of a new
generation of efficient, size-reduced backlight
converters. The UCC3975/6/7 family of 8-pin PZT
controllers integrate the necessary circuitry for
operating a PZT-based backlight supply using a
flyback, half-bridge, or push-pull topology. The
choice of power topology depends on application
requirements such as input voltage, lamp voltage,
and PZT gain.
D
D
D
D
D
Programmable Voltage Controlled Oscillator
Open Lamp Protection
Low Shutdown Current (15-µA Typical)
Dual MOSFET Drivers
8-Pin TSSOP package
APPLICATIONS
D
D
D
Notebook Computers
Portable Electronics Displays
Portable Instruments
D
OPEN
SHUTDOWN
VDD
C
OPEN
R
OPEN
1
2
OPEN/SD
VDD
8
7
R
OSC
OUTP
HV
LRES
C
OSC
RANGE
UCC3976
R
OSC
R
3
COMP
OUTN
6
5
PIEZO
XFMR
C
CNT
FB
4
FB
GND
R
R
FB
D
FB
CCFL
CS
UDG–01092
Figure 1. UCC3976-Based CCFL Power Supply Using a Resonant Half-Bridge Topology
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Copyright 2002, Texas Instruments Incorporated
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1
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢄ
ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
description (continued)
A half-bridge PZT converter, using the UCC3976 is shown in Figure 1. External P- and N-channel MOSFETs
are driven out of phase at a fixed 50% duty cycle with anti-cross conduction circuitry provided by the controller.
The half-bridge topology uses only a single magnetic component (LRES) reducing board area. As explained
in the applications section of this datasheet, regulation of lamp current is achieved by controlling the operating
frequency of the system.
The UCC3977 is designed to control a resonant push-pull topology as shown in Figure 2. This controller
alternately drives external N-channel MOSFETs at 50% duty cycle. The push-pull topology requires two external
inductors (L1 and L2), but has the advantage of providing increased voltage across the piezoelectric transformer
primary. In this case a small overlap is provided to the gate drives, assuring an uninterrupted path for inductor
current.
D
OPEN
SHUTDOWN
C
R
OPEN
OPEN
VDD
1
2
OPEN/SD VDD 8
L1
L2
UCC3977
OSC
PIEZO XFMR
R
HV
N1
N2
OUT1 7
R
C
OSC
OSC
R
ANGE
3
4
COMP
FB
OUT2 6
R
C
FB
CNT
GND
5
V
CNT
R
FB
D
FB
CCFL
R
CS
UDG–01097
Figure 2. UCC3977 Based CCFL Power Supply Using a Resonant Push-Pull Topology
For piezoelectric transformer applications requiring additional gain, a resonant flyback topology can be
implemented using the UCC3975. As shown in Figure 3, a magnetic transformer (T1) provides a stepped up
voltage to the piezoelectric transformer primary. When compared to a traditional high-voltage transformer used
in a CCFL application, T1 is small and low profile because of its reduced turns ratio and voltage rating. In the
resonant flyback application, a single switch is driven at 50% duty cycle producing a half wave rectified sinusoid
at the piezoelectric transformer primary.
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
description (continued)
SHUTDOWN
C
R
OPEN
OPEN
VDD
1
2
OPEN/SD VDD
UCC3975
8
PIEZO
XFMR
OSC
R
HV
OUTP
7
6
R
C
OSC
OSC
RANGE
N
3
4
COMP
FB
OUTN
GND
R
C
CNT
FB
5
V
CNT
R
FB
D
FB
CCFL
R
CS
UDG–01098
Figure 3. UCC3975-Based CCFL Power Supply Using a Resonant Flyback Topology
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage
Input voltage
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
OPEN/SD, OSC, COMP, FB, VDD, OUTP . . . . . . . . . . . . . . GND–0.5 V to V +0.5 V
DD
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
stg
J
†
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are respect to GND.
AVAILABLE OPTIONS
†
PACKAGED DEVICES TSSOP (PW)
TOPOLOGY
T
A
FLYBACK
HALF-BRIDGE
UCC2976PW
UCC3976PW
PUSH-PULL
–40°C to 85°C
0°C to 70°C
UCC2975PW
UCC3975PW
UCC2977PW
UCC3977PW
†
The PW package is available taped and reeled. Add TR suffix to device type
(e.g. UCC2975TRPW) to order quantities of 2500 devices per reel.
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢄ
ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
electrical characteristics V
A
= 3 V to 13.5 V, T = 0°C to 70°C for UCC3975/UCC3976/UCC3977,
A
DD
T = –40°C to 85°C for the UCC2975/UCC2976/UCC2977, T = T (unless otherwise noted)
A
J
input supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.5
UNITS
mA
µA
Normal,
V
= 12 V
1
DD
VDD supply current
Shutdown
20
2.85
200
100
3.00
300
VDD UVLO (turn-on) threshold voltage
UVLO hysteresis
2.70
100
V
mV
output
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.9
UNITS
P–channel driver output voltage, V
I
I
I
= 100 mA,
= –100 mA,
= 100 mA,
Driving logic low
0.5
0.5
0.5
OUTP
– V
PIN
PIN
PIN
P-channel driver output voltage, (V
Driving logic high
Driving logic low
0.9
DD
OUTP)
V
Low-level N–channel driver output voltage, V
0.9
OUTN
High-level N–channel driver output voltage,
I
= –100 mA,
Driving logic high
0.5
0.9
PIN
(V
DD
– V
OUTN)
Rise time
Fall time
200
200
250
V
= 5 V,
C = 1 nF,
L
DD
See Note 1
ns
Dead (overlap) time
See Note 1
oscillator
PARAMETER
TEST CONDITIONS
MIN
1.6
TYP
MAX
1.8
UNITS
Upper threshold voltage
Lower threshold voltage
Frequency
1.7
0.70
100
V
0.65
95
0.80
105
R
= 24 kΩ,
C
= 470 pF
OSC
kHz
OSC
error amplifier
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.535
6
UNITS
V
Input voltage
1.465
–2
1.500
2
Line regulation voltage
Input bias current
Open loop gain
3 V ≤ V
DD
≤ 13.5 V
mV
nA
–500
60
–100
80
0.5 V ≤ COMP ≤ 3.0V,
FB = 2 V, OPEN/SD = 1 V
= 0.23 mA
See Note 1
dB
Low-level output voltage
0.08
0.15
5.0
10
6
V
mA
µA
I
COMP
FB = 1 V,
COMP = 2 V
1.5
–10
2.5
Output source current
FB = 1 V,
COMP = 2 V,
OPEN/SD = 3 V
FB = 2 V,
COMP = 2 V
COMP = 2 V,
4.5
2
mA
µA
Output sink current
FB = 2 V,
–10
10
OPEN/SD = 3 V
Unity gain bandwidth frequency
T = 25°C,
J
See Note 1
MHz
NOTE: 1. Ensured by design. Not production tested.
4
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SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
electrical characteristics V
A
= 3 V to 13.5 V, T = 0°C to 70°C for UCC3975/UCC3976/UCC3977,
A
DD
T = –40°C to 85°C for the UCC2975/UCC2976/UCC2977, T = T (unless otherwise noted)
A
J
mode select
PARAMETER
TEST CONDITIONS
MIN
2.45
TYP
2.50
MAX
2.65
0.7
UNITS
Shutdown threshold voltage
Restart threshold voltage
0.3
0.5
V
UCC2975
UCC2976
UCC2977
1.3
1.5
1.6
1.6
Open lamp detect enable threshold voltage
UCC3975
UCC3976
UCC3977
1.4
1.5
V
MODE pull-down current
No lock threshold voltage
200
2.4
250
2.5
300
2.6
mA
V
functional block diagram
The UCC397x family of controllers contain an error amplifier whose output is preconditioned at startup, a
precision window comparator used to form the VCO, and dual MOSFET drivers customized for half-bridge or
push-pull operation. The part includes a frequency lock retry circuit, low current shutdown, and open lamp fault
protection.
2.5 V
SHUT DOWN
S
R
Q
Q
SLEEP
OPEN/SD
+
+
PWRUP
FAULT
FAULT
COUNTER
PWRUP
0.5 V
RESET
SLEEP
RESET COUNT
REF
UVLO
FAULT
OPEN LAMP
1.5 V
INIT
+
NO LOCK
0.1 V
2.5 V
COMP
FB
SLEEP
+
R
+
INIT
S
Q
VDD
ERROR
AMPLIFIER
SLEEP
INIT
OUTP/OUT1
+
1.5 V
1.5 V
1.4 V
OUTN/OUT2
GND
D
Q
Q
R
S
1.7 V
0.7 V
+
+
Q
CK
OSC
1.75 V
Figure 4
UDG–01053
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SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
Terminal Functions
TERMINAL
NO.
UCCx975
UCCx976
UCCx977
I/O
DESCRIPTION
NAME
COMP
3
4
5
1
O
I
Output of the error amplifier and control voltage used to set the VCO frequency
Inverting input to the error amplifier
FB
GND
O
I
Ground reference for the device
OPEN/SD
Open lamp protection and a low power shut down
Common connection point for components that control the frequency range for the voltage con-
trolled oscillator (VCO)
OSC
2
7
I
Output of an internal CMOS driver used to drive an N-channel MOSFET (for UCC3977), or a
P-channel MOSFET (for UCC3976) left open for UCC3975
OUTP/OUT1
O
OUTN/OUT2
VDD
6
8
O
O
Output of an internal CMOS driver used to drive an N-channel MOSFET.
Connects to the battery or system voltage
UCC2975, UCC2976
UCC3975, UCC3976
PW PACKAGE
UCC2977, UCC3977
PW PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
8
7
6
5
1
8
7
6
5
OPEN/SD
OSC
VDD
OPEN/SD
OSC
VDD
2
3
4
OUT1
OUT2
GND
OUTP
OUTN
GND
COMP
FB
COMP
FB
6
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SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
pin assignments
OPEN/SD: This dual-purpose pin provides open lamp protection and a low power shutdown capability for the
part. This pin can also be used to provide burst mode dimming explained in the applications section that follows.
open lamp function
During startup this pin is internally driven low setting the initial condition for the open lamp circuit. An
external peak detection circuit interfaces between this pin and the lamp. If the voltage at the pin exceeds
1.5 V, an open lamp is assumed and the part re-initiates a startup sequence up to 7 times. If the lamp fails
to strike after 7 tries, the device enters an error shutdown mode. An open lamp induced shutdown can be
cleared either by cycling power on the device or by pulling the pin above 2.5 V and then below 0.5 V.
shutdown function
The device is put into shutdown mode (15-µA of typical quiescent current) by forcing the pin above 2.5 V.
When this pin is subsequently brought below 0.5 V, the device comes out of shutdown mode and initiates
a new startup cycle. This pin can be used to delay startup until the system voltage is sufficient to strike
and operate the piezoelectric transformer.
OSC: This pin is the common connection point for components that control the frequency range for the voltage
controlled oscillator (VCO). An external RC circuit connected from this pin to ground sets the center frequency
for the VCO, where a second resistor connected from this pin to the COMP pin sets the allowable frequency
range. A precision window comparator is used to keep the exponentially decaying ramp voltage at this pin
between 0.7 V and 1.7 V. When the voltage decays below 0.7 V, an internal pull-up circuit charges this pin to
1.7 V, the voltage is then allowed to decay to 0.7 V at a rate determined by the external components. Equations
are provided in the applications section to assist in determining the size of the external components to achieve
the desired frequency range.
COMP: This pin is the output of the error amplifier and control voltage used to set the VCO frequency. During
startup internal switches precondition this output to 0 V producing the maximum frequency of operation. The
error amplifier is then allowed to slew its output voltage until the lamp strikes and lamp current is regulated. The
slew rate is set by the external feedback components. If this pin reaches 2.5 V, regulation was not achieved and
startup will be re–initiated up to 7 times.
FB: This is the inverting input to the error amplifier. This input is compared to 1.5 V and is used to control lamp
current.
OUTP/OUT1: This pin is the output of an internal CMOS driver used to drive an N-channel MOSFET in the case
of the UCC3977 or a P-channel MOSFET in the case of the UCC3976. This pin is low slightly less than 50%
duty cycle in the case of the UCC3976 to prevent cross-conduction and is high slightly more than 50% duty cycle
in the case of the UCC3977 to provide overlap. This pin is left open for the UCC3975.
OUTN/OUT2: This pin is the output of an internal CMOS driver used to drive an N-channel MOSFET in the case
of the UCC3975 and UCC3976 or the second N-channel MOSFET in the case of the UCC3977. This pin is high
slightly less than 50% duty cycle in the case of the UCC3975 and UCC3976. The pin is high slightly more than
50% duty cycle in the case of the UCC3977 to provide overlap.
VDD: This pin connects to the battery or system voltage. This pin should be bypassed with a minimum of 0.1-µF
of capacitance directly at the device , with an additional 5-µF to 10-µF low ESR bulk capacitor (ceramic is
preferred).
GND: Ground reference for the device. This pin should be used as the common ground point for power and
signal level ground traces.
7
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SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
state diagram
A logic state diagram for the UCC397x family of controllers is shown in Figure 5. During power-up the controller
transitions from UVLO to the momentary startup state. During startup, the COMP pin is preconditioned at
maximum frequency and the OPEN/SD capacitor is discharged before beginning normal operation. In the
normal operating state, the frequency is swept from high to low allowing the lamp to be struck and the current
in the lamp to be regulated.
ERROR
SHUTDOWN
YES
Increment COUNT
COUNT=7?
OSC active
OUT off state
* Momentary states
NO
UVLO
STARTUP *
NO–LOCK *
VDD>3.0V
VDD < 3.0V
OSC inactive
OUT off state
COUNT=0
OPEN/SD = 0V
COMP = 0V
OSC, OUT active
COMP > 2.5V
OPEN/SD < 1.5V
OSC, OUT active
SHUTDOWN
OPEN/SD > 2.5V
COUNT =0
NORMAL OPERATION
OPEN LAMP *
OSC inactive
OUT off state
Low current VDD,
OPEN/SD
OPEN/SD < 1.5V
COMP < 2.5V
OSC, OUT active
1.5V < OPEN/SD <2.5V
COMP < 2.5V
OPEN/SD
< 0.5V
OSC, OUT active
OUT off state
UCC3975: OUT1 low, OUT2 low
UCC3976: OUTP high, OUTN high
UCC3977: OUT1 low, OUT2 low
UDG–01102
Figure 5. State Diagram
The normal operating state can be exited in one of four ways:
•
•
•
•
bringing V
< 3 V
DD
a user commanded shutdown (OPEN/SD > 2.5 V)
an open lamp condition (OPEN/SD > 1.5 V), or
if the device fails to achieve regulation before reaching minimum frequency (EAO > 2.5 V).
The latter two conditions cause an internal retry counter to increment before attempting another startup. If the
application does not operate normally after seven retrys, the controller enters an error induced shutdown state
removing power to the load. The error state and counter can be cleared by removing V
user commanded shutdown.
to the part or by a
DD
8
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
PZT operation
Ceramic piezoelectric transformers were first proposed by C.A. Rosen in 1956. Unlike magnetic transformers
that rely on electromagnetic energy transfer, PZTs transfer electric potential to mechanical force as shown in
Figure 6. The electrical-to-mechanical conversion of energy is referred to as the reverse piezoelectric effect
whereas the mechanical-to-electrical energy conversion is referred to as the direct piezoelectric effect.
MECHANICAL
FORCE
ELECTRIC
POTENTIAL
MECHANICAL
FORCE
ELECTRIC
POTENTIAL
+
+
UDG–01099
Figure 6. Piezoelectric Effect
Each manufacturer has a unique recipe of materials and structural layering that determine their PZT’s operating
characteristics. Common materials used to make PZTs include lead zirconate, lead titanate and lithium niobate.
Single layer PZTs are less costly and easier to manufacture, but have a lower voltage gain (typically 5 to 10 )
and may require a step-up magnetic transformer in order to operate the lamp. Multi-layered PZT designs are
more difficult to manufacture, but have a higher voltage gain (20 to 70) allowing a CCFL to be driven using
conventional off-the-shelf inductors.
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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
VOUT
PRIMARY
FORCE
SECONDARY
VIN
FORCE
h = HEIGHT
T = THICKNESS
SUPPORTS
L = LENGTH
MECHANICAL
DISPLACEMENT
0
0
MECHANICAL
STRESS
UDG–01076
Figure 7. Typical Longitudinal Mode Piezoelectric Transformer for CCFL Applications.
A typical multi-layer PZT with longitudinal mode geometry is shown in Figure 7, a single layer design would have
similar construction without the layering on the primary. An ac voltage is applied to the V electrodes causing
IN
mechanical expansion and compression in the thickness direction (see Figure 6). This displacement on the
primary is transferred as a force in the longitudinal direction. Supports at ¼ and ¾ wavelength provide a means
for a standing wave to be generated at a resonant frequency as shown. Mechanical resonance occurs at
multiple standing wave frequencies (n) based on the transformer’s length and material velocity (v).
v
f + n
n
2 length
(1)
Voltage gain is a function of the PZT material coefficient g[ω], the number of primary layers, the thickness of
the material and the overall length as follows:
length layers
[ ]
g w
V
+
GAIN
thickness
(2)
An electrode at V
is used to recover the amplified electrical potential at the secondary.
OUT
PZT electrical model
In order to predict PZT performance in a system, it is useful to develop an electrical circuit model. The model
shown in Figure 8 is often used to describe the behavior of a PZT near the fundamental resonant frequency.
Many PZT manufacturers will provide component values for the model based on measurements taken at
various frequencies and output loads.
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
L
C
R
1 : n
C
C
R
OUT
INPUT
V
IN
V
OUT
LOAD
UDG–01100
Figure 8. Equivalent Piezoelectric Transformer Circuit Model
The component values depend on the PZT’s construction. A large primary capacitance (C
) is formed as
INPUT
a result of the multi-layer construction of the primary electrodes and material dielectric constant. The output
capacitance is much smaller due to the distance between the primary and secondary electrodes. Typical values
of C
and C
for a multi–layer PZT may be 0.2 µF and 20 pF respectively, where a single layer design
INPUT
OUT
would have lower C
since layers =1.
INPUT
length width layers å
C
C
+
INPUT
2 thickness
(3)
(4)
2 thickness width å
+
OUTPUT
length
C
and an external transformer or inductor(s) are used to form a primary-side L-C resonant circuit as
INPUT
depicted in Figures 1, 2 and 3. These circuits provide sinusoidal waveforms at the primary, allowing the PZT
to operate at higher efficiency. The mechanical resonant frequency (ω ) of the PZT (which differs from the
0
natural primary L-C resonant frequency) is proportional to the material elasticity (Y), density (ρ) and length.
1
Y
ò
Ǹ
w T
0
length
(5)
The mechanical piezoelectric gain near a single resonant frequency can modeled by a series R, L, and C circuit
as depicted in Figure 8.
1
w +
0
Ǹ
L C
(6)
(7)
L
R
Q + w
0
Figure 9 illustrates the gain-vs-output load and frequency characteristics for a 12-layer, 70-kHz PZT with the
following Figure 8 values:
•
•
•
•
C
= 0.2 µF
INPUT
C
= 30 pF
OUT
n = 30
series RLC (2 Ω, 1 µH, 6 nF)
As shown in Figure 9, the ceramic transformer provides high Q and gain under light or no-load conditions
producing a high-strike potential. Once the lamp strikes the transformer becomes loaded, causing the
transformer gain to decrease and resonant frequency to shift. The piezoelectric transformer is typically operated
on the right side of resonance to allow the lamp to be struck and operated with a single direction control circuit.
A typical application has separate start (A), strike (B), and operating (C) frequencies (see Figure 9).
11
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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
lamp characteristics
A cold cathode fluorescent lamp has non-linear V-I characteristics as shown in Figure 10. The lamp’s intensity
(lumens) is roughly proportional to lamp current where lamp voltage remains somewhat constant over the
operating range. Lamp voltage is dependant on the diameter and length of the lamp used in the application. This
results in increased impedance when the lamp is dimmed. The impedance of the lamp will influence the gain
of the piezoelectric transformer (see Figure 9) and thus the operating frequency of the system.
PIEZOELECTRIC GAIN
CCFL CURRENT
vs
vs
FREQUENCY
LAMP VOLTAGE AND IMPEDANCE
300
250
200
150
100
50
800
750
700
650
600
550
3000
2500
2000
1500
1000
500
LAMP
VOLTAGE
R
= 750 kΩ
OUT
R
= 500 kΩ
OUT
strike
B
LAMP
R
= 250 kΩ
OUT
IMPEDANCE
R
= 100 kΩ
OUT
start
C
A
operate
500
0
0
1
2
3
4
5
6
0
60
65
70
75
80
I
– Lamp Current – mA
LAMP
f – Frequency – kHz
Figure 10
Figure 9
variable frequency control system
A simplified block diagram of a PZT based backlight converter is shown in Figure 11. The PZT is driven by a
resonant power stage whose amplitude is proportional to input voltage. The PZT then provides the voltage gain
necessary to drive the lamp. A control loop is formed around the error amplifier that compares average lamp
current to a reference signal (REF) allowing the intensity of the lamp to be regulated. The resulting control
voltage V drives a VCO that determines the operating frequency of the resonant power stage.
C
The frequency range of the VCO must include the strike and operating frequencies of the PZT with some
tolerance included for component variation. Minimizing the programmable range improves the control response
of the feedback loop. For example, a frequency range of 67 kHz to 77 kHz might be used for the PZT in Figure 9.
The gain of the PZT must guarantee sufficient lamp voltage at minimum input voltage to ensure that the control
loop will always operate on the right side of resonance.
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
DC INPUT
VOLTAGE
RESONANT
POWER
STAGE
PIEZOELECTRIC
TRANSFORMER
ERROR
AMPLIFIER
CCFL
VOLTAGE
CONTROLLED
OSCILLATOR
REF
+
V
C
–
LAMP CURRENT
SENSE
UDG–01101
Figure 11. Control System for Variable Frequency PZT Backlight Control
programming the frequency range
The frequency range of the UCC397x family is programmed with external components R
, C
, and R
OSC OSC ANGE
(see Figures 2 and 3). The programmed range should include the strike and operating frequency required for
lamp operation, plus sufficient tolerance for component variations. An accurate NPO capacitor is recommended
for C
(between 100 pF and 1000 pF) while 1% resistors are recommended for R
and R
. The VCO
OSC
OSC
ANGE
frequency is determined by the charge and decay times between 0.7 V and 1.7 V at the OSC pin. When the
voltage reaches 0.7 V, an internal pull-up circuit charges OSC back to 1.7 V, the charge time (t ) varies with
CHG
the value of C
but is typically on the order of 500 ns. The decay time (t
) is determined by the value
OSC
DISCH
of C
by R
the R
and the discharge currents generated in R
and C
and R
. The nominal discharge time at OSC is set
(see equation [8]), the frequency range is programmed by adjusting the discharge time with
OSC
OSC
OSC
ANGE
OSC
resistor and the COMP voltage (see equation [9]):
ANGE
nominal
1.7
lnǒ Ǔ
t
+ R
C
DISCH
OSC
OSC
0.7
(8)
with lamp
1.7 ǒR
Ǔ * V
) R
) R
R
R
R
R
C
OSC
OSC
ANGE
COMP
COMP
OSC
OSC
OSC
ANGE
OSC
ǒV
Ǔ +
t
ln
ƪ
ƫ
DISCH
COMP
R
) R
0.7 ǒR
Ǔ * V
OSC
ANGE
ANGE
(9)
resulting frequency
1
Frequency ǒV
Ǔ +
COMP
ǒV
Ǔ
t
) t
CHG
DISCH
COMP
(10)
13
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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
Equations 8 and 9 are derived by solving Laplace or differential equations for the RC decay time from 1.7 V to
0.7 V with and without the effect of V . The resulting frequency of the system is given in equation 10. This
COMP
frequency should be verified in the lab and may need adjustment depending on factors such as extra
capacitance at the OSC pin (oscilloscope measurements can affect frequency) as well as noise. Figure 12
shows the resulting frequency-to-control voltage relationship with the component values listed below the figure
and a t
time of 500 ns.
CHG
ERROR AMPLIFIER VOLTAGE
vs
OSCILLATOR FREQUENCY
80
78
R
C
R
= 15.8 kΩ
= 560 pF
OSC
OSC
= 162 kΩ
ANGE
76
74
72
70
68
66
64
62
60
0
0.5
1.0
1.5
2.0
2.5
V
– Error Amplifier Voltage – V
COMP
Figure 12
14
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
setting lamp current
The lamp current is controlled by adjusting the frequency of the PZT. System frequency and lamp current control
is accomplished through the error amplifier (EA) and the voltage controlled oscillator (VCO) as shown in
Figure 12. Lamp current is sensed at RCS and is averaged at EA– by RFB and CFB.
Ǹ
2
V
+ I
RCS
CS
LAMP
p
(11)
Equation (11) assumes the error amplifier loop is closed, the relationship between V
and V
(dimming
CS
CNT
control voltageǒ)Vis given in equation (4).
Ǔ ) ǒV
Ǔ
R
R
CNT
FB
CNT
CNT
CNT
1.5 V +
R
) R
FB
(12)
The relationship between control voltage and lamp current can be easily programmed for the application. For
example suppose maximum lamp current is 5 mA (V 0 V) and minimum lamp current is 1 mA
is calculated to be 1100 Ω by using equation (12) and setting the lamp current to 3 mA
=
CNT
(V
(V
= 3 V). R
CS
CNT
CNT
= 1.5 V, V = 1.5 V). R
is calculated to be 150 kΩ by selecting R at 100 kΩ and solving equation
CS
CNT
FB
(12) at maximum lamp current (V
current equation becomes:
= 0 V, I
= 5 mA). Using these, the resulting control voltage to lamp
CNT
LAMP
3.75 * V
CNT
I
+
LAMP
742
(13)
•
•
•
R
= 1100 Ω
= 150 kΩ
CS
R
CNT
R
= 100 kΩ
FB
sizing the feedback capacitor
Feedback design with a PZT requires both modeling and measurement. The uncompensated feedback gain
for the system is primarily affected by the gain slope of the PZT near its resonant operating frequency as shown
in Figure 9. For most designs, the safe unity gain crossover frequency of the feedback loop will be determined
by the amount of gain peaking that occurs at the resonant frequency of the PZT transformer. R and C
are
FB
FB
selected to have a fairly low crossover frequency to ensure that the system gain does not increase above unity
at the resonant switching frequency. Since the gain slope is dependant on the lamp load and PZT model, it is
recommended that a network analyzer is used to validate sufficient gain and phase margin for the design.
A simple first order (or integral) feedback stage is used to stabilize the feedback response of the system.
Selection of the feedback capacitor (C ) and resistor (R ) is primarily dependant upon the small signal gain
FB
FB
of the system and the desired sweep rate of the VCO. If the frequency is swept too rapidly at startup (with an
undersized C ), the feedback loop will not stabilize after the lamp is struck and the controller will cycle through
FB
the VCO frequency range without locking. A feedback capacitor that is too large has poor transient performance.
A C value of 0.1 µF is usually a good starting point for most designs if R is 100 kΩ. With analog dimming,
FB
FB
the C value must be large enough to be stable at high V and minimum lamp current (maximum PZT gain
FB
IN
slope and load). The C value can be decreased with burst dimming since the lamp is operated at full load
FB
where the PZT gain slope is reduced.
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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
matching the PZT to the lamp, input voltage and topology
A fundamental challenge in the design of a piezoelectric transformer-based CCFL application is to match the
lamp’s power requirements with the transformer. Since the piezoelectric transformer is a mechanical system,
the energy delivered by the transformer is a function of its mass and its vibrational velocity (ν).
2
energy T mass n
(14)
The power delivered by the transformer is described in equation (15):
d
dt
power + energy + energy frequency
(15)
The design challenge becomes how operate the transformer within its gain and power delivering capabilities
while optimizing overall system efficiency. This optimization requires knowledge of both the lamp and
piezoelectric transformer for the particular application. Achieving optimal efficiency with a given lamp and
piezoelectric transformer will require bench measurements and design iterations. There are several factors that
should be taken into consideration when selecting a piezoelectric transformer:
•
•
•
•
What is the recommended input voltage for the PZT?
What is the input capacitance of the PZT?
What is the gain of the transformer at various load conditions? (see Figure 9)
At what frequency does the PZT give maximum gain?
The recommended input voltage and gain of the piezoelectric transformer influence the power topology
selection. As mentioned earlier, the half-bridge topology gives the least gain where the push-pull topology
doubles the primary voltage. The flyback topology can provide additional gain through the flyback transformer.
The input capacitance and operating frequency of the piezoelectric transformer determines the required value
of the external inductor(s) (or transformer inductance in the case of the flyback). The external inductance value
may need to be further optimized to get the best performance.
16
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
half-bridge operation and inductor selection
In the half-bridge topology, the external inductor and piezoelectric capacitance form a low-pass filter between
the common switch node of the external MOSFETs and the piezoelectric primary as shown on the front page.
The L-C filter formed by these components should pass the resonant frequency, required by the piezoelectric
transformer, yet attenuate higher harmonic components. The choice of inductor will require bench
measurements and modeling of the resonant circuit:
•
•
•
An inductor value that is too low (high L-C resonant frequency) will result in non-sinusoidal primary
waveforms since higher order harmonics are allowed though the filter. A low value also allows excess
circulating currents, impacting efficiency.
An inductor value that results in a L-C resonant frequency close to the resonant frequency of the
piezoelectric transformer causes interference, making control of the primary voltage difficult. The
interference occurs since the gain of the L-C tank depends heavily on load in this region of operation.
An inductor value that is too large causes an attenuation of the input voltage, increasing the gain
requirements of the piezoelectric transformer and/or the system.
As an example, suppose a piezoelectric transformer is selected that operates efficiently at 67 kHz (similar to
Figure 9) and has 0.2-µF of primary capacitance. An external inductance value of 15 µH gives a L-C filter corner
frequency of 92 kHz. The L-C circuit would provide little attenuation at 67 kHz yet attenuate higher harmonics.
UCC3976 L-C TANK FREQUENCY
vs
LAMP LOADS
2.0
f
= 67 kHz
PZT
LAMP LOAD
150 kΩ
100 kΩ
50 kΩ
1.5
1
0.5
0
0
50
100
150
200
250
300
f – Frequency – kHz
Figure 13
17
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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
half-bridge operation and inductor selection (continued)
Waveforms for the UCC3976 half-bridge circuit operated with a 12-Vdc input are shown in Figure 14. P- and
N-Channel MOSFETs are driven out of phase with 50% duty cycle producing a square wave at the drains (see
Figure15: trace 1). Inductor LRES and the PZT primary capacitance form a low-pass filter. The resulting in a
near sinusoid across the PZT primary (trace 2). Due to the high Q of the PZT, lamp voltage (trace 4) is sinusoidal.
Lamp current is sensed by the half-wave rectification circuit at RCS (trace 3). Lamp current is in phase with lamp
current since the load is primarily resistive with some capacitance due to the reflector’s proximity to the lamp.
The lamp reflector should be grounded for safety reasons and in order to keep the secondary capacitance
constant allowing the PZT load to be constant.
V
= 12 Vdc
IN
= 600 V
Figure 14. UCC3976 Half-Bridge Waveforms
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
push-pull operation and inductor selection
For the push-pull circuit, MOSFETs N1 and N2 are driven out of phase with 50% duty cycle at variable frequency
(see Figure 15: trace 2). Inductors L1 and L2 resonate with the PZT primary capacitance, forming a half
sinusoids at the drain of N1 (trace 1) and S2 (trace 4). The resulting voltage across the PZT primary is a near
sinusoid (trace M1). Due to the high Q of the ceramic transformer, the lamp voltage, which is approximately
600 V in this application, is sinusoidal (trace 3). In order to achieve zero-voltage switching, each drain voltage
must return to zero before the next switching cycle. This dictates that the L-C resonant frequency be greater
than the switching frequency. The maximum inductance to meet these conditions can be found from
equation (16):
1
L t
2
2
4 p f C
p
(16)
V
= 7 Vdc
IN
Figure 15. UCC3977 Push-Pull Waveforms
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ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
flyback operation
For single layer PZT applications requiring additional gain, a resonant flyback topology can be implemented as
shown in Figure 16. In the resonant flyback application, a single N-channel switch is driven at 50% duty cycle
producing a half sinusoid at the drain (see Figure 16: trace 1). The magnetic transformer provides a stepped
up voltage to the PZT primary (trace 4). The resulting lamp voltage at the PZT secondary, which is approximately
250 V in this case, is sinusoidal resulting from the high Q of the ceramic transformer (trace 3). When compared
to a high-voltage magnetic CCFL transformer, the magnetic step-up transformer is small and low profile
because of the reduced turns ratio (3.5:1) and voltage rating. To ensure zero-voltage switching, as in the case
of the push-pull converter, equation (16) must be validated. The L-C relationship can be analyzed on either the
primary or secondary side of the magnetic transformer. If viewed from the primary, PZT capacitance is reflected
by the turns ratio.
V
= 4 Vdc
IN
V
Figure 16. UCC3975 Resonant Flyback Waveforms
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ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
analog dimming PZT performance
High efficiency can be achieved by selecting the best power topology while matching the lamp, input voltage
and PZT characteristics. Figure 17 shows the performance of a 3-W rated multi-layer PZT operating a 600 V
lamp using the push-pull topology at various input voltage and lamp current conditions. Electrical efficiency is
greater than 85% at lower input voltages, decreasing at higher input voltages as the PZT gain is reduced. This
circuit and lamp can operate from 2 Li-Ion cells with voltages between 5 V and 8.2 V. The same PZT and lamp
would require three Li–Ion cells for the half-bridge topology but would yield similar efficiency.
Dimming by linearly reducing lamp current causes the efficiency to degrade since the PZT is operated at less
than optimal gain (see 1.5 mA curve). Improved efficiency can be achieved by using burst mode dimming. This
dimming method involves running the lamp at full power, but controlling average lamp current by modulating
the on/off duty cycle at a frequency higher than the eye can detect (100 Hz, for example).
Figure 18 shows plots of PZT operating frequency over the same lamp conditions as Figure 17. As expected,
frequency decreases at higher lamp currents as the PZT characteristics shift to a lower operating frequency
when loaded (see Figure 2). Frequency increases linearly with input voltage, since the required V
to operate the lamp is decreased.
/V gain
OUT IN
TYPICAL PIEZO TRANSFORMER EFFICIENCY
PIEZO TRANSFORMER FREQUENCY
vs
vs
INPUT VOLTAGE
INPUT VOLTAGE
65.0
95
90
85
80
75
1.5 mA
570 V
64.5
64.0
63.5
3.0 mA
610 V
4.5 mA
570 V
63.0
62.5
62.0
61.5
61.0
60.5
3.0 mA
610 V
70
65
60
55
50
4.5 mA
570 V
1.5 mA
660 V
60.0
4
5
6
7
8
9
10
4
5
6
7
8
9
10
V
– Input Voltage – Vdc
V
– Input Voltage – Vdc
IN
IN
Figure 17
Figure 18
21
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢄ
ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
open lamp shutdown/no-lock operation
Due to the high gain characteristics of the piezoelectric transformer, it is important that the operation of the power
stage is suspended if an open lamp occurs. Figure 19 shows the output voltage of a piezoelectric transformer
with no output load and driven with a 5-V
sinusoid on the primary. The primary frequency is swept through
RMS
the resonant frequency of the piezoelectric transformer. As seen in Figure 19 the output voltage approaches
2 kV with open lamp disabled, a gain of 400! If the input voltage were increased to 10 V , the output would
RMS
reach 4 kV
RMS
and possibly crack the PZT transformer.
RMS
OPEN LAMP
PROTECTION
DISABLED
PZT Resonant
Frequency
Maximum
Frequency
Minimum
Frequency
Figure 19. Damaging Voltages at Piezoelectric Transformer Secondary
In order to prevent damaging voltages at the piezoelectric transformer secondary, a 1.5-V comparator at the
OPEN/SD pin is used to shutdown the converter if an open lamp is detected. The RMS secondary voltage at
which an open lamp fault is triggered can be calculated using equation (17).
ǒ1.5 ) V
Ǔ
R
OPEN
DIODE
HV
V
+
OPEN
Ǹ
2 R
(17)
R
will typically consist of several inexpensive high impedance resistors to minimize current in the divider and
HV
to stand–off high voltage. R
issue, however, impedance of the capacitor over frequency needs to be taken into consideration.
can be replaced with a single high voltage capacitor if component count is an
HV
22
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢂꢃ ꢄꢄ
ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
open lamp shutdown/no-lock operation (continued)
Figure 20 shows the startup performance of the UCC397x family based system with a broken or open lamp.
The open lamp trip level is typically set 20% to 50% higher than the required strike voltage of the lamp, in this
example the open lamp trip level is set at a low 500 V
. As seen in Figure 21, the lamp does not strike before
RMS
the OPEN/SD pin reaches 1.5 V indicating an open lamp, the controller retries seven times before entering an
error shutdown state (see the state diagram in the pin description section).
V
COMP
V
V
OPEN/SD
PZT
Figure 20. Start-Up With Open Lamp
A second type of failure mode occurs if the system fails to control lamp current. Assuming a proper feedback
network, this failure can occur if the input voltage is too low to operate the lamp or if one of the components in
the power path is open, shorted, or broken. These failures are detected at the COMP pin. Figure 21 shows the
system response where the input voltage is not sufficient for lamp operation. At startup the frequency sweeps
through the range until COMP reaches 2.5 V, the controller attempts seven retries before entering the error
shutdown state. Notice the slope on the COMP pin (trace 2) changes as the system attempts to operate the lamp
in a high gain region but is ultimately unsuccessful.
23
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢄ
ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
open lamp shutdown/no-lock operation (continued)
V
COMP
V
V
OPEN/SD
PZT
Figure 21. Start-Up With Insufficient Input Voltage
24
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢂꢃ ꢄꢄ
ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
burst dimming with the OPEN/SD pin
A burst dimming technique can be used with CCFLs when a wide dimming range is required, this technique can
also yield better efficiency at light loads. Burst dimming is implemented by running the lamp at full current when
on, where the on/off duty factor is controlled a low frequency to provide dimming. In order to prevent visible
flicker, the burst frequency needs to be set higher than 80 Hz.
The UCC397x family is initially targeted for operating the PZT using analog dimming, however, burst dimming
can be implemented by controlling the OPEN/SD pin directly with a square wave. Figure 22 shows burst
dimming performance using the UCC3976 at 125 Hz and 50% duty cycle. In Figures 22–25, trace 1 is the drain
connection of the external P- and N-Channel MOSFETs, trace 2 is the OPEN/SD pin which is externally driven
with a 5-V square wave, trace 3 is the COMP pin which is used to lock the operating frequency and trace 4 is
the lamp voltage. These scope graphics were captured with a digital oscilloscope, so aliasing is present in
Figures 22–24. Referring back to Figure 22, when OPEN/SD is driven to 5 V the part is in shutdown and the
controller is disabled. When OPEN/SD is forced to 0 V by the external source the controller goes through its
startup sequence with COMP starting at 0 V allowing the PZT to strike the lamp and lock on the frequency
required to regulate the lamp at full current. The size of the feedback capacitor determines the slew rate at which
COMP can lock the system frequency which effects the achievable duty cycle of burst dimming. Fortunately,
the feedback cap with burst dimming can be smaller than with analog dimming since the system small signal
gain is lower at full lamp load. Figures 23 and 24 show burst dimming at approximately 10% and 90% duty cycle
respectively. Figure 25 shows a close up of the startup sequence when OPEN/SD is pulled low. COMP is
preconditioned to 0 V before switching begins and then allowed to ramp up. PZT secondary voltage ramps as
the frequency decreases until the lamp strikes and operates. Strike voltage for the lamp is barely detectable
since the lamp is warm and operating from the previous burst cycles.
V
V
= 12 Vdc
IN
LAMP
= 125 Hz
= 600 V
f
OSC
50% Duty Cycle
= 5 mA
I
LAMP
V
V
OPEN/SD
OPEN/SD
V
COMP
LAMP
V
Figure 22. UCC3976 Burst Dimming at 50% Duty Cycle
25
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢄ
ꢀ ꢁꢁꢈ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢈ ꢃ ꢄ ꢇ ꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
TYPICAL WAVEFORMS
V
V
= 12 Vdc
IN
LAMP
= 125 Hz
= 600 V
f
OSC
10% Duty Cycle
= 5 mA
I
LAMP
V
V
OPEN/SD
OPEN/SD
V
COMP
LAMP
V
Figure 23. UCC3976 Externally Controlled Bursting Dimming
at 10% Duty Cycle
V
V
= 12 Vdc
IN
LAMP
= 125 Hz
= 600 V
f
OSC
90% Duty Cycle
= 5 mA
I
LAMP
V
V
OPEN/SD
OPEN/SD
V
COMP
LAMP
V
Figure 24. UCC3976 Externally Controlled Bursting Dimming
at 90% Duty Cycle
26
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢂꢃ ꢄꢄ
ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢇ ꢆ ꢀ ꢁꢁ ꢈꢃ ꢄꢄ
SLUS499A – NOVEMBER 2001 – REVISED JANUARY 2002
TYPICAL WAVEFORMS
V
V
= 12 Vdc
IN
LAMP
= 125 Hz
= 600 V
f
OSC
10% Duty Cycle
= 5 mA
V
V
OPEN/SD
OPEN/SD
V
COMP
LAMP
V
Figure 25. UCC3976 Close-Up of Bursting Dimming Operation
at 10% Duty Cycle
27
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