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UCC29950

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

UCC29950 CCM PFC 和 LLC 组合控制器

1 特性

2 应用

•

高效功率因数校正 (PFC) 和半桥谐振逻辑链路控制

(LLC) 组合控制器

•

离线交流-直流服务器电源（通过 80 PLUS^®铜牌/

1

银牌/金牌认证）

工业 DIN 导轨和开放式电源

游戏机和打印机电源

高密度适配器

•

连续导通模式 (CCM) 升压功率因数校正

支持自偏置或辅助（外部）偏置工作模式

完全内部补偿的 PFC 环路

•

3 步轻松设计 PFC 级

（设计电压反馈、电流反馈和功率级）

照明驱动器

3 说明

•

100kHz 固定 PFC 频率，具有抖动特性，可确保符

合 EMI 标准

UCC29950 可为交流-直流转换器提供 LLC 转换器级

和 CCM 升压功率因数校正 (PFC) 级，从而实现全部

控制功能。这款转换器经过了优化，非常便于使用。

•

真正的输入功率限制，独立于线路电压

固定 LLC 频率工作范围为 70kHz 至 350kHz

死区变化范围为 LLC 半桥功率级的整个负载范围，

可扩展零电压开关 (ZVS) 范围

凭借专有 CCM PFC 算法，系统能够获得高效率、更

小的转换器尺寸以及高功率因数等诸多优势。集成的

LLC 控制器可实现高效直流-直流转换级，利用软开关

来降低电磁干扰 (EMI) 噪声。这款组合控制器兼具

PFC 控制和 LLC 控制，使得控制算法能够充分利用来

自两级的信息。

•

三级 LLC 过流保护

Hiccup 工作模式，可提供连续过载和短路保护

低待机功耗，由高压启动金属氧化物半导体场效应

晶体管 (MOSFET) 和 X-Cap 放电功能共同实现

•

内置软启动和转换器排序功能，可简化设计

交流线路欠压保护，具有故障指示器

PFC 总线过压和欠压保护

该控制器包含一个启动控制电路，此电路采用耗尽型

MOSFET 且内置器件电源管理功能，可最大程度降低

外部元件需求，并且有助于降低系统实现成本。

过温保护

用于扩展功率级的外部栅极驱动器

小外形尺寸集成电路 (SOIC)-16 封装

为进一步降低待机功耗，该控制器还集成了 X-Cap 放

电电路。 UCC29950 实现了一整套系统保护功能，其

中包括交流线路欠压保护、PFC 总线欠压 PFC 和

LLC、过流保护和热关断保护。

器件信息⁽¹⁾

器件型号

UCC29950

封装

封装尺寸（标称值）

SOIC 16 引脚 (D)

9.90mm x 6.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

简化电路原理图

V_BLK

LLC 级过流保护曲线

C_BLK

V_AC

13

16

8

11

900

600

VCC

10 AC1

GD2

2

Vout

9

4

5

AC2

GD1 14

UCC29950

SUFG

SUFS

12

3

FB

400

300

VCC

1

6

15

7

0

10

52

Time (ms)

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLUSC18

UCC29950

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

www.ti.com.cn

7.3 Feature Description................................................. 15

7.4 Device Functional Modes........................................ 29

Application and Implementation ........................ 36

8.1 Application Information............................................ 36

8.2 Typical Application ................................................. 36

8.3 Do's and Don'ts ...................................................... 57

Power Supply Recommendations...................... 58

1

2

3

4

5

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

5.1 Detailed Pin Descriptions ......................................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 Storage Conditions.................................................... 6

6.3 ESD Ratings.............................................................. 6

6.4 Recommended Operating Conditions....................... 7

6.5 Thermal Information.................................................. 7

6.6 Electrical Characteristics........................................... 8

6.7 Typical Characteristics............................................ 11

Detailed Description ............................................ 13

7.1 Overview ................................................................. 13

7.2 Functional Block Diagram ....................................... 14

8

9

6

10 Layout................................................................... 59

10.1 Layout Guidelines ................................................. 59

10.2 Layout Example .................................................... 61

11 器件和文档支持 ..................................................... 61

11.1 文档支持................................................................ 61

11.2 商标....................................................................... 61

11.3 静电放电警告......................................................... 61

11.4 术语表 ................................................................... 61

12 机械封装和可订购信息 .......................................... 61

7

4 修订历史记录

Changes from Original (September 2014) to Revision A

Page

•

已更改销售状态从产品定制到产品目录。.............................................................................................................................. 1

2

UCC29950

www.ti.com.cn

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

5 Pin Configuration and Functions

SOIC (D)

16 Pins

Top View

GND

1

2

3

4

5

6

7

8

16

PFC_GD

AC_DET

GD1

GD2

VCC

15

14

13

12

11

10

9

SUFG

SUFS

AGND

PFC_CS

FB

LLC_CS

AC1

MD_SEL/

PS_ON

VBULK

AC2

Pin Functions

I/O

DESCRIPTION

NAME

NO.

GND

1

-

Power ground. Connect all the gate driver pulsating current returns to this pin.

Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink

(C_LOAD= 1 nF)

GD2

2

O

VCC

3

4

5

6

-

O

I

Bias supply input.

SUFG

SUFS

AGND

Start-up MOSFET gate drive output. Leave open circuit if not used.

Start-up MOSFET Source. Connect to VCC if not used.

-

Signal ground. Connect all device control signal returns to this ground.

Dual function pin:

MD_SEL/PS_

ON

1. Mode Select Function (MD_SEL): Select self bias or Aux bias mode of operation.

7

I

2. Power Supply On Function (PS_ON): Stop/start control of PFC and LLC stages, Aux

Bias mode only.

VBULK

AC2

8

I

Voltage sense input for PFC stage output.

9

AC line voltage detection. Connect 9.3 MΩ between AC line and this pin.

Current sense input for the LLC stage.

AC1

10

11

12

13

LLC_CS

FB

Feedback signal input for LLC stage.

PFC_CS

Current sense input for the PFC stage.

Gate drive output for LLC stage MOSFET. The typical peak current is 1-A source, 1.6-A sink

(C_LOAD= 1 nF).

GD1

14

O

AC_DET

PFC_GD

15

16

O

AC line voltage fail signal output, for system use.

The typical peak current is 0.6-A source, 1.3-A sink (C_LOAD= 1 nF).

3

UCC29950

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

www.ti.com.cn

5.1 Detailed Pin Descriptions

5.1.1 VCC

The VCC pin is the power supply input terminal to the device. This pin should be decoupled with a 10-μF ceramic

bypass capacitor in both Aux Bias and Self Bias Modes. An additional hold-up capacitor is needed at this pin if

operating in Self Bias Mode.

5.1.2 MD_SEL/PS_ON

MD_SEL/PS_ON pin. This pin can be used to make the UCC29950 operate in Self Bias or Auxiliary Bias Mode.

If MD_SEL/PS_ON pin is high during start up the controller enters Self Bias Mode. In this mode, the capacitor on

the device’s VCC rail is charged by an external depletion mode MOSFET connected at the SUFS and SUFG

pins. Once the VCC rail reaches an appropriate operating voltage, the FET is turned off and the VCC rail is then

supplied from an auxiliary winding on the LLC transformer. This avoids the standing or static losses incurred if a

drop resistor from rectified AC line were used to charge the VCC rail during startup.

If the MD_SEL/PS_ON pin is held low for at least 10 ms during start up the UCC29950 enters Aux Bias Mode.

Once this time has passed this pin may be used to turn on the PFC stage on its own or both the PFC and LLC

stages according to the values given in the MD_SEL/PS_ON part of the Electrical Characteristics.

5.1.3 SUFG, SUFS

The SUFG and SUFS are the control pins for an external start-up depletion mode FET. The use of a switched

device here eliminates the static power dissipation in a conventional resistive start-up approach where a drop

resistor from the rectified AC line to VCC is typically used. As a result standby power consumption is reduced.

Connect the FET gate to SUFG and its source to SUFS. The drain of the FET is connected to the rectified AC

voltage. SUFG and SUFS control the initial charging of the capacitor on the VCC rail during start-up in the Self-

Bias mode of operation. In this mode SUFG tracks SUFS as C_VCCis charged and VCC rises. When VCC

reaches VCC_SB(start)(typically 16.2 V) SUFG goes low. This turns the start-up FET off and the PFC and LLC gate

outputs start running. SUFG remains low unless VCC falls below VCC_{SB_UVLO(stop)}(typically 7.9 V) or an X-Cap

discharge is required. If VCC falls below VCC_{SB_UVLO(stop)}then SUFG goes high to turn the start-up FET on and

recharge C_VCCback up to VCC_{SB_START}

.

SUFG and SUFS also provide an X-Cap discharge function in both Aux Bias and Self Bias Modes. This function

is described fully in Active X-Cap Discharge.

If the UCC29950 is used in Aux Bias Mode then VCC is supplied by an external source and the external

depletion mode FET is used only to provide the X-Cap discharge function. SUFG is at 0 V after a time

T_{MODE_SEL_READ}has elapsed during power up after C_VCCexceeds VCC_START. SUFG goes high whenever an X-

Cap discharge is required. If the start up FET is not used and X-Cap discharge is not desired then SUFS should

be connected to VCC and SUFG should be left open circuit.

5.1.4 GD1, GD2

GD1 and GD2 are the LLC gate drive outputs for the LLC half-bridge power MOSFETs. A gate drive transformer

or other suitable device is required to generate a floating drive for the high-side MOSFET. The first and last LLC

gate drive pulses are normally half width and appear on GD1 and GD2 respectively. If the LLC_OCP3 level is

exceeded then the final pulse is of normal width. The typical peak current is 1-A source, 1.6-A sink (1-nF load).

4

UCC29950

www.ti.com.cn

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

Detailed Pin Descriptions (continued)

5.1.5 GND

GND is the power ground for the device. Connect all the gate-driver pulsating current returns to this pin.

5.1.6 AGND

AGND is the signal ground for device control signals. Connect all control signal returns to this pin.

5.1.7 LLC_CS

LLC_CS is the LLC stage current sense input. LLC_CS is used for LLC stage over-load protection. The load

current is reflected to the primary side of the transformer where it is sensed using a resistor. The UCC29950

senses the LLC stage input current level and enters the over-current protection Shut-Down Mode when the

current-sense signal exceeds the current and time thresholds described in LLC Three Level Over-Current

Protection . The controller tries to resume operation at 1-s intervals.

5.1.8 FB

FB is the LLC stage control-loop feedback input. Connect the opto-coupler emitter to this pin. The FB pin is the

input to the internal VCO. The VCO generates the switching frequency of the LLC converter. GD1 and GD2 stop

switching if this pin is driven above V_{FB_LLC(off)}(typically 3.75 V) and resume operation when it falls below V_FB(max)

(typically 3.0 V). If this pin is held below V_FB(min)(typically 200 mV) the GD1 and GD2 outputs runs at their

minimum frequency.

5.1.9 PFC_GD

PFC_GD is the gate-driver output for a PFC MOSFET. Connect the PFC MOSFET gate through a resistor to

control its switching speed. Because of the limited driving capability an external gate driver might be needed to

support certain power MOSFET input capacitance conditions. The typical peak current is 0.6-A source, 1.3-A

sink (C_LOAD= 1 nF).

5.1.10 PFC_CS

PFC_CS is the current sense input for the PFC stage. It is recommended to add a current-limiting resistor

between the current-sense resistor and current-sense pin, to prevent damage during inrush conditions. A 1-kΩ

resistor normally suffices. The UCC29950 implements a new hybrid average current-control method which

controls the average current but uses the peak PFC_CS signal to terminate each switching cycle (see Hybrid

PFC Control Loop). Correct PCB layout is important to ensure that the signal at this pin is an accurate

representation of the current being controlled.

5.1.11 VBULK

The VBULK pin is used for PFC output-voltage sensing. Connect the sensing resistors to this pin. The upper

resistor in the potential divider must be 30 MΩ and the lower resistor must be 73.3 kΩ. The high impedance

reduces the static power dissipation.

5.1.12 AC1, AC2

AC1 and AC2 are the AC line voltage sensing inputs. The UCC29950 uses differential sensing for more accurate

measurement of line voltage. These pins must be connected to the two line inputs via 9.3-MΩ resistors.

5.1.13 AC_DET

The AC_DET is a system-level signal which may be used for indication and system control. AC_DET goes high if

the instantaneous AC voltage remains below the brownout level for longer than 32 ms. An opto-coupler can be

used to send a signal to a system supervisor device so that appropriate action can be taken. In order to provide

hold-up time to the system, the power stages continue to operate for 100 ms after AC_DET goes high. This

behavior is shown in Figure 10, Figure 11 and Figure 12.

5

UCC29950

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

0

MAX

20

UNIT

V

Supply Voltage

VCC

Continuous Input

Voltage Range

LLC_CS

4.5

V

FB, AC1, AC2, VBULK, MD_SEL/PS_ON

VCC+0.3

4.5

V

AC_DET

V

SUFS

–0.3

–0.5

–1.3

20

V

SUFG

SUFS+0.3

VCC+0.5

4.5

V

GD1, GD2, PFC_GD

PFC_CS

V

Continuous Input

Current Range

PFC_CS

±15

mA

T_SOL

Lead temperature (10 s)

260

125

°C

Operational Junction Temperature, T_J

–40

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Storage Conditions

MIN

MAX

UNIT

T_stg

Storage temperature range

–40

150

°C

6.3 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6

UCC29950

www.ti.com.cn

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

11

0

NOM

MAX

18

UNIT

V

VCC

Supply voltage range

V_FB

FB pin voltage range

VCC

V

V_{MD_SEL/PS_ON}

RL1/RL2

MD_SEL/PS_ON pin voltage range

Line sensing resistors

0

V

9.3

MΩ

6.5 Thermal Information

UCC29950

THERMAL METRIC⁽¹⁾

SOIC (D)

16 PINS

78.9

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

40.3

Junction-to-board thermal resistance

36.3

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

8.9

ψ_JB

36.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7

UCC29950

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

www.ti.com.cn

MAX UNIT

6.6 Electrical Characteristics

–40°C < T_J< 125°C⁽¹⁾, VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted)

PARAMETER

VCC Bias Supply (Self Bias Mode)

TEST CONDITIONS

MIN

TYP

–2

I_SUFS

Charging current into V_CC

SUFS = 7.5 V, VCC = 4 V

–1

–4

mA

V

In Self Bias mode, the controller will not start

PFC and LLC gate drive outputs until the start up MD_SEL/PS_ON = VCC at

FET has charged the capacitance on the VCC

pin above this level

VCC_SB(start)

15.0

16.2

17.4

power-up (self bias mode)

In Self Bias mode, VCC must be greater than this

VCC_{SB_UVLO(stop)}level to allow the controller to continue to output

the PFC and LLC gate drives.

VCC falling Self Bias Mode

7.3

7.9

8.5

VCC Bias Supply (Aux Bias Mode)

(2)

VCC_START

Controller logic starts at this VCC voltage

Controller logic stops at this VCC voltage

VCC rising

VCC falling

4.4

3.7

6

7.0

5.8

(2)

VCC_STOP

5.0

In Aux Bias Mode, VCC must be greater than this VCC rising MD_SEL/PS_ON

VCC_{AB_UVLO(start}

)

level to allow the controller to start the PFC and

LLC gate drive outputs.

= 0 V at power-up (Aux Bias

Mode)

10.0

9.1

10.5

9.6

10.9

10.0

V

In Aux Bias Mode, VCC must be greater than this

VCC_{AB_UVLO(stop)}level to allow the controller to continue to output

the PFC and LLC gate drives.

VCC falling Aux Bias Mode

VCC Supply Current

GD1, GD2 at LLC_FMAX

.

Device is Enabled and providing PFC & LLC gate PFC_GD at f_PFC(100 kHz

ICC_ENABLE

7.5

8.0

1.6

18.3

2.1

mA

drive outputs

nom). GD1, GD2 and

PFC_GD pins unloaded.

MD_SEL/PS_ON, Mode Select Function at Power Up

Minimum voltage on the MD_SEL/PS_ON pin

that will select Self Bias mode on power up (see

Device Functional Modes).

V_{MODE_SELSB}

1.1

10

V

After VCC pin exceeds VCC_START. This is the

minimum time that the MD_SEL/PS_ON pin must

T_{MODE_SEL_READ}remain below V_{MODE_SELSB}to ensure that Aux

Bias Mode is selected (see Device Functional

Modes).

ms

MD_SEL/PS_ON, Power Supply On Function, Aux Bias Mode Only

Minimum voltage on the MD_SEL/PS_ON pin

V_{PS_ONPFC_RUN}

20

66

25

75

33 %VCC

85 %VCC

that causes PFC stage to run⁽³⁾

V_{PS_ONLLCPFC_R}Minimum voltage on the MD_SEL/PS_ON pin

that causes PFC and LLC stages to run⁽³⁾

UN

AC_DET

V_{OH_TP_LZ}

V_OL

I_{O(max_source)}

I_{O(max_sink)}

(1)

AC_DET output high

AC_DET output low

AC_DET source current

AC_DET sink current

I_{(AC_DET)}= –1 mA

I_{(AC_DET)}= 1 mA

V_OUT> 2.4 V

2.5

19

3.1

35

4.1

80

V

mV

mA

–1.6

6.0

V_OUT< 0.5 V

The device has been characterized over the entire temperature range during development. Individual devices may enter temperature

shutdown (T_SD) at T_Jlower than 125°C.

(2) VCC_STARTis always greater than VCC_STOP

.

(3) Threshold voltage will track VCC and is therefore specified as a percentage of VCC.

8

UCC29950

www.ti.com.cn

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

Electrical Characteristics (continued)

–40°C < T_J< 125°C⁽¹⁾, VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted)

PARAMETER

VBULK, PFC OUTPUT VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX UNIT

PFC output overvoltage protection (auto

recovery)

V_BULK(ovp)

1.06

1.10

1.14

V

V_BULK(reg)

V_BULKregulation set-point

LLC operation start threshold

LLC operation stop threshold

0.907

0.70

0.45

0.940

0.73

0.49

0.973

0.77

0.53

V

V_{BULK(llc_start)}

V_{BULK(llc_stop)}

AC1, AC2, AC LINE SENSING FOR PFC

R_AC1

R_AC2

AC1 pin resistance to AGND

AC2 pin resistance to AGND

AC1 pin

45

60

71

kΩ

AC2 pin

Force current into AC1 or

AC2 pins. Unused pin input

at 0 V.

AC_DET is active HIGH when I_ACis below this

level

(4)(5)

I_AC(det)

7.03

8.04

30.7

31.8

32.8

7.48

8.55

32.0

33.1

34.2

7.93

9.1

Force current into AC1 or

AC2 pins. Unused pin input

at 0 V.

PFC stage stops 100 ms after I_ACis at or below

this level

(4)(5)

I_{AC(low_falling)}

Force current into AC1 or

AC2 pins. Unused pin input

at 0 V.

PFC stage is allowed to start when I_ACis at or

above this level

(4)(5)

I_{AC(low_rising)}

µA_RMS

Force current into AC1 or

AC2 pins. Unused pin input

at 0 V.

(4)(5

I_{AC(high_falling)}

PFC stage restarts if I_ACfalls below this level. No

soft-start

33.3

34.4

35.6

)

Force current into AC1 or

AC2 pins. Unused pin input

at 0 V.

(4)(5)

I_{AC(high_rising)}

PFC stage stops if I_ACis at or above this level

Force current into AC1 or

AC2 pins. Unused pin input

at 0 V.

PFC and LLC stages stop if I_ACis at or above

this level

(4)(5)

I_AC(halt)

PFC_CS, PFC CURRENT SENSE

Maximum voltage at PFC_CS pin, (ignoring

signal ripple due to inductor ripple current) that

determines maximum power delivered. Used to

determine R_{CS_PFC}. (see PFC Stage Current

Sensing Figure 13 and Figure 6)

V_{PFCCS(cav_max)}

–200

–570

–225

–800

–250

–950

mV

VBULK pin = 800 mV,

|V_AC1– V_AC2| = V_{AC_PEAK}

V_PFCCS(max)

Maximum voltage at PFC_CS pin

(6)

PFC_GD, PFC GATE DRIVER

V_{HI(pfc_2mA)}

V_{HI(pfc_75mA)}

R_{PFC(gd_hi)}

R_{PFC(gd_lo)}

PFC_GD high level

I_{O(PFC_GD)}= –2 mA

I_{O(PFC_GD)}= –75 mA

I_{O(PFC_GD)}= –50 mA

I_{O(PFC_GD)}= 75 mA

11.5

8.5

11.8

9.5

14

12.0

10.5

25

V

PFC_GD high level

PFC_GD pull-up resistance

PFC_GD pull-down resistance

Ω

4.4

10

Capacitive load of 1.0 nF on

PFC_GD pin, 20% to 80%

t_R(pfc)

t_F(pfc)

f_PFC

PFC_GD rise time

PFC_GD fall time

Switching frequency

30

10

98

45

25

ns

Capacitive load of 1.0 nF on

PFC_GD pin, 20% to 80%

Includes dithering of ±2 kHz

at nominal 333-Hz rate.

87

109

kHz

(4) These are specified at 25°C. The relative levels for these specifications track each other. The equivalent line voltages are given in

Table 3, assuming a source impedance of 9.3 MΩ.

(5) This is the current into the AC1 or AC2 pins.

(6) Tested at peak of line voltage or 90° from zero crossing.

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Electrical Characteristics (continued)

–40°C < T_J< 125°C⁽¹⁾, VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted)

PARAMETER

FB, LLC Control Loop Feedback

TEST CONDITIONS

MIN

TYP

MAX UNIT

Minimum voltage on FB pin where LLC frequency Below V_{FB_MIN}, LLC

(7)

V_FB(min)

0.17

2.90

0.2

3

0.23

is modulated

frequency is LLC_Fmin

Between V_{FB_MAX}, and

V_{FB_LLC_OFF}LLC frequency is

LLC_Fmax

Maximum voltage on FB pin where LLC

frequency is modulated

(7)

V_FB(max)

3.10

V

Once V_FBexceeds

V_{FB_LLC_OFF}, V_FBmust fall

below V_{FB_MAX}to resume

switching

Voltage on FB pin above which LLC gate drive

terminated

(7)

V_{FB(llc_off)}

3.62

3.75

3.88

(7)

LLC_FMIN

LLC_FMAX

Minimum LLC switching frequency

Maximum LLC switching frequency

63.7

321

70

74.8

kHz

378

350

Time for which GD1 and GD2 are both low during LLC dead-time at minimum

(8)

LLC_T(dead)

224

45

300

60

388

71

ns

LLC operation at LLC_FMIN

switching frequency.

R_FB

Internal resistance from FB pin to AGND

kΩ

LLC_CS, LLC Current Sense

If this level is exceeded the

PFC and LLC stages will stop

for t_LONG(fault). Restart with a

normal soft-start sequence

(9)

V_CS(ocp3)

LLC Overcurrent threshold level three

0.87

0.27

0.9

0.94

0.33

V

V_{CS(llc_max)}

Voltage at LLC_CS pin at 100% of full load

0.30

FAULT Section

t_LONG(fault)

Recovery time after long fault

Recovery time after short fault

0.9

90

1.0

1.5

s

t_SHORT(fault)

100

150

ms

GD1, GD2, LLC GATE Drive Output

V_{GD(hi_2mA)}

V_{GD(hi_75mA)}

R_GD(hi)

GD1, GD2 output high level

I_O(GDx)= –2 mA

I_O(GDx)= –75 mA

I_O(GDx)= –50 mA

I_O(GDx)= 75 mA

11.5

9.3

11.8

10.1

5.8

12

10.9

10.5

5

V

GD1, GD2 output high level

GD1, GD2 gate driver pull-up resistance

GD1, GD2 gate driver pull-down resistance

Ω

R_GD(lo)

1.6

Capacitive load of 1 nF on

GD1, GD2 pins

t_r(llcgd)

t_f(llcgd)

Thermal Shutdown

LLC gate driver rise time

12

11

30

25

ns

°C

capacitive load of 1 nF on

GD1, GD2 pins (20% to 80%)

LLC gate driver fall time

T_SD

T_ST

Thermal shutdown temperature

Start / restart temperature

125

113

(7) Refer to Figure 1.

(8) Refer to Figure 2.

(9) Refer to Table 4 for other LLC Stage Over-Current Protection Levels.

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6.7 Typical Characteristics

400

350

300

250

200

150

100

50

900

800

700

600

500

400

300

200

0

0.5

1

1.5

2

2.5

3

3.5

4

0

1

2

3

4

Feedback Voltage (V)

D001

Figure 1. LLC Switching Frequency vs V_FB

Figure 2. LLC Dead Time vs V_FB

400

350

300

250

200

150

100

50

16

14

12

10

8

6

4

2

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Time (ms)

D001

Figure 3. LLC Period vs Time During Soft-Start

Figure 4. LLC Frequency vs Time During Soft-Start

0

1.005

1

V_PFCCS(cav)

V_{PFCCS(cav_max)}

V_PFCCS(cav)

-0.03

-0.06

-0.09

-0.12

-0.15

-0.18

-0.21

-0.24

-0.27

-0.3

0.995

0.99

0.985

0.98

0.975

0.97

-0.33

-50

-25

0

25

50

75

100

125

0

2

4

6

8

10

12

14

16

18

20

Temperature (C°)

Time (ms)

D001

Figure 5. Switching Frequency vs Temperature

(for PFC and LLC). Normalized to 1 at 20°C

Figure 6. PFC_CS Signal (diagrammatic)

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Typical Characteristics (continued)

57.3

-1.6

-1.7

-1.8

-1.9

-2

57

56.7

56.4

56.1

55.8

55.5

55.2

54.9

54.6

54.3

-2.1

-2.2

-2.3

-2.4

-2.5

-2.6

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

D001

Figure 7. R_AC1, R_AC2Resistance vs Temperature

Figure 8. SUFS to VCC Current vs Temperature

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7 Detailed Description

7.1 Overview

The UCC29950 combines all the functions necessary to control a Boost PFC and LLC power system. It is

packaged in an SOIC-16 package. The SUFG and SUFS pins allow the system designer to use an external

depletion mode MOSFET to provide start up power instead of using a dissipative resistor. The use of high-

impedance voltage sensing networks further reduces standby power. The combo device uses information from

both PFC and LLC stages to optimize the system efficiency, transient response and standby power. The

controller can be operated with bias current supplied from a small external PSU (Aux Bias) or from a winding on

the LLC transformer (Self Bias). In Aux Bias Mode, the MD_SEL/PS_ON pin allows the user to turn on the PFC

stage alone or both PFC and LLC stages.

The UCC29950 has many protection features, these include:

•

Bias Rail Under-Voltage Lockout

Active X-Cap Discharge

Line Under-Voltage Detection

Line Over-Voltage Detection

Line Brownout Detection

Three Level Output Overcurrent Profile on LLC Stage

PFC Stage Constant Input Power Limit

PFC Stage Input Current Limit

PFC Stage Second Current Limit

PFC Stage Output Overvoltage Protection

V_BLKSensing Network Fault Detection

V_BLKOver-Voltage Protection

PFC and LLC Stage Soft-Start

PFC Stage Frequency Dithering

Thermal Shutdown

The UCC29950 implements an advanced control algorithm to control the PFC stage input current. This

proprietary hybrid method combines both average and peak-mode control methods.

•

Accurate control of the average current drawn from the line gives good THD.

Peak inductor current information is used to terminate each PFC switching cycle.

The algorithm is insensitive to variations in the peak-to-average current ratio.

The input current is accurately controlled so that it follows the correct sinusoidal shape and also gives inherent

cycle-by-cycle protection against excess MOSFET current. A further advantage is that the control loop is

insensitive to PFC inductor and bulk capacitor variations. The UCC29950 takes full advantage of this fact to

implement internal compensation of the PFC stage. This simplifies the system designer’s task and reduces the

external component count. A sophisticated soft-start algorithm is used to achieve a constant soft-start ramp time

over a wide range of bulk capacitor values and initial conditions.

An LLC stage is typically used to convert the PFC stage output to an isolated final voltage for system use. The

UCC29950 provides all the primary-side functions needed to control such a second stage. The input to the FB

pin is an isolated control signal from the output. This signal is fed into a voltage-to-frequency converter (VCO).

The VCO inserts an appropriate dead time and the resulting signals are routed through some on-chip drivers

connected to the GD1 and GD2 outputs. The dead time is shortest at low LLC frequencies and is increased

automatically as frequency is increased. A three level Over-Current Protection (OCP) function stops the GD1 and

GD2 signals if the current signal at the LLC_CS pin goes outside of a defined current vs time profile.

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7.2 Functional Block Diagram

Over

Temperature

Protection

Fault Timer

and Control

Brownout

4

5

15

10

9

SUFG

SUFS

AC_DET

AC1

X-cap Discharge

| V_AC1± V_AC2

|

AC Line

Process

Current

Limit

AC2

V_REF

3

+

VCC

Voltage

Loop

8

UVLO_REF

VBULK

Soft Start

I_{AV_DEM}

MD_SEL/

PS_ON

7

CONTROL

PFC_CS

Current Loop

13

+

PFC_OCP

16

PWM

PFC_GD

OCP_REF

PFC_OVP

VCC_UVLO

Brownout

PFC Stop

14

2

Three Level OCP

Dead Time Profile

Soft Start

11

LLC_CS

FB

GD1

GD2

VCO

12

LLC_UV

1

6

GND

AGND

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7.3 Feature Description

Table 1. UCC29950 Features and Benefits

Feature

Benefit

Self-Bias Mode allowing off-line operation

Eliminate cost of Auxiliary Flyback Bias supply in system

Control output for external high-voltage, depletion mode start-up

MOSFET

Eliminates drop resistor from rectified AC line, reduces stand-by

power

Integrated X-Cap discharge function using external start-up

MOSFET

Eliminates bleed resistor across differential EMI filter capacitor,

reduces stand-by power

PFC stage design in 3 easy steps - (i) design voltage feedback

network, (ii) choose current sense feedback resistor, (iii) design

power stage

Greatly simplifies design effort

Good iTHD and insensitivity to inductor and bulk capacitor variations,

Cycle by cycle PFC overcurrent protection

Advanced control algorithm for PFC Stage

Internal compensation of PFC Stage Voltage and Current feedback

loops

Reduces Component count, eliminates 2 design steps (voltage and

current loop compensation)

Accurate measurement of line conditions under no-load or start-up

conditions for improved performance and protection - Eliminates 1

design step (AC line sensing)

Differential AC Line sensing with fixed 9.3M-ohm resistors

PFC frequency dithering

Simplifies EMI filtering and eases EMI compliance

Limit set by choice of R_CS(pfc)allowing designer greater flexibility

compared to fixed limits that depending on AC line voltage

True input power limit, independent of line voltage

Zero Voltage Switching (ZVS) over a wide range of operating

conditions

Reduced switching losses in the LLC converter power devices

Allows the power stage to ride through a short-term transient

overload but reacts quickly to protect the power stage from heavy

overload or output short-circuit events.

Three Level over current protection for LLC and Hiccup mode of

operation

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7.3.1 Sense Networks

The UCC29950 uses fixed scaling factors to measure the signals at its pins. The circuit position of the voltage

sensing resistors is shown in Figure 9. The current sensing resistors are shown in Figure 13.

The resistors in the V_BLKsensing network, R_TOPand R_BOTin Figure 9 have been chosen to minimize the power

dissipation and ensure correct operation over the expected tolerance bands. The impedance in this network may

be reduced by choosing lower value resistors provided that the potential division ratio is unchanged or kept within

the limits given below.

The nominal ratio is 30 MΩ/73.33 kΩ = 409.28. This has been chosen to give a nominal V_BULKregulation setpoint

of 385 V. This voltage is the ideal operating point for the PFC. It prevents direct conduction into the bulk

capacitor at high line and prevents false OVP tripping due to load transients - especially under high load

conditions where the voltage ripple on the bulk capacitor is maximum. It is possible to change the nominal

setpoint within the limits below.

If the ratio is increased above the nominal value then there is a risk of triggering a sense network fault condition

at startup - as described in the next section. The maximum ratio is not an absolutely fixed value but is likely to be

about 425 with a corresponding V_BULKregulation setpoint of 400 V. The minimum ratio is governed by the desire

to avoid direct conduction into the bulk capacitor when operating at high line. V_BULKmust be greater than 374 V

to avoid this condition on a 264 VRMS line. The corresponding minimum ratio is about 395.

Table 2. Sensing Resistor Values

RESISTOR

DESCRIPTION

MIN

TYP

MAX

UNIT

1% tolerance parts are recommended. To meet

voltage ratings, it may be necessary to split the

resistance across more than one part.

R_L1and R_L2

9.21

29.7

9.30

30.0

9.40

30.3

MΩ

1% tolerance parts are recommended. To meet

voltage ratings, it may be necessary to split the

resistance across more than one part.

R_TOP

1% tolerance parts are recommended. A parallel

combination of a 75-kΩ and a 3.3-MΩ resistor

gives a nominal 73.33 kΩ

R_BOT

72.50

73.33

74.07

kΩ

Value depends on system power level and is

given by Equation 59

R_CS(pfc)

R_CS(llc)

33

mΩ

Value depends on system power level and is

given by Equation 36

400

V_BLK

V_AC

R_TOP

C_BLK

R_BOT

R_L1

R_L2

8

10 AC1

AC2

9

UCC29950

Figure 9. Voltage Sensing Network

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7.3.2 Sense Network Fault Detection

In a boost converter, there is a direct conduction path from AC line to the bulk capacitor which ensures that it will

be charged to peak of line even if the PFC stage controller is inactive. At start-up the UCC29950 measures AC

line voltage and the voltage on the PFC bulk energy storage capacitor. If the UCC29950 measures V_BLKto be

lower than V_ACit enters a latched fault condition. This feature prevents the PFC stage from running if the upper

resistor in the voltage sensing network has gone open circuit. If the lower resistor has gone open circuit, then the

UCC29950 detects this as an over-voltage event on the output and PFC switching will not start.

7.3.3 PFC Stage Soft-Start

The UCC29950 soft-start will typically charge the PFC boost capacitor within 50 ms to 100 ms of starting.

7.3.4 AC Line Voltage Sensing

The UCC29950 uses differential AC line sensing through its AC1 and AC2 pins. Differential sensing provides

more accurate measurements than single ended sensing, especially at startup and under light load conditions. It

also allows faster detection of AC line disconnection or failure.

Normal single ended sensing assumes that the diodes connected to the negative going AC line are forward

biased and that a single measurement of the positive going AC line is a true representation of the input voltage.

This is normally true but if there is no current being drawn, as is the case under no-load or start up conditions,

then it is possible that all the diodes in the bridge are reverse biased. If this happens then a single ended

measurement will overestimate the true AC line voltage. The differential AC line sensing used in the UCC29950

avoids these errors.

The external resistor value impedance for AC1 and AC2 is required to be 9.3 MΩ. This reduces the static power

dissipation and provides the correct divider ratio in conjunction with the GAIN and OFFSET factors of the device,

(see Equation 1).

These factors are set at the time the UCC29950 is tested. They are used to compensate for device to device

variations in R_AC1and R_AC2

.

ꢀ

8#% = #%1 F #%2 F 1((5'6 × )#+0

(1)

AC1 and AC2 must be connected to the AC line side of the bridge rectifier through 9.3-MΩ resistors. The high

impedance sensing network is effectively a current source which is why the levels in the electrical characteristics

table are given in terms of currents rather than voltages. The equivalent voltages are given in Table 3.

The 9.3-MΩ resistors must be able to support the full voltage at peak of AC line and are conveniently made from

three 3.09-MΩ resistors in series. It is recommended to minimize the length of track between the ACx pins and

the lowest resistor in the chain.

Table 3. PFC AC Line Voltage Action Levels⁽¹⁾

VOLTAGE

PARAMETER

MIN

65.5

TYP

MAX

74.5

UNIT

V_AC(det)

AC_DET will be active HIGH when VAC

is below this level

I_AC(det)

70

80

V_RMS

V_{AC(low_falling)}

V_{AC(low_rising)}

V_{AC(high_falling)}

V_{AC(high_rising)}

V_AC(halt)

PFC stage stops 100 ms after VAC is at I_{AC(low_falling)}

or below this level

65.5

75

74.5

85.2

313

323

333

PFC stage is allowed to start when VAC I_{AC(low_rising)}

is at or above this level

PFC stage restarts if VAC falls below this I_{AC(high_falling)}

level

287

297

306

300

310

320

PFC stage stops if VAC is at or above

this level

I_{AC(high_rising)}

PFC and LLC stages stop if VAC is at or I_AC(halt)

above this level

(1) Based on parameter values in Electrical Characteristics table and calculated assuming 9.3 MΩ resistors in AC1 and AC2 lines. The

relative levels of these action levels track each other.

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7.3.5 V_BLKSensing

V_BLKis sensed through a potential divider with a resistance of 30 MΩ between the VBULK pin and V_BLK. The

bottom resistor in the potential divider is 73.3 kΩ. The 30 MΩ resistor has to support the full V_BLKvoltage and it is

normal to split this resistance into three separate parts of 10 MΩ each. As noted in Sense Network Fault

Detection the UCC29950 will not start the power stages if it detects that V_BLKis less than peak of VAC. Because

of the high impedance nature of the sensing network it is recommended to minimize the length of track between

the VBULK pin and the lowest resistor in the sensing chain.

7.3.6 AC Input UVLO and Brownout Protection

The UCC29950 provides full brownout protection and will not react to single-cycle AC line dropouts. While the

PFC stage is running the controller checks each AC line half-cycle. A valid AC line input is detected if the peak

voltage during an AC line half-cycle is greater than the brownout level (equivalent to 70 V_RMS). The AC_DET

output goes high if no valid AC line input is detected for a period greater than 32 ms and both the PFC and LLC

stages stop operating 100 ms later.

NOTE

The LLC stage always stops immediately if VBULK falls below V_{BULK(llc_stop)}

.

V

AC_DET

V

AC

t30 mst

AC_DET

PFC_GD

GD1/GD2

Time

Figure 10. AC Line Dropout

V

AC_DET

V

AC

AC_DET

PFC_GD

32 ms (typ)

100 ms

GD1/GD2

Time

Figure 11. AC Line Disconnect

V

AC_DET

V

AC

AC_DET

PFC_GD

32 ms (typ)

100 ms

GD1/GD2

Time

Figure 12. AC Line Brownout

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7.3.7 Dither

The PFC stage switching frequency is stepped between three discrete frequencies at a rate of 333 Hz. The

frequencies are spaced at nominal 2-kHz intervals. The dither rate is selected to avoid harmonics of the major

AC line frequencies. Dither is effective in reducing the average EMI level and also reduces the quasi-peak levels

but to a lesser extent.

7.3.8 Active X-Cap Discharge

If the Active X-Cap discharge function is to be used, the drain of the start-up FET must be connected to the AC

side of the bridge rectifier, as shown in Figure 20. The X-Cap is discharged by bringing SUFG low to turn the

start-up FET on. The discharge path is then through the startup FET, via the SUFS pin and into C_VCC

.

NOTE

A Zener diode should be used to clamp VCC and prevent multiple X-Cap discharge

events from over charging the capacitor. This Zener diode should be 18V rated device in

Self-bias applications. A lower voltage Zener could be used in Aux bias applications,

providing that the Zener voltage is greater than the normal operating VCC rail voltage.

When the AC line is removed the UCC29950 detects that the zero voltage crossings on V_AChave ceased. If the

PFC stage is running at that time then the X-Cap is discharged through the switching action of the PFC stage

and no further action is needed. If the PFC stage is not running at the time of disconnection, perhaps because

MD_SEL/PS_ON is held low or VBULK is > V_BULK(reg), then SUFG is set high if VC_X-Cap(the voltage on the X-

Cap) is greater than 42 V and the X-Cap is discharged. If VC_X-Capis < 42 V then it is regarded as being at a safe

level, discharge is not needed and SUFG is not set high. The X-Cap is always discharged within the 1 s allowed

by the safety standards but there may be up to 300 ms delay or latency in SUFG operation if the controller is

operating in burst mode, for example at light loads. The UCC29950 makes the decision to set SUFG high based

on the voltage on the X-Cap at the end of this latency period.

7.3.9 LLC Stage Soft Start

The LLC stage soft-start ramps the LLC gate drive frequency from min period (1/LLC_F(max)) to max period

(1/LLC_F(min)) over a 100-ms interval. The ramp is terminated when the voltage at the FB pin is such that it would

command a higher frequency than the ramp. The first pulse from the GD1 output is half width.

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7.3.10 PFC Stage Current Sensing

The UCC29950 controls the average current in the PFC inductor. This means that the current sense signal at the

PFC_CS pin must represent the inductor current during the full PFC switching cycle. That is when the MOSFET

is ON and also when the MOSFET is OFF. This is achieved by putting the current sensing resistor, R_CS(pfc), in the

position shown in Figure 13 and Figure 34.

NOTE

The current sense signal, V_{CS_PFC}, is negative going, so the signal goes more negative as

the inductor current increases.

The current sensing resistor is on the input current return path and inrush currents flow through it. These may

generate large voltage drops on the current sense resistor. These voltages may be higher than the negative

voltage rating on the PFC_CS pin. A resistor, recommended value = 1 kΩ, between the current sensing resistor

and the PFC_CS pin is used to avoid over stressing the device. Signal diodes may be necessary to provide

additional clamping. A small filter capacitor may be useful to further reduce the noise level at this pin but be

careful that this part does not significantly attenuate the ripple component of the current sense signal. These

components are shown in Figure 13.

The current drawn from the AC line is limited so that the peak voltage on the PFC_CS pin, ignoring PFC stage

switching ripple, does not exceed –225 mV, V_{TH(PFCCS(cav_max)}), as shown in Figure 6.

There is a second current limit point at V_PFCCS(max)and the peak voltage at the PFC_CS pin should not be

allowed to exceed this limit (–570 mV). The operation of this second current limit is explained later. The PFC

current sense resistor (R_CS(pfc)) value needed can be calculated using Equation 59.

V_BLK

V_AC

C_BLK

R_CS(pfc)

R_CS(llc)

C1

R_F(pfc)

R_F(llc)

C_F(pfc)

C_F(llc)

AGND

13

11

AGND

Figure 13. Current Sensing Connections

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7.3.11 Input Power Limit

The UCC29950 has a true input power limit which limits the PFC stage power at a level which is independent of

the AC line voltage. This is more useful than a simple fixed input current limit where the power would be limited

at different levels depending on the AC line voltage. The power limit is set by the choice of R_CS(pfc)according to

Equation 59.

7.3.12 PFC Stage Soft Start

When the power system is first connected, the bulk capacitor charges to the peak value of the AC line voltage.

The PFC stage soft-start process first calculates the current needed to charge the bulk capacitor from this initial

stage to the regulation setpoint (VBULK at V_BULK(reg)) in a nominal 50 ms. This is an approximate calculation

based on a bulk capacitance of 0.8-µF per watt and varies if a larger or smaller capacitor is used. The PFC stage

is then started using this current limit value.

7.3.13 Hybrid PFC Control Loop

The UCC29950 controls a continuous-conduction mode PFC stage by using a novel method combining average

current-mode control with peak-current sensing. Among other advantages, this method eliminates the peak-mode

line current distortions due to a varying peak-to-average current ratio. The average current is used to control the

average value of the PFC inductor current and the peak current is used to terminate each PWM cycle and

provide high bandwidth, cycle-by-cycle current control or limiting. Good power factor is achieved by forcing the

average input current to follow a demand signal that is derived from the AC line voltage.

Traditional current-mode control systems require resistor and capacitor compensation components to shape the

system response. It is difficult to integrate these components into a semiconductor chip and external parts must

be used. The UCC29950 avoids the need for external compensation networks by implementing the average

portion of the control loop digitally. The entire outer-voltage control loop is digital and the required slow response

is easily achieved without the need for external parts. This mixed signal approach uses digital methods for low-

frequency compensation and analog op-amps and comparators for the actual PWM duty-cycle generation.

The input AC line voltage is sensed differentially through the AC1 and AC2 pins, as shown in Figure 14.

Differential sensing allows more accurate measurement of the AC line voltage over the entire input power range,

including no load, than single ended sensing. The output of the voltage loop is multiplied by the instantaneous

line voltage, |V_AC1- V_AC2|, to give an average current demand signal, I_AV(dem), for the current loop. The I_AV(dem)

,

the voltage loop and |V_AC1- V_AC2| signals are all implemented digitally. The voltage loop provides correct

compensation over the expected range of bulk capacitor values, based on a capacitance to power ratio between

0.5 μF W^-1and 2.4 μF W^-1. This eliminates the need for external compensation components and simplifies the

design task.

The current-demand signal normally has a rectified sinusoidal shape. The current-loop output is used to program

a duty cycle which is then sent to the PFC_GD pin through a driver. The minimum duty cycle is 0% at which

point the PFG_GD output is kept low for the entire switching cycle. The maximum duty cycle for the PFC_GD

output is at least 92%.

NOTE

The maximum duty cycle is imposed by the PWM block independently of the input from

the current loop and does not depend on inputs from the current loop or elsewhere.

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10

AC1

| V_AC1± V_AC2

|

AC2

9

8

I_AV(dem)

Current

Loop

PWM

16 PFC_GD

Voltage

Loop

VBULK

PFC

Stop

V_REF

PFC_CS 13

Figure 14. PFC Control Loop

The inner current loop uses a hybrid mixed signal control method as shown in Figure 15. The I_AV(dem)signal

(digital average current demand) is converted to an analog form and summed with the sensed current signal I_CS

by the unity gain inverting amplifier, A1. The current sensed is the total inductor current which means that the

sensing resistor must be placed in the negative return as shown in Figure 13. The I_AV(dem)signal is positive going,

greater I_AV(dem)values commands larger currents. The signal at the PFC_CS pin is negative going so that larger

currents give a more negative signal level. The action of the control loop is to keep the inverting and non-

inverting inputs to A1 at the same level (450 mV). The output of the A1 amplifier contains both average and

peak-inductor current information. The average level at the A1 amplifier output is extracted by the ADC and

digital filter shown in the block called A2 in Figure 15. This average level is then subtracted from the fixed PWM

ramp coming from the waveform generator. The result is converted into an analog signal by the DAC and sent to

the inverting input of the fast analog PWM Comparator. The comparator ramp has an offset which is a function of

the digital-filter output. This offset value moves up and down in response to changes at the A1 output. The

comparator ramp at the inverting input is negative going and that at the non-inverting input is positive going. This

increases the noise immunity of the comparator making an incorrect, early termination of the cycle is less likely.

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If the I_AV(dem)signal increases, for example in response to an AC line voltage or load change then the average

output of the A1 amplifier initially decreases by the same amount. The PWM duty cycle, and inductor current, will

then increase because as V_A1(out)moves negative, it takes longer for the two signals at the comparator inputs to

intersect and terminate the cycle. The digital-filter output also increases in response to the change in V_A1(out)

according to its frequency response characteristic and the average value of the comparator ramp moves

negative. This tends to reduce the PWM duty cycle. Eventually, as the PFC inductor current increases the V_A1(out)

signal returns to its equilibrium point at 450 mV. The digital filter dynamically adjusts its output up or down so as

to keep the average value of the comparator ramp at the level where V_A1(out)is kept at 450 mV. The overall effect

is that a unipolar sinusoidal demand signal is translated into a unipolar sinusoidal PFC inductor current.

Digital

Waveform

Generator

+

PWM Ramp

DAC

ꢀ

-

A2

Digital Filter

I

AVG(dem)

(Analog)

I

AV(dem)

DAC

ADC

Comparator

Ramp

B

A

V

PFC_CS 13

A1(out)

+

A1

+

I

CS

PWM

Comparator

450 mV

Unity Gain Inverting

Analog Amplifier

+

OCP

Comparator

850 mV

Figure 15. UCC29950 Hybrid Current-Mode Control

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7.3.14 PFC Stage Second Current Limit

An individual PFC switching cycle is normally terminated by the PWM Comparator. If for some reason the PWM

Comparator fails or has stopped operating then there is a second comparator monitoring the output of the A1

amplifier (OCP Comparator in Figure 15). The OCP comparator turns the PFC MOSFET off and provides an

additional protection function for the devices in the power train.

If the output of A1 reaches 850 mV then the OCP comparator trips. Two actions follow:

1. The existing PWM cycle is terminated immediately.

2. Both the PFC and LLC stages shut down for 1 s followed by a re-start.

7.3.15 PFC Inductor and Bulk Capacitor Recommendations

The CCM Boost converter current-mode control loop is insensitive to PFC inductor value and can operate over a

wide range of inductance values. The inductor value in a given application is a trade off between ripple current,

physical size, losses, cost and several other parameters. For example, in Detailed Design Procedure for the PFC

stage a value of 600 µH for a 300-W application is chosen.

The hybrid control loop has been designed to be stable for any bulk capacitance between 0.5 µF W^-1and 2.4 µF

W^-1. For a 300-W application, this would allow the use of a bulk capacitance between 150 µF and 720 µF. These

limits on PFC inductance and bulk capacitance are conservative.

7.3.16 PFC Stage Over Voltage Protection

In normal operation the PFC stage control loop in the UCC29950 regulates the PFC stage output voltage (V_BLK

)

such that the voltage at the VBULK pin is held at V_BULK(reg). If the recommended sensing network is used then

this corresponds to 385 V on the bulk capacitor. If the voltage at the VBULK pin exceeds V_BULK(ovp)the PFC

stage is stopped immediately. It restarts once VBULK falls back to the V_BULK(reg)level. The OVP level

corresponds to 450 V at the PFC bulk capacitor. This protects the PFC stage against over stresses due to rapid

increases in V_BLK, occurring if an AC line surge event were to happen. The LLC stage continues to operate in

order to load and discharge the bulk capacitor. The OVP response is immediate, of the order of 100 µs, and is

more rapid than the response of the normal PFC voltage control loop.

V

BULK(ovp)

V

BULK(reg)

PFC_GD

GD1/GD2

Time

Figure 16. VBULK Over-Voltage Protection

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7.3.17 LLC Stage Control

The UCC29950 has three pins dedicated to the control of an LLC power stage, the two gate drives GD1 and

GD2, and the feedback pin, FB. If the controller is operating in Aux Bias Mode then the MD_SEL/PS_ON pin

may also be used to turn the LLC stage on or off. The UCC29950 includes an on chip Voltage to Frequency

Converter (VCO) which converts the voltage on the FB pin into a square wave at the desired frequency

according to the graph in Figure 1. The basic response time of the voltage to frequency conversion process is

typically less than 40 µs. This means that the overall response of the LLC power system is dominated by the

other components in the loop, for example, the opto-coupler and error amplifier on the output , rather than by the

UCC29950. Inverted and non-inverted versions of the square wave are produced and a dead time is added. The

dead time added is a function of the frequency being generated according to the graph in Figure 2. The signal is

then passed to the on-chip drivers connected at the GD1 and GD2 pins. The duty cycles of the GD1 and GD2

signals are highly symmetrical, typically they match to better than 0.1%.

The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2 respectively. The

half width pulses reduce any DC flux in the transformer at start up or shutdown. If the LLC_OCP3 level is

exceeded then the final pulse is of normal width.

GD1

GD2

Time

Figure 17. LLC GD1 and GD2 Start and Stop

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7.3.18 Driver Output Stages and Characteristic

The output stage pull-up features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The

function of the N-Channel MOSFET is to provide an increased sourcing current enabling fast turn-on, as it

delivers the highest peak-source current during the Miller plateau region of the power-switch turn-on transition,

when the power switch drain or collector voltage experiences high dV/dt. The N-Channel device can pull the

driver output to within one threshold voltage drop of the V+ rail. The P-Channel device can pull the driver output

all the way to V+.

The effective resistance of the UCC29950 pull-up stage during the turn-on instant is therefore lowest during the

time when the highest current is needed. The pull-down structure in UCC29950 is composed of an N-Channel

MOSFET which can pull the output all the way to GND.

The structure in Figure 18 is used in the output circuit of the low power driver used to output the AC_DET signal.

It has the same pull up characteristics, but at an impedance level more suitable for driving a signal level load

such as an optocoupler LED.

V+

R

OH

Output

R

OL

Input

Figure 18. Driver Output Stage (simplified)

7.3.19 LLC Stage Dead Time Profile

The UCC29950 programs a dead time into the LLC gate drive outputs (GD1 and GD2) which follows the profile

shown in Figure 2. The dead time is longest at high frequencies because the currents in the resonant tank circuit

are less and so the stray capacitances at the switched node take longer to swing from one rail to the other. At

low frequencies the opposite is true, the currents in the resonant tank are greater and the switched node swings

more quickly.

7.3.20 LLC Stage Current Sensing

The UCC29950 uses primary-side current sensing to monitor the output current. This has the advantage that

current limiting can be implemented without having to bring a current limit signal across the primary-to-secondary

isolation barrier. Also, assuming that the output voltage of the LLC stage is lower than the input, the currents in

the primary circuit are lower than those in the secondary. This allows a larger value of sensing resistor to be

used without incurring excessive power dissipation. One side effect of sensing on the transformer primary is that

the sensed current includes start up charging currents onto the LLC stage output capacitance. The three level

OCP feature allows this charging current to flow without tripping a fault. Even if the current sensing were done on

the secondary side and outboard of the LLC stage output capacitance there may still be additional, off-board

capacitance whose charging current does flow in the sensing resistor.

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7.3.21 LLC Three Level Over-Current Protection

The UCC29950 uses the LLC stage input current to represent the output current. The value of the LLC current

sense resistor that should be used is given by Equation 36.

Three levels of overcurrent protection as shown in Figure 19, are provided to allow the UCC29950 to react in a

flexible manner to an over current event. V_CS(ocp1)and V_CS(ocp2)faults are triggered after a short delay. V_CS(ocp3)

level faults are acted on immediately.

Table 4. LLC Stage Over-Current Protection Levels

OCP PARAMETER

V_CS(ocp1)

DESCRIPTION

VALUE

First overload detection level. If this threshold is exceeded for t_OCP1then both 133% of V_{CS(llc_max)}

the PFC and LLC stages will shut-down. Restart with a normal soft-start

sequence after t_LONG(fault)(1 s typ).

.

Typically 400 mV

t_OCP1

52 ms

V_CS(ocp2)

Second overload detection level. If this threshold is exceeded for t_OCP2then

both the PFC and LLC stages will shut-down. Restart with a normal soft start Typically 600 mV

sequence after t_LONG(fault)(1 s typ).

200% of V_{CS(llc_max)}

t_OCP2

10 ms

V_CS(ocp3)

Third overload detection level. If this threshold is exceeded for t_OCP3then

300% of V_{CS(llc_max)}

both the PFC and LLC stages will shut-down. Restart with a normal soft start Typically 900 mV

sequence after t_LONG(fault)(1 s typ).

t_OCP3

This is the time the UCC29950 takes to react to a level three overload

voltage at the LLC_CS pin. Board level filtering can reduce the signal rise

time at the pin and significantly increase the overall reaction time.

<5 µs

If any of these over-current protection events occurs the controller enters a hiccup mode of operation and it tries

to restart the power stages at 1-s intervals. This graduated response allows the power stage to ride through a

short-term transient overload but reacts quickly to protect the power stage from heavy overload or output short-

circuit events.

LLC_CS

tt

t

OCP3

V_CS(ocp3)

tt

t

OCP2

V_CS(ocp2)

tt

t

OCP1

V_CS(ocp1)

CS_LLC(max)

V

t t

t

LONG(fault)

Time

Figure 19. UCC29950 Output Over-Current Protection Profile

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7.3.22 Over-Temperature Protection

If the UCC29950 junction reaches its T_SD(Thermal Shutdown Temperature) it stops both the PFC and LLC

stages. The device then cools down to its T_ST(Start / Restart Temperature). It then initiates a full soft start of

both stages, provided that the other conditions for start up are met. An over-temperature protection event is

treated as a long fault with a 1-s recovery time. The thermal inertia in the device package normally prevents the

junction temperature from falling to T_STwithin 1 s so that this 1 s fault time is not apparent to the user.

7.3.23 Fault Timer and Control

Three types of faults are recognized by the UCC29950:

•

Latching

Long with Auto Recovery (1 s)

Short with Auto Recovery (100 ms)

A latching shutdown is triggered by the following events. VCC must be cycled off and on to reset these faults:

•

V_BLK< Peak of AC line. (This can happen only if there is a fault in the V_BLKsensing network or an open circuit

in the path between the line input and C_BLK. This condition is evaluated each time the UCC29950 turns on. It

is not evaluated during normal operation.)

•

At start-up the UCC29950 performs a cyclic redundancy check on its internal memory. If the device fails this

check it stops immediately and will not attempt to start the power stages.

A long fault is triggered by any of the following events:

•

LLC stage Over Current Protection

PFC Stage Second Current Limit

X-Cap Discharge (This reduces average power dissipation in the high-voltage depletion mode MOSFET)

Over Temperature Fault (Thermal inertia increases the recovery time)

A short fault is triggered by any of the following events:

•

VCC Under Voltage

VAC < V_{AC(low_falling)}(Brownout)

VAC > V_{AC(high_rising)}

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7.4 Device Functional Modes

7.4.1 Mode Selection

The UCC29950 may be operated in one of two modes. In Aux Bias Mode VCC is supplied from an external

source. A small, separate fly-back supply is normally used for this purpose. Aux Bias Mode allows the user to

turn both the LLC and PFC stages off or to run only the PFC stage or to run both PFC and LLC stages together

and to run the system at no load if desired. In Self Bias Mode the VCC rail is powered from a small auxiliary

winding on the LLC transformer and ON/OFF control of the PFC and LLC stages is not possible in Self Bias

Mode.

7.4.2 Start-Up in Aux Bias Mode

A small external PSU is used to supply VCC in Aux Bias Mode. A 12-V 50-mA supply is normally sufficient but

this does depend on system level factors such as the gate-driver circuitry used, the load presented by the

switching MOSFETs and other factors.

C_X-cap

V_AC

13

16

8

11

10 AC1

GD1 14

GD2 2

9

4

5

AC2

UCC29950

SUFG

SUFS

12

3

FB

VCC

C_VCC

VCC

1

6

15

7

External

Control

Signal

Figure 20. External Control Signal

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Device Functional Modes (continued)

Aux Bias Mode is selected if the MD_SEL/PS_ON pin is kept lower than V_MODE(selsb)for a time greater than

T_{MODE(sel_read)}after VCC passes the VCC_STARTthreshold. After this time has passed, the MD_SEL/PS_ON pin

may be used to turn on the PFC stage alone by setting this pin to a voltage between the V_{PS_ONPFC_RUN}and

V_{PS_ONLLCPFC_RUN}levels. The PFC and LLC stages may both be turned on by setting the MD_SEL/PS_ON pin to

a voltage greater than V_{PS_ONLLCPFC_RUN}. Refer to the Electrical Characteristics table for the related tolerances on

these thresholds.

The MD_SEL/PS_ON pin may be driven from an active source such as a comparator or digital output (with

appropriate level shifting, provided by an optocoupler for example). A simple RC network may also be used if an

active source is not available. Connect a capacitor from MD_SEL/PS_ON to AGND and a resistor from

MD_SEL/PS_ON to VCC. The RC time constant should be chosen so that the voltage at the MD_SEL/PS_ON

pin is less than V_{MODE_SELSB}10 ms after VCC increases past V_CC(start). Normally an RC time constant of 100ms

will be satisfactory. The slow rise of the MD_SEL/PS_ON signal between the V_{PS_ONPFC_RUN}and

V_{PS_ONLLCPFC_RUN}levels increases overall start-up time by a few 100 ms.

The normal sequence in a system is that V_ACis applied, MD_SEL/PS_ON is held low, VCC comes up and

MD_SEL/PS_ON is then used to turn the PFC/LLC stages on as shown in Figure 21.

This sequence applies whether or not the X-Cap discharge function is being used.

Typical start-up times in Aux Bias Mode are in the range 150 ms to 250 ms after MD_SEL/PS_ON is brought

high.

V

BULK_LLC_START

V

C_Bulk

V

AC

VCC

tT

MODE_SEL_READ

MD_SEL/

PS_ON

V

PS_ONPFC_RUN

V

PS_ONLLCPFC_RUN

T

PFC_PS_ON_DELAY

PFC_GD

GD1/GD2

tLLC_Soft_Start_Delayt

Time

Figure 21. Typical Aux Bias Turn-On Sequence

(both PFC and LLC stages are turned on simultaneously by pulling MD_SEL/PS_ON above

V_{PS_ONLLCPFC_RUN}

)

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Device Functional Modes (continued)

7.4.3 Start-Up Operation in Self-Bias Mode

In Self Bias Mode, the MD_SEL/PS_ON pin should be tied to VCC as shown. The start-up FET is a normally on

depletion mode device, a BSS126 for example. C_VCCis charged via the start-up FET and the internal current-

limiting block. Initial charging of C_VCChappens automatically even though VCC is below VCC_START. When VCC

reaches VCC_STARTthe SUFG pin goes low, which turns the start-up FET off. If the MD_SEL/PS_ON pin is tied to

VCC, the UCC29950 enters Self Bias Mode. SUFG goes high again to turn the start-up FET on again and allow

C_VCCto charge further. When C_VCChas been charged to VCC_SB(start)(typically 16.2 V) the start-up FET is turned

off and providing that the current into the AC1 and AC2 pins is greater than I_{AC(low_rising)}and that the sensed V_BLK

voltage is greater than peak of AC line the PFC stage is started. As noted earlier, an 18-V zener diode should be

used to clamp the voltage on C_VCC. The switching operation of the PFC and LLC stage is maintained as long as

C_VCCis above VCC_SB(stop). Equation 2 allows the user to select the value of C_VCC

.

V_AC

C_X-Cap

13

16

8

11

Bias Winding on

LLC transformer

10 AC1

GD2

2

9

4

5

AC2

GD1 14

UCC29950

Start Up

FET

SUFG

SUFS

12

3

FB

VCC

C_VCC

1

6

15

7

Figure 22. Self Bias Mode

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Device Functional Modes (continued)

The start-up time in Self Bias Mode depends strongly on the current available for charging and on the

capacitance on the VCC rail and. A first pass estimate of start-up time can be made using:

_8%%× VCC

P_{5$(OP=NP )}N ^%

+ 200 ms

5$ (OP=NP )

+

57(5

(2)

For typical values, assuming C_VCCis 200 µF, t_STARTis therefore 1.8 s.

V

BULK(LLC(start))

V

C(bulk)

V

AC

VCC

SB(start)

VCC

SB(UVLO(stop))

VCC

START

SUFG

T

MODE_SEL_READ

PFC_GD

GD1/GD2

Time

Figure 23. Typical Self Bias Turn-On Sequence

7.4.4 Bias Rail UVLO

The UCC29950 continuously monitors the voltage at its VCC pin. It stops both the PFC and LLC stages if VCC

falls below VCC_{AB(uvlo_stop)}or VCC_{SB(uvlo_stop)}, depending on whether it is operating in Aux Bias or Self Bias

Modes respectively. In Aux Bias Mode, the device simply waits for VCC to recover to a voltage greater than

VCC_{AB(uvlo_stop)}. At which point it restarts. If it is operating in Self Bias Mode it sets SUFG HI to turn the start-up

FET on. The current through the start-up FET then charges the capacitance on the VCC rail up to VCC_SB(start)at

which point the system tries to restart as described earlier.

7.4.5 LLC Stage MOSFET Drive

UCC29950 includes two high-power drivers that are capable of directly driving both MOSFETs in the half bridge

LLC circuit through a suitable gate drive transformer as shown in Figure 24. Alternatively an external driver

device, with its own high-side channel, can be used to interface between UCC29950 and half bridge MOSFETs

as shown in Figure 25.

If a gate drive transformer is used then GD1 should be used to drive the high-side MOSFET and GD2 used to

drive the low-side MOSFET. If a gate driver device is used then GD1 should be used to drive the low-side

MOSFET and GD2 used to drive the high-side MOSFET. TI recommends the UCC22714 as a suitable gate

driver device. The first and last LLC gate drive pulses are normally half width and appear on GD1 and GD2

respectively, see Figure 17.

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Device Functional Modes (continued)

V_IN

Q1

D1

0.5 C_R

N_P:N_S:N_S

+

R_L

C_O

V_SQ

GD1

GD2

L_R

L_M

-

Q2

V_OUT

D2

0.5 C_R

R_{CS_LLC}

V_{CS_LLC}

Figure 24. LLC MOSFET Gate Drive Using a Gate Drive Transformer (simplified)

D_B

V_IN

VCC

12V

VCC HB

C_B

(typ)

GD2

HI

HO

HS

Q1

Q2

D1

D2

0.5 C_R

N_P:N_S:N_S

+

R_L

C_O

V_SQ

L_R

L_M

-

LI

LO

GD1

V_OUT

COM

GND

0.5 C_R

R_{CS_LLC}

V_{CS_LLC}

Figure 25. LLC MOSFET Gate Drive Using a Driver Device (simplified)

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Device Functional Modes (continued)

7.4.6 Gate Drive Transformer

Gate driver transformers are robust and less susceptible to noise than gate drive devices but will also be larger

than a solution using a gate driver device.

The GD1 and GD2 outputs from the UCC29950 are symmetrical, with 180˚ phase shift and a duty cycle less than

50%. If the gate drive transformer is driven as shown in Figure 24, then the waveform at its primary has no DC

component. The gate-drive transformer must be able to support the maximum V sec product based on the GD1

and GD2 signal at LLC F_MIN. In steady state conditions, the duty cycles of GD1 and GD2 outputs are extremely

well matched, typically within 0.1% of each other. When using a gate-drive transformer, the GD1 signal should be

used to driver the high-side MOSFET and the GD2 signal used to drive the low-side MOSFET, as shown in

Figure 24. The initial half-width pulse on GD1 and final half-width pulse on GD2 ensures that there is no DC flux

imbalance on either the gate-drive transformer or in the main transformer see Figure 17.

The gate-drive transformer used to directly drive the LLC power MOSFETs should have a low common-mode

capacitance. The common-mode current that flows from the upper-gate winding, back through the UCC29950

drivers, during bridge-switching transitions must return to the power circuit via the UCC29950 GND pin. Voltage

disturbance on the GND pins during LLC bridge transitions may lead to audible interaction between the PFC and

LLC power stages.

Placing a screen between the controller winding and gate-drive windings is one way to reduce the common-

mode capacitance of the transformer. This screen should be connected to the source of the lower half-bridge

MOSFET (Q2).

The gate-drive transformer should drive both the low-side and high-side MOSFETs as shown in Figure 24. This

ensures that propagation delays through the transformer are matched and the symmetry of the dead time is

maintained.

7.4.7 Gate Drive Device

A gate-driver device solution is less bulky than a gate-drive transformer and may be easier to design and layout.

The capacitance from output to input is very low which means that interference from common-mode currents will

not normally occur. In both Aux Bias and Self Bias Modes, the HO and LO outputs must make a clean transition

between their active state (where they obey the HI and LI inputs) and their UVLO state (where they are latched

low). Additionally, if operating in Aux Bias Mode it is very important to make sure that the UVLO level of the gate-

driver device is less than that of the UCC29950 (V_{CCAB_UVLO(stop})). This ensures that the GD1 and GD2 signals

are always passed on to the switching MOSFETs and that the UCC29950 maintains control of the LLC power

train. It also ensures, if there is a UVLO condition on the bias rail, that the UCC29950 can enter and exit the

UVLO condition correctly with a proper soft start during the recovery phase. In Self Bias Mode, it is not

necessary that the driver UVLO is lower than that of the UCC29950, if the MOSFET gate drives stop for any

reason then the bias always collapse to the UCC29950 V_{CCSB_UVLO(stop)}level, followed by a full restart as

described in LLC Stage Soft Start.

High-side driver devices use a bootstrap capacitor, C_Bin Figure 25, to supply the current to charge the gate of

the high side MOSFET. This capacitor must first be charged to the driver high-side UVLO voltage before any HO

pulses are delivered to the high-side MOSFET gate. C_Bis charged during the first few LO pulses. Once the

voltage across C_Breaches the high side driver UVLO level there is normally a short delay, 20 µs, before HO

pulses appear. The current in the circuit during the first few switching cycles, when both high-side and low-side

MOSFETs are being driven, will be higher than normal. The circuit designer must ensure that the LLC power-

circuit components are rated for these stresses.

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Device Functional Modes (continued)

7.4.8 Comparison

Users who employ a gate-drive transformer benefit from special features in UCC29950 to ensure a much

smoother start-up transition of the LLC converter. This allows magnetics with a lower peak-current rating to be

used safely. It is important to use a gate-drive transformer with a low common-mode capacitance.

If an external high-side driver is used then the smooth start-up feature is effectively disabled and the designer

must ensure that the LLC magnetics are rated to cope with the resulting increased peak current during start-up.

Figure 26 compares the LLC resonant current waveform observed during the start-up transient. Both traces are

triggered on GD1 output at the same point. The lower trace is observed when directly driving the LLC bridge

MOSFETs via a gate drive transformer. The upper trace is observed when driving the LLC bridge MOSFETs via

an external gate device driver. Vertical scale is 2 A/div. Horizontal scale is 10 µs/div.

Figure 26. Typical LLC Transformer Primary Current During Startup

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8 Application and Implementation

8.1 Application Information

The UCC29950 device is a highly-integrated combo controller. It is designed for applications requiring a CCM

boost PFC input stage followed by an LLC output / isolation stage. The PFC loop is internally compensated and

requires no external loop-compensation components. EMI filtering is simplified because the PFC stage operates

at a fixed frequency with dither. A three level output overload protection current/time profile is included.

8.2 Typical Application

A typical application for this device would be in a 300-W, universal input isolated PSU with a 24-V (12.5-A)

output.

1

4

3

6

1

4

3

6

Figure 27. Controller Application

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Typical Application (continued)

2

1

3

4

1

6

3

2

3

9

4

~

Figure 28. Power Stage Application

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Typical Application (continued)

8.2.1 Design Requirements

The typical application should meet the following requirements:

Table 5. Typical Application Requirements

PARAMETER

V_AC

REQUIREMENT

Input voltage

85 V_ACto 264 V_AC

f_LINE

Line frequency

47 Hz to 63 Hz

385 V

V_BLK

Nominal PFC stage output voltage

Max V_BLKripple (2 x Line Frequency)

Maximum PFC stage output voltage, V_BLK+ ½ V_BLK(ripple)

Minimum PFC stage output voltage, V_BLK– ½ V_BLK(ripple)

Minimum PFC stage output voltage at end of hold-up time

Output voltage

V_BLK(ripple)

V_BLK(max)

V_BLK(min)

V_BLK(hu)

V_OUT

30 V_PP

400 V

370 V

300 V

24 VDC

V_OUT(min)

V_OUT(max)

I_OUT

Min output voltage

21.6 V (V_OUT– 10%)

26.4 V (V_OUT+10%)

12.5 A

Max output voltage

Full load output current

V_{OUT(pk_pk)}

P_OUT

Output voltage ripple

300 mV

Output power

300 W

η

Efficiency

90 %

P_F

Power factor

0.99

t_H

Hold-up time

20 ms

f_PFC

PFC stage switching frequency

98 kHz

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8.2.2 Detailed Design Procedure

8.2.2.1 LLC Stage

Start the design by deciding on the component values in the LLC power train and then move to the PFC stage.

The LLC stage design procedure outlined here follows the one given in the TI publication “Designing an LLC

Resonant Half-Bridge Power Converter” which is available at http://www.ti.com/lit/ml/slup263/slup263.pdf. The

document contains a full explanation of the origin of each of the equations used. The equations given below are

based on the First Harmonic Approximation (FHA) method commonly used to analyze the LLC topology. This

method gives a good starting point for any design, but a final design requires an iterative approach combining the

FHA results, circuit simulation and hardware testing. An alternative design approach is given in TI Application

Note, LLC Design for UCC29950, Texas Instruments Literature Number SLUA733.

One of the reasons that the LLC topology is so popular is that it can achieve Zero Voltage Switching (ZVS) over

a wide range of operating conditions. ZVS is important because it reduces switching losses in the power devices.

The schematic for a basic LLC is shown in Figure 29.

Q1

C_R

L_R

N_P:N_S:N_S

D1

+

V_IN

+

V_SQ

±

R_L

C_O

V_OUT

-

Q2

L_M

R_CS(llc)

D2

V_CS(llc)

Figure 29. Basic LLC Schematic

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In this system the input V_INis the output of the PFC stage. V_INis a DC voltage with some AC ripple at twice the

line frequency. The two switches Q1 and Q2 are driven in anti-phase to generate a high-frequency square wave

input signal V_SQat the input to the resonant network formed by C_R, L_Rand L_M. R_CS(llc)is a current sensing

resistor. Current flows in R_CS(llc)only during the on time of Q1 in this single ended version of the LLC topology.

This has two effects.

1. There is a significant voltage ripple on the current sense signal as Q1 and Q2 are switched.

2. Fault currents in Q2 are measured indirectly by their effect on currents in Q1.

The modified LLC topology shown in Figure 33 eliminates these disadvantages.

The resistor R_Lloads this circuit through the transformer turns ratio and the peak gain is therefore a function of

load, as shown in Figure 30. At no load, R_Lis very high and its influence may be neglected and circuit has a

resonance at:

1

B =

L

2è (. + . )%

4

¥

4

/

(3)

At the other extreme, R_Lis zero and it effectively shorts the transformer magnetizing inductance L_M. The

resonant frequency under this condition is:

1

B =

0

2è . %

¥

4

(4)

This means that as the load changes from no load to short circuit the peak-gain frequency (f_C0) moves between

these two values so that:

B Q B Q B

0

L

%0

(5)

Output voltage regulation is achieved by changing the switching frequency of the LLC stage. If V_INincreases the

LLC stage gain must reduce in order to keep V_OUTunchanged. The gain is reduced by increasing the switching

frequency as can be seen in Figure 30. If V_INreduces, then the gain must be increased and this is done by

reducing the switching frequency. The frequency must remain above the resonant frequency f_C0to maintain zero

voltage switching and to avoid control law reversal. This is especially important in a short circuit condition where

the control loop would try to reduce the switching frequency and where simultaneously f_C0has increased to its

maximum at f₀. Short circuit and overload protection are provided in the UCC29950 and are discussed in LLC

Stage Over-Current Protection, Current Sense Resistor below.

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8.2.2.2 LLC Switching Frequency

Selecting the nominal full-load switching frequency is relatively straightforward. Most EMI standards for

conducted emissions have a lower limit at 150 kHz. If the fundamental switching frequency is lower than this then

it does not appear in the EMI test scans which makes EMI filtering easier. Otherwise, if it is too low then the

magnetic components are larger than necessary and the efficiency benefits of ZVS are reduced. A switching

frequency of 120 kHz is a good compromise and is the one used in this design.

8.2.2.3 LLC Transformer Turns Ratio

The transformer turns ratio is given by the equation:

8 /2

385 8/2

24 8

+0

0 =

=

= 8.02 8

8₁₇₆

(6)

V_INis the voltage on the bulk capacitor. This is regulated at 385 V_DCif the resistor values suggested in Table 2

are used for the potential divider at the VBULK pin and ignoring diode forward voltage drops V_OUTis 24 V.

8.2.2.4 LLC Stage Equivalent Load Resistance

This is the effective load resistance reflected through the transformer turns ratio. Re is determined at the full load

point.

8 0²

è²

64

24 8

4_'=

4_.= 8 ×

×

= 99.6 À

9.87 12.5 #

(7)

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8.2.2.5 LLC Gain Range

These parameters set the gain range required of the LLC stage. It is assumed a 0.5-V drop in the rectifier diodes

(V_f) and a further 0.5-V drop due to other losses (V_LOSS).

8_{176(IEJ )}

(21.6 8 + 0.5 8)

/

)(IEJ )

= 0

= 8 ×

= 0.88

8

(400 8)

^{+0(I=T )}W

W

2

(8)

(9)

8₁₇₆+ V_B+ V_.155

(24 8 + 0.5 8 + 0.5 8)

/

)(I=T )

= 0

= 8 ×

= 1.33

8

(300 8)

^BLK(hu)W

W

2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

Q=0.00143

Q=0.29

Q=0.44

Q=0.48

0.9

0.8

0.7

0.6

0.5

0

0.5

1

1.5

2

2.5

3

3.5

Normalized Frequency (F_N)

D001

Figure 30. LLC Stage Gain Curve

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8.2.2.6 Select L_Nand Q_E

From Figure 31 and Figure 32 select suitable L_Nand Q_Evalues to meet the M_{G_MIN}and M_{G_MAX}values from

Equation 8 and Equation 9.

L_Nis the primary inductance ratio and is given by:

.

/

.

0

=

= 5.0

.

4

(10)

Q_Eis the quality factor of the resonant network.

¤

¥.₄

%

4

3_'=

= 0.4

4_'

(11)

Set L_N= 5.0 and Q_E= 0.40 for this application. The LLC peak gain curves below show a maximum which is

greater than the maximum calculated by Equation 9.

7

6.5

6

3.6

3.3

3

Ln, 1.5

Ln, 2.0

Ln, 2.5

Ln, 3.0

Ln, 3.5

Ln, 4.0

Ln, 5.0

Ln, 6.0

Ln, 7.0

Ln, 8.0

Ln, 9.0

5.5

5

2.7

2.4

2.1

1.8

1.5

1.2

0.9

4.5

4

3.5

3

2.5

2

1.5

1

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Quality Factor, (Q_E)

D001

Figure 31. LLC Peak Gain Curves

Figure 32. LLC Peak Gain Curves

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8.2.2.7 LLC No-Load Gain

The gain required at no load is:

.

5.0

0

/

)(»)

=

= 0.83

.₀+ 1 5.0 + 1

(12)

Figure 30 shows that the design can achieve a minimum gain of 0.8 at the maximum frequency of the UCC29950

(350 kHz or 2.9 times the normalized f₀of 120 kHz).). If the gain is too high then the UCC29950 enters a burst

mode of operation to keep the output voltage under control.

8.2.2.8 Parameters of the LLC Resonant Circuit

The value of the resonant capacitor is given by the equation:

1

%₄=

=

= 33 J( 32 J(

2 è B₅₉4_'3_'2 è × 120 G*V × 99.6 À × 0.4

(13)

The resonant inductor is given by the equation:

1

.₄=

=

= 55 ä*

(2 è B₅₉)²%₄

(2 è 120 G*V)²× 32 J(

(14)

(15)

Rearranging Equation 10 gives a value for L_M, the transformer magnetizing inductance:

= .₀.₄= 5.0 × 55 ä* = 275 ä*

.

/

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8.2.2.9 Verify the LLC Resonant Circuit Design

The series resonant frequency is given by Equation 4.

1

B =

0

=

= 120 G*V

2è . %

2è 55 ä* × 32 J(

¥

4

(16)

(17)

The inductance ratio is given by:

.

275 ä*

/

.

=

= 5.0

0

.

55 ä*

4

The quality factor at full load is given by:

¤

¥.₄

%

4

¥55 ä* 32 J(

3_'=

=

= 0.42

4_'

99.6 À

(18)

This differs from the initial value of 0.45 because a rounded value for C_Ris used here and in the calculation of

L_R.

The difference is not significant.

Figure 30 has been normalized to the series resonant frequency which is 120 kHz in this example.

At the minimum gain condition with minimum output voltage and maximum input voltage (M_G(min)) the frequency

is 1.6 times f₀or f_SW(max)= 192 kHz.

At the maximum gain condition with maximum output voltage and minimum input voltage (M_G(max)) the frequency

is 0.6 times f₀or f_SW(min)= 72 kHz.

8.2.2.10 LLC Primary-Side Currents

The primary-side RMS load current is given by:

è

1

0

è

1

8

+

1'

=

×

× +₁=

×

× 110% × 12.5 # = 1.91 #

2 2

¾

2 2

¾

(19)

The RMS magnetizing current at minimum switching frequency is:

2 2 08 2 2 8 × 24

è 2è × 72 G*V × 275 ä*

¾

è

¾

176

+

/

=

= 1.4 #

ñ._/

(20)

(21)

The total current in the resonant circuit is then given by:

2

§

¥

(1.91 #) + (1.4 #) = 2.4 #

+₄= +₉₂= +_%4

=

+_/+ +_1'

=

This current also flows in the transformer primary winding (I_WP) and the resonant capacitor (I_CR).

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8.2.2.11 LLC Secondary-Side Currents

The total secondary-side RMS current is the current referred from the primary side (I_OE) to the secondary side.

= 0 +_1'= 8 × 1.91 # = 15.3 #

+

1'(5)

(22)

The design uses a centre tapped secondary so that this current is shared equally between the two windings. The

current in each winding is then:

2 +

¾

2 × 15.3 #

¾

1'(5)

+

95

=

= 10.8 #

2

(23)

(24)

And the half-wave average current in the secondary windings is:

2 +

¾

2 × 15.3 #

¾

1'(5)

+

5#8

=

= 6.89 #

è

8.2.2.12 LLC Transformer

The transformer can be built or purchased according to these specifications:

•

Turns Ratio (N): 8

Primary Magnetizing Inductance: L_M= 275 µH

Primary Terminal Voltage: 450 V_AC

Primary Winding Rated Current: I_WP= 2.4 A

Secondary Terminal Voltage: 56 V_AC

Secondary Winding Rated Current: I_WS= 10.8 A

No Load Operating Frequency: f_SW(max)= 192 kHz

Full Load Operating Frequency: f_SW(min)= 72 kHz

Reinforced Insulation Barrier from Primary-to-Secondary to IEC60950

The minimum operating frequency during normal operation is that calculated above but during shutdown the LLC

can operate at at LLC_FMIN.The magnetic components in the resonant circuit, the transformer and resonant

inductor, should be rated to operate at this lower frequency.

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8.2.2.13 LLC Resonant Inductor

The AC voltage across the resonant inductor is given by its impedance times the current:

= ñ.₄+₄= 2è × 72 G*V × 55 µH × 2.4 A = 59.6 V 60 V

8

.

4

(25)

As with the transformer, the resonant inductor can be built or specified according to these specifications:

•

Inductance: L_R= 55 µH

Rated Current: I_R= 2.4 A

Terminal AC Voltage: V_LR= 60 V

Frequency Range: 72 kHz to 192 kHz.

The minimum operating frequency during normal operation is that calculated above but during shutdown the LLC

can operate at at LLC_FMIN.The magnetic components in the resonant circuit, the transformer and resonant

inductor, should be rated to operate at this lower frequency.

8.2.2.14 Combining the LLC Resonant Inductor and Transformer

All physical transformers have a certain amount of leakage inductance. This inductance appears in series with

the magnetizing inductance. It degrades the performance of most topologies so designers usually try to minimize

it. In the LLC topology however, the leakage inductance appears in the same position as the Resonant Inductor

L_Rin Figure 29. This means that it is possible to design the transformer so that its leakage inductance replaces

the separate resonant inductor.

The Advantages:

•

Fewer Magnetic Components

Simpler PCB

Lower Cost

The disadvantage to the transformer must be designed to have a relatively large and well controlled amount of

leakage inductance. The resonant inductance in the design above is about 20% of the total L_R+ L_M. This is a

high ratio and careful control of the winding geometry and layering is needed to keep the leakage inductance

within acceptable limits.

The design procedure given above is valid irrespective of whether a design uses a separate resonant inductor

and transformer or uses a single high-leakage transformer.

8.2.2.15 LLC Resonant Capacitor

This capacitor carries the full-primary current at a high frequency. A low dissipation factor part is needed to

prevent overheating in the part.

The AC voltage across the resonant capacitor is given by its impedance times the current.

+

2.4 A

%4

8

%4

=

= 166 8

ñ%₄

2è × 72 G*V × 32 J(

(26)

(27)

2

8

400 8

2

8

=

^{+0(I=T )}p + 8²

=

p + 166 8²= 260 8

¨

l

¨

l

%4(NIO )

%4

2

And the corresponding peak voltage:

8

400 8

2

8

=

^{+0(I=T )}+ ¾28

=

%4

+ ¾2 × 260 8 = 434 8

%4(LA=G )

2

(28)

The part selected must meet these specifications:

•

Rated Current: I_CR= 2.4 A

AC Voltage: V_CR(peak)= 434 V

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8.2.2.16 LLC Stage with Split Resonant Capacitor

It is possible to split the resonant capacitor in Figure 29 into two separate parts as shown below. The two circuits

are topologically equivalent but there are some differences in circuit stresses. The calculation of the resonant

circuit components is the same and the values of L_R, L_Mand C_Rare unchanged. The two resonant capacitors are

each half the value of C_R.

The major advantages are:

•

The current stresses in the capacitors are halved because the resonant current is shared between the two

parts.

•

The currents during the conduction times of both Q1 and Q2 flow in the current sensing resistor.

The main disadvantage is two parts are needed.

D1

0.5 C_R

Q1

N_P:N_S:N_S

+

R_L

C_O

V_SQ

+

V_IN

L_R

L_M

-

±

V_OUT

D2

Q2

0.5 C_R

R_CS(llc)

V_CS(llc)

Figure 33. Basic LLC Schematic with Split Resonant Capacitor

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8.2.2.17 LLC Primary-Side MOSFETs

V_INappears across the MOSFET which is not conducting. The voltage rating must then be:

8_{31(LA=G )}= 8_{32(LA=G )}= 8 = 400 8 500 8

+0

(29)

This is a minimum rating and a 650-V rated part would be a better choice to allow margin for line-surge tests.

In the steady state, each MOSFET carries half of the resonant current. Start-up currents can be significantly

higher so we set the RMS current rating to 110 % of the resonant current.

+

= +_{32(NIO )}= 110% +₄= 1.1 × 2.4# = 2.65 #

31(NIO )

(30)

8.2.2.18 LLC Output Rectifier Diodes

The voltage rating for the output diodes is given by:

8

400 8

+0(I=T )

8_&$

=

= 50 8 62 8

0

8

(31)

(32)

The current rating for the output diodes is given by:

2 +

¾

2 × 15.3 #

¾

1'(5)

+

5#8

=

= 6.9 #

è

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8.2.2.19 LLC Stage Output Capacitors

The LLC converter topology does not require an output filter although a small second stage filter inductor may be

useful in reducing peak-to-peak output noise.

Assuming that the output capacitors carry the rectifier’s full wave output current then the capacitor ripple current

rating is:

è

+

= +₅₉

=

+

176

=

× 12.5 # = 13.9 #

4'%6

2 2

¾

2 2

¾

(33)

(34)

The capacitor’s RMS current rating at 120 kHz is:

è

è²

2

¨

+

=

(

¨

+

₁₇₆)²F +₁₇₆

=

F 1 × +₁₇₆= 0.483 × 12.5 # = 6.04 #

%(KQP )

8

2 2

¾

Solid Aluminum capacitors with conductive polymer technology have high ripple-current ratings and are a good

choice here. The ripple-current rating for a single capacitor may not be sufficient so multiple capacitors are often

connected in parallel.

The ripple voltage at the output of the LLC stage is a function of the amount of AC current that flows in the

capacitors. To estimate this voltage, we assume that all the current, including the DC current in the load, flows in

the filter capacitors.

V_OUT(pkFpk)

300 I8

'54_/#:

=

= 15.3 IÀ

è

+

4'%6(LG)

2

+

176

2

× 12.5 #

4

(35)

The capacitor specifications are:

•

Voltage Rating: 30 V

Ripple Current Rating: 6.04 A at 120 kHz

ESR: < 15 mΩ

8.2.2.20 LLC Stage Over-Current Protection, Current Sense Resistor

This resistor shown in Figure 29 and Figure 33 senses the LLC stage input current. This current contains a

significant component at the switching frequency in additional to a DC component. Only the DC component is

proportional to the load current. This means that the signal should be filtered before it is applied to the LLC_CS

pin of the UCC29950. The degree of filtering is a compromise between response time and accuracy. A

recommended schematic is shown in Figure 13. An RC filter with a pole at about 1 kHz is used to filter the signal.

An additional capacitor, C1, across the current sense resistor provides a higher frequency pole at approximately

10 kHz.

The LLC current sensing resistor is selected so that the LLC_CS signal is at 90% of the OCP1 level (400 mV x

0.9 = 360 mV) when the converter is operating at full load and nominal input and output conditions. The resistor

value is then given by:

8

_{%5(HH?_BH)}8_{$.-(IEJ )}

0.36 8 × 370 8

110% × 300 9

4_%5(HH?)

=

= 403 IÀ 400 IÀ

1

2₁₇₆

ß

(36)

Where V_BLK(min)is the voltage at the bottom of the line ripple on C_BLK

.

Assuming there is no ripple current in the current sensing resistor, the full load power dissipated in this resistor is

given by:

8²

0.36 8²

400 IÀ

%5(HH?_BH)

2₄

=

= 324 I9

%5 (..% )

4_%5(HH?)

(37)

The resistor should be able to dissipate the power due to an overload which is just lower than the OCP_1

threshold.

8²

0.4 8²

%5(1%21)

2_{4 (HH?_I=T )}

=

= 400 I9

%

4_%5(..%)400 IÀ

(38)

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8.2.2.21 Detailed Design Procedure for the PFC stage

The boost topology operated in Continuous Conduction Mode (CCM) is a popular choice for a Power Factor

Correction (PFC) stage because it has lower component stresses than other topologies. This becomes more

important at higher power levels.

The schematic for a basic PFC is shown in Figure 34. The basic schematics for the three boost PFC circuits,

Discontinuous Conduction Mode (DCM), Transition Mode (TM) and CCM, are the same. The differences relate to

whether or not the inductor current is allowed to go to zero for part of the PWM cycle (DCM) and whether the

PFC frequency is held constant or used as a control variable (TM)

L_PFC

D₁

V_BLK

V_AC

R_TOP

C_BLK

30 Mꢀ

BR₁

Q₁

VBULK

C_IN

R_CS(pfc)

R_BOT

73.3 kꢀ

V_CS(pfc)

Figure 34. Basic PFC Schematic

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8.2.2.22 PFC Stage Output Current Calculation

The first step is to determine the maximum load current on the PFC stage, allowing for an overload to 110 % of

maximum load power.

110% 2₁₇₆

1.1 × 300 9

+

=

= 0.9 #

176(LB? )

8_{$.-(IEJ )}

370 8

(39)

8.2.2.23 Line Current Calculation

Next determine the maximum RMS input-line current, allowing for an overload to 110% of maximum load power.

110% 2₁₇₆

1.1 × 300 9

0.9 × 85 8

+

=

;

)

=

= 4.31 #

:

.+0'(4/5 I=T

ß 8

#%(IEJ )

(40)

(41)

The peak line current is:

= ¾2 +_{.+0'(4/5 I=T )}= ¾2 × 4.07 # = 6.1 #

+

:

;

:

;

.+0'(2'#- I=T )

The average line current is given by:

2 +_{.+0'(2'#- I=T}

2 × 6.1 #

:

;

)

+

=

;

)

=

= 3.88 #

:

.+0'(#8) I=T

è

(42)

8.2.2.24 Bridge Rectifier

A typical bridge rectifier has a forward voltage drop V_{F_BR}of 0.95 V. The power loss in the bridge rectifier can be

calculated from:

2_$4= 2 8

+

= 2 × 0.95 8 × 3.88 # = 7.37 9

;

)

:

(($4) .+0'(#8) I=T

(43)

The bridge rectifier must be rated to carry the full-line current (I_{LINE(avg_max)}). The voltage rating of the bridge

should be at least 600 V. The bridge rectifier also carries the full inrush current as the bulk capacitor (C_BLK

charges when the line is connected. The amplitude and duration of this current is difficult to determine in

advance because it depends on many unknown parameters.

)

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8.2.2.25 PFC Boost Inductor

The boost inductor is usually chosen so that the peak-to-peak amplitude of the switching frequency ripple

current, I_HFR(pfc), is between 20% and 40% of the average current at peak of line. This design example uses

I_{HFR_PFC}= 30%. Numerically this is, (from Equation 41)

+

= 0.30 +_{.+0'(2'#- I=T}= 0.30 × 6.1 # = 1.83 #

: ;

)

*(4(LB? )

(44)

The minimum boost inductor value is calculated from a worst case duty cycle of 50%.

:

;

:

;

8_$.-& 1 F &

385 8 × 0.5 × 1 F 0.5

.

R

=

= 536 µ* 550 µ*

2(%

B

+

98 G*V × 1.83 #

2(% *(4_2(%

(45)

(46)

The boost inductor must be able to support a maximum current of:

+

1.83 #

*(4(LB? )

+

= +_{.+0'(LA=G (I=T ))}

+

= 6.1 # +

= 7.0#

.(LA=G )

2

The boost inductor specifications are:

•

L_PFC= 550 µH

Current = 7 A

8.2.2.26 PFC Input Capacitor

The purpose of the input capacitor is to provide a local, low-impedance source for the high-frequency ripple

currents which flow in the PFC inductor. The allowed voltage ripple on C_INis ΔV_IN.

ꢀV = 5% ¾2 8

= 5% × ¾2 × 85 8 = 6.0 8

+0

#%(IEJ )

(47)

(48)

+

1.83 #

8 × 98 G*V × 6.0 8

*(4(LB? )

%

+0

=

= 390 J( 470 J(

8 B_2(%ꢀV

+0

An X2 film capacitor is normally chosen for this application.

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8.2.2.27 PFC Stage MOSFET

The main specifications for the PFC stage MOSFET are:

•

B_VDSS, Drain Source Breakdown Voltage, ≥ 650 V

R_DS(on), On State Drain Source Resistance, 460 mΩ (125 °C)

C_OSS, Output Capacitance, 87 pF

t_r, device rise time, 30 ns

t_fdevice fall time, 34 ns

The losses in the device are calculated below. These calculations are approximations because the losses are

dependent on parameters which are not well controlled. For example the R_DS(on)of a MOSFET can vary by a

factor of 2 from 25°C to 125°C. Therefore several iterations may be needed to choose an optimum device for an

application different to the one discussed.

The conduction losses are estimated by:

2_{176(I=T )}

16 28

¾

2_{31(?KJ@ )}= (

^{#%(IEJ )})²4_&5(KJ)

¨

2 F

3è8

28

¾

$.-

#%(IEJ )

(49)

Numerically:

300 9

16 2 × 85 8

¾

¨

2 F

2_{31(?KJ@ )}= (

)²× 0.46 À = 4.21 9

3è × 385 8

2 × 85 8

¾

(50)

(51)

The switching losses in the MOSFET are estimated by:

1

2_31(OS)

=

B

_2(%(8 + )

_{$.- .+0'(4/5(I=T ))}kP_N+ P_Bo + %₁₅₅8²

$.-

2

Numerically:

2_31(OS)

1

2

:

;

=

₂× 98 G*V × 385 8 × 4.31 # × 30 JO + 34 JO + 87 L( × 385 8 = 5.84 9

(52)

(53)

2₃₁= 2_{31(?KJ@ )}+ 2_31(OS)= 4.21 9 + 5.84 9 = 10.05 9

8.2.2.28 PFC Boost Diode

Reverse recovery losses can be significant in a CCM boost converter so a silicon carbide diode is chosen here

because it has no reverse recovery charge, Q_RR, and therefore zero reverse recovery losses. The disadvantage

is that the cost is higher than that of Silicon ultra fast diodes. The losses are estimated as follows:

2_&1= 8 +

= 1.5 8 × 0.9 # = 1.35 9

B 176

(54)

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8.2.2.29 Bulk Capacitor

The value of the bulk capacitor is determined by three factors.

1. To ensure loop stability, the capacitance must be between 0.5 μF W^-1and 2.4 μF W^-1(see PFC Inductor and

Bulk Capacitor Recommendations). For this 300-W application a bulk capacitance in the range 150 μF to 720

μF is allowed.

2. It must be large enough to provide the required hold-up time.

3. It must be large enough to keep the ripple at twice line frequency within the required limits.

The UCC29950 continues to run the LLC stage until the voltage at the VBULK pin has fallen below V_{BULK(llc_stop)}

(0.49 V). This corresponds to a V_BLKof 200 V if the specified values for R_BOTand R_TOPare used. From

Equation 55 it can be see that the LLC stage will not have enough gain to maintain V_OUTwith such a low input

voltage. The minimum voltage at which the LLC stage regulates is determined from Equation 55 which is a

rearrangement of Equation 10. M_G(max)is found from Figure 31 which gives a maximum gain of the LLC stage of

1.33.

2 8₁₇₆

2 × 24 8

8

= 0

= 8 ×

= 288 8 300 8

+0(IEJ )

/

)(I=T )

1.33

(55)

(56)

The value of the capacitor is then given by:

2 2₁₇₆P_*

2 × 300 9 × 20 IO

%

$.-

R

=

= 255 µ( 270 µ(

8_$²_{.-(IEJ )}F 8_$²_.-

370²F 300²

*7

270 µF for 300 W is equal to 0.9 µF W^-1which lies within the allowed range for loop stability.

The peak-to-peak ripple voltage at twice line frequency on C_BLKis calculated as follows:

+

0.9 #

176(LB? )

8_{$.-(NELLHA )}

=

= 11.3 8

è 2 B

%

è × 2 × 47 *V × 270 µ(

.+0'(IEJ ) $.-

(57)

The result of this calculation, 11.3 V, is significantly better than the specification, 30 V. This is because the size

of the bulk capacitor is determined by the hold-up time rather than by the peak-to-peak line ripple specification.

The ripple current flowing in the bulk capacitor depends on the duty cycle which varies over the line cycle and

also as a function of the RMS value of the line voltage. This makes a precise calculation difficult however

Equation 58 gives a good approximation.

&

0.5

¨

+

%

= +_{176(LB? )}

N 0.9 # ×

N 0.9 #

$.- _4

1 F &

1 F 0.5

(58)

8.2.2.30 PFC Stage Current Sense Resistor

The current sense resistor is selected so that:

ß

4_{%5(LB? )}= V_{PFCCS (cav _max )}

8

#%(min )

2 125% 2

¾

176

(59)

(60)

Numerically this is:

4_{%5(LB? )}= 225 mV × 85 V

90%

= 33 IÀ

2 125% 2

¾

176

55

UCC29950

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

www.ti.com.cn

8.2.3 Application Curves

0.3

20

0

100

Gain

Phase

90 V

115 V

230 VTHD (%)

0.25

0.2

50

0

0.15

0.1

-20

-40

0.05

0

-50

0

50

100

150

200

250

300

1

2

3

4

5 6 7 8 10

20 30 40 50 70 100

Input Power (W)

Frequency (Hz)

D001

D00182

Figure 35. Typical THD vs. Input Power

Figure 36. PFC Loop Gain/Phase at 300 W, 115 V

20

100

Gain

Phase

0

-20

-40

50

0

-50

1

2

3

4

5 6 7 8 10

20 30 40 50 70 100

Frequency (Hz)

Figure 38.

D00281

Figure 37. PFC Loop Gain/Phase at 300 W, 230 V

Figure 39. Line Current 115 V

Figure 40. Line Current 230 V

56

UCC29950

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ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

Figure 41. LLC Stage Switching

(C1: VSQ, C2: GD1, C3: GD2 See Figure 33)

Figure 42. PFC Stage Switching (C1: V_DS, C2: PFC_GD See

Figure 34)

8.3 Do's and Don'ts

Don’t probe the SUFG pin unless absolutely necessary. A normal X10 Oscilloscope probe can significantly load

the very high output impedance of this pin .

Pay careful attention to grounding and to the routing of the sensing signals at PFC_CS, LLC_CS, VBULK, AC1

and AC2 pins.

The UCC29950 uses low value PFC current sense resistors, 38 mΩ in the example above. Careful attention to

layout is needed to avoid significant errors in the PFC current and power limit points. Use Kelvin connections to

the resistors.

57

UCC29950

ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

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9 Power Supply Recommendations

The UCC29950 should be operated from a VCC rail which is within the limits given in the VCC Bias Supply

section of the Electrical Characteristics table. To avoid the possibility that the device might stop switching, VCC

must not be allowed to fall into the UVLO range. In order to minimize power dissipation in the device, VCC

should not be unnecessarily high. Keeping VCC at 12 V is a good compromise between these competing

constraints. The gate drive outputs from the UCC29950 deliver large current pulses into their loads. This

indicates the need for a low ESR decoupling capacitor to be connected as directly as possible between the VCC

and PGND terminals. Ceramic capacitors with a stable dielectric characteristic over temperature, such as X7R,

are recommended. Avoid capacitors which have a large drop in capacitance with applied DC voltage bias and

use a part that has a low voltage co-efficient of capacitance. The recommended decoupling capacitance is 10

µF, X7R, with at least a 25-V rating.

Operation in Self Bias Mode requires an additional, larger, energy storage capacitor. The value required depends

on the details of the application but typically this part is between 100 µF and 300 µF. This energy storage

capacitor does not require low ESR and it does not need to be placed close to the UCC29950. A 25-V rated

aluminum electrolytic capacitor is a good choice.

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UCC29950

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ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

10 Layout

10.1 Layout Guidelines

In order to increase the reliability and robustness of the design, it is recommended that the following layout

guidelines be met.

10.1.1 GND Pin

•

This pin is the power ground connection and should be used as the return connection for the driver pins

PFC_GD, GD1 and GD2.

•

GND and AGND must be connected at a star point close to the pins on the controller

If possible use a ground plane to minimize noise pickup.

10.1.2 GD1, GD2 Pins

•

The GD1 and GD2 gate drive pins can be used to directly drive the primary winding of a gate-drive

transformer or a high voltage gate driver device. The tracks connected to these pins carry high dv/dt signals.

Minimize noise pickup by routing them as far away as possible from tracks connected to the device inputs,

AC1, AC2, VBULK, FB, PFC_CS and LLC_CS.

10.1.3 VCC Pin

•

The VCC pin must be decoupled to GND and AGND by two 10-µF 1206 ceramic capacitors placed close to

the pins. In addition it is recommended that an additional 0.1-µF ceramic capacitor 0603 be placed in parallel

between the VCC and AGND pin.

10.1.4 SUFG Pin

•

The SUFG is a high-impedance pin and can only be connected to the gate of the external depletion mode

MOSFET when the external high-voltage start-up feature is required. If the application does not require the

external high-voltage start-up circuit then the SUFG pin should be left open circuit.

10.1.5 SUFS Pin

•

The SUFS connects to the source of an external depletion mode MOSFET, if this feature in not required,

SUFS should be connected to the VCC rail.

10.1.6 AGND Pin

•

As with all PWM controllers, the effectiveness of the filter capacitors on the signal pins depends upon the

integrity of the ground return. Place all decoupling and filter capacitors as close as possible to the device pins

with short traces. The AGND pin is used as the return connection for the low-power signaling and sensitive

signal traces, AC1, AC2, VBULK, FB, MD_SEL/PS_ON and AC DET. It is also used as local decoupling

return for PFC_CS and LLC_CS. It is connected to the GND pin at a star point close to the device.

10.1.7 MD_SEL/PS_ON Pin

This pin is not especially sensitive but minimize coupling to tracks carrying high dv/dt signals.

•

10.1.8 VBULK Pin

•

The VBULK sense chain is connected to the high-voltage rail on the PFC stage. Typically the top resistive

element of the sense chain is split into two or three separate resistors to reduce the voltage stress on each

device and permit the use of standard low-cost resistors, such as 1206 sized SMT devices, in the sense

chain. Sufficient PCB spacing must be given between the high-voltage connections to the low voltage and

GND nets. The VBULK is a high-impedance connection and should be shielded by a ground plane from any

high-voltage switching nets. The copper area connecting the VBULK pin to the lower resistor/filter capacitor

and the last resistor in the high-side divider chain should be kept to a minimum to reduce parasitic

capacitance to any nearby switching nets. The bottom resistor in the divider network and filter capacitor must

be placed close to the VBULK pin.

59

UCC29950

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www.ti.com.cn

Layout Guidelines (continued)

10.1.9 AC1, AC2 Pins

•

The AC1 and AC2 are connected to the AC input lines by resistive divider chains. These divider chains are

normally formed using several discrete resistors in series. The AC1 and AC2 are high-impedance pins and

care must be taken to route the resistor divider components away from high voltage switching nets. Ideally

the connections should be shielded by ground planes. Sufficient PCB spacing must be given between the

high-voltage connections and any low-voltage nets. A filter capacitor, 470 pF, must be placed in close

proximity to the pins on the controller to decouple any high-frequency noise picked up on the AC1 and AC2

sense-chain connections.

10.1.10 LLC_CS

•

The LLC_CS pin should be decoupled by an external RC filter placed close to the pin. Suitable values are a

2.2-kΩ resistor and 0.1-µF ceramic capacitor.

10.1.11 FB

The FB signal is a low-power, high-impedance signal from the LLC regulation circuit. The PCB tracks from the

•

opto-coupler should be tracked to minimize the loop area by running the VÌ feed track and FB signal from the

opto-coupler in parallel. It is also recommended to provide screening for these traces with ground plane(s).

10.1.12 PFC_CS

•

The PFC_CS requires an external resistor, recommended value of 1 kΩ, between the current sensing resistor

and the PFC_CS pin to avoid overstressing the device during inrush. A small filter capacitor (1 nF) may be

useful to further reduce the noise level at this pin. These components should be placed close to PFC_CS pin.

•

The PFC_CS resistor is a low resistance part. Be careful that the connections to this resistor connect directly

to the part terminals to avoid adding extra parasitic resistance. Be especially careful of the connection to the

ground side of this resistor.

10.1.13 AC_DET

•

The AC_DET is a signal output. This is a low-voltage signal trace and must be kept clear of any high-voltage

switching nodes.

10.1.14 PFC_GD

•

The track connected to the PFC_GD pin carries high dv/dt signal. Minimize noise pickup by routing the trace

to this pin as far away as possible from tracks connected to the device inputs – AC1, AC2, VBULK, FB,

PFC_CS and LLC_CS

60

UCC29950

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ZHCSDI3A –SEPTEMBER 2014–REVISED MARCH 2015

10.2 Layout Example

PFC_CS

LLC_CS

GND

PFC_GD

AC_DET

GD1

Star

Point

GD2

VCC

SUFG

SUFS

AGND

PFC_CS

FB

PFC_CS

LLC_CS

AC1

MD_SEL/

PS_ON

AC2

VBULK

V_BLK

Figure 43.

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

1. 《采用数字辅助模拟器件实现峰值电流模式控制与平均电流模式控制相结合》；Seamus O’Driscoll，德州仪器

(TI) 和 David A. Grant，德州仪器；2014 IEEE 电力电子技术及应用国际会议暨展示会 (APEC 2014)，PP76

2. TI 应用手册《UCC29950 的 LLC 设计》（德州仪器 (TI) 文献编号：SLUA733）

11.2 商标

is a registered trademark of ~ECOVA, INC..

All other trademarks are the property of their respective owners.

11.3 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.4 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

12 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

61

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC29950DR

SOIC

D

16

2500

330.0

16.4

6.5

10.3

2.1

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC 16

SPQ

Length (mm) Width (mm) Height (mm)

340.5 336.1 32.0

UCC29950DR

D

2500

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jan-2022

TUBE

*All dimensions are nominal

Device

Package Name Package Type

SOIC

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

UCC29950D

D

16

40

507

8

3940

4.32

Pack Materials-Page 3

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC29950
厂家：	TEXAS INSTRUMENTS
描述：	高效 CCM PFC/LLC 组合控制器控制器功率因数校正
文件：	总69页 (文件大小：3524K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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