UCC35701QTR [TI]
Advanced Voltage Mode Pulse Width Modulator; 先进的电压模式脉冲宽度调制器
| 型号： | UCC35701QTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Advanced Voltage Mode Pulse Width Modulator |
| 文件： | 总24页 (文件大小：1110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UCC15701/2
UCC25701/2
UCC35701/2
available
Advanced Voltage Mode Pulse Width Modulator
FEATURES
DESCRIPTION
700kHz Operation
The UCC35701/UCC35702 family of pulse width modulators is intended for
isolated switching power supplies using primary side control. They can be
used for both off-line applications and DC/DC converter designs such as in
a distributed power system architecture or as a telecom power source.
Integrated Oscillator/ Voltage Feed
Forward Compensation
Accurate Duty Cycle Limit
Accurate Volt-second Clamp
Optocoupler Interface
The devices feature low startup current, allowing for efficient off-line start-
ing, yet have sufficient output drive to switch power MOSFETs in excess of
500kHz.
Voltage feed forward compensation is operational over a 5:1 input range
and provides fast and accurate response to input voltage changes over a
4:1 range. An accurate volt-second clamp and maximum duty cycle limit
are also featured.
Fault Counting Shutdown
Fault Latch off or Automatic Shutdown
Soft Stop Optimized for Synchronous
Rectification
Fault protection is provided by pulse by pulse current limiting as well as the
ability to latch off after a programmable number of repetitive faults has oc-
curred.
1A Peak Gate Drive Output
130mA Start-up Current
750mA Operating Current
Two UVLO options are offered. UCC35701 family has turn-on and turn-off
thresholds of 13V/9V and UCC35702 family has thresholds of 9.6V/8.8V.
The UCC35701/2 and the UCC25701/2 are offered in the 14 pin SOIC (D),
14 pin PDIP (N) or in 14 pin TSSOP (PW) packages. The UCC15701/2 is
offered in the 14 pin CDIP (J) package.
TYPICAL APPLICATION DIAGRAM
V
SUPPLY
IN
R1
R6
R2
R7
VFF
6
VDD
3
R3
7
RT
VREF
UCC35701
CT
V
C6
OUT
10 CT
C4
C1
R4
9
VSCLAMP
R8
C2
OUT
ILIM
4
2
R5
11 SYNC
14 SS
R10
CS
CF
RCS
1
COUNT
C3
R
F
12 VREF
PGND
GND
5
V RETURN
IN
R8
RGND
8
FB
13
R11
V
OUT
C5
R13
C7
R12
C6
R14
R15
UDG-98005-1
SLUS293C - JANUARY 2000 - REVISED JUNE 2005
UCC15701/2
UCC25701/2
UCC35701/2
ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
Supply voltage (Supply current limited to 20mA) . . . . . . . . 15V
Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Input pins ( ILIM,VFF,RT,CT,VSCLAMP,SYNC,SS, FB) . . . 6V
Output Current (OUT) DC. . . . . . . . . . . . . . . . . . . . . +/–180mA
Output Current (OUT) Pulse (0.5ms) . . . . . . . . . . . . . . +/–1.2A
Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C
TA = TJ
UVLO
Option
13V / 9V
9.6V / 8.8V CDIP-14
SOIC-14
13V / 9V
Package Part Number
CDIP-14
UCC15701J
UCC15702J
UCC25701D
UCC25701N
–55°C to +125°C
PDIP-14
TSSOP-14 UCC25701PW
–40°C to +85°C
0°C to +70°C
SOIC-14
9.6V / 8.8V PDIP-14
UCC25702D
UCC25702N
TSSOP-14 UCC25702PW
Note: All voltages are with respect to GND. Currents are posi-
tive into the specified terminal. Consult Packaging Section of
the Databook for thermal limitations and considerations of
packages.
SOIC-14
PDIP-14
UCC35701D
UCC35701N
13V / 9V
TSSOP-14 UCC35701PW
SOIC-14
9.6V / 8.8V PDIP-14
UCC35702D
UCC35702N
CONNECTION DIAGRAMS
DIL-14, SOIC-14, TSSOP-14 (TOP VIEW)
N or J, D, PW PACKAGE
TSSOP-14 UCC35702PW
The D and PW packages are available taped and reeled. Add
TR suffix to the device type (e.g., UCC35701DTR).
COUNT
ILIM
14
13
12
11
10
9
SS
1
2
3
4
5
6
7
GND
VREF
SYNC
CT
VDD
OUT
PGND
VFF
VS CLAMP
FB
RT
8
ELECTRICAL CHARACTERISTICS:Unless otherwise specified, VDD = 11V, RT = 60.4k, CT = 330pF, CREF = CVDD
0.1mF, VFF = 2.0V, and no load on the outputs.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
UVLO Section
Start Threshold
(UCCX5701)
(UCCX5702)
(UCCX5701)
(UCCX5702)
(UCCX5701)
(UCCX5702)
12
8.8
8
13
9.6
9
14
10.4
10
V
V
V
V
V
V
Stop Threshold
Hysteresis
8.0
3
8.8
4
9.6
0.3
0.8
Supply Current
Start-up Current
(UCCX5701) VDD = 11V, VDD Comparator Off
(UCCX5702) VDD = 8V, VDD Comparator Off
VDD Comparator On
130
120
0.75
14.3
13.8
1.3
200
190
1.5
15
mA
mA
mA
V
IDD Active
VDD Clamp Voltage
(UCCX5701) IDD = 10mA
(UCCX5702) IDD = 10mA
(UCCX5701)
13.5
13
15
V
VDD Clamp – Start Threshold
V
(UCCX5702)
4.2
V
Voltage Reference
VREF
VDD = 10V to 13V, IVREF = 0mA to 2mA
VDD = 10V to 13V
4.9
5
20
2
5.1
50
V
Line Regulation
Load Regulation
Short Circuit Current
mV
mV
mA
IVREF = 0mA to 2mA
VREF = 0V, TJ = 25°C
20
2
UCC15701/2
UCC25701/2
UCC35701/2
ELECTRICAL CHARACTERISTICS:Unless otherwise specified, VDD = 11V, RT = 60.4k, CT = 330pF, CREF = CVDD
0.1mF, VFF = 2.0V, and no load on the outputs.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Line Sense
Vth High Line Comparator
Vth Low Line Comparator
Input Bias Current
Oscillator Section
Frequency
3.9
0.5
4
4.1
0.7
100
V
V
0.6
–100
nA
VFF = 0.8V to 3.2V
90
90
2
100
100
110
110
kHz
kHz
V
Frequency
VFF = 0.6V to 3.4V (Note 1)
SYNC VIH
SYNC VIL
0.8
10
V
SYNC Input Current
RT Voltage
VSYNC = 2.0V
VFF = 0.4V
3
mA
V
0.5
0.75
1.95
3.15
3.3
0.6
0.8
2.0
3.2
3.4
0.8
3.2
0
0.7
VFF = 0.8V
0.85
2.05
3.25
3.5
V
VFF = 2.0V
V
VFF = 3.2V
V
VFF = 3.6V
V
CT Peak Voltage
CT Valley Voltage
VFF = 0.8V (Note 1)
VFF = 3.2V (Note 1)
(Note 1)
V
V
V
Soft Start/Shutdown/Duty Cycle Control Section
ISS Charging Current
10
18
500
25
30
mA
mA
ISS Discharging Current
300
750
100
Saturation
VDD = 11V, IC Off
mV
Fault Counter Section
Threshold Voltage
Saturation Voltage
Count Charging Current
Current Limit Section
Input Bias Current
Current Limit Threshold
Shutdown Threshold
Pulse Width Modulator Section
FB Pin Input Impedance
Minimum Duty Cycle
Maximum Duty Cycle
PWM Gain
VFF = 0.8V to 3.2V
VFF = 0.8V to 3.2V
3.8
10
4
4.2
100
30
V
mV
mA
18
–100
180
0
100
220
700
nA
mV
mV
200
600
500
VFB = 3V
30
50
100
0
kW
%
VFB <= 1V
VFB >= 4.5V, VSCLAMP >= 2.0V
VFF = 0.8V
95
35
99
50
100
70
%
%/V
Volt Second Clamp Section
Maximum Duty Cycle
Minimum Duty Cycle
Output Section
VFF = 0.8V, VSCLAMP = 0.6V
VFF = 3.2V, VSCLAMP = 0.6V
69
17
74
19
79
21
%
%
VOH
IOUT = –100mA, (VDD – VOUT
IOUT = 100mA
)
0.4
0.4
20
1
V
V
VOL
1
Rise Time
CLOAD = 1000pF
100
100
ns
ns
Fall Time
CLOAD = 1000pF
20
Note 1: Ensured by design. Not 100% tested in production.
3
UCC15701/2
UCC25701/2
UCC35701/2
DETAILED BLOCK DIAGRAM
2*I
RT
11 SYNC
S
VFF
RT
6
7
3mA
R
Q
D
PEAK
I
RT
3
VDD
CT 10
PWM
0.2V
0.7V
S
Q
4
5
OUT
VALLEY
FB
8
9
R
D
1.5R
R
PGND
VS CLAMP
4V
HIGH LINE
LOW LINE
V
13/9V (35701)
9.6/8.8V (35702)
RUN
REF
I
0.6V
4.5V
14
SS
SSDONE
25*I
CURRENT FAULT
CURRENT LIMIT
0.6V
0.2V
R
Q
0.2V
VDD
ILIM
2
V
REF
S
D
FAULT
LATCH
I
D
R
Q
R
S
Q
5.0V
REF
PWM
SSDONE
12 VREF
D
COUNT
1
4V
13
GND
SHUTDOWN
LATCH
UDG-98004
PIN DESCRIPTIONS
VDD: Power supply pin. A shunt regulator limits supply RT: The voltage on this pin mirrors VFF over a 0.8V to
voltage to 14V typical at 10mA shunt current.
3.2V range. A resistor to ground sets the ramp capacitor
charge current. The resistor value should be between
20k and 200k.
PGND: Power Ground. Ground return for output driver
and currents.
CT: A capacitor to ground provides the oscillator/
feedforward sawtooth waveform. Charge current is 2 ·
IRT, resulting in a CT slope proportional to the input volt-
GND: Analog Ground. Ground return for all other circuits.
This pin must be connected directly to PGND on the
board.
age. The ramp voltage range is GND to VRT
.
OUT: Gate drive output. Output resistance is 10W maxi-
mum.
Period and oscillator frequency is given by:
VRT ·CT
T =
F »
+ tDIS CH » 0.5 ·RT ·CT
VFF: Voltage feedforward pin. This pin connects to the
power supply input voltage through a resistive divider
and provides feedforward compensation over a 0.8V to
3.2V range. A voltage greater than 4.0V or less than
0.6V on this pin initiates a soft stop cycle.
2 ·IRT
2
RT ·CT
4
UCC15701/2
UCC25701/2
UCC35701/2
PIN DESCRIPTIONS (cont.)
VSCLAMP: Voltage at this pin is compared to the CT source. While the soft start capacitor is charging, and
voltage, providing a constant volt-second limit. The com-
parator output terminates the PWM pulse when the ramp
voltage exceeds VSCLAMP. The maximum on time is
given by:
while VSS < (0.4 VFB), the duty cycle, and therefore the
output voltage of the converter is determined by the soft
start circuitry.
At High Line or Low Line fault conditions, the soft start
capacitor is discharged with a controlled discharge cur-
rent of about 500mA. During the discharge time, the duty
cycle of the converter is gradually decreased to zero.
This soft stop feature allows the synchronous rectifiers to
gradually discharge the output LC filter. An abrupt shut
off can cause the LC filter to oscillate, producing unpre-
dictable output voltage levels.
VVS CLAMP ·CT
tON
=
2 ·IRT
The maximum duty cycle limit is given by:
tON VVS CLAMP
=
DMAX
=
T
VRT
FB: Input to the PWM comparator. This pin is intended
to be driven with an optocoupler circuit. Input impedance
is 50kW Typical modulation range is 1.6V to 3.6V.
All other fault conditions (UVLO, VREF Low, Over Cur-
rent (0.6V on ILIM) or COUNT) will cause an immediate
stop of the converter. Furthermore, both the Over Current
fault and the COUNT fault will be internally latched until
VDD drops below 9V or VFF goes below the 600mV
threshold at the input of the Low Line comparator.
SYNC: Level sensitive oscillator sync input. A high level
forces the gate drive output low and resets the ramp ca-
pacitor. On-time starts at the negative edge the pulse.
There is a 3mA pull down current on the pin, allowing it to
be disconnected when not used.
After all fault conditions are cleared and the soft start ca-
pacitor is discharged below 200 mV, a soft start cycle will
be initiated to restart the converter.
VREF: 5.0V trimmed reference with 2% variation over
line, load and temperature. Bypass with a minimum of
0.1mF to ground.
ILIM: Provides a pulse by pulse current limit by terminat-
ing the PWM pulse when the input is above 200mV. An
input over 600mV initiates a latched soft stop cycle.
SS: Soft Start pin. A capacitor is connected between this
pin and ground to set the start up time of the converter.
After power up (VDD>13V AND VREF>4.5V), or after a
fault condition has been cleared, the soft start capacitor
is charged to VREF by a nominal 18mA internal current
COUNT: Capacitor to ground integrates current pulses
generated when ILIM exceeds 200mV. A resistor to
ground sets the discharge time constant. A voltage over
4V will initiate a latched soft stop cycle.
APPLICATION INFORMATION
(Note: Refer to the Typical Application Diagram on the first
page of this datasheet for external component names.) All the
equations given below should be considered as first order ap-
proximations with final values determined empirically for a spe-
cific application.
The circuit will start at this point. IVDD will increase from
the start up value of 130mA to the run value of 750mA.
The capacitor on SS is charged with a 18mA current.
When the voltage on SS is greater than 0.8V, output
pulses can begin, and supply current will increase to a
level determined by the MOSFET gate charge require-
ments to IVDD ~ 1mA + QT · fs. When the output is ac-
tive, the bootstrap winding should be sourcing the supply
current. If VDD falls below the UVLO stop threshold, the
controller will enter a shutdown sequence and turn the
controller off, returning the start sequence to the initial
condition.
Power Sequencing
VDD is normally connected through a high impedance
(R6) to the input line, with an additional path (R7) to a
low voltage bootstrap winding on the power transformer.
VFF is connected through a divider (R1/R2) to the input
line.
For circuit activation, all of the following conditions are
required:
VDD Clamp
An internal shunt regulator clamps VDD so the voltage
does not exceed a nominal value of 14V. If the regulator
is active, supply current must be limited to less than
20mA.
1. VFF between 0.6V and 4.0V (operational input voltage
range).
2. VDD has been under the UVLO stop threshold to reset
the shutdown latch.
3. VDD is over the UVLO start threshold.
5
UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
Output Inhibit
VFF is intended to operate accurately over a 4:1 range
between 0.8V and 3.2V. Voltages at VFF below 0.6V or
above 4.0V will initiate a soft stop cycle and a chip restart
when the under/over voltage condition is removed.
During normal operation, OUT is driven high at the start
of a clock period and is driven low by voltages on CT, FB
or VSCLAMP.
Volt-Second Clamp
The following conditions cause the output to be immedi-
ately driven low until a clock period starts where none of A constant volt-second clamp is formed by comparing the
the conditions are true:
timing capacitor ramp voltage to a fixed voltage derived
from the reference. Resistors R4 and R5 set the
volt-second limit. For a volt-second product defined as
VIN tON(max), the required voltage at VSCLAMP is:
1. ILIM > 0.2V
2. FB or SS is less than 0.8V
Current Limiting
æ
ç
è
ö
÷
ø
R2
· VIN ·tON max
(
)
.
(
)
ILIM is monitored by two internal comparators. The cur-
rent limit comparator threshold is 0.2V. If the current limit
comparator is triggered, OUT is immediately driven low
and held low for the remainder of the clock cycle, provid-
ing pulse-by-pulse over-current control for excessive
loads. This comparator also causes CF to be charged for
the remainder of the clock cycle.
R1+ R2
RT ·CT
The duty cycle limit is then:
VVS CLAMP
V
VS CLAMP , or
VVFF
.
æ
ç
ö
÷
R2
R1+ R2
VIN
·
è
ø
If repetitive cycles are terminated by the current limit
comparator causing COUNT to rise above 4V, the shut-
down latch is set. The COUNT integration delay feature
will be bypassed by the shutdown comparator which has
a 0.6V threshold. The shutdown comparator immediately
sets the shutdown latch. RF in parallel with CF resets the
COUNT integrator following transient faults. RF must be
greater than (4 · R4) · (1 – DMAX).
The maximum duty cycle is realized when the
feedforward voltage is set at the low end of the operating
range (VFF = 0.8V).
The absolute maximum duty cycle is:
VVS CLAMP VREF
=
R5
DMAX
=
·
0.8
0.8 R4 + R5
Frequency Set
Latched Shutdown
The frequency is set by a resistor from RT to ground and
a capacitor from CT to ground. The frequency is approxi-
If ILIM rises above 0.6V, or COUNT rises to 4V, the shut-
down latch will be set. This will force OUT low, discharge
SS and COUNT, and reduce IDD to approximately
750mA. When, and if, VDD falls below the UVLO stop
threshold, the shutdown latch will reset and IDD will fall
to 130mA, allowing the circuit to restart. If VDD remains
above the UVLO stop threshold (within the UVLO band),
an alternate restart will occur if VFF is momentarily re-
duced below 1V. External shutdown commands from any
source may be added into either the COUNT or ILIM
pins.
2
mately: F =
(RT ·CT
)
External synchronization is via the SYNC pin. The pin
has a 1.5V threshold , making it compatible with 5V and
3.3V CMOS logic. The input is level sensitive, with a high
input forcing the oscillator ramp low and the output low.
An active pull down on the SYNC pin allows it to be un-
connected when not used.
Gate Drive Output
Voltage Feedforward
The UCC35701/2 is capable of a 1A peak output current.
Bypass with at least 0.1mF directly to PGND. The capac-
itor must have a low equivalent series resistance and in-
ductance. The connection from OUT to the power
MOSFET gate should have a 2W or greater damping re-
sistor and the distance between chip and MOSFET
should be minimized. A low impedance path must be es-
tablished between the MOSFET source (or ground side
of the current sense resistor), the VDD capacitor and
PGND. PGND should then be connected by a single path
(shown as RGND) to GND.
The voltage slope on CT is proportional to line voltage
over a 4:1 range and equals 2·VFF (RT·CT). The capac-
itor charging current is set by the voltage across RT.
V(RT) tracks VFF over a range of 0.8V to 3.2V. A chang-
ing line voltage will immediately change the slope of
V(CT), changing the pulse width in a proportional manner
without using the feedback loop, providing excellent dy-
namic line regulation.
6
UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
Transitioning From UCC3570 To UCC35701
UCC35701/2 is pin to pin compatible to UCC3570 but is
not a direct drop-in replacement for UCC3570 sockets.
The changes required to the power supply printed circuit
board of for existing UCC3570 designs are minimal. For
conversion, only one extra resistor to set the volt-second
clamp needs to be added to the existing PC board lay-
outs. In addition, some component values will need to
be changed due to the functionality change in of four of
the IC pins.
The UCC35701/2 is an advanced version of the popular,
low power UCC3570 PWM. Significant improvements
were made to the IC’s oscillator and PWM control sec-
tions to enhance overall system performance. All of the
key attributes and functional blocks of the UCC3570
were maintained in the UCC35701/2. A typical applica-
tion using UCC3570 and UCC35701/2 is shown in Fig. 6
for comparison.
The Pinout Changes from UCC3570 are as follows.
The advantages of the UCC35701/2 over the UCC3570
are as follows.
Pin 7 was changed from SLOPE to RT (for timing
resistor)
Improved oscillator and PWM control section.
Pin 8 was changed from ISET to VSCLAMP (requiring
one additional resistor from pin 9 to VREF)
A precise maximum volt-second clamp circuit. The
UCC3570 has a dual time base between oscillator and
feedforward circuitry. The integated time base in
UCC35701/2 improves the duty cycle clamp accuracy,
providing better than ± 5% accurate volt- second
clamp over full temperature range.
Pin 10 was changed from RAMP to CT (single timing
capacitor)
Pin 11 was changed from FREQ to SYNC (input only)
Additional Information
Separately programmable oscillator timing resistor
(RT) and capacitor (CT) circuits provide a higher
degree of versatility.
Please refer to the following two Unitrode application
topics on UCC3570 for additional information.
An independent SYNC input pin for simple external
synchronization.
[1] Application Note U-150, Applying the UCC3570 Volt-
age-Mode PWM Controller to Both Off-line and DC/DC
Converter Designs by Robert A. Mammano
A smaller value filter capacitor (0.1mF) can be used
with the enhanced reference voltage.
[2] Design Note DN-62, Switching Power Supply Topol-
ogy, Voltage Mode vs. Current Mode by Robert
Mammano
TYPICAL WAVEFORMS
FEEDBK
VS CLAMP
CT
SOFTST
SOFT START
HIGH DC
LOW DC
ZERO DC
SOFT STOP
V-S CLAMP
UDG-98207
Figure 1. Timing diagram for PWM action with forward, soft start and volt-second clamp.
7
UCC15701/2
UCC25701/2
UCC35701/2
TYPICAL WAVEFORMS (cont.)
VFF
CT
SYNC
UDG-98208
Figure 2. Timing diagram for oscillator waveforms showing feedforward action and synchronization.
TYPICAL CHARACTERISTIC CURVES
1.03
1000
VFF=3.2
1.02
1.01
VFF=0.8
100
1.00
0.99
0.98
0.97
100pF
150pF
220pF
330pF
470pF
10
20
60
100
140
180
220
-55
-35
-15
5
25
45
65
85
105
125
RT [K
]
TEMPERATURE [°C]
Figure 3. Oscillator frequency vs. RT and CT.
Figure 5. Normalized maximum duty cycle vs.
temperature.
1.02
CT=330pF
FOSC = 100kHz
1.01
VFF=0.8
1
0.99
0.98
VFF=3.2
-55
-35
-15
5
25
45
65
85
105
125
TEMPERATURE [°C]
Figure 4. Oscillator frequency vs. temperature.
8
UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
V
IN+
R1
R5
UCC3570
R2
R6
6
7
VFF
VDD
3
V
OUT
R3
C
C4
SLOPE
C1
R8
R9
R
10 RAMP
OUT
ILIM
4
2
R4
C
9
IS ET
T
C2
11 FREQ
R
R
T
SNS
C
SS
14 SS
PGND
5
C
F
1
COUNT
R
F
R
GND
C3
12 VREF
R7
GND 13
8
FB
R11
V
OUT
C5
R13
C6
R12
R14
C7
R15
V
IN+
UCC35701
R1
R5
R2
R6
6
7
VFF
RT
VDD
3
V
OUT
R3
C
C4
C1
R8
R9
T
10 CT
OUT
ILIM
4
2
R4
9
VS CLAMP
C2
R
NEW
SS
11 SYNC
14 SS
R
SNS
C
PGND
5
C
F
1
COUNT
R
F
R
GND
C3
12 VREF
R7
GND 13
8
FB
R11
V
OUT
C5
R13
C6
R12
R14
C7
R15
UDG-98210
Figure 6. Single-ended forward circuit comparison between UCC3570 and UCC37501.
9
UCC15701/2
UCC25701/2
UCC35701/2
REVISION HISTORY
DATE
02/16/05
6/16/05
REVISION
SLUS293B
SLUS293C
REASON
Add FB to abs max table. Created revision history table.
Updated block diagram and the SS pin description.
10
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
UCC15701J
UCC15701L
UCC25701D
OBSOLETE
OBSOLETE
ACTIVE
CDIP
LCCC
SOIC
J
FK
D
14
20
14
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
-40 to 85
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UCC25701D
UCC25701D
UCC25701D
UCC25701D
UCC25701N
UCC25701N
25701
UCC25701DG4
UCC25701DTR
UCC25701DTRG4
UCC25701N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2500
2500
25
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
PDIP
N
Green (RoHS
& no Sb/Br)
UCC25701NG4
UCC25701PW
PDIP
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
90
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
UCC25701PWG4
UCC25701PWTR
UCC25701PWTRG4
UCC25702D
90
Green (RoHS
& no Sb/Br)
25701
2000
2000
50
Green (RoHS
& no Sb/Br)
25701
Green (RoHS
& no Sb/Br)
25701
Green (RoHS
& no Sb/Br)
UCC25702D
UCC25702D
UCC25702D
UCC25702D
UCC25702N
UCC25702N
UCC25702DG4
UCC25702DTR
UCC25702DTRG4
UCC25702N
SOIC
D
50
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
PDIP
N
Green (RoHS
& no Sb/Br)
UCC25702NG4
PDIP
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
UCC25702PW
UCC25702PWG4
UCC25702PWTR
UCC25702PWTRG4
UCC35701D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
14
14
14
14
14
14
14
14
14
14
14
14
90
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
25702
Green (RoHS
& no Sb/Br)
25702
2000
2000
50
Green (RoHS
& no Sb/Br)
25702
Green (RoHS
& no Sb/Br)
25702
Green (RoHS
& no Sb/Br)
UCC35701D
UCC35701D
UCC35701D
UCC35701D
UCC35701N
UCC35701N
35701
UCC35701DG4
UCC35701DTR
UCC35701DTRG4
UCC35701N
SOIC
D
50
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
D
Green (RoHS
& no Sb/Br)
0 to 70
PDIP
N
Green (RoHS
& no Sb/Br)
0 to 70
UCC35701NG4
UCC35701PW
PDIP
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
TSSOP
TSSOP
PW
PW
90
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
UCC35701PWG4
90
Green (RoHS
& no Sb/Br)
0 to 70
35701
UCC35701Q
UCC35701QTR
UCC35702D
OBSOLETE
OBSOLETE
ACTIVE
UTR
UTR
D
20
20
14
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
SOIC
SOIC
PDIP
50
50
25
25
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
UCC35702D
UCC35702D
UCC35702N
UCC35702N
35702
UCC35702DG4
UCC35702N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
N
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-2-260C-1 YEAR
0 to 70
0 to 70
0 to 70
0 to 70
Green (RoHS
& no Sb/Br)
UCC35702NG4
UCC35702PW
PDIP
N
Green (RoHS
& no Sb/Br)
TSSOP
PW
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
UCC35702PWG4
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
35702
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC15701, UCC35701 :
Catalog: UCC35701
•
Military: UCC15701
•
NOTE: Qualified Version Definitions:
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC25701DTR
UCC25701PWTR
UCC25702DTR
UCC25702PWTR
UCC35701DTR
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
14
14
2500
2000
2500
2000
2500
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
16.4
6.5
6.9
6.5
6.9
6.5
9.0
5.6
9.0
5.6
9.0
2.1
1.6
2.1
1.6
2.1
8.0
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
TSSOP
SOIC
PW
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC25701DTR
UCC25701PWTR
UCC25702DTR
UCC25702PWTR
UCC35701DTR
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
14
14
2500
2000
2500
2000
2500
333.2
367.0
333.2
367.0
333.2
345.9
367.0
345.9
367.0
345.9
28.6
35.0
28.6
35.0
28.6
TSSOP
SOIC
PW
D
Pack Materials-Page 2
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