UCC35705DR [TI]
0.02A SWITCHING CONTROLLER, 4000kHz SWITCHING FREQ-MAX, PDSO8, GREEN, PLASTIC, MS-012AA, SOP-8;
| 型号： | UCC35705DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 0.02A SWITCHING CONTROLLER, 4000kHz SWITCHING FREQ-MAX, PDSO8, GREEN, PLASTIC, MS-012AA, SOP-8 开关 光电二极管 |
| 文件： | 总13页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢇ
ꢉꢊ ꢋꢉ ꢌꢍꢎꢏ ꢏꢐ ꢑꢒ ꢓꢔꢕꢋ ꢏ ꢖ ꢒꢐ ꢏ ꢎꢀꢓ ꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
D, OR P PACKAGE
(TOP VIEW)
D
D
Greater Than 4-MHz Operation
Integrated Oscillator / Voltage Feed Forward
Compensation
ILIM
FB
VDD
OUT
GND
RC
1
2
3
4
8
7
6
5
D
D
D
D
D
D
D
>4:1 Input Voltage Range
DGK PACKAGE
(TOP VIEW)
VFF
25-ns Current Limit Delay
DISCH
Programmable Maximum Duty Cycle Clamp
Optocoupler Interface
1
2
3
4
8
7
6
5
ILIM
VDD
50-µA Start-Up Current
FB
OUT
GND
RC
4.2-mA Operating Current @ 1 MHz
VFF
Smallest Footprint of the 8-pin MSOP
Package Minimizes Board Area and Height
DISCH
description
The UCC35705 and UCC35706 devices are 8-pin voltage mode primary side controllers with fast over-current
protection. These devices are used as core high-speed building blocks in high performance isolated and non-isolated
power converters.
UCC35705/UCC35706 devices feature a high speed oscillator with integrated feed-forward compensation for
improved converter performance. A typical current sense to output delay time of 25 ns provides fast response to
overload conditions. The IC also provides an accurate programmable maximum duty cycle clamp for increased
protection which can also be disabled for the oscillator to run at maximum possible duty cycle.
Two UVLO options are offered. The UCC35705 with lower turn-on voltage is intended for dc-to-dc converters while
the higher turn-on voltage and the wider UVLO range of the UCC35706 is better suited for offline applications.
The UCC35705/UCC35706 family is offered in 8-pin MSOP (DGK), SOIC (D) and PDIP (P) packages.
typical application schematic
+
+
V
OUT
–
V
IN
–
VDD
FB
8
2
4
DISCH
TPS2829
5
3
RC
OUT
7
1
VFF
FET DRIVER
SOFT
START
CIRCUIT
6
GND
ILIM
UCC35705/6
MODE = 1
UDG-99181
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2001, Texas Instruments Incorporated
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1
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢃꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢃꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢇ
ꢉ ꢊꢋ ꢉꢌꢍ ꢎꢏꢏ ꢐ ꢑꢒꢓꢔꢕꢋ ꢏ ꢖꢒ ꢐꢏ ꢎ ꢀꢓꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Input voltage (VFF,RC,ILIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage (FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Input current (DISCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA
Output current (OUT) dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
J
Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Power
Supply Control Data Book (TI Literature Number SLUD003) for thermal limitations and considerations of packages.
‡
AVAILABLE OPTIONS
Packaged Devices
MSOP-8
T
A
= T
J
SOIC-8
PDIP-8
Small Outline
UVLO Option
†
Plastic Dip (P)
Small Outline (D)
†
(DGK)
8.8V/8V
12V/8V
8.8V/8V
12V/8V
UCC25705D
UCC25706D
UCC35705D
UCC35706D
UCC25705P
UCC25706P
UCC35705P
UCC35706P
UCC25705DGK
UCC25706DGK
UCC35705DGK
UCC35706DGK
–40°C to 85°C
0°C to 70°C
†
D (SOIC–8) and DGK (MSOP–8) packages are available taped and reeled. Add R suffix to device type (e.g.
UCC35705DR) to order quantities of 2500 devices per reel for SOIC-8 and 2000 devices per reel for the MSOP-8.
electrical characteristics, V
= 11 V, V = 30 V, R = 47 k, R
= 400 k, R = 14 k, C = 220 pF,
DD
IN
T
DISCH FF T
C
= 0.1 µF, and no load on the outputs, 0°C ≤ T ≤ 70°C for the UCC3570x and –40°C ≤ T ≤ 85°C
VDD
A A
for the UCC2570x, T = T , (unless otherwise specified)
A
J
UVLO section (UCCx5705)
PARAMETER
Start threshold
TEST CONDITIONS
MIN
8.0
7.4
0.3
TYP MAX UNITS
8.8
8.2
0.6
9.6
9.0
1.0
V
V
V
Stop threshold
Hysteresis
UVLO section (UCCx5706)
PARAMETER
Start threshold
TEST CONDITIONS
MIN
11.2
7.2
TYP MAX UNITS
12.0
8.0
12.8
8.8
V
V
V
Stop threshold
Hysteresis
3.5
4.0
4.5
supply current section
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
Start-up current
V
V
= UVLO start – 1 V, V
comparator off
30
90
µA
DD
DD
I
active
comparator on, oscillator running at 1 MHz
4.2
5.0
mA
DD
DD
2
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SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
electrical characteristics, V
= 11 V, V = 30 V, R = 47 k, R
= 400 k, R = 14 k, C = 220 pF,
DD
IN
T
DISCH FF T
C
= 0.1 µF, and no load on the outputs, 0°C ≤ T ≤ 70°C for the UCC3570x and –40°C ≤ T ≤ 85°C
VDD
A A
for the UCC2570x, T = T , (unless otherwise specified)
A
J
line sense section
PARAMETER
TEST CONDITIONS
MIN
0.95
–100
TYP MAX UNITS
Low line comparator threshold
Input bias current (VFF)
1.00
1.05
100
V
nA
oscillator section
PARAMETER
TEST CONDITIONS
VFF = 1.2 V to 4.8 V
MIN
TYP MAX UNITS
Frequency
0.9
1.0
1.2
4.8
0
1.1
MHz
V
VFF = 1.2 V,
VFF = 4.8 V,
See Note 1
See Note 1
See Note 1
CT peak voltage
CT valley voltage
V
V
NOTE 1: Ensured by design. Not production tested.
current limit section
PARAMETER
Input bias current
TEST CONDITIONS
MIN
0.2
TYP MAX UNITS
–0.2
200
25
–1
220
35
µA
mV
ns
Current limit threshold
180
Propagation delay, ILIM to OUT
50 mV overdrive
pulse width modulator section
PARAMETER
FB input impedance
TEST CONDITIONS
MIN
TYP MAX UNITS
V
V
V
V
= 3 V
< 2 V
30
50
90
0
kΩ
%
FB
FB
FB
Minimum duty cycle
= V
DD
,
F
F
= 1 MHz
= 1 MHz
70
75
93
12
65
80
%
OSC
Maximum duty cycle
= 0 V,
%
DISCH
OSC
PWM gain
VFF = 2.5 V,
MODE = 1
%/V
ns
Propagation delay, PWM to OUT
120
output section
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNITS
VOH
I
I
= –5 mA,
V
DD
– output
0.3
0.15
10
0.6
0.4
25
V
V
OUT
VOL
= 5 mA
OUT
Rise time
Fall time
C
C
= 50 pF
= 50 pF
ns
ns
LOAD
LOAD
10
25
3
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢃꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢃꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢇ
ꢉ ꢊꢋ ꢉꢌꢍ ꢎꢏꢏ ꢐ ꢑꢒꢓꢔꢕꢋ ꢏ ꢖꢒ ꢐꢏ ꢎ ꢀꢓꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
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SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
pin descriptions
DISCH: A resistor to VIN sets the oscillator discharge current programming a maximum duty cycle. When grounded,
an internal comparator switches the oscillator to a quick discharge mode. A small 100-pF capacitor between DISCH
and GND may reduce oscillator jitter without impacting feed-forward performance. I
must be between 25 µA
DISCH
and 250 µA over the entire V range.
IN
FB: Input to the PWM comparator. This pin is intended to interface with an optocoupler. Input impedance is 50-kΩ
typical.
GND: Ground return pin.
ILIM: Provides a pulse-by-pulse current limit by terminating the PWM pulse when the input is above 200 mV. This
provides a high speed (25 ns typical) path to reset the PWM latch, allowing for a pulse-by-pulse current limit.
OUT: The output is intended to drive an external FET driver or other high impedance circuits, but is not intended to
directly drive a power MOSFET. This improves the controller’s noise immunity. The output resistance of the PWM
controller, typically 60 Ω pull-up and 30 Ω pull-down, will result in excessive rise and fall times if a power MOSFET
is directly driven at the speeds for which the UCC35705/6 is optimized.
RC: The oscillator can be configured to provide a maximum duty cycle clamp. In this mode the on–time is set by RT
and CT, while the off-time is set by RDISCH and CT. Since the voltage ramp on CT is proportional to VIN, feed-forward
action is obtained. Since the peak oscillator voltage is also proportional to VIN, constant frequency operation is
maintained over the full power supply input range. When the DISCH pin is grounded, the duty cycle clamp is disabled.
The RC pin then provides a low impedance path to ground CT during the off time.
VDD: Power supply pin. This pin should be bypassed with a 0.1-µF capacitor for proper operation. The undervoltage
lockout function of the UCC35705/6 allows for a low current startup mode and ensures that all circuits become active
in a known state. The UVLO thresholds on the UCC35705 are appropriate for a dc-to-dc converter application. The
wider UVLO hysteresis of the UCC35706 (typically 4 V) is optimized for a bootstrap startup mode from a high
impedance source.
VFF: The feed-forward pin provides the controller with a voltage proportional to the power supply input voltage. When
the oscillator is providing a duty cycle clamp, a current of 2 × I
RFF between VFF and GND then set VFF to:
is sourced from the VFF pin. A single resistor
DISCH
2 R
FF
ǒ
Ǔ
VFF [ VIN
2 R ) R
FF
DISCH
When the DISCH pin is grounded and the duty cycle clamp is not used, the internal current source is disabled and
a resistor divider from VIN is used to set VFF. In either case, when the voltage on VFF is less than 1.0 V, both the
output and oscillator are disabled.
4
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ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
pin descriptions (continued)
MODE
50 mV
–
DISCH
4
1.0 V
+
VDD
CLK
LOW LINE
S
Q
Q
PWM
LATCH
I
2 * I (MODE=1)
0 (MODE = 0)
–
RD
RD
RD
+
7
8
OUT
VDD
VFF
RC
3
5
–
Q
S
+
+
RD Q
UVLO
UCC35705 (8.8 V/8 V)
UCC35706 (12 V/8 V)
30 * I (MODE=1)
–
Ω
80 (MODE = 0)
100 mV
6
1
GND
ILIM
0.7 V
PWM
–
FB
2
200 mV
+
CURRENT LIMIT
Ω
30 k
+
Ω
20 k
1 pF
–
Figure 1. Block Diagram
FUNCTIONAL DESCRIPTION
oscillator and PWM
The oscillator can be programmed to provide a duty cycle clamp or be configured to run at the maximum possible
duty cycle.
The PWM latch is set during the oscillator discharge and is reset by the PWM comparator when the C waveform
T
is greater than the feedback voltage. The voltage at the FB pin is attenuated before it is applied to the PWM
comparator. The oscillator ramp is shifted by approximately 0.65-V at room temperature at the PWM comparator. The
offset has a temperature coefficient of approximately –2 mV/°C.
The ILIM comparator adds a pulse by pulse current limit by resetting the PWM latch when V
> 200 mV. The PWM
ILIM
latch is also reset by a low line condition (V <1.0 V).
FF
All reset conditions are dominant; asserting any output will force a zero duty cycle output.
oscillator with duty cycle clamp (MODE = 1)
The timing capacitor CT is charged from ground to VFF through RT. The discharge path is through an on-chip current
sink that has a value of 30 × I , where I is the current through the external resistor RDISCH. Since the
DISCH
DISCH
charge and discharge currents are both proportional to VIN, their ratio, and the maximum duty cycle remains constant
as VIN varies.
5
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢃꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢃꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢇ
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ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
FUNCTIONAL DESCRIPTION
V
IN
R
T
R
DISCH
RC
DISCH
5
4
VDD
C
T
I
DISCH
2 * I
DISCH
30 * I
VFF
DISCH
3
R
FF
Figure 2. Duty Cycle Clamp (MODE = 1)
The on-time is approximately:
+T R C
T
V
2 R
FF
FF
T
where T+
[
ON
T
V
R
IN
DISCH
The off-time is:
+T
C ǒR RDISCHǓ
T
T
T
OFF
30 ǒR * RDISCHǓ
T
The frequency is:
1
1
f + ǒ
Ǔ
T R C
R
T
T
DISCH
1 )
30 ǒR DISCHǓ
T*R
The maximum duty cycle is:
T
R
ON
DISCH
+ ǒ1 * Ǔ
Duty Cycle +
T
) T
30 R
T
ON
OFF
6
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢇ
ꢉꢊ ꢋꢉ ꢌꢍꢎꢏ ꢏꢐ ꢑꢒ ꢓꢔꢕꢋ ꢏ ꢖ ꢒꢐ ꢏ ꢎꢀꢓ ꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
FUNCTIONAL DESCRIPTION
component selection for oscillator with duty cycle clamp (MODE = 1)
For a power converter with the following specifications:
D
D
D
D
D
V
V
V
F
= 18 V
= 75 V
IN(min)
IN(max)
= 15 V
IN(shutdown)
= 1 MHz
OSC
D
= 0.78 at V
MAX
IN(min)
In this mode, the on-time is approximately:
D
D
T
= 780 ns
= 220 ns
18
ON(max)
OFF(min)
T
D
V
=
= 1.20 V
FF(min)
15
(1) Pick C = 220 pF.
T
(2) Calculate R .
T
V
T
Ǔ
ǒ
(
)
ON max
IN min
R +
T
V
C
Ǔ
ǒ
T
FF min
R = 51.1 kΩ
T
(3) R
DISCH
30 R
T
R
+
DISCH
V
ȡ
R C ȣ
FF(min)
ǒ Ǔ
T
T
V
ȧ
IN(min)
ȧ
1 )ȧ
ȧ
ȧ
ȧ
ȧ
T
OFF(min)
ȧ
Ȣ
ꢀ
R
= 383 kΩ.
DISCH
I
must be between 25 µA and 250 µA over the entire VIN range.
DISCH
With the calculated values, I
must be decreased.
ranges from 44 µA to 193 µA, within the allowable range. If I
is too high, C
DISCH
DISCH T
(4) R
FF
V
R
DISCH
FF(min)
R
+
FF
2 ǒV
* 1Ǔ
IN(min)
The nearest 1% standard value to the calculated value is 13.7 k.
7
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢃꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢃꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢇ
ꢉ ꢊꢋ ꢉꢌꢍ ꢎꢏꢏ ꢐ ꢑꢒꢓꢔꢕꢋ ꢏ ꢖꢒ ꢐꢏ ꢎ ꢀꢓꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
FUNCTIONAL DESCRIPTION
oscillator without duty cycle clamp (MODE = 0)
In this mode, the timing capacitor is discharged through a low impedance directly to ground. The DISCH pin is
externally grounded. A comparator connected to DISCH senses the ground connection and disables both the
discharge current source and VFF current source. A resistor divider is now required to set VFF.
V
IN
R
T
RC
DISCH
5
4
C
T
VFF
3
Figure 3. Ocsillator Without Clamp (MODE = 0)
In this mode, the on-time is approximately:
V
FF
T
+T R C
T
where T+
ON
T
V
IN
The off-time is:
[ 75 ns
T
OFF
The frequency is:
1
f +
T R C ) 75 ns
T
T
8
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢇ
ꢉꢊ ꢋꢉ ꢌꢍꢎꢏ ꢏꢐ ꢑꢒ ꢓꢔꢕꢋ ꢏ ꢖ ꢒꢐ ꢏ ꢎꢀꢓ ꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
FUNCTIONAL DESCRIPTION
component selection for oscillator without duty cycle clamp (MODE = 0)
For a power converter with the following specifications:
D
D
D
D
V
V
V
F
= 18 V
= 75 V
IN(min)
IN(max)
= 15 V
IN(shutdown)
= 1 MHz
OSC
With these specifications,
18
V
+
+ 1.2 V
FF(min)
15
(1) Pick C = 220 pF
T
(2) Calculate R .
T
V
V
IN(min)
FF(min)
1
ǒ
* 75 ns
Ǔ
F
OSC
R +
T
C
T
TYPICAL CHARACTERISTICS
UCC35706 UVLO THRESHOLDS
UCC35705 UVLO THRESHOLDS
vs
vs
TEMPERATURE
TEMPERATURE
8.9
8.8
8.7
8.6
8.5
8.4
13
12
11
10
9
8.3
8.2
8.1
8.0
8
7
–50
–25
0
25
50
C
75
100
125
–50
–25
0
25
50
75
100
125
C
Temperature
Temperature
Figure 4
Figure 5
9
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢃꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢃꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢇ
ꢉ ꢊꢋ ꢉꢌꢍ ꢎꢏꢏ ꢐ ꢑꢒꢓꢔꢕꢋ ꢏ ꢖꢒ ꢐꢏ ꢎ ꢀꢓꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS
OPERATING CURRENT (AT 1mHz)
LOW-LINE THRESHOLD
vs.
vs
TEMPERATURE
TEMPERATURE
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.65
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
–50
–25
0
25
50
C
75
100
125
–50
–25
0
25
50
75
100
125
C
Temperature
Temperature
Figure 6
Figure 7
PROGRAMMABLE MAXIMUM
DUTY CYCLE
OSCILLATOR FREQUENCY
vs
vs
TEMPERATURE
TEMPERATURE
82
80
78
76
74
72
1.10
1.05
1.00
0.95
0.90
70
68
–50
–25
0
25
50
C
75
100
125
0
–50
–25
25
50
C
75
100
125
Temperature
Temperature
Figure 8
Figure 9
10
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢇ ꢆ ꢀꢁꢁ ꢈ ꢃꢄ ꢅ ꢃ ꢆ ꢀꢁ ꢁꢈ ꢃꢄ ꢅꢇ
ꢉꢊ ꢋꢉ ꢌꢍꢎꢏ ꢏꢐ ꢑꢒ ꢓꢔꢕꢋ ꢏ ꢖ ꢒꢐ ꢏ ꢎꢀꢓ ꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
TYPICAL CHARACTERISTICS
CURRENT-LIMIT THRESHOLD
CURRENT-LIMIT PROP DELAY
vs
vs
TEMPERATURE
TEMPERATURE
35
33
31
29
27
220
215
210
205
200
25
23
21
19
17
15
195
190
185
180
–50
–25
0
25
50
C
75
100
125
–50
–25
0
25
50
75
100
125
Temperature C
Temperature
Figure 10
Figure 11
11
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢃꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢇꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢃꢆ ꢀꢁ ꢁꢈ ꢃ ꢄ ꢅ ꢇ
ꢉ ꢊꢋ ꢉꢌꢍ ꢎꢏꢏ ꢐ ꢑꢒꢓꢔꢕꢋ ꢏ ꢖꢒ ꢐꢏ ꢎ ꢀꢓꢍ ꢏ ꢗ ꢊꢐꢔ ꢉ ꢖ ꢒꢐ ꢀꢓ ꢕꢔꢒ ꢘ
ꢙ
SLUS473A – NOVEMBER 1999 – REVISED MARCH 2001
MECHANICAL DATA
Detailed package drawing for MSOP-8 (DGK) is shown below. For SOIC-8 (D) and PDIP-8 (P) package drawings,
consult Packaging Section of the Power Supply Control Data Book (TI Literature Number SLUD003).
DGK (MSOP-8)
MINI SMALL OUTLINE PACKAGE
0,38
0,25
M
0,65
0,25
8
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–ā6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073329/B 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
12
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