UCC3580DTR-2G4 [TI]
Single Ended Active Clamp/Reset PWM; 单端有源钳位/复位PWM
| 型号： | UCC3580DTR-2G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single Ended Active Clamp/Reset PWM |
| 文件： | 总16页 (文件大小：567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
Single Ended Active Clamp/Reset PWM
FEATURES
DESCRIPTION
Provides Auxiliary Switch Activation
Complementary to Main Power
Switch Drive
The UCC3580 family of PWM controllers is designed to implement a variety
of active clamp/reset and synchronous rectifier switching converter topolo-
gies. While containing all the necessary functions for fixed frequency, high
performance pulse width modulation, the additional feature of this design is
the inclusion of an auxiliary switch driver which complements the main
power switch, and with a programmable deadtime or delay between each
transition. The active clamp/reset technique allows operation of single
ended converters beyond 50% duty cycle while reducing voltage stresses
on the switches, and allows a greater flux swing for the power transformer.
This approach also allows a reduction in switching losses by recovering en-
ergy stored in parasitic elements such as leakage inductance and switch
capacitance.
Programmable deadtime (Turn-on
Delay) Between Activation of Each
Switch
Voltage Mode Control with
Feedforward Operation
Programmable Limits for Both
Transformer Volt- Second Product
and PWM Duty Cycle
The oscillator is programmed with two resistors and a capacitor to set
switching frequency and maximum duty cycle. A separate synchronized
ramp provides a voltage feedforward pulse width modulation and a pro-
grammed maximum volt-second limit. The generated clock from the oscilla-
tor contains both frequency and maximum duty cycle information.
High Current Gate Driver for Both
Main and Auxiliary Outputs
Multiple Protection Features with
Latched Shutdown and Soft Restart
Low Supply Current (100 mA Startup,
1.5 mA Operation)
(continued)
BLOCK DIAGRAM
UDG-95069-2
Pin Numbers refer to DIL-16 and SOIC-16 packages
SLUS292C - FEBRUARY 1999 - REVISED MAY 2005
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
DESCRIPTION (cont.)
The main gate drive output (OUT1) is controlled by the Undervoltage lockout monitors supply voltage (VDD), the
pulse width modulator. The second output (OUT2) is in- precision reference (REF), input line voltage (LINE), and
tended to activate an auxiliary switch during the off time the shutdown comparator (SHTDWN). If after any of
of the main switch, except that between each transition these four have sensed a fault condition, recovery to full
there is deadtime where both switches are off, pro- operation is initiated with a soft start. VDD thresholds, on
grammed by a single external resistor. This design offers and off, are 15V and 8.5V for the -2 and -4 versions, 9V
two options for OUT2, normal and inverted. In the -1 and and 8.5V for the -1 and -3 versions.
-2 versions, OUT2 is normal and can be used to drive
The UCC1580-x is specified for operation over the mili-
PMOS FETs. In the -3 and -4 versions, OUT2 is inverted
tary temperature range of 55°C to 125°C. The
and can be used to drive NMOS FETs. In all versions,
UCC2580-x is specified from 40°C to 85°C. The
both the main and auxiliary switches are held off prior to
UCC3580-x is specified from 0°C to 70°C. Package op-
startup and when the PWM command goes to zero duty
tions include 16-pin surface mount and dual in-line.
cycle. During fault conditions, OUT1 is held off while
OUT2 operates at maximum duty cycle with a guaran-
teed off time equal to the sum of the two deadtimes.
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAMS
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
DIL-16, SOIC-16 (Top View)
J, N, or D Packages
I
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
LINE, RAMP . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to VDD + 1V
LINE, IRAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3V
I
I
I
I
I
DELAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
OUT1 (tpw < 1 s and Duty Cycle < 10%) . . . . . . . 0.6A to 1.2A
OUT2 (tpw < 1 s and Duty Cycle < 10%) . . . . . . . 0.4A to 0.4A
CLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA to 100mA
OSC1, OSC2, SS, SHTDWN, EAIN . . . . . 0.3V to REF + 0.3V
I
I
EAOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA to 5mA
REF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2V to 0.2V
Storage Temperature . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . 55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
ORDER INFORMATION
2
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
ELECTRICAL CHARACTERISTICSUnless otherwise stated, all specifications are over the full temperature range, VDD =
12V, R1 = 18.2 kW, R2 = 4.41 kW, CT = 130 pF, R3 = 100 kW, COUT1 = 0 F, COUT2 = 0 F. TA = 0°C to 70°C for the UCC3580,
40°C to 85°C for the UCC2580, 55°C to 125°C for the UCC1580, TA = TJ.
PARAMETER
Oscillator Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Frequency
370
650
4.3
400
750
4.7
0.3
430
850
kHz
ns
V
CLK Pulse Width
CLK VOH
ICLK
= 3 mA
CLK VOL
ICLK = 3 mA
0.5
V
Ramp Generator Section
Ramp VOL
IRAMP = 100 mA
50
100
mV
V
Flux Comparator Vth
Pulse Width Modulator Section
Minimum Duty Cycle
Maximum Duty Cycle
PWM Comparator Offset
Error Amplifier Section
EAIN
3.16
3.33
3.50
OUT1, EAOUT = VOL
OUT1, EAIN = 2.6 V
0
%
%
V
63
66
69
0.9
0.1
0.4
EAOUT = EAIN
2.44
2.5
150
0.3
5
2.56
400
0.5
V
nA
V
IEAIN
EAOUT = EAIN
EAOUT, VOL
EAIN = 2.6 V, IEAOUT = 100 mA
EAOUT, VOH
EAIN = 2.4 V, IEAOUT
f = 100 kHz (Note 1)
=
100 mA
4
70
2
5.5
V
AVOL
80
6
dB
MHz
Gain Bandwidth Product
Softstart/Shutdown Section
Start Duty Cycle
SS VOL
EAIN = 2.4 V
0
%
mV
mV
mA
V
ISS = 100 mA
100
400
–20
0.5
50
350
550
–35
0.6
SS Restart Threshold
ISS
SHTDWN VTH
0.4
ISHTDWN
150
nA
Undervoltage Lockout Section
VDD On
UCC3580-2,-4
UCC3580-1,-3
14
8
15
9
16
10
V
V
VDD Off
7.5
4.7
4.2
8.5
5
9.5
5.3
4.8
150
V
LINE On
V
LINE Off
4.5
50
V
ILINE
LINE = 6 V
nA
Supply Section
VDD Clamp
IVDD = 10 mA
VDD < VDD On
No Load
14
15
160
2.5
16
250
3.5
V
A
IVDD Start
IVDD Operating
Output Drivers Section
OUT1 VSAT High
OUT1 VSAT Low
OUT2 VSAT High
OUT2 VSAT Low
OUT1 Fall Time
OUT1 Rise Time
OUT2 Fall Time
OUT2 Rise Time
mA
IOUT1
IOUT1 =100 mA
IOUT2 30 mA
IOUT2 = 30 mA
=
50 mA
0.4
0.4
0.4
0.4
20
1.0
1.0
1.0
1.0
50
V
V
=
V
V
COUT1 = 1nF, RS = 3 W
COUT1 = 1nF, RS = 3 W
ns
ns
ns
ns
40
80
COUT2 = 300pF, RS = 10 W
COUT2 = 300pF, RS = 10 W
20
50
20
40
3
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
ELECTRICAL CHARACTERISTICSUnless otherwise stated, all specifications are over the full temperature range, VDD =
12V, R1 = 18.2 kW, R2 = 4.41 kW, CT = 130 pF, R3 = 100 kW, COUT1 = 0 F, COUT2 = 0 F. TA = 0°C to 70°C for the UCC3580,
40°C to 85°C for the UCC2580, 55°C to 125°C for the UCC1580, TA = TJ.
PARAMETER
Output Drivers Section (cont.)
Delay 1 OUT2 to OUT1
TEST CONDITIONS
MIN
TYP
MAX UNITS
R3 = 100 kW, COUT1 = COUT2 = 15 pF
TA = TJ = 25°C
90
120
120
170
170
160
140
250
200
ns
ns
ns
ns
100
110
140
Delay 2 OUT1 to OUT2
R3 = 100 kW, COUT1 = COUT2 = 15 pF
TA = TJ = 25°C
Reference Section
REF
IREF = 0
4.875
5
1
1
5.125
20
V
Load Regulation
Line Regulation
IREF = 0 mA to 1 mA
VDD = 10 V to 14 V
mV
mV
20
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
CLK: Oscillator clock output pin from a low impedance Maximum Duty Cycle for OUT1 is slightly less due to
CMOS driver. CLK is high during guaranteed off time. Delay1 which is programmed by R3.
CLK can be used to synchronized up to five other
UCC3580 PWMs.
OUT1: Gate drive output for the main switch capable of
sourcing up to 0.5A and sinking 1A.
DELAY: A resistor from DELAY to GND programs the
OUT2: Gate drive output for the auxiliary switch with
nonoverlap delay between OUT1 and OUT2. The delay
0.3A drive current capability.
times, Delay1 and Delay2, are shown in Figure 1 and are
PGND: Ground connection for the gate drivers. Connect
PGND to GND at a single point so that no high frequency
components of the output switching currents are in the
ground plane on the circuit board.
as follows:
Delay 1= 1.1pF ·R3
Delay2 is designed to be larger than Delay1 by a ratio
shown in Figure 2.
RAMP: A resistor (R4) from RAMP to the input voltage
and a capacitor (CR) from RAMP to GND programs the
feedforward ramp signal. RAMP is discharged to GND
when CLK is high and allowed to charge when CLK is
low. RAMP is the line feedforward sawtooth signal for the
PWM comparator. Assuming the input voltage is much
greater than 3.3V, the ramp is very linear. A flux
comparator compares the ramp signal to 3.3V to limit the
maximum allowable volt-second product:
EAIN: Inverting input to the error amplifier. The
noninverting input of the error amplifier is internally set to
2.5V. EAIN is used for feedback and loop compensation.
EAOUT: Output of the error amplifier and input to the
PWM comparator. Loop compensation components
connect from EAOUT to EAIN.
GND: Signal Ground.
LINE: Hysteretic comparator input. Thresholds are 5.0V
and 4.5V. Used to sense input line voltage and turn off
OUT1 when the line is low.
Volt-Second Product Clamp = 3.3 • R4 • CR.
REF: Precision 5.0V reference pin. REF can supply up to
5mA to external circuits. REF is off until VDD exceeds 9V
(–1 and –3 versions) or activates the 15V clamp (–2 and
–4 versions) and turns off again when VDD droops below
8.5V. Bypass REF to GND with a 1mF capacitor.
OSC1 & OSC2: Oscillator programming pins. A resistor
connects each pin to a timing capacitor. The resistor
connected to OSC1 sets maximum on time. The resistor
connected to OSC2 controls guaranteed off time. The
combined total sets frequency with the timing capacitor.
Frequency and maximum duty cycle are approximately
given by:
SHTDWN: Comparator input to stop the chip. The
threshold is 0.5V. When the chip is stopped, OUT1 is low
and OUT2 continues to oscillate with guaranteed off time
equal to two non-overlap delay times. OUT2 continues to
switch after SHTDWN is asserted until the voltage on
VDD falls below VCS (typically 4 V) in order to discharge
the clamp capacitor.
1.44
Frequency =
R1+ R2 · CT + 27 pF
(
) (
)
R1
Maximum Duty Cycle =
R1+ R2
4
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
PIN DESCRIPTIONS (cont.)
SS: A capacitor from SS to ground programs the soft VDD: Chip power supply pin. VDD should be bypassed
start time. During soft start, EAOUT follows the amplitude to PGND. The –1 and –3 versions require VDD to ex-
of SS’s slowly increasing waveform until regulation is ceed 9V to start and remain above 8.5V to continue run-
achieved.
ning. A shunt clamp from VDD to GND limits the supply
voltage to 15V. The –2 and –4 versions do not start until
APPLICATION INFORMATION
UDG-95070-2
Note: Waveforms are not to scale.
Figure 1. Output time relationships.
UVLO and Startup
this clamp must be activated as an indication of reaching
the UVLO on threshold. The internal reference (REF) is
brought up when the UVLO on threshold is crossed. The
startup logic ensures that LINE and REF are above and
SHTDWN is below their respective thresholds before
outputs are asserted. LINE input is useful for monitoring
actual input voltage and shutting off the IC if it falls be-
low a programmed value. A resistive divider should be
used to connect the input voltage to the LINE input. This
feature can protect the power supply from excessive
currents at low line voltages.
For self biased off-line applications, -2 and -4 versions
(UVLO on and off thresholds of 15V and 8.5V typical)
are recommended. For all other applications, -1 and -3
versions provide the lower on threshold of 9V. The IC re-
quires a low startup current of only 160mA when VDD is
under the UVLO threshold, enabling use of a large trickle
charge resistor (with corresponding low power dissipa-
tion) from the input voltage. VDD has an internal clamp
at 15V which can sink up to 10mA. Measures should be
taken not to exceed this current. For -2 and -4 versions,
5
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
The soft start pin provides an effective means to start
the IC in a controlled manner. An internal current of
20 A begins charging a capacitor connected to SS once
the startup conditions listed above have been met. The
voltage on SS effectively controls maximum duty cycle
on OUT1 during the charging period. OUT2 is also con-
trolled during this period (see Figure 1). Negation of any
of the startup conditions causes SS to be immediately
discharged. Internal circuitry ensures full discharge of
SS (to 0.3V) before allowing charging to begin again,
provided all the startup conditions are again met.
Delay Times
1400
1.80
1.70
1.60
1.50
1.40
1.30
1.20
1.10
Delay Ratio
1200
1000
Delay2
800
600
Delay1
400
200
0
Oscillator
Simplified oscillator block diagram and waveforms are
shown in Figure 3. OSC1 and OSC2 pins are used to
program the frequency and maximum duty cycle. Capac-
itor CT is alternately charged through R1 and discharged
through R2 between levels of 1.67 V and 3.3 V. The
charging and discharging equations for CT are given by
t
0
100
200
300
400
500
600
700
800
900
1000
W
k
R3 ProgrammingResistor
Figure 2. Delay times.
æ
è
ö
ø
t
1
ç
÷
VC(charge) = V
• 1-
• e -
2
REF
3
t
t
2
2
VC(dis cha rge ) =
· VREF ·e -
3
where t1 = R1 • CT and t2 = R2 • CT. The charge time
and discharge time are given by
tCH = 0.69 • R1 • CT and tDIS = 0.69 • R2 • CT
The CLK output is high during the discharge period. It
blanks the output to limit the maximum duty cycle of
OUT1. The frequency and maximum duty cycle are
given by
1.44
Frequency =
(R1+ R2)• CT+ 27 pF
(
)
R1
R1+ R2
Maximum Duty Cycle =
Maximum Duty Cycle for OUT1 will be slightly less due
to Delay1 which is programmed by R3.
Voltage Feedforward and Volt-Second Clamp
UCC3580 has a provision for input voltage feedforward.
As shown in Figure 3, the ramp slope is made propor-
tional to input line voltage by converting it into a charging
current for CR. This provides a first order cancellation of
the effects of line voltage changes on converter perfor-
mance. The maximum volt-second clamp is provided to
protect against transient saturation of the transformer
core. It terminates the OUT1 pulse when the RAMP volt-
age exceeds 3.3V. If the feedforward feature is not used,
the ramp can be generated by tying R4 to REF. How-
ever, the linearity of ramp suffers and in this case the
maximum volt-second clamp is no longer available.
UDG-96016-1
Figure 3. Oscillator and ramp circuits.
6
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
Output Configurations
a single pin is used to program the delays between
OUT1 and OUT2 on both sets of edges. Figure 1 shows
the relationships between the outputs. Figure 2 gives the
ratio between the two delays. During the transition from
main to auxiliary switch, the delay is not very critical for
ZVS turn-on. For the first half of OUT1 off-time, the body
diode of the auxiliary switch conducts and OUT2 can be
turned on any time. The transition from auxiliary to main
switch is more critical. Energy stored in the parasitic in-
ductance(s) at the end of the OUT2 pulse is used to dis-
charge the parasitic capacitance across the main switch
during the delay time. The delay (Delay 1) should be op-
timally programmed at 1/4 the resonant period deter-
mined by parasitic capacitance and the resonant
inductor (transformer leakage and/or magnetizing induc-
tances, depending on the topology). However, depend-
ing on other circuit parasitics, the resonant behavior can
change, and in some cases, ZVS turn-on may not be ob-
tainable. It can be shown that the optimum delay time is
independent of operating conditions for a specific circuit
and should be determined specifically for each circuit.
The UCC3580 family of ICs is designed to provide con-
trol functions for single ended active clamp circuits. For
different implementations of the active clamp approach,
different drive waveforms for the two switches (main and
auxiliary) are required. The -3 and -4 versions of the IC
supply complementary non-overlapping waveforms
(OUT1 and OUT2) with programmable delay which can
be used to drive the main and auxiliary switches. Most
active clamp configurations will require one of these out-
puts to be transformer coupled to drive a floating switch
(e.g. Figure 5). The -1 and -2 versions have the phase of
OUT2 inverted to give overlapping waveforms. This con-
figuration is suitable for capacity coupled driving of a
ground referenced p-channel auxiliary switch with the
OUT2 drive while OUT1 is directly driving an n-channel
main switch (e.g. Figure 4).
The programmable delay can be judiciously used to get
zero voltage turn-on of both the main and auxiliary
switches in the active clamp circuits. For the UCC3580,
UDG-95071-2
Figure 4. Active clamp forward converter.
7
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
UDG-96017-1
Figure 5. Off-line active clamp flyback converter.
The use of active reset in a flyback power converter topology may be covered by U.S. Patent No. 5,402,329 owned by Technical
Witts, Inc., and for which Unitrode offers users a paid up license for application of the UCC1580 product family.
8
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
APPLICATION INFORMATION (cont.)
UDG-96018-1
Figure 6. UCC3580 used in a synchronous rectifier application.
REVISION
DATE
COMMENT
SLUS292B
MAY 2005
Updated OSC frequency and maximum duty cycle, CT charge and discharge
equations.
Updated SHTDWN pin description.
Updated typical CT value used for measurements in electrical characteristics
table.
SLUS292C
MAY 2005
Removed Q package from datasheet.
9
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
UCC1580J-2
UCC1580J-4
UCC2580D-1
OBSOLETE
OBSOLETE
ACTIVE
UTR
J
TBD
TBD
Call TI
Call TI
Call TI
Call TI
CDIP
SOIC
16
16
D
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC2580D-2
UCC2580D-3
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
PDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
D
D
D
D
D
D
D
N
N
N
N
N
N
D
D
D
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC2580D-3G4
UCC2580D-4
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC2580D-4G4
UCC2580DTR-1
UCC2580DTR-1G4
UCC2580DTR-2
UCC2580DTR-2G4
UCC2580DTR-3
UCC2580DTR-3G4
UCC2580DTR-4
UCC2580DTR-4G4
UCC2580N-1
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC2580N-1G4
UCC2580N-2
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC2580N-2G4
UCC2580N-3
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC2580N-4
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC3580D-1
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3580D-1G4
UCC3580D-2
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3580D-3
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
UCC3580D-3G4
UCC3580D-4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
PDIP
PDIP
PDIP
PDIP
D
D
D
D
D
D
D
D
D
D
N
N
N
N
N
N
N
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3580DTR-1
UCC3580DTR-1G4
UCC3580DTR-2
UCC3580DTR-2G4
UCC3580DTR-3
UCC3580DTR-3G4
UCC3580DTR-4
UCC3580DTR-4G4
UCC3580N-1
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC3580N-2
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC3580N-2G4
UCC3580N-3
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC3580N-3G4
UCC3580N-4
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
UCC3580N-4G4
25 Green (RoHS & CU NIPDAU Level-NC-NC-NC
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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