UCC3585NG4 [TI]
1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDIP16, GREEN, PLASTIC, DIP-16;
| 型号： | UCC3585NG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDIP16, GREEN, PLASTIC, DIP-16 信息通信管理 开关 光电二极管 |
| 文件： | 总17页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢁ ꢂꢃ ꢄꢃ
ꢀ ꢁꢁ ꢅꢃ ꢄꢃ
SLUS304F − JULY 1999 − REVISED JANUARY 2005
ꢆꢇ ꢈꢉꢊ ꢇ ꢆꢋꢌꢍ ꢎ ꢏꢐ ꢑꢁꢒꢓꢇ ꢑꢇ ꢀꢏ
ꢔꢀꢁ ꢕ ꢁꢇ ꢑꢋ ꢓꢇ ꢆ ꢆꢎ ꢓ
FEATURES
DESCRIPTION
D
D
D
D
D
VOUT Resistor Programmable Down to 0.9 V
3.3-V or 5.0-V Input Supply
The UCC3585 synchronous buck controller
provides flexible high efficiency power conversion
for output voltages as low as 0.9 V with ensured
1% dc accuracy. With an input voltage range of
3.0 V to 5.5 V, it is the ideal choice for 3.3 V only,
5.0 V only, or other low voltage systems. The fixed
frequency oscillator is capable of providing
practical PWM operation to 500 kHz.
1% DC Accuracy
High Efficiency Synchronous Switching
Drives P-Channel (High Side) and N-Channel
(Low Side) MOSFETs
D
Lossless Programmable Current Limit
Logic Compatible Shutdown
D
The UCC3585 drives a complementary pair of
power MOSFET transistors. A P-channel on the
high side, and an N-channel on the low side step
down the input voltage at up to 90% efficiency.
APPLICATIONS
D
Local Microprocessor Core Voltage Power
Supplies for Desktop and Notebook
Computers
A
programmable two-level current limiting
function is provided by sensing the voltage drop
across the high side P-channel MOSFET. This
circuit can be configured to provide pulse-
by-pulse limiting, timed shutdown after seven
consecutive faults, or latch-off after fault detec-
tion, allowing maximum application flexibility. The
current limit threshold can be programmed over a
wide range with a single resistor.
D
D
DSP Core or I/O Powering
High-Speed GTL Bus Regulation
VIN
C7
0.47 µ F
R4
14 kΩ
V
V
= 3.3 V
= 1.8 V
IN
OUT
= 3 A (max)
UCC3585
CLSET
R1
10 kΩ
+
I
OUT
C1
Q1
SI4562DY
15 VIN
8
150 µ F
ENABLE
L1
3.7 µ H
1
2
4
ENB
COMP ISENSE 11
VFB NDRV 14
PDRV 12
C2 5600 pF
C3 47 pF
R2 10 kΩ
V
OUT
R5
2 kΩ
+
+
10 SD
SS
16 CT
ISET
N/C
N/C
6
9
C4 0.47 µ F
C5 0.1 µ F
C6 470 pF
R3 100 kΩ
C8
150 µ F
C9
10 µ F
3
PWRGND 13
R6
2 kΩ
7
GND
5
RTN
RTN
UDG−01127
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Copyright 2001, Texas Instruments Incorporated
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1
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
description (continued)
The UCC3585 also includes undervoltage lockout, a logic controlled enable, and softstart functions. The
UCC3585 is offered in the 16-pin surface mount and through-hole packages.
†}
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Analog pins
Minimum and maximum forced voltage (reference to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.3 V
Digital pins
Minimum and maximum forced voltage (reference to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.3 V
Power driver output pins
Maximum forced current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A
Operating junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
J
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
} Unless otherwise noted, voltages are reference to ground and currents are positive into, negative out of, the specified terminals. Pulsed is defined
as a less than 10% duty cycle with a maximum duration of 500 ns.
N, D and M PACKAGES
(TOP VIEW)
ENB
COMP
SS
CT
1
2
3
4
5
6
7
8
16
15
14
13
12
VIN
NDRV
PWRGND
PDRV
VFB
GND
N/C
11 ISENSE
10 SD
ISET
CLSET
9
N/C
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
DIL (N)
SOIC (D)
UCC2585D
UCC3585D
QSOP (M)
UCC2585M
UCC3585M
−40°C to 85°C
0°C to 85°C
UCC2585N
UCC3585N
The M and D packages are available taped and reeled. Add an R suffix to the device
type (e.g., UCC3585DR).
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
N
D
M
1.1 W
11 mW/°C
8.3 mW/°C
5.8 mW/°C
610 mW
440 mW
830 mW
450 mW
330 mW
580 mW
320 mW
230 mW
2
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
electrical characteristics, these specifications hold for T = 05C to 855C for the UCC3585 and
A
T = −405C to 855C for the UCC2585, T = T
V
= 3.3 V, V
, V
= V , V = 0.9 V,
IN FB
A
A
J, IN
ENB ISENSE
V
= 1.5 V, C = 330 pF, R
= 100 kΩ, R
= 10 kΩ, (unless otherwise noted)
COMP
T
ISET
CLSET
input supply
PARAMETER
TEST CONDITIONS
MIN
TYP
2.3
MAX UNITS
Supply current − total (active)
Supply current – shutdown
VIN turnon threshold (UVLO)
VIN turnon hysteresis
3.5
25
mA
µA
V
ENB = 0 V
10
1.95
110
1.60
2.20
200
mV
voltage amplifier
PARAMETER
TEST CONDITIONS
= 25°C,
MIN
TYP
MAX UNITS
V
V
= 3.0 V to 3.6 V,
= 3.0 V to 3.6 V,
T
A
See Note 1
0.891
0.9
0.909
IN
T
A
= 0°C to 85°C,
IN
0.889
0.886
0.9
0.911
V
See Note 1
Input voltage (internal reference)
V
= 3.0 V to 3.6 V,
T
A
= −40°C to 85°C,
IN
0.9
0.914
dB
See Note 1
Open loop gain
COMP = 0.5 V to 2.5 V
60
80
2.95
0.10
–300
3.0
Output voltage high
Output voltage low
Output source current
Output sink current
I
I
= –50 µA
= 50 µA
2.80
COMP
V
0.25
COMP
–175
2.0
µA
mA
NOTE: 1. Measured on COMP with the error amplifier in a unity gain (voltage follower) configuration.
oscillator/PWM
PARAMETER
TEST CONDITIONS
MIN
345
345
1.8
TYP
420
425
2.1
MAX UNITS
VIN = 3.3 V
VIN = 5.0 V
475
485
2.3
2.3
2.8
kHz
kHz
Initial accuracy
T
A
= 0°C to 85°C
CT ramp peak-to-valley
CT ramp peak
T
A
= −40°C to 85°C
1.7
2.1
2.5
V
T
= 0°C to 85°C
0.3
0.27
100
0.4
A
CT ramp valley voltage
T
A
= −40°C to 85°C
0.40
PWM maximum duty cycle
PWM delay to outputs
Enable high threshold
Enable low threshold
COMP = 2.8 V,
COMP = 2.5 V
Measured on ENB,
Measured on ENB
SS = 0 V,
Measured on PDRV
See Note 3
%
85
2.8
140
ns
V
0.5
T
A
= 0°C to 85°C
9.0
9.0
13.5
13.5
16.0
19.0
Softstart charge current
µA
SS = 0 V,
T
A
= −40°C to 85°C
NOTE: 3. Enable high threshold = (V − 0.5).
IN
3
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
electrical characteristics, these specifications hold for T = 05C to 855C for the UCC3585 and
A
T = −405C to 855C for the UCC2585, T = T
V
= 3.3 V, V
, V
= V , V = 0.9 V,
IN FB
A
A
J, IN
ENB ISENSE
V
= 1.5 V, C = 330 pF, R
= 100 kΩ, R
= 10 kΩ, (unless otherwise noted)
COMP
T
ISET
CLSET
current limit
PARAMETER
TEST CONDITIONS
MIN
−25
TYP
MAX UNITS
Comparator offset voltage
0
25
14.0
15.0
14.0
15.0
13.5
13.5
mV
V
V
V
V
= 3.3 V,
= 5 V,
T
= 0°C to 85°C
= 0°C to 85°C
= −40°C to 85°C
= −40°C to 85°C
= 0°C to 85°C
= −40°C to 85°C
10.0
11.0
9.0
11.5
12.5
11.5
12.5
11.0
11.0
1.1
IN
IN
IN
IN
A
T
A
CLSET current
= 3.3 V,
= 5 V,
T
A
µA
T
A
9.5
SD = 2 V,
T
A
8.5
SD sink current
SD = 2 V,
T
A
7.5
SD source current
Restart threshold
SD = 2 V
0.7
mA
V
Measured on SD
0.40
0.55
0.70
output driver
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
–50 mA (source),
–50 mA (source),
50 mA (sink),
50 mA (sink),
–50 mA (source),
–50 mA (source),
100 mA (sink),
50 mA (sink),
See Note 2
T
= 0°C to 85°C
= −40°C to 85°C
= 0°C to 85°C
= −40°C to 85°C
= 0°C to 85°C
= −40°C to 85°C
= 0°C to 85°C
= −40°C to 85°C
4.5
3.5
6.0
4.0
4.5
3
6.0
6.0
9.0
9.0
6.0
6
9.0
9.0
A
Pullup resistance (PDRV)
Pulldown resistance (PDRV)
Pullup resistance (NDRV)
Pulldown resistance (NDRV)
T
A
T
A
16.5
16.5
T
A
Ω
T
A
9.0
T
A
9
4.5
4.5
250
T
A
2.0
1.5
150
70
3.0
3.0
215
125
T
A
Deadtime delay (PDRV high to NDRV high)
Deadtime delay (NDRV low to PDRV low)
ns
See Note 2
175
NOTE: 1. Measured on COMP with the error amplifier in a unity gain (voltage follower) configuration.
NOTE: 2. 50% point of PDRV rise to NDRV rise and 50% point of NDRV fall to PDRV fall.
NOTE: 3. Enable high threshold = (V − 0.5).
IN
pin descriptions
CLSET: CLSET is used to program the pulse-by-pulse and overcurrent shutdown levels for the UCC3585. A
resistor connected between CLSET and VIN sets the over-current threshold. The over-current threshold follows
the following relationship:
1.25
R
CLSET
R
ISET
R
l
+
CL
ǒ
Ǔ
DS on
COMP: Output of the voltage error amplifier. Loop compensation components are connected between COMP
and VFB.
4
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
pin descriptions
CT: A high quality ceramic capacitor connected between this pin and ground sets the PWM oscillator frequency
by the following relationship:
1
f +
ǒ
TǓ
7000 C
The oscillator is capable of reliable operation up to 500 kHz.
ENB: A logical 1 (V – 0.5 V) on this input will activate the output drivers. A logical zero (0.5 V) will prevent
IN
switching of the output drivers. Do not allow ENB to remain between these levels steady state.
GND: Reference level for the IC. All voltages and currents are with respect to GND.
ISENSE: ISENSE monitors the voltage dropped across the high side P-channel MOSFET switch while it is
conducting. This information is used to detect overcurrent conditions by the current limit circuitry.
ISET: A resistor is connected between ISET and ground to program a precision bias for many of the UCC3585
circuit blocks. This resistor should be 100 kΩ with a maximum tolerance of 5%. 1.25 V is provided to ISET via
a buffered version of the internal bandgap voltage reference. The resulting current, 1.25 V / R
directly over to CLSET to program the overcurrent threshold.
, is mirrored
ISET
NDRV: High current driver output for the low side N-channel MOSFET switch.
PDRV: High current driver output for the high side P-channel MOSFET switch.
PWRGND: High current return path for the MOSFET drivers. PWRGND and GND should be terminated
together as close as possible to the device package .
SD: This pin can configure current limit to operate in any one of three different ways.
1. A forced voltage of less than 250 mV on SD inhibits the shutdown function causing pulse by pulse limiting.
2. A capacitor from SD to GND provides a controller-converter shutdown timeout after seven consecutive
overcurrent signals are received by the current limit circuitry. An internal 11-µA (typ) current sink
discharges the SD capacitor to the 0.55-V (typ) restart threshold. The shutdown time is given by:
ǒVIN
Ǔ
* 0.55 V ƫ
ƪCSD
t
+
SHUT
where C
11 mA
is the value of the capacitor from SD to GND, and VIN is the chip supply voltage (on pin 15).
SD
At this point, a softstart cycle is initiated, and a 1-mA current source (typ) quickly recharges SD to VIN.
During softstart, pulse-by-pulse current limiting is enabled, and the 7-cycle counter is disabled until
softstart is complete (i.e. charged to approximately VIN volts).
3. A forced voltage of greater than 1 V on SD will cause the UCC3585 to latch off after seven overcurrent
signals are received. After the controller is latched off, SD must drop below 250 mV to restart the
controller.
SS: A low leakage capacitor connected between SS and GND will provide a softstart function for the converter.
The voltage on this capacitor slowly charges on start-up via an internal 13.5 µA (typ.) current source. The output
of the voltage error amplifier (COMP) tracks this voltage, thereby limiting the controller duty ratio.
VFB: Inverting input to the voltage type error amplifier. The common mode input range for VFB extends from
GND to 1.5 V.
VIN: Supply voltage for the UCC3585. Bypass with a 0.1-µF ceramic capacitor (minimum) to supply the peak
gate drive currents required to change and discharge the power MOSFET gates. See application information
for details.
5
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
block diagram
ISET
7
CLSET
8
UVLO
2 V
PRECISION
BIAS SET
CURENT
LIMIT ADJ
VIN 15
ILIM
CURRENT
LIMIT
11 ISENSE
12 PDRV
UVLO
DRIVER
1.25 V
REF
ENABLE
ENB
1
VIN
−0.8 V
ANTI
SHOOT THRU
PWM
COMP
VFB
2
4
R
Q
D
PWM
V
LATCH
IN
DRIVER
S
Q
0.9 V
UVLO
14 NDRV
13.5 µA
SS
3
SOFTSTART COMPLETE
PRECISION
BIAS
13 PWRGND
OVER CURRENT COUNTER
SHUTDOWN TIMER
NC
NC
9
6
ILIM
CLK
OSCILLATOR
11 µA
L = NO SHUTDOWN
DISABLE DRIVERS
H = LATCHED SHUTDOWN
CAP = TIMED SHUTDOWN
UDG−00070
16
CT
5
GND
10
SD
APPLICATION INFORMATION
ISET pin operation
The ISET pin develops a precision current reference for many of the UCC3585’s internal circuit blocks. A
resistor, R , connected from the ISET pin to ground sets the precision current value. The internal current
ISET
reference is set by buffering the 1.25-V internal reference to the ISET pin, which results in a current of
1.25 V/R . The UCC3585 is designed for R = 100 kΩ with a maximum tolerance of 5%. Using a different
ISET
ISET
resistor value results in changed parametric performance and possibly unpredictable operation.
oscillator
The oscillator frequency is programmed by a timing capacitor connected from CT to ground. The maximum
recommended frequency is 500 kHz. The timing capacitor is charged and discharged by current sources
derived from the ISET pin. The voltage waveform on CT is a sawtooth ramp with approximately 95% of the period
spent charging the timing capacitor. Ceramic capacitors should be used, and the capacitance tolerance adds
to the accuracy of the oscillator frequency. For applications that operate over a wide temperature range or where
the highest accuracy is required, temperature stable ceramic capacitors such as NPO or COG dielectric should
be used for the CT capacitor. The aproximate operating frequency is determined by:
1
f +
ǒ
TǓ
7000 C
6
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
APPLICATION INFORMATION
soft-start
The SS pin provides a way to prevent overshoot of the output voltage by slowly increasing the duty cycle of the
PDRV output. A capacitor on SS to ground provides a controlled start-up of the supply. During start-up the
COMP pin is directly clamped to the SS pin. The SS pin has an internal current source of 13.5 µA (typical) which
charges the SS capacitor. Figure 1 shows the waveforms during softstart. The SS pin charges the external
capacitor to VIN volts after start-up is complete.
SS
VIN
ENB or VIN
COMP
V
OUT
V = 0.4 V + D x 2.1
0.4 V
t
t
SS
switching
switching
starts, V
V
V
in
in
OUT
OUT
disabled until
regulation, SS
continues to
charge to VIN
regulation, SS
charged to VIN
OUT
SS
reaches
charging up
0.4 V
Figure 1. Waveforms During Softstart
The softstart time is approximately:
V
OUT
0.4 )
ƪ
2.1
ƫ
V
IN
t
+ C
SS
SS
13.5 mA
current limit operation
The UCC3585 has a user configurable current limit for output overload protection. To reduce external
component count and minimize losses, the P-channel MOSFET’s R is used as a current sense element.
DS(on)
The ISENSE pin is connected to the P-channel MOSFET drain, which is internally connected to the negative
input to the current-sense comparator. The positive comparator input is connected to the CLSET pin, which has
an internal current sink of 11.5 µA (typical). For highest accuracy, this current sink is derived from the ISET
circuitry. A resistor from VIN to CLSET sets the current limit threshold. To eliminate errors due to PCB trace
impedances, the CLSET resistor should be connected directly to the P-channel MOSFET source, and the
ISENSE pin should be directly connected to the P-channel MOSFET drain. Figure 2 shows a simplified diagram
of the current limit circuitry.
7
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
APPLICATION INFORMATION
VIN
R
15
CLSET
S
12
G
P−Channel
MOSFET
Package
8
D
To
PWM
Logic
11
VOUT
ISENSE
ENABLE
14
11.5 µA
Figure 2. Current Limit Circuitry
The peak current limit is calculated using the following equation:
1.25
R
CLSET
R
ISET
R
l
+
CL
ǒ
Ǔ
DS on
When the R
of the P-channel MOSFET is used as the sense element, several issues arise. Before the
DS(on)
current limit comparator is enabled, the P-channel MOSFET must be fully enhanced, and the drain to source
voltage must be allowed to settle. The UCC3585 has an internal circuit that disables the current limit comparator,
t
for a fixed time, starting at the PDRV output falling edge. It is important that no external gate resistor
ISENSE,
is used between the PDRV output and the P-channel gate. If a resistor is used, the PDRV output falls quickly,
and the turnon of the P-channel MOSFET is delayed, possibly causing a false overcurrent event to be detected.
Figure 3 shows the waveforms at the P-channel turnon instance and the t
time interval.
ISENSE
8
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
APPLICATION INFORMATION
VIN
ISENSE
t
ISENSE
PDRV
VIN/2
I
SENSE
Comparator
Enabled
0 V
−0.7 V
time
Figure 3. t
Time Interval
ISENSE
The t
t
time interval follows the approximate relationship:
ISENSE
ǒVBE
Ǔ
) 12.5 mA R
3.2 pF
CLSET
12.5 mA
+
ISENSE
As can be seen from the above equation, t
is dependent upon two variables. First, t
is longer for
ISENSE
ISENSE
higher values of R
current limit threshold. Second, t
. This allows more time for ISENSE to settle, which is beneficial for supplies with a higher
CLSET
varies with the inherent temperature dependence of the V
in the
ISENSE
BE
above equation. V can be assumed to be 0.65 V at 25°C with a temperature coefficient of −2 mV/°C. Since
BE
the t
time interval decreases at high temperature, operation of the supply must be verified at the maximum
ISENSE
ambient temperature at full output load.
Another issue with using the MOSFET R
MOSFET. Since there is a blanking interval, t
for the sense element is the minimum on time for the P-channel
DS(on)
, there is a minimum time that the P-channel MOSFET stays
ISENSE
on during any PWM period. The minimum on time occurs even with the power supply output shorted,
experimentally the minimum on time is approximately 400 ns. When a converter is operated continuously into
a shorted or overloaded output, this minimum on time results in a significant power dissipation and stress on
both MOSFETs.
9
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
APPLICATION INFORMATION
A solution to this minimum on-time is a counter and time-out circuit. As described in the SD pin description, a
capacitor on SD enables the time-out circuit. An internal digital counter is used to count the overcurrent events
at the current-sense comparator output. When seven overcurrent conditions are reached, both MOSFET
switches are turned off, the SS capacitor is discharged, and an 11 µA (typical) internal current sink discharges
the SD capacitor. During this discharge time, both MOSFETs are held off, and the inductor current decays to
zero. When the SD capacitor voltage reaches 0.55 V (typical), a softstart cycle restarts the converter. During
softstart, the 7-cycle counter is disabled. However, the peak current limit comparator is enabled. When the SS
voltage reaches the threshold equal to (V − 0.5 V), the 7-cycle counter is enabled. By sizing the SS capacitor
IN
relative to the SD capacitor, the amount of time spent switching the MOSFETs can be reduced when the output
is overloaded. If the timeout mode is used, the relative capacitance values for C and C
following relationship:
must fall into the
SS
SD
C
v 20 C
SD
SS
This equation also states that, if the time-out mode is used, a softstart capacitor must be used. Figure 4 shows
the waveforms when the converter is operated into a short circuit.
VIN
V(PDRV)
0 V
VIN
VIN−0.5 V
V(SD)
tSHUT
V(SS)
0.55 V
time
Figure 4. Converter Operated Into Short Circuit
10
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SLUS304F − JULY 1999 − REVISED JANUARY 2005
APPLICATION INFORMATION
VIN bypass capacitor selection
A ceramic capacitor must be used across VIN to GND on the UCC3585. This capacitor supplies the transient
currents required to turn on and off both power MOSFETs. It is important to select a high enough capacitance
value to keep the peak-to-peak ripple voltage at VIN below 100 mV. The maximum peak-to-peak ripple on VIN
is somewhat arbitrary, and 100 mV is used as an estimate. Knowing the P-channel total gate charge, Q and
P
the total gate charge for the N-channel MOSFET, Q , the minimum capacitance can be found:
N
Q
) Q
P
N
C
+
VIN(min)
100 mV
An estimate of Q can be found from the manufacturer’s data sheet curve for gate charge vs gate to source
P
voltage. Since the N-channel MOSFET is switched with essentially zero volts across it, a better estimation of
Q is found by multiplying the input capacitance, C
and the V voltage. Because C
is voltage dependent,
N
ISS
IN
ISS
it is important to use the C
value for approximately zero volts drain to source. This gives a more accurate
ISS
estimation of the N-channel gate charge.
power MOSFET drivers
The UCC3585 contains two high current power MOSFET drivers. The source and sink current capability of
these drivers has been sized to allow operation without external gate resistors. The P-channel driver has
approximately three times stronger source current than sink current. This intentionally slows down the turnon
of the P-channel MOSFET, which reduces the reverse recovery snap of the N-channel MOSFET body diode.
The N-channel driver has a stronger sink current than source current which aids in keeping the N-channel
MOSFET off when the P-channel MOSFET is turned on. Adding a gate resistor from NDRV to the N-channel
MOSFET gate makes the N-channel more sensitive to dV/dt induced turnon and should be avoided. The
MOSFET drivers have lower resistance at VIN = 5 V as compared to VIN = 3.3 V. At VIN = 5 V, the drivers have
approximately 60% of the resistance specified at VIN = 3.3 V.
operation over wide VIN ranges
It is possible to design UCC3585 based supplies to operate over both the 3.3-V and 5-V input ranges. The
resulting V range can be as wide at 3.0 V to 5.5 V. For a successful design, several design steps must be taken.
IN
First, both MOSFETs should have R
rated at 2.7 V or 2.5 V. This assures reasonable efficiency at the
DS(on)
lowest input voltage. Second, the current limit threshold should be set at the minimum input voltage. At the
minimum input voltage, the P-channel MOSFET has maximum R . As VIN is increased to 5.5 V, the R
DS(on)
DS(on)
DS(on)
decreases considerably. The effect of this reduction in R
is a higher current limit. Also, note that critical
parameters, such as CLSET current and oscillator frequency are specified at both 3.3 V and 5.0 V.
11
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
UCC2585D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC2585DG4
UCC2585M
SOIC
D
DBQ
DBQ
D
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC2585MG4
UCC3585D
SSOP/
QSOP
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SOIC
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3585DG4
UCC3585M
SOIC
D
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
DBQ
DBQ
DBQ
N
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3585MTR
UCC3585MTRG4
UCC3585N
SSOP/
QSOP
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SSOP/
QSOP
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PDIP
Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UCC3585NG4
PDIP
N
Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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24-Feb-2006
to Customer on an annual basis.
Addendum-Page 2
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