UCC3626DWTRG4 [TI]
BRUSHLESS ESS DC MOTOR CONTROLLER;
| 型号： | UCC3626DWTRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | BRUSHLESS ESS DC MOTOR CONTROLLER 电动机控制 信息通信管理 光电二极管 |
| 文件： | 总23页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
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voltage- or current-mode configurations. The
oscillator is easily synchronized to an external
master clock source via the SYNCH input.
Additionally, a QUAD select input configures the
chip to modulate either the low-side switches only,
or both upper and lower switches, allowing the
user to minimize switching losses in less
demanding two-quadrant applications.
FEATURES
D
D
D
D
Two-Quadrant and Four-Quadrant Operation
Integrated Absolute Value Current Amplifier
Pulse-by-Pulse and Average Current Sensing
Accurate, Variable Duty-Cycle Tachometer
Output
D
D
D
Trimmed Precision Reference
Precision Oscillator
The device includes a differential current-sense
amplifier and absolute-value circuit which provide
an accurate reconstruction of motor current,
useful for pulse-by-pulse overcurrent protection,
as well as closing a current control loop. A
precision tachometer is also provided for
implementing closed-loop speed control. The
TACH_OUT signal is a variable duty-cycle,
frequency output, which can be used directly for
digital control or filtered to provide an analog
feedback signal. Other features include COAST,
BRAKE, and DIR_IN commands, along with a
direction output, DIR_OUT.
Direction Output
DESCRIPTION
The UCC3626 motor controller device combines
many of the functions required to design a
high-performance, two- or four-quadrant, three-
phase, brushless dc motor controller into one
package. Rotor position inputs are decoded to
provide six outputs that control an external power
stage. A precision triangle oscillator and latched
comparator provide PWM motor control in either
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Copyright 2002, Texas Instruments Incorporated
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1
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
AVAILABLE OPTIONS
PACKAGED DEVICES
{
{
T
A
PDIP
(N)
SOIC
(DW)
TSSOP
(PW)
–40_C to 85_C
0_C to 70_C
UCC2626N
UCC3626N
UCC2626DW
UCC3626DW
UCC2626PW
UCC3626PW
{The DW and PW packages are available taped and reeled. Add TR suffix to device
type (e.g. UCC2626DWTR) to order quantities of 2,000 devices per reel.
N PACKAGE
(TOP VIEW)
DW and PW PACKAGES
(TOP VIEW)
GND
VREF
VDD
1
28
27
26
25
24
23
22
21
20
19
18
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
VREF
TACH_OUT
R_TACH
C_TACH
CT
SYNCH
DIR_OUT
SNS_NI
SNS_I
VDD
AHI
ALOW
BHI
BLOW
CHI
CLOW
DIR_IN
QUAD
BRAKE
COAST
HALLC
HALLB
HALLA
AHI
2
2
TACH_OUT
R_TACH
C_TACH
CT
ALOW
BHI
3
3
4
4
BLOW
CHI
5
5
6
6
SYNCH
DIR_OUT
SNS_NI
SNS_I
CLOW
DIR_IN
QUAD
BRAKE
COAST
7
7
8
8
9
9
10
11
10
11
12
13
14
IOUT
IOUT
OC_REF
PWM_I
OC_REF 12
PWM_I 13
PWM_NI 14
17 HALLC
16 HALLB
15 HALLA
PWM_NI
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage V
Input voltage, BRAKE, COAST, DIR_IN, HALLA, HALLB, HALLC,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
DD
OC_REF, QUAD, SYNCH, PWM_I, PWM_NI . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
SNS_I, SNS_NI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
DD
DD
Output current AHI, ALOW, BHI, BLOW, CHI, CLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
DIR_OUT, IOUT, TACH_OUT, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
J
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into negative out of the specified terminal.
2
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
block diagram
28 VDD
QUAD 20
BRAKE 19
5 VOLT
REFERENCE
2
VREF
COAST 18
DIR_IN 21
HALLA 15
HALLB 16
HALLC 17
1.75V
27 AHI
25 BHI
23 CHI
DIRECTION
SELECT
HALL
DECODER
26
ALOW
DIRECTION
DETECTOR
DIR_OUT
8
EDGE
DETECTOR
24 BLOW
22 CLOW
PWM_NI 14
PWM_I 13
SYNCH 7
PWM
COMPARATOR
OSCILLATOR
RxC
S
R
Q
Q
TACH_OUT
3
CT
6
OVERCURRENT
COMPARATOR
OC_REF 12
5
4
C_TACH
R_TACH
S
R
Q
Q
ONE
SHOT
11
9
IOUT
SENSE AMPLIFIER
X5
SNS_NI
PWM LOGIC
1
GND
SNS_I 10
UDG–97173
3
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
electrical characteristics over recommended operating conditions, VCC = 12 V; CT = 1 nF,
R_TACH = 250 kΩ, C_TACH = 100 pF, T = T , T = –40°C to 85°C for the UCC2626, and 0°C to 70°C
A
J
A
for the UCC3626 (unless otherwise noted)
overall
PARAMETER
TEST CONDITIONS
Outputs not switching
MIN
TYP
MAX UNIT
mA
Supply current
1
3
5
undervoltage lockout
PARAMETER
TEST CONDITIONS
MIN
9.0
TYP
10.5
0.40
MAX UNIT
Start threshold
11.0
0.50
V
V
UVLO hysteresis
0.35
5-V reference
PARAMETER
TEST CONDITIONS
= –2 mA
MIN
TYP
MAX UNIT
Output voltage
I
4.9
5
5.1
10
V
VREF
11 V < VCC < 14.5 V
Line regulation voltage
Load regulation voltage
Short circuit current
mV
mV
mA
–1 mA > I
> –5 mA
10
VREF
40
120
240
coast input comparator
PARAMETER
TEST CONDITIONS
TEST CONDITIONS
MIN
1.60
0.04
TYP
1.75
0.10
MAX UNIT
Threshold voltage
Hysteresis
2.00
0.16
V
V
current sense amplifier
PARAMETER
MIN
TYP
MAX UNIT
Input offset voltage
Input bias current
Gain
VCM = 0 V
VCM = 0 V
VCM = 0 V
8
15
mV
µA
V/V
dB
V
5
4.85
60
10
5.00
5.15
PSRR
11 V < VCC < 14.5 V
High-level output voltage
Low-level output voltage
I
I
= –100 µA
= 100 µA
6.3
IOUT
70
mV
µA
µA
IOUT
UCC3626
UCC2626
V
V
= 2 V
= 2 V
500
300
IOUT
Output source current
IOUT
pwm comparator
PARAMETER
TEST CONDITIONS
MIN
2.0
75
TYP
MAX UNIT
Input common mode range
Propagation delay time
8.0
V
150
ns
overcurrent comparator
PARAMETER
TEST CONDITIONS
MIN
0.0
50
TYP
MAX UNIT
Input common mode range
Propagation delay time
5.0
V
175
250
ns
logic inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-level logic input voltage
Low-level logic input voltage
QUAD, BRAKE, DIR, SYNCH
QUAD, BRAKE, DIR, SYNCH
3.6
V
1.4
V
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
electrical characteristics over recommended operating conditions, VCC = 12 V; CT = 1 nF,
R_TACH = 250 kΩ, C_TACH = 100 pF, T = T , T = –40°C to 85°C for the UCC2626, and 0°C to 70°C
A
J
A
for the UCC3626 (unless otherwise noted)
hall buffer inputs
PARAMETER
TEST CONDITIONS
MIN
1.7
TYP
MAX UNIT
High-level input voltage
Hysteresis
HALLA, HALLB, HALLC
HALLA, HALLB, HALLC
0V < VIN < 5 V
1.9
2.1
1.0
V
V
0.6
Input current
–25
µA
oscillator
PARAMETER
TEST CONDITIONS
= 250 kΩ, C = 1nF
MIN
TYP
MAX UNIT
Frequency
R
9.0
10.0
11.0
3%
kHz
TACH
T
Frequency change with voltage
CT peak voltage
12 V < VCC < 14.5 V
7.25
4.75
500
7.5
5.0
7.75
5.25
V
V
CT peak-to-valley voltage
SYNCH pin minimum pulse width
ns
tachometer
PARAMETER
TEST CONDITIONS
= –10 µA
MIN
99%
0
TYP
MAX UNIT
High-level output voltage/VREF
Low-level output voltage
High-level on-resistance
Low-level on-resistance
High-level ramp threshold voltage
Ramp voltage
I
I
I
I
100%
OUT
OUT
OUT
OUT
= 10 µA
20
1.5
1.5
mV
kΩ
kΩ
V
= –100 µA
= 100 µA
1
1
2.5
2.375 2.500 2.625
V
C
charge current
R
= 49.9 kΩ
48
–3%
–4%
51
53
3%
3%
µA
TACH
TACH
UCC3626
UCC2626
See Note 1
See Note 1
On-time accuracy
direction output
PARAMETER
TEST CONDITIONS
= –100 µA
MIN
4.5
0
TYP
MAX UNIT
High-level output voltage
Low-level output voltage
I
I
5.2
0.5
V
V
OUT
= 100 µA
OUT
output
PARAMETER
TEST CONDITIONS
MIN
TYP
0.1
MAX UNIT
Maximum duty cycle
100%
I
I
I
I
= 2 mA
0.0
0.0
4.0
4.7
0.5
0.1
5.2
5.2
100
V
V
OUT
OUT
OUT
OUT
Low-level output voltage
= 100 µA
= –2 mA
= –100 µA
4.8
V
High-level output voltage
Rise and fall time
V
CI = 10 pF
ns
ǒ
Ǔ
CTACH VHI * VLO
NOTE 1:
t
is calculated using the formula t
+
ON
ON
ICHARGE
5
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
pin descriptions
AHI, BHI, CHI: Digital outputs used to control the high-side switches in a three-phase inverter. For specific
decoding information reference Table I.
ALOW, BLOW, CLOW: Digital outputs used to control the low-side switches in a three-phase inverter. For
specific decoding information reference Table I.
BRAKE: BRAKE is a digital input which causes the device to enter brake mode. In brake mode all three high-
side outputs (AHI, BHI & CHI) are turned off, while all three lowside outputs (ALOW, BLOW, CLOW) are turned
on. During brake mode the tachometer output remains operational. The only conditions that can inhibit the
low-side commands during brake are UVLO, exceeding peak current, the output of the PWM comparator, or
the COAST command.
COAST: The COAST input consists of a hysteretic comparator which disables the outputs. The input is useful
in implementing an overvoltage bus clamp in four-quadrant applications. The outputs are disabled when the
input is above 1.75 V.
CT: This pin is used in conjunction with the R_TACH pin to set the frequency of the oscillator. A timing capacitor
is normally connected between this point and ground and is alternately charged and discharged between 2.5 V
and 7.5 V.
C_TACH: A timing capacitor is connected between this pin and ground to set the width of the TACH_OUT pulse.
The capacitor is charged with a current set by the resistor on pin R_TACH .
DIR_IN: DIR_IN is a digital input which determines the order in which the HALLA, HALLB, and HALLC inputs
are decoded. For specific decode information reference Table I.
DIR_OUT: DIR_OUT represents the actual direction of the rotor as decoded from the HALLA, HALLB, and
HALLC inputs. For any valid combination of HALLA, HALLB, and HALLC inputs there are two valid transitions;
one of which translates to a clockwise rotation and another which translates to a counterclockwise rotation. The
polarity of DIR_OUT is the same as DIR_IN while motoring, (i.e. sequencing from top to bottom in Table 1.)
GND: GND is the reference ground for all functions of the part. Bypass and timing capacitors should be
terminated as close as possible to this point.
HALLA, HALLB, HALLC: These three inputs are designed to accept rotor position information positioned 120°
apart. For specific decode information reference Table I. These inputs should be externally pulled up to VREF
or another appropriate external supply.
IOUT: IOUT represents the output of the current sense and absolute value amplifiers. The output signal
appearing is a representation of the following expression:
+ ABSǒI
Ǔ
I
* I
5
OUT
SNS_I
SNS_NI
This output can be used to close a current control loop as well as provide additional filtering of the current sense
signal.
OC_REF: OC_REF is an analog input which sets the trip voltage of the overcurrent comparator. The sense input
of the comparator is internally connected to the output of the current sense amplifier and absolute value circuit.
PWM_NI: PWM_NI is the noninverting input to the PWM comparator.
PWM_I: PWM_I is the inverting input to the PWM comparator.
QUAD: The QUAD input selects between two-quadrant operation (QUAD = 0) and four-quadrant operation
(QUAD = 1) . When in two-quadrant mode, only the low-side devices are effected by the output of the PWM
comparator. In four-quadrant mode both high- and low-side devices are controlled by the PWM comparator.
6
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
pin descriptions
SYNCH: The SYNCH input is used to synchronize the PWM oscillator with an external digital clock. When using
the SYNCH feature, a resistor equal to R_TACH must be placed in parallel with CT. When not using the SYNCH
feature, SYNCH must be grounded.
SNS_NI, SNS_I: These inputs are the noninverting and inverting inputs to the current sense amplifier,
respectively. The integrated amplifier is configured for a gain of five. An absolute value function is also
incorporated into the output in order to provide a representation of actual motor current when operating in
four-quadrant mode.
TACH_OUT: TACH_OUT is the output of a monostable triggered by a change in the commutation state, thus
providing a variable duty cycle, frequency output. The on time of the monostable is set by the timing capacitor
connected to C_TACH. The monostable is capable of being retriggered if a commutation occurs during its
on-time.
R_TACH: A resistor connected between R_TACH and ground programs the current for both the oscillator and
tachometer.
VDD: VDD is the input supply connection for this device. Undervoltage lockout keeps the outputs off for inputs
below 10.5 V. The input should be bypassed with a 0.1-µF ceramic capacitor, minimum.
VREF: VREF is a 5-V, 2% trimmed reference output with 5 mA of maximum available output current. This pin
should be bypassed to ground with a ceramic capacitor with a value of at least 0.1 µF.
APPLICATION INFORMATION
Table 1 provides the decode logic for the six outputs, AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function
of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and HALLC inputs.
Table 1. Commutation Truth Table
HALL
INPUTS
HIGH-SIDE
OUTPUTS
LOW-SIDE
OUTPUTS
BRAKE COAST DIR_IN
A
1
1
1
0
0
0
1
0
0
0
1
1
X
X
1
0
B
0
0
1
1
1
0
0
0
1
1
1
0
X
X
1
0
C
A
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
B
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
C
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
A
0
0
0
1
1
0
1
0
0
0
0
1
0
1
0
0
B
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
C
0
1
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
X
X
X
X
1
0
0
0
1
1
1
1
1
0
0
0
X
X
1
0
7
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
The UCC3626 is designed to operate with 120° position sensor encoding. In this format, the three position
sensor signals are never simultaneously high or low. Motors whose sensors provide 60° encoding, can be
converted to 120° using the circuit shown in Figure 1.
In order to prevent noise from commanding improper commutation states, some form of low-pass filtering on
HALLA, HALLB, and HALLC is recommended. Passive RC networks generally work well and should be located
as close as possible to the device. Figure 2 illustrates these techniques.
VREF
VREF
1 kΩ
499 Ω
1 kΩ
HALLB
499 Ω
HALLA
HALLA
HALLA
2.2 nF
2.2 nF
VREF
1 kΩ
VREF
HALLA
1 kΩ
1 kΩ
499 Ω
HALLB
2N2222A
HALLB
HALLB
2.2 nF
2.2 nF
VREF
VREF
1 kΩ
499 Ω
1 kΩ
499 Ω
HALLC
HALLC
HALLC
HALLC
2.2 nF
2.2 nF
UDG–97182
UDG–97185
Figure 1. Converting Hall Code From 60° to 120°
Figure 2. Passive Hall Filtering Technique
8
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ꢀꢁꢁ ꢂ ꢃꢂ ꢃ ꢄ ꢀ ꢁꢁ ꢅꢃ ꢂꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
configuring the oscillator
The UCC3626 oscillator is designed to operate at frequencies up to 250 kHz and provide a triangle waveform
on CT with a peak-to-peak amplitude of 5 V for improved noise immunity. The current used to program CT is
derived from the R_TACH resistor according to the following equation:
25
R_TACH
I
+
Amps
OSC
(1)
The oscillator frequency is set by R_TACH and CT according to the following relationship:
2.5
f
+
Hz
OSC
R_TACH CT
(2)
Timing resistor values should be between 25 kΩ and 500 kΩ, while capacitor values should be between 100 pF
and 1 µF. Figure 3 provides a graph of oscillator frequency for various combinations of timing components. As
with any high-frequency oscillator, timing components should be located as close as possible to the device pins
when laying out the printed-circuit board. It is also important to reference the timing capacitor directly to the
ground pin on the UCC3626 rather than daisy chaining it to another trace or the ground plane. This technique
prevents switching current spikes in the local ground from causing jitter in the oscillator.
synchronizing the oscillator
A common system specification is to have all oscillators synchronized to a master clock. The UCC3626 provides
a SYNCH input for this purpose. The SYNCH input is designed to interface with a digital clock pulse generated
by the master oscillator. A positive-going edge on this input causes the UCC3626 oscillator to begin discharging.
In order for the slave oscillator to function properly, it must be programmed for a frequency slightly lower than
that of the master. Also, a resistor equal to R_TACH must be placed in parallel with CT. Figure 4 illustrates the
waveforms for a slave oscillator programmed to 20 kHz with a master frequency of 30 kHz. The SYNCH pin
must be grounded when not used.
OSCILLATOR FREQUENCY
vs
TIMING CAPACITANCE
1.E+06
R_TACH = 25 kΩ
R_TACH = 100 kΩ
1.E+05
1.E+04
1.E+03
R_TACH = 250 kΩ
R_TACH = 500 kΩ
1.E–09
1.E–07
1.E–08
1.E–10
C
– Oscillator Timing Capacitance – F
T
Figure 3
9
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ꢀ ꢁꢁꢂ ꢃ ꢂ ꢃ ꢄ ꢀ ꢁꢁ ꢅ ꢃꢂ ꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
programming the tachometer
The UCC3626 tachometer consists of a precision 5-V monostable, triggered by either a rising or falling edge
on any of the three Hall inputs, HALLA, HALLB, and HALLC. The resulting TACH_OUT waveform is a variable
duty-cycle square wave whose frequency is proportional to motor speed, as given by:
V P
TACH_OUT +
Hz
20
where P is the number of motor pole pairs and V is motor velocity in RPM.
(3)
The on time of the monostable is programmed via timing resistor R_TACH and capacitor C_TACH according
to the following equation:
t
+ R_TACH C_TACH sec
ON
(4)
Figure 5 provides a graph of on times for various combinations of R_TACH and C_TACH. On time is typically
set to a value less than the minimum TACH_OUT period as given by:
20
t
+
sec
PERIOD (min)
V
P
MAX
(5)
where P is the number of motor pole pairs and V is motor velocity in RPM.
TACHOMETER ON-TIME
vs
TIMING CAPACITANCE
1.E+00
R_TACH = 500 kΩ
1.E–01
1.E–02
1.E–03
R_TACH = 250 kΩ
SYNCH
R_TACH = 100 kΩ
WITHOUT SYNCH
1.E–04
1.E–05
CT
WITH SYNCH
R_TACH = 25 kΩ
1.E–08
1.E–06
1.E–10
1.E–09
1.E–07
1.E–06
C_TACH – Tachometer Timing Capacitance – F
Figure 4. Oscillator Waveforms
Figure 5
10
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ꢀꢁꢁ ꢂ ꢃꢂ ꢃ ꢄ ꢀ ꢁꢁ ꢅꢃ ꢂꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
The TACH_OUT signal can be used to close a digital velocity loop using a microcontroller, as shown in Figure 6,
or directly low-pass filtered in an analog implementation, Figure 7.
UCC3626
4
5
6
R_TACH
C_TACH
CT
MC68HC11
AD558
DB0–DB7
PB0–PB7
PC0
VCE
14 PWM_NI
VCS VOUT
13 PWM_I
V SENSE
OUT
V SELECT
OUT
IC1
3
TACH_OUT
UDG–97188
Figure 6. Digital Velocity Loop Implementation Using MC68HC11
two quadrant vs four quadrant control
Figure 8 illustrates the four possible quadrants of operation for a motor. Two-quadrant control refers to a system
in which operation is limited to quadrants I and III (where torque and velocity are in the same direction). With
a two-quadrant brushless dc amplifier, there are no provisions other than friction to decelerate the load, limiting
the approach to less demanding applications. Four-quadrant controllers, on the other hand, provide controlled
operation in all quadrants, including II and IV, where torque and rotation are of opposite direction.
UCC3626
VREF
VELOCITY
CW
2
4
5
6
R_TACH
C_TACH
CT
II
I
TORQUE
CW
CCW
14 PWM_NI
13 PWM_I
III
IV
–
+
3
TACH_OUT
CCW
UDG–97189
UDG–01118
Figure 8. Four Quadrants of Operation
Figure 7. Simple Analog Velocity Loop
11
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
When configured for two-quadrant operation, (QUAD=0), the UCC3626 modulates only the low-side devices
of the output power stage. The current paths within the output stage during the PWM on- and off-times are
illustrated in Figure 9. During the on interval, both switches are on, and current flows through the load down to
ground. During the off time, the lower switch is shut off, and the motor current circulates through the upper half
bridge via the flyback diode. The motor is assumed to be operating in either quadrant I or III.
If operation is attempted in quadrants II or IV by changing the DIR bit and reversing the torque, switches 1 and
4 are turned off and switches 2 and 3 turned on. Under this condition motor current very quickly decays, reverses
direction and increases until the control threshold is reached. At this point, switch 2 turns off and current once
again circulates in the upper half bridge. However, in this case, the motor’s BEMF is in phase with the current,
(i.e. the motor’s direction of rotation has not yet changed.) Figure 10 illustrates the current paths when operating
in this mode. Under these conditions there is nothing to limit the current other than motor and drive impedance.
These high-circulating currents can result in damage to the power devices in addition to high, uncontrolled
torque.
VMOT
VMOT
S3
S5
S1
S3
S5
S1
IOFF
IPHASE
IOFF
ION
IPHASE
+ BEMF –
+ BEMF –
ION
S4
S2
S6
S4
S2
S6
UDG–01119
UDG–01120
Figure 10. Two-Quadrant Reversal
Figure 9. Two-Quadrant Chopping
12
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ꢀꢁꢁ ꢂ ꢃꢂ ꢃ ꢄ ꢀ ꢁꢁ ꢅꢃ ꢂꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
By pulse width modulating both the upper and lower power devices (QUAD=1), motor current always decays
during the PWM off time, eliminating any uncontrolled circulating currents. In addition, current always flows
through the current sense resistor, providing a suitable feedback signal. Figure 11 illustrates the current paths
during a four-quadrant torque reversal. Motor drive waveforms for both two- and four-quadrant operation are
illustrated in Figure 12.
VMOT
S3
S5
S1
IPHASE
+ BEMF –
IOFF
ION
S4
S2
S6
UDG–01121
Figure 11. Four-Quadrant Reversal
13
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ꢀ
ꢁ
ꢁ
ꢂ
ꢃ
ꢂ
ꢃ
ꢄ
ꢀ
ꢁ
ꢁ
ꢅ
ꢃ
ꢂ
ꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
ROTOR POSITION IN ELECTRICAL DEGREES
0
60
120 180 240 300 360 420 480 540 600 660 720
H1
H2
SENSOR
INPUTS
H3
101 100 110 010 011 001 101 100
010 011 001
Code
110
AHI
HIGH SIDE
OUTPUTS
QUAD=0
BHI
CHI
ALO
BLO
LOW SIDE
OUTPUTS
QUAD=0
CLO
+
A
0
–
+
MOTOR
PHASE
CURRENTS
QUAD=0
B
0
–
+
C
0
–
AHI
BHI
HIGH SIDE
OUTPUTS
QUAD=1
CHI
ALO
BLO
LOW SIDE
OUTPUTS
QUAD=1
CLO
+
A
0
–
+
MOTOR
PHASE
CURRENTS
QUAD=1
B
0
–
+
C
0
–
100% Duty Cycle PWM
50% Duty Cycle PWM
UDG–97190
Figure 12. Motor Drive and Current Waveforms for Two-Quadrant (QUAD=0)
and Four-Quadrant (QUAD=1) Operation
14
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ꢀꢁꢁ ꢂ ꢃꢂ ꢃ ꢄ ꢀ ꢁꢁ ꢅꢃ ꢂꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
power stage design considerations
The flexible architecture of the UCC3626 requires the user to pay close attention to the design of the power
output stage. Two- and four-quadrant applications not requiring the brake function are able to use the power
stage approach illustrated in Figure 13a. In many cases the body diode of the MOSFET can be used to reduce
parts count and cost. If efficiency is a key requirement, Schottky diodes can be used in parallel with the switches.
UDG–97190
VMOT
VMOT
VMOT
TO
TO
TO
MOTOR
MOTOR
MOT
CURRENT
SENSE
CURRENT
SENSE
CURRENT
SENSE
(a)
(b)
(c)
UDG–01122
CURRENT SENSE
TWO
QUADRANT
FOUR
QUADRANT
SAFE
BRAKING
POWER
REVERSAL
PULSE-BY-
AVERAGE
PULSE
(a)
(b)
(c)
YES
YES
YES
YES
NO
NO
YES
YES
Four-Quad Only
No
YES
YES
NO
YES
YES
Four-Quad Only
YES
YES
Figure 13. Power Stage Topologies
If the system requires a braking function, diodes must be added in series with the lower power devices and the
lower flyback diodes must be returned to ground, as pictured in Figure 13b, and 13c. This requirement prevents
brake currents from circulating in the lower half bridge and bypassing the sense resistor. In addition, the
combination of braking and four-quadrant control necessitates an additional resistor in the diode path to sense
current during the PWM off time as illustrated in Figure 13c.
15
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SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
current sensing
The UCC3626 includes a differential current-sense amplifier with a fixed gain of five, along with an absolute
value circuit. The current-sense signal should be low pass filtered to eliminate leading-edge spikes. In order to
maximize performance, the input impedance of the amplifier should be balanced. If the sense voltage must be
trimmed for accuracy reasons, a low-value input divider or a differential divider should be used to maintain
impedance matching, as shown in Figure 14.
R
R
F
F
SNS_NI
SNS_NI
R
F
R
ADJ
R
ADJ
R
C
R
C
F
S
F
S
R
R
F
F
SNS_I
SNS_I
R
<< R
F
ADJ
(a)
(b)
UDG–01123
Figure 14. (a) Differential Divider and (b) Low-Value Divider
With four-quadrant chopping, motor current always flows through the sense resistor. However, during the
flyback period the polarity across the sense resistor is reversed. The absolute value amplifier cancels the
polarity reversal by inverting the negative sense signal during the flyback time, see Figure 15. Therefore, the
output of the absolute value amplifier is a reconstructed analog of the motor current, suitable for protection as
well as feedback loop closure.
VMOT
Ip
Is
S3
IPHASE
S5
S1
Ip
If
+ BEMF –
IOFF
5*Ip
ION
S4
S2
S6
Im
Is
X5
Im
UDG–01124
If
Figure 15. Current Sense Amplifier Waveform
16
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ꢀꢁꢁ ꢂ ꢃꢂ ꢃ ꢄ ꢀ ꢁꢁ ꢅꢃ ꢂꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
Figure 17 illustrates a simple 175-V, 2-A, two-quadrant velocity controller using the UCC3626. The power stage
is designed to operate with a rectified off-line supply using IR2210s to provide the interface between the low
voltage control signals and the power MOSFETs. The power topology illustrated in Figure 13c is implemented
in order to provide braking capability.
SIGN/MAGNITUDE CONVERTER
11
IOUT
10 kΩ
10 kΩ
10 kΩ
10 kΩ
–
–
U1
U5
VELOCITY
COMMAND
± 5 V
+
+
–
U8
13 PWM_I
–
10 kΩ
U6
+
+
CURRENT
ERROR
AMPLIFIER
CURRENT
MAGNITUDE
U7
21 DIR
CURRENT SIGN
BIPOLAR
10 kΩ
10 kΩ TACH GAIN
TACHOMETER
FILTER
–
4.99 kΩ
4.99 kΩ
U3
–
U2
+
3
8
TACH_OUT
+
2N7002
DIR_OUT
UDG–99061
Figure 16. Four-Quadrant Control Loop
The controller’s speed command is set by potentiometer R30, while the speed feedback signal is obtained by
low-pass filtering and buffering the TACH_OUT signal using R11 and C9. Small signal compensation of the
velocity control loop is provided by amplifier U5A, whose output is used to control the PWM duty cycle. The
integrating capacitor, C8, places a pole at 0 Hz and a zero in conjunction with R10. This zero can be used to
cancel the low-frequency motor pole and to cross the loop-over with a –20 dB gain response.
Four-quadrant applications require the control of motor current. Figure 16 illustrates a sign/magnitude current
control loop within an outer bipolar velocity loop using the UCC3626. U1 serves as the velocity loop error
amplifier and accepts a ± 5-V command signal. Velocity feedback is provided by low-pass filtering and scaling
the TACH_OUT signal using U2. The direction output switch, DIR_OUT, and U3 set the polarity of the
tachometer gain according to the direction of rotation. The output of the velocity error amplifier, U1, is then
converted to sign/magnitude form using U5 and U6. The sign portion is used to drive the DIR input while the
magnitude commands the current error amplifier, U8. Current feedback is provided by the internal current sense
amplifier via the IOUT pin.
17
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ꢀ ꢁꢁꢂ ꢃ ꢂ ꢃ ꢄ ꢀ ꢁꢁ ꢅ ꢃꢂ ꢃ
SLUS318B – APRIL 1999 – REVISED JANUARY 2002
APPLICATION INFORMATION
UDG–01117
Figure 17. Two-Quadrant Velocity Controller
18
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
UCC2626DW
UCC2626DWG4
UCC2626PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
PW
PW
DW
DW
DW
DW
N
28
28
28
28
28
28
28
28
28
28
28
28
20
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
Purchase Samples
Purchase Samples
Request Free Samples
Request Free Samples
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Request Free Samples
Request Free Samples
TSSOP
TSSOP
SOIC
50
Green (RoHS
& no Sb/Br)
UCC2626PWG4
UCC3626DW
50
Green (RoHS
& no Sb/Br)
20
Green (RoHS
& no Sb/Br)
UCC3626DWG4
UCC3626DWTR
UCC3626DWTRG4
UCC3626N
SOIC
20
Green (RoHS
& no Sb/Br)
SOIC
1000
1000
13
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
PDIP
Green (RoHS
& no Sb/Br)
UCC3626NG4
UCC3626PW
PDIP
N
13
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
PW
PW
50
Green (RoHS
& no Sb/Br)
UCC3626PWG4
50
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2010
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC3626DWTR
SOIC
DW
28
1000
330.0
32.4
11.35 18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 28
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
UCC3626DWTR
1000
Pack Materials-Page 2
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