UCC3751DTRG4 [TI]
SPECIALTY TELECOM CIRCUIT, PDSO16, SOIC-16;
| 型号： | UCC3751DTRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY TELECOM CIRCUIT, PDSO16, SOIC-16 电信 信息通信管理 光电二极管 电信集成电路 |
| 文件： | 总9页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC2751
UCC3751
Single Line Ring Generator Controller
FEATURES
DESCRIPTION
• Novel Topology for Low-Cost, Efficient The UCC3751 controller is designed for driving a power stage that gener-
Generation of Ring Voltage
ates low frequency, high voltage sinusoidal signals for telephone ringing
applications. The controller and the power stage are most suitable for sin-
gle line applications where low cost, high efficiency and minimum parts
count are critical. In addition to providing the sinusoidal ringing signal, the
controller and the power stage are designed to provide the required DC
voltage across the output when the phone goes off-hook. The DC voltage is
also added as the offset to the ringing signal. This feature eliminates the
need to have a separate talk battery voltage power supply as well as relays
and drivers to switch between the ringing voltage and the talk battery.
• Provides DC Offset and “Talk Battery”
Voltage for Off-Hook Conditions
• Selectable 20, 25 and 50 Hz Ring
Frequency
• Secondary (AC) Current Limiting
Allows Removal of AC Voltage under
Off-Hook Conditions
The UCC3751 directly drives primary side switches used to implement a
push-pull resonant converter topology and transformer coupled sampling
switches located on the secondary of the converter. For normal ring signal
generation, the primary switching frequency and secondary sampling fre-
quency are precisely offset from each other by the ringing frequency to pro-
duce a high voltage low frequency alias signal at the output. The off-hook
condition is detected by sensing the AC current and when AC limit is ex-
ceeded, the sampling frequency is set to be equal to the primary switching
frequency to produce a DC output.
• Primary Current Limiting to turn Power
Stage off under Fault Conditions
• Operates from a Single 12V Supply
The drive signal frequencies are derived from a high frequency (3579545
Hz) crystal. The primary switching frequency is 89.488 kHz and the sam-
pling frequency is 20, 25 or 50 Hz less depending on the status of fre-
quency select pins FS0 and FS1.
The circuits described in this datasheet are covered under US Patent #5,663,878 and other patents pending.
TYPICAL APPLICATIONS CIRCUIT
D1
R
SENSE
L
IN
T1
DC SIGNAL
C
DC
V
IN
V
V
1
12V
AC SIGNAL
C
C
F
R2
L
L
R
R
SAMPLING
CIRCUIT
OUT
12V
C
BYP1
9
12
2
6
4
C
R1
N:1
C
BYP2
VS12
11 DRV1
DRVS
RINGEN
OHD
VDD
ENABLE 10
Q1
UCC3751
5
DCLIM
DELAY
1
Q2
13 DRV2
GND
XTAL2 15
PGND
14
FS0
7
FS1
8
XTAL1
16
3
UDG-98047
3.579545MHz
APRIL 1999 - REVISED AUGUST 2000 - SLUS267B
UCC2751
UCC3751
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Analog Inputs (OHD, DCLIM, XTAL1, XTAL2)
Maximum Forced Voltage. . . . . . . . . . . . . . . . . . . . –0.3 to 5V
Logic Inputs
DIL-16, SOIC-16 (TOP VIEW)
N or D Packages
Maximum Forced Voltage . . . . . . . . . . . . . . . . . . –0.3 to 7.5V
Reference Output Current (VDD). . . . . . . . . . . Internally Limited
Output Current (DRV1, DRV2, DRVS) Pulsed . . . . . . . . . . 1.5A
Operating Junction Temperature . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
DELAY
RINGEN
GND
16 XTAL1
15 XTAL2
14 PGND
13 DRV2
12 DRVS
11 DRV1
1
2
3
4
5
6
7
8
Note: Unless otherwise indicated, voltages are referenced to
ground and currents are positive into, negative out of, the spe-
cific terminals. Pulsed is defined as a less than 10% duty cycle
V
DD
DCLIM
OHD
FS0
with a maximum duration of 500 S.
10 ENABLE
FS1
9
VS12
BLOCK DIAGRAM
ENABLE 10
XTAL2 15
MODULO
20
COUNTER
MODULO
2
COUNTER
XTAL1 16
11 DRV1
13 DRV2
12 DRVS
14 PGND
ONE-SHOT
DCLIM
5
PROGRAMMABLE
COUNTER
300mV
CLR
CLK
2 BIT
A/D
ONE-SHOT
1/FOSC
DELAY
OHD
1
6
300mV
MODULO
1,800
COUNTER
RINGEN
FS1
2
8
2/FOSC
MODULO
40
COUNTER
3
9
4
GND
VS12
VDD
MODULO
3,560
COUNTER
ONE-SHOT
5 VOLT
REFERENCE
FS0
7
MODULO
4,480
COUNTER
4.5V
UDG-98020
2
UCC2751
UCC3751
Table I. Frequency selectability decoding.
RINGEN
OHD
FS1
FS0
FDRVS
FDRV–
FS1
FS0
MODE
Sine Wave
Frequency (Hz)
FDRVS
20Hz
25Hz
50Hz
0.0Hz
0.0Hz
0
0
1
0
1
1
1
1
3
2
20
25
50
0
1
1
1
0
X
0
0
0
X
1
0
0
1
X
X
0
1
0
X
X
89.469kHz
89.464kHz
89.439kHz
89.489kHz
89.489kHz
0
1
1
OHD = 0.5
0
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the
UCC3751 and –40°C to +85°C for the UCC2751, TA = TJ.
PARAMETER
V12 Supply Current Section
Supply Current
TEST CONDITIONS
MIN
TYP
MAX UNITS
ENABLE = 0V
ENABLE = 5V
1.0
1.0
3.0
3.0
mA
mA
Internal Reference with External Bypass Section
Output Voltage (VDD)
4.85
5
5
5
5.15
20
V
Load Regulation
0mA ≤ IVDD ≤ 2mA
mV
mV
mA
Line Regulation
10V < VS12 < 13V, IVDD = 1mA
VDD = 0
3
20
Short Circuit Current
Output Drivers Section (DRV1, DRV2)
Pull Up Resistance
Pull Down Resistance
Rise Time
10
I
LOAD = 10mA to 20mA
6
6
15
15
ILOAD = 10mA to 20mA
CLOAD = 1nF
50
50
100
100
nS
nS
Fall Time
CLOAD = 1nF
Output Drivers Section (DRVS)
Pull Up Resistance
Pull Down Resistance
Sample Pulse-Width
Rise Time
I
LOAD = 10mA to 20mA
4
4
10
10
ILOAD = 10mA to 20mA
Mode 1 and 2, (Note 1)
CLOAD = 1nF
240
250
280
50
50
320
100
100
nS
nS
nS
Fall Time
CLOAD = 1nF
Current Limit Section
OHD Threshold
300
350
350
mV
nA
OHD Input Current
DCLIM Threshold
VOHD = 0V
–900 –100
250 300
mV
nA
DCLIM Input Current
Frequency Section (Note 1)
Primary Switching Frequency
Sampling Switching Frequency
VDCLIM = 0V
–900 –100
All cases 3.579545 MHz Crystal
FS0 = 0, FS1 = 0, Mode 1, (Note 1)
FS0 = 1, FS1 = 0, Mode 1
89489
89469
89464
89439
Hz
Hz
Hz
Hz
FS0 = 0, FS1 = 1, Mode 1
3
UCC2751
UCC3751
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications hold for TA = 0°C to 70°C for the
UCC3751 and –40°C to +85°C for the UCC2751, TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Off-Hook Sampling Delay (Note 2)
td0
td1
td2
td3
td4
V
DELAY < 0.9V
0
20
nS
nS
nS
nS
nS
1.1V < VDELAY < 1.9V
2.1V < VDELAY < 2.9V
3.1V < VDELAY < 3.9V
4.1V < VDELAY
252
504
756
280
560
840
308
616
924
1008 1120 1232
Note 1. Frequency setting is as shown in the Frequency Selectability Decoding Table. Sine Wave Frequency = Primary – Sampling
Frequency.
Note 2. The delay function will delay the sample pulse from the rising edge of DRV2 to allow adjustment of the DC level provided
during Mode 2.
PIN DESCRIPTIONS
frequencies (20,25 and 50 Hz). See Note 1 in the spec
table.
DCLIM: Primary current sense input. Signal proportional
to the primary switch current. All outputs are turned off
when a threshold of 300mV is exceeded on this pin.
This current limit works on a cycle-by-cycle basis.
GND: Reference point for all the internal voltages and
common return for the device.
DELAY: A resistive divider from VDD to GND is pro-
grammed and fed into DELAY pin. The voltage at this pin
sets the phase difference between the sampling pulses
and primary pulses under off-hook condition. By pro-
gramming the delay, desired level of DC voltage can be
attained at the ringer output when the OHD threshold is
exceeded.
OHD: Secondary current sense input. Voltage propor-
tional to output current DC level is fed into this pin and
compared to an internal threshold of 300mV. If the thresh-
old is exceeded, the sampling scheme is changed to
eliminate the AC component in the output voltage as re-
quired by the off-hook condition.
PGND: Return point for the output drivers. Connect to
GND at a single point in the circuit.
DRV1, DRV2: Low impedance driver outputs for the pri-
mary switches.
RINGEN: Logic input used to determine when the ring
signal is needed. When this signal is high and OHD low,
normal ring signal is available at the output of the ring
generator.
DRVS: Low impedance driver output for the sampling
switch(es). The pulse width of this output is 280ns.
Typically, a pulse transformer is used to couple the short
sampling pulses at DRVS to the floating sampling
switch(es).
VDD: Internal regulated 5V supply. This voltage is used to
power all the internal precision circuits of the IC. This pin
needs to be bypassed to GND with ceramic capacitor.
ENABLE: Logic input which turns off the outputs when
low.
VS12: External 12V power supply for the IC. Powers VDD
and provides voltage for the output drivers.
FS0, FS1: Frequency select pins for determining the dif-
ference frequency between primary and secondary
pulses under normal operation. These pins can be hard-
wired to GND or VDD to get one of the available output
XTAL1, XTAL2: Pins for connecting precision Crystal to
attain the accurate output frequencies. An external
square-wave pulse can also be applied to XTAL2 if XTAL1
is tied to VDD/2.
4
UCC2751
UCC3751
APPLICATION INFORMATION
Power Stage Operation
transformer. Typical pulsewidth of the sampling signal is
280ns. As a result of sampling, the resultant output signal
matches the secondary voltage in amplitude and has a
low output frequency desired for ring generation.
The power stage used for the UCC3751 application has
two distinct switching circuits which together produce the
required low frequency signal on the output. The primary
side switching circuit consists of a current fed push-pull
resonant circuit that generates the high frequency sinu-
soidal waveform across the transformer winding. The op-
eration of this type of circuit is extensively covered in
Unitrode Application notes U-141 and U-148. Resonant
components CR1, CR2, LR, N should be chosen so that
the primary and secondary resonances are well
matched. Also, for the UCC3751 operation, switching fre-
quency is fixed by crystal selection. So, the resonant
components must be selected to yield a resonant fre-
quency close enough to the switching frequency to get a
low distortion sine-wave. Practically, since it is impossi-
ble to get an exact match between the two frequencies,
the switching frequency should always be higher than
the resonant frequency to ensure low distortion and take
advantage of ZVT operation. Switches Q1 and Q2 are
pulsed at 50% duty cycle at the switching frequency
(89.489 kHz) determined by a crystal (3.579545 MHz)
connected to the UCC3751. The input voltage for the
resonant stage (typically 12V) determines the voltage
stress of Q1 and Q2. Transformer turns ratio is deter-
mined by the output voltage requirements. On the sec-
ondary side, the high frequency waveform is sampled at
a predetermined frequency (e.g. 89.469 kHz) which dif-
fers from the primary switching frequency by the desired
output frequency (e.g. 20 Hz). The sampling is accom-
plished using a bi-directional switching circuit as shown
in Figure 2 and Figure 3. Figure 2 shows the sampling
mechanism consisting of two back-to-back FET switches
allowing current flow in both directions. The sampling
can also be done with a single active switch and a
full-bridge rectifier as shown in Fig. 3. The DRVS pin of
the UCC3751 provides the drive signal for the sampling
switch(es) and this signal is coupled through a pulse
The secondary winding of the power transformer also has
a tap (or a separate winding) to generate a loosely regu-
lated DC voltage. This DC voltage can be used to offset
the ring generator output. The UCC3751 is also config-
ured such that the AC output can go to zero under certain
conditions. Table 2 provides the logic levels for different
operating modes of UCC3751. Operation in mode 2 is
achieved by altering the sampling frequency to match the
switching frequency and sampling the secondary AC volt-
age at zero crossings. As a result, the resultant total out-
put voltage between VOUT and GND is the semi-regulated
DC voltage achieved through the tapped secondary. This
feature allows the circuit to operate under off-hook and
idle conditions when only the DC portion of the voltage is
required. The activation of this mode occurs when the
OHD voltage exceeds a set threshold or RINGEN is low.
The incorporation of this mode eliminates any need for
external relays or switching circuits as well as eliminating
the need for an additional power supply for powering the
phone. The DC voltage level can be fine tuned by adjust-
ing the voltage on the DELAY pin of the UCC3751. This
pin sets the sampling delay time during the off-hook
mode and allows a DC voltage to be developed between
V1 and VOUT during this mode. Fig. 1 illustrates the oper-
ation of this mode. When the DELAY is set between 0
and 1V, the sampling is done in phase with the primary
switching instances (at points A), leading to an average
voltage of 0V between V1 and VOUT for a sinusoidal sec-
ondary signal. If DELAY is set to another level, the sam-
pling instance shifts (e.g. to point B) leading to an
effective voltage VB being developed between V1 and
VOUT. The actual VOUT is the sum of VB and the DC off-
set voltage derived from the additional (or tapped) wind-
ing (V1).
Table II. Operating mode selection.
OHD RINGEN
High
Condition
Sampling Output Mode
Continuous Ringing
Low
Low
Frequency Offset from Primary (Mode 1)
Idle (On Hook, No Ringing)
Low
Synchronized to Primary Frequency with Phase
Controlled by DELAY (Mode 2)
Off-Hook
High
Low
X (Low/High)
High/Low
Mode 2
Cadenced Ringing
Mode 1/Mode 2
5
UCC2751
UCC3751
TRANSFORMER SECONDARY
VOLTAGE
VB
B
A
B
A
B
0
V
0
DRV2
Figure 1. Effects of sampling delay during off-hook operation.
TO TRANSFORMER
TO TRANSFORMER
DRVS
DRVS
TO OUTPUT
TO OUTPUT
Figure 2. Sampling circuit with two FETs.
Figure 3. Sampling circuit with single FET and
full-bridge rectifier.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
6
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TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
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to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI’s publication of information regarding any third party’s products
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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
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Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
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Post Office Box 655303
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Copyright 2001, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
UCC3751D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3751DTR
UCC3751DTRG4
UCC3751N
SOIC
SOIC
PDIP
PDIP
D
D
N
N
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
UCC3751NG4
Green (RoHS & CU NIPDAU N / A for Pkg Type
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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their products and applications using TI components. To minimize the risks associated with customer products
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