UCC3808-1 [TI]
Low Power Current Mode Push-Pull PWM; 低功耗电流模式推挽PWM
| 型号： | UCC3808-1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Power Current Mode Push-Pull PWM |
| 文件： | 总7页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
Low Power Current Mode Push-Pull PWM
FEATURES
DESCRIPTION
• 130µA Typical Starting Current
The UCC3808 is a family of BiCMOS push-pull, high-speed, low power,
pulse width modulators. The UCC3808 contains all of the control and drive
circuitry required for off-line or DC-to-DC fixed frequency current-mode
switching power supplies with minimal external parts count.
• 1mA Typical Run Current
• Operation to 1MHz
• Internal Soft Start
The UCC3808 dual output drive stages are arranged in a push-pull configu-
ration. Both outputs switch at half the oscillator frequency using a toggle
flip-flop. The dead time between the two outputs is typically 60ns to 200ns
depending on the values of the timing capacitor and resistors, thus limits
each output stage duty cycle to less than 50%.
• On Chip Error Amplifier With 2MHz
Gain Bandwidth Product
• On Chip VDD Clamping
The UCC3808 family offers a variety of package options temperature range
options, and choice of undervoltage lockout levels. The family has UVLO
thresholds and hysteresis options for off-line and battery powered systems.
Thresholds are shown in the table below.
• Dual Output Drive Stages In Push-Pull
Configuration
• Output Drive Stages Capable Of
500mA Peak Source Current, 1A
Peak Sink Current
Part Number
UCCx808-1
UCCx808-2
Turn on Threshold
Turn off Threshold
12.5V
4.3V
8.3V
4.1V
BLOCK DIAGRAM
FB
2
COMP
1
CS
3
8
7
VDD
OVERCURRENT
COMPARATOR
PEAK CURRENT
COMPARATOR
14V
0.75V
2.0V
0.5V
2.2V
OUTA
VDD OK
VDD–1V
OSCILLATOR
S
R
S
R
0.8V
PWM
COMPARATOR
Q
Q
PWM
LATCH
1.2R
Q
Q
S
Q
R
T
VDD
0.5V
R
SOFT START
6
5
OUTB
GND
VOLTAGE
REFERENCE
SLOPE = 1V/ms
4
RC
UDG-99076
04/99
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
Supply Voltage (IDD ≤ 10mA) . . . . . . . . . . . . . . . . . . . . . . . 15V
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
OUTA/OUTB Source Current (peak) . . . . . . . . . . . . . . . . –0.5A
OUTA/OUTB Sink Current (peak) . . . . . . . . . . . . . . . . . . . 1.0A
Analog Inputs (FB, CS) . –0.3V to VDD+0.3V, not to exceed 6V
Power Dissipation at TA = 25°C (N Package). . . . . . . . . . . . 1W
Power Dissipation at TA = 25°C (D Package) . . . . . . . . 650mW
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C
DIL-8, SOIC-8 (Top View)
J or N Package, D Package
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations
and considerations of package.
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS: Unless otherwise specified,TA = 0°C to 70°C for the UCC3808-X, –40°C to 85°C for
the UCC2808-X and –55°C to 125°C for the UCC1808-X, VDD = 10V (Note 6), 1µF capacitor from VDD to GND, R = 22kΩ,
C = 330pF. TA = TJ.
PARAMETER
Oscillator Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Oscillator Frequency
Oscillator Amplitude/VDD
Error Amplifier Section
Input Voltage
175
194
0.5
213
kHz
V/V
(Note 1)
0.44
0.56
COMP = 2V
1.95
–1
2
2.05
1
V
Input Bias Current
Open Loop Voltage Gain
COMP Sink Current
COMP Source Current
PWM Section
µA
dB
mA
mA
60
80
2.5
FB = 2.2V, COMP = 1V
FB = 1.3V, COMP = 3.5V
0.3
–0.2
–0.5
Maximum Duty Cycle
Minimum Duty Cycle
Current Sense Section
Gain
Measured at OUTA or OUTB
COMP = 0V
48
49
50
0
%
%
(Note 2)
1.9
2.2
0.5
100
2.5
0.55
200
V/V
V
Maximum Input Signal
CS to Output Delay
CS Source Current
CS Sink Current
COMP = 5V (Note 3)
COMP = 3.5V, CS from 0 to 600mV
0.45
ns
nA
mA
V
–200
5
CS = 0.5V, RC = 5.5V (Note 7)
CS = 0V
10
0.75
0.8
Over Current Threshold
COMP to CS Offset
Output Section
0.7
0.35
0.8
1.2
V
OUT Low Level
I = 100mA
0.5
0.5
25
1
1
V
V
OUT High Level
I = –50mA, VDD – OUT
CL = 1nF
Rise Time
60
60
ns
ns
Fall Time
CL = 1nF
25
Undervoltage Lockout Section
Start Threshold
UCCx808-1 (Note 6)
UCCx808-2
11.5
4.1
12.5
4.3
13.5
4.5
V
V
2
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
ELECTRICAL CHARACTERISTICS: Unless otherwise specified,TA = 0°C to 70°C for the UCC3808-X, –40°C to 85°C for
the UCC2808-X and –55°C to 125°C for the UCC1808-X, VDD = 10V (Note 6), 1µF capacitor from VDD to GND, R = 22kΩ,
C = 330pF. TA = TJ.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
Undervoltage Lockout Section (cont.)
Minimum Operating Voltage After Start
UCCx808-1
UCCx808-2
UCCx808-1
UCCx808-2
7.6
3.9
3.5
0.1
8.3
4.1
4.2
0.2
9
V
V
V
V
4.3
5.1
0.3
Hysteresis
Soft Start Section
COMP Rise Time
FB = 1.8V, Rise from 0.5V to 4V
3.5
20
ms
Overall Section
Startup Current
VDD < Start Threshold
130
1
260
2
µA
mA
V
Operating Supply Current
VDD Zener Shunt Voltage
FB = 0V, CS = 0V (Note 5 and 6)
IDD = 10mA (Note 4)
13
14
15
Note 1: Measured at RC. Signal amplitude tracks VDD.
∆V
Note 2: Gain is defined by A = COMP , 0 VCS 0.4V.
∆VCS
Note 3: Parameter measured at trip point of latch with FB at 0V.
Note 4: Start threshold and Zener Shunt threshold track one another.
Note 5: Does not include current in the external oscillator network.
Note 6: For UCCx808-1, set VDD above the start threshold before setting at 10V.
Note 7: The internal current sink on the CS pin is designed to discharge an external filter capacitor. It is not intended to be a DC
sink path.
PIN DESCRIPTIONS
COMP: COMP is the output of the error amplifier and the stages. Both stages are capable of driving the gate of a
input of the PWM comparator. The error amplifier in the power MOSFET. Each stage is capable of 500mA peak
UCC3808 is a true low-output impedance, 2MHz opera- source current, and 1A peak sink current.
tional amplifier. As such, the COMP pin can both source
The output stages switch at half the oscillator frequency,
and sink current. However, the error amplifier is internally
in a push/pull configuration. When the voltage on the RC
current limited, so that zero duty cycle can be externally
pin is rising, one of the two outputs is high, but during fall
forced by pulling COMP to GND.
time, both outputs are off. This “dead time” between the
The UCC3808 family features built-in full cycle soft start. two outputs, along with a slower output rise time than fall
Soft start is implemented as a clamp on the maximum time, insures that the two outputs can not be on at the
COMP voltage.
same time. This dead time is typically 60ns to 200ns and
depends upon the values of the timing capacitor and re-
sistor.
CS: The input to the PWM,
overcurrent comparators. The overcurrent comparator is
peak current, and
only intended for fault sensing. Exceeding the The high-current output drivers consist of MOSFET out-
overcurrent threshold will cause a soft start cycle. An in- put devices, which switch from VDD to GND. Each out-
ternal MOSFET discharges the current sense filter ca- put stage also provides a very low impedance to
pacitor to improve dynamic performance of the power overshoot and undershoot. This means that in many
converter.
cases, external schottky clamp diodes are not required.
FB: The inverting input to the error amplifier. For best RC: The oscillator programming pin. The UCC3808’s os-
stability, keep FB lead length as short as possible and FB cillator tracks VDD and GND internally, so that variations
stray capacitance as small as possible.
in power supply rails minimally affect frequency stability.
Fig. 1 shows the oscillator block diagram.
GND: Reference ground and power ground for all func-
tions. Due to high currents, and high frequency operation Only two components are required to program the oscil-
of the UCC3808, a low impedance circuit board ground lator, a resistor (tied to the VDD and RC), and a capaci-
plane is highly recommended.
tor (tied to the RC and GND). The approximate oscillator
frequency is determined by the simple formula:
OUTA and OUTB: Alternating high current output
3
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
PIN DESCRIPTIONS (cont.)
1.41
VDD: The power input connection for this device. Al-
though quiescent VDD current is very low, total supply
current will be higher, depending on OUTA and OUTB
current, and the programmed oscillator frequency. Total
VDD current is the sum of quiescent VDD current and
the average OUT current. Knowing the operating fre-
quency and the MOSFET gate charge (Qg), average
OUT current can be calculated from
fOSCILLATOR
=
RC
where frequency is in Hertz, resistance in Ohms, and ca-
pacitance in Farads. The recommended range of timing
resistors is between 10kΩ and 200kΩ and range of tim-
ing capacitors is between 100pF and 1000pF. Timing re-
sistors less than 10kΩ should be avoided.
For best performance, keep the timing capacitor lead to
GND as short as possible, the timing resistor lead from
VDD as short as possible, and the leads between timing
components and RC as short as possible. Separate
ground and VDD traces to the external timing network
are encouraged.
I
= Qg • F, where F is frequency.
OUT
To prevent noise problems, bypass VDD to GND with a
ceramic capacitor as close to the chip as possible along
with an electrolytic capacitor. A 1µF decoupling capacitor
is recommended.
UDG-97009
The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but both
stages are off during the RC fall time. The output stages switch a ½ the oscillator frequency, with guaranteed duty cycle of <
50% for both outputs.
Figure 1. Block diagram for oscillator.
APPLICATION INFORMATION
A 200kHz push-pull application circuit with a full wave rec- Isolation is provided by an optocoupler with regulation
tifier is shown in Fig. 2. The output, V , provides 5V at done on the secondary side using the UC3965 Precision
O
75W maximum and is electrically isolated from the input. Reference with Low Offset Error Amplifier. Small signal
Since the UCC3808 is a peak current mode controller the compensation with tight voltage regulation is achieved
2N2222A emitter following amplifier (buffers the CT wave- using this part on the secondary side. Many choices ex-
form) provides slope compensation which is necessary ist for the output inductor depending on cost, volume,
for duty ratios greater than 50%. Capacitor decoupling is and mechanically strength. Several design options are
very important with a single ground IC controller and a iron powder, molypermalloy (MPP), or a ferrite core with
an air gap as shown here. The main power transformer
is a low profile design, EFD size 25, using Magnetics
Inc. P material which is a good choice at this frequency
and temperature. The input voltage may range from 36V
dc to 72V dc. Refer to application note U-170 for addi-
tion design information.
1µF is suggested as close to the IC as possible. The con-
troller supply is a series RC for startup, paralleled with a
bias winding on the output inductor used in steady state
operation.
4
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
APPLICATION INFORMATION (cont.)
UDG-97010-1
Figure 2. Typical application diagram.
5
UCC1808-1/-2
UCC2808-1/-2
UCC3808-1/-2
TYPICAL CHARACTERISTIC CURVES
1000
180
160
140
120
100
80
90
80
70
60
100
10
1
CT=100pF
PHASE
50
40
30
20
10
0
CT=220pF
CT=330pF
CT=560pF
CT=820pF
CT=1000pF
60
GAIN
40
20
0
1
100
10000
FREQUENCY (Hz)
1000000
0
50
100
150
200
250
TIMING RESISTOR, RT (kOhms)
Figure 3. Typical oscillator frequency.
Figure 6. Typical error amplifier response.
120
100
80
60
40
20
0
CT=1000pF
CT=820pF
14
VDD = 10v, T = +25°C
12
IDD
with 1nF load
10
8
CT=560pF
CT=330pF
6
CT=220pF
CT=100pF
IDD
without load
4
2
0
0
200
400
600
800
1000 1200
OSCILLATOR FREQUENCY (kHz)
0
20
40
60
80
100
TIMING RESISTOR (RT) kOhms
Figure 4. Typical I active current.
Figure 7. Typical dead time between output stages.
DD
1.2
1
0.8
0.6
0.4
0.2
0
-55 -35 -15
5
25 45 65 85 105 125
TEMPERATURE (°C)
Figure 5. Typical COMP to CS offset vs. temperature.
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6
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