UCC38086_技术文档

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SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

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FEATURES

APPLICATIONS

D

Programmable Slope Compensation

D

High-Efficiency Switch-Mode Power Supplies

Telecom dc-to-dc Converters

Internal Soft-Start on the UCC38083/4

Cycle-by-Cycle Current Limiting

Point-of-Load or Point-of-Use Power Modules

Low Start-Up Current of 120 µA and 1.5 mA

Typical Run Current

Low-Cost Push-Pull and Half-Bridge

Applications

D

Single External Component Oscillator

Programmable from 50 kHz to 1 MHz

DESCRIPTION

The UCC38083/4/5/6 is a family of BiCMOS pulse width

modulation (PWM) controllers for dc-to-dc or off-line

fixed-frequency current-mode switching power

supplies. The dual output stages are configured for the

push-pull topology. Both outputs switch at half the

oscillator frequency using a toggle flip-flop. The dead

time between the two outputs is typically 110 ns, limiting

each output’s duty cycle to less than 50%.

High-Current Totem-Pole Dual Output Stage

Drives Push-Pull Configuration with 1-A Sink

and 0.5-A Source Capability

D

Current Sense Discharge Transistor to

Improve Dynamic Response

D

Internally Trimmed Bandgap Reference

Undervoltage Lockout with Hysteresis

D

The new UCC3808x family is based on the UCC3808A

architecture. The major differences include the addition

of a programmable slope compensation ramp to the CS

signal and the removal of the error amplifier. The current

flowing out of the ISET pin through an external resistor

is monitored internally to set the magnitude of the slope

compensation function. This device also includes an

^OUTinternal discharge transistor from the CS pin to ground,

which is activated at each clock cycle after the pulse is

terminated. This discharges any filter capacitance on

the CS pin during each cycle and helps minimize filter

capacitor values and current sense delay.

BASIC APPLICATION

V

IN

POWER

TRANSFORMER

V

VDD

UCC3808x

CTRL OUTA

The UCC38083 and the UCC38084 devices have a

typical soft-start interval time of 3.5 ms while the

UCC38085 and the UCC38086 has less than 100 µs for

applications where internal soft-start is not desired.

RT

OUTB

CS

R

F

ISET

The UCC38083 and the UCC38085 devices have the

turn-on/off thresholds of 12.5 V / 8.3 V, while the

UCC38084 and the UCC38086 has the turn-on/off

thresholds of 4.3 V / 4.1 V. Each device is offered in 8-pin

TSSOP (PW), 8-pin SOIC (D) and 8-pin PDIP (P)

packages.

GND

R

T

R

S

R

SET

C

F

FEEDBACK

UDG−01080

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2002−2003, Texas Instruments Incorporated

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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ

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1

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢉ

ꢀ ꢁꢁꢅ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

ORDERING INFORMATION

THERMAL RESISTANCE TABLE

PACKAGE

SOIC−8 (D)

PDIP−8 (P)

θjc(°C/W)

θja(°C/W)

(1)

84 to 160

(1)

42

50

110

(2)

32

(2)

TSSOP−8 (PW)

232 to 257

2

NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch FR4 PC board

with one ounce copper where noted. When resistance range is given, lower values

are for 5 inch aluminum PC board. Test PWB was 0.062 inch thick and typically

2

used 0.635-mm trace widths for power packages and 1.3-mm trace widths for

non-power packages with a 100-mil x 100-mil probe land area at the end of each

trace.

(2). Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal

copper ground plane, higher value is for 1x1-inch. ground plane. All model data

assumes only one trace for each non-fused lead.

AVAILABLE OPTIONS

UVLO

PACKAGES

PDIP-8 (P)

INTERNAL

SOFT START

T

A

ON

OFF

8.3 V

4.1 V

8.3 V

4.1 V

8.3 V

4.1 V

8.3 V

4.1 V

SOIC-8 (D)

UCC28083D

UCC28084D

UCC28085D

UCC28086D

UCC38083D

UCC38084D

UCC38085D

UCC38086D

TSSOP-8 (PW)

UCC28083PW

UCC28084PW

UCC28085PW

UCC28086PW

UCC38083PW

UCC38084PW

UCC38085PW

UCC38086PW

12.5 V

4.3 V

UCC28083P

UCC28084P

UCC28085P

UCC28086P

UCC38083P

UCC38084P

UCC38085P

UCC38086P

3.5 ms

75 µs

−40°C to 85°C

0°C to 70°C

12.5 V

4.3 V

12.5 V

4.3 V

3.5 ms

12.5 V

4.3 V

75 µs

†

The D and PW packages are available taped and reeled. Add R suffix to device type, e.g. UCC28083DR (2500 devices

per reel) or UCC38083PWR (2000 devices per reel).

PW PACKAGE

(TOP VIEW)

D OR P PACKAGE

(TOP VIEW)

1

2

3

4

8

7

6

5

OUTA

VDD

OUTB

GND

RT

CTRL

ISET

CS

VDD

1

2

3

4

8

7

6

5

OUTA

OUTB

GND

CTRL

ISET

CS

RT

2

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ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢃꢉ

ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢅ ꢃꢄ ꢃꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

(I

< 10 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V

DD DD

Supply current, I

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

OUTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A

OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A

DD

Sink current (peak):

Source current (peak): OUTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 A

OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 A

Analog inputs:

CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

+0.3 V

DD

CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

+0.3 V, not to exceed 6 V

DD

R

(minimum) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5 kΩ

SET

R (−100 µA < I < 100 µA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.0 V

T

RT

Power dissipation at T = 25°C (P package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W

A

Power dissipation at T = 25°C (D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW

Power dissipation at T = 25°C (PW package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mW

Junction operating temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

J

Storage temperature, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND.

Currents are positive into, and negative out of the specified terminal.

electrical characteristics over recommended operating virtual junction temperature range,

= 10 V (See Note 1),1-µF capacitor from VDD to GND, R = 165 kΩ, R = 1 kΩ, C = 220 pF,

V

R

DD

SET

T

F

= 50 kΩ, T = −40°C to 85°C for UCC2808x, T = 0°C to 70°C for UCC3808x, T = T

A

J

(unless otherwise noted)

overall

PARAMETER

Start-up current

TEST CONDITIONS

MIN

TYP

MAX UNITS

VDD < UVLO start threshold voltage

120

1.5

200

2.5

µA

Supply current

CTRL = 0 V,

See Note 1

CS = 0 V,

mA

undervoltage lockout

PARAMETER

TEST CONDITIONS

MIN

11.5

4.1

7.6

3.9

3.5

0.1

TYP

12.5

4.3

MAX UNITS

UCC38083/5

UCC38084/6

UCC38083/5

UCC38084/6

UCC38083/5

UCC38084/6

See Note 1

13.5

4.5

Start threshold voltage

8.3

9.0

Minimum operating voltage

after start

V

4.1

4.3

4.2

5.1

0.3

Hysteresis voltage

0.2

oscillator

PARAMETER

Frequency

TEST CONDITIONS

MIN

180

1.4

TYP

200

1.5

MAX UNITS

2 x f(OUTA)

See Note 2

220

1.6

220

1.6

kHz

V

Voltage amplitude

Oscillator fall time (dead time)

RT pin voltage

110

1.5

ns

V

1.2

3

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢉ

ꢀ ꢁꢁꢅ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

electrical characteristics over recommended operating virtual junction temperature range,

= 10 V (See Note 1),1-µF capacitor from VDD to GND, R = 165 kΩ, R = 1 kΩ, C = 220 pF,

V

R

DD

SET

T

F

= 50 kΩ, T = −40°C to 85°C for UCC2808x, T = 0°C to 70°C for UCC3808x, T = T

A

J

(unless otherwise noted)

current sense

PARAMETER

Gain

TEST CONDITIONS

MIN

1.9

TYP

MAX UNITS

See Note 3

2.2

0.52

100

2.5

0.57

200

V/V

V

Maximum input signal voltage

CS to output delay time

Source current

CTRL = 5 V,

CTRL = 3.5 V,

See Note 4

0.47

0 mV ≤ CS ≤ 600 mV

ns

nA

−200

3

CS = 0.5 V,

See Note 5

RT = 2.0 V,

Sink current

7

12

mA

Overcurrent threshold voltage

0.70

0.55

0.37

0.75

0.70

0.80

0.90

1.10

V

CS = 0 V, 25°C

CTRL to CS offset voltage

CS = 0 V

pulse width modulation

PARAMETER

Maximum duty cycle

TEST CONDITIONS

MIN

TYP

MAX UNITS

Measured at OUTA or OUTB

CTRL = 0 V

48%

49%

50%

0%

Minimum duty cycle

output

PARAMETER

Low-level output voltage (OUTA or OUTB)

High-level output voltage (OUTA or OUTB)

Rise time

TEST CONDITIONS

= 100 mA

MIN

TYP

0.5

25

MAX UNITS

I

1.0

OUT

V

= −50 mA,

(VDD − VOUT), See Note 6

1.0

OUT

C

= 1 nF

60

LOAD

ns

Fall time

25

60

soft-start

PARAMETER

TEST CONDITIONS

CS = 0 V,

Duty cycle from 0 to full

MIN

TYP

MAX UNITS

OUTA/OUTB soft-start interval time,

UCC38083/4

CTRL = 1.8 V,

1.3

3.5

8.5

ms

OUTA/OUTB soft-start interval time,

UCC38085/6

CTRL = 1.8 V,

Duty cycle from 0 to full

CS = 0 V,

30

75

110

µs

slope compensation

PARAMETER

TEST CONDITIONS

, peak = 30 µA, Full duty cycle

MIN

TYP

MAX UNITS

175 µA

I , peak

RAMP

I

125

150

SET

NOTE 1: For UCCx8083/5, set VDD above the start threshold before setting to 10 V.

NOTE 2: Measured at ISET pin.

DV

NOTE 3: Gain is defined by A +

^CTRL, 0 ≤ V

≤ 0.4 V.

CS

DV_CS

NOTE 4: Measured at trip point of latch with CS ramped from 0.4 V to 0.6 V.

NOTE 5: This internal current sink on the CS pin is designed to discharge and external filter capacitor. It is not intended to be a dc sink path.

NOTE 6: Not 100% production tested. Ensured by design and also by the rise time test.

4

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ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢃꢉ

ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢅ ꢃꢄ ꢃꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

functional block diagram

Soft Start and Fault Latch

S

Bias/UVLO

VREF

Q

CTRL

1

Iss

0.5V

Slope Circuit

I

8

R

S

R

SLOPE

Vdd−1

VDD

+

C

T

Css

I

=

SLOPE

ISET

2

5 x I

SET

CS Circuitry

0.75V

PWM Comparator/Latch

Output Driver

7

OUTA

80 k

Ω

S

Q

T

60 k

0.5V

R

Q

0.3 V

CS

3

6

OUTB

Oscillator

1.5V

S

R

Q

1.5V

I

CT

RT

4

5

0.2V

C

T

GND

UDG−01081

Terminal Functions

TERMINAL

NAME

PACKAGE

I/O

DESCRIPTION

D OR P

CS

3

I

The current-sense input to the PWM comparator, the cycle-by-cycle peak current comparator, and the

overcurrent comparator. The overcurrent comparator is only intended for fault sensing. Exceeding the

overcurrent threshold causes a soft-start cycle. An internal MOSFET discharges the current-sense filter

capacitor to improve dynamic performance of the power converter.

CTRL

GND

1

5

I

Error voltage input to PWM comparator.

−

Reference ground and power ground for all functions. Due to high currents, and high-frequency operation

of the IC, a low-impedance circuit board ground plane is highly recommended.

ISET

OUTA

OUTB

RT

2

7

6

4

8

I

O

I

Current selection for slope compensation.

Alternating high-current output stages.

Programs the oscillator.

Power input connection.

VDD

I

5

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢉ

ꢀ ꢁꢁꢅ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

detailed pin descriptions

CTRL: The error voltage is typically generated by a secondary-side error amplifier and transmitted to the

primary-side referenced UCC3808x by means of an opto-coupler. CTRL has an internal divider ratio of 0.45 to

maintain a usable range with the minimum V

full-cycle soft start while the UCC38085/6 does not.

of 4.1 V. The UCC38083/UCC38084 family features a built-in

DD

For the UCC38083/4, soft-start is implemented as a clamp at the input to the PWM comparator. This causes

the output pulses to start near 0% duty cycle and increase until the clamp exceeds the CTRL voltage.

ISET: Program the slope compensation current ramp by connecting a resistor, RSET, from ISET to ground. The

voltage of the ISET pin tracks the 1.5-V internal oscillator ramp, as shown in Figure 1.

V(CS)

VDD

I

= 5 x ISET, peak

RAMP, peak

IRAMP

10k

UCC38083

I

CTRL

VDD

OUTA

OUTB

GND

1

2

8

7

6

5

SET

RSET

ISET

CS

1uF

3

4

OUTA

RF

1k

RT

I

RAMP

RT

165k

220pF

OUTB

Figure 1. Full Duty Cycle Output

The compensating current source, I

relation:

, at the CS pin is proportional to the ISET current, according to the

SLOPE

I

+ 5 I

SLOPE

SET

(1)

The ramping current due to I

develops a voltage across the effective filter impedance that is normally

SLOPE

connected from the current sense resistor to the CS input. In order to program a desired compensating slope

with a specific peak compensating ramp voltage at the CS pin, use the RSET value in the following equation:

5 RF

ǒ

Ǔ

RSET + V

OSC(peak)

RAMP VOLTAGE HEIGHT

(2)

Where V

+ 1.5 V

OSC(peak)

Notice that the PWM Latch drives an internal MOSFET that will discharge an external filtering capacitor on the

CS pin. Thus, I will appear to terminate when the PWM comparator or the cycle-by-cycle current limit

SLOPE

comparator sets the PWM latch. The actual compensating slope is not affected by premature termination of the

switching cycle.

6

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ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢃꢉ

ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢅ ꢃꢄ ꢃꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

detailed pin descriptions (continued)

OUTA and OUTB: Alternating high-current output stages. Both stages are capable of driving the gate of a power

MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current.

The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the

internal oscillator capacitor is rising, one of the two outputs is high, but during fall time, both outputs are off. This

dead time between the two outputs, along with a slower output rise time than fall time, ensures that the two

outputs cannot be on at the same time. This dead time is typically 110 ns.

The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output

stage also provides a very low impedance to overshoot and undershoot. This means that in many cases,

external Schottky clamp diodes are not required.

RT: The oscillator programming pin. The oscillator features an internal timing capacitor. An external resistor,

R , sets a current from the RT pin to ground. Due to variations in the internal C , nominal V of 1.5 V can vary

T

RT

from 1.2 V to 1.6 V

Selecting RT as shown programs the oscillator frequency:

1

−7

ǒ

Ǔ

RT +

* 2.0 10

−12

f

28.7 10

OSC

(3)

where f

is in Hz, resistance in Ω. The recommended range of timing resistors is between 25 kΩ and 698 kΩ.

OSC

For best performance, keep the timing resistor lead from the RT pin to GND (pin 5) as short as possible.

1.5 V

S

R

Q

I

1.5 V

RT

CT

OSCILLATOR

OUTPUT

4

0.2 V

C

T

R

T

1

Approximate Frequency +

−7

28.7 10⁻¹² R_T) 2.0 10

ǒ

Ǔ

UDG−01083

Figure 2. Block Diagram for Oscillator

VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply

current may be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total

VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating

frequency and the MOSFET gate charge (Q ), average OUT current can be calculated from:

G

I

+ Q f

OSC

OUT

G

(4)

where f is the oscillator frequency.

To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along

with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.

7

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢉ

ꢀ ꢁꢁꢅ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

APPLICATION INFORMATION

The following application circuit shows an isolated 12-V to 2.5 V

power (20 W to 200 W). Note that the pinout shown is for SOIC-8 and PDIP-8 packages.

push-pull converter with scalable output

IN

OUT

typical application

V

O

= 2.2 V TO 3.3 V

ADJUSTABLE

V

= 12 V

IN

+/−20%V

SR

DRIVE

F

1

µ

8

VDD

4.7

Ω

7

OUTA

RT 4

UCC3808x

4.7

Ω

6

5

6

3

OUTB

R

1 kΩ

CTRL 1

F

1

CS

GND

5

165

Ω

ISET

2

3

k

4

R

S

C

F

TL431

220 pF

R

T

UDG−01084

8

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ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢃꢉ

ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢅ ꢃꢄ ꢃꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

APPLICATION INFORMATION

operational waveforms

Figure 3 illustrates how the voltage ramp is effectively added to the voltage across the current sense element

V

, to implement slope compensation.

CS

OUTA

OUTB

V

RS

ADDED

RAMP

VOLTAGE

V , Pin 3

CS

UDG−01085

Figure 3. Typical Slope Compensation Waveforms at 80% Duty Cycle

In Figure 3, OUTA and OUTB are shown at a duty cycle of 80%, with the associated voltage VRS across the

current sense resistor of the primary push-pull power MOSFETs. The current flowing out of CS generates the

ramp voltage across the filter resistor R that is positioned between the power current sense resistor and the

F

CS pin. This voltage is effectively added to VRS to provide slope compensation at VCS, pin 3. A capacitor C

is also recommended to filter the waveform at CS.

F

9

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢉ

ꢀ ꢁꢁꢅ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

layout considerations

To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along

with an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.

Use a local ground plane near the small signal pins (CTRL, ISET, CS and RT) of the IC for shielding. Connect

the local ground plane to the GND pin with a single trace. Do not extend the local ground plane under the power

pins (VDD, OUTA, OUTB and GND). Instead, use signal return traces to the GND pin for ground returns on the

side of the integrated circuit with the power pins.

For best performance, keep the timing resistor lead from RT pin (pin 4) to GND (pin 5) as short as possible.

special layout considerations for the TSSOP package

Due to the different pinout and smaller lead pitch of the TSSOP package, special attention must be paid to

minimize noise problems. The pinout is different because the device had to be rotated 90° to fit into the smaller

TSSOP package.

For example, the two output pins are now on opposite sides of the package. The traces should not run under

the package together as they will couple switching noise into analog pins.

Another common problem is when RT and OUTB (pins 6 and 8) are routed together for some distance even

though they are not immediate side by side pins. Because of this, when OUTB rises, a voltage spike of upto

400 mV can couple into the RT. This spike causes the internal charge current into CT to be turned off

momentarily resulting in lower duty cycle. It is also important that note that the RT pin voltage cannot be

stabilized with a capacitor. The RT pin is just a dc voltage to program the internal CT. Instead, keep the OUTB

and RT runs short and far from each other and follow the printed wiring board layout suggestions above to fix

the problem.

reference design

A reference design is discussed in 50-W Push-Pull Converter Reference Design Using the UCC38083, TI

Literature Number SLUU135. This design controls a push-pull synchronous rectified topology with input range

of 18 V to 35 V (24 nominal) and 3.3-V output at 15 A. The schematic is shown in Figure 5 and the board layout

for the reference design is shown in Figure 4. Refer to the document for further details.

Figure 4. Reference Design Layout

10

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ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢃꢉ

ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢅ ꢃꢄ ꢃꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

APPLICATION INFORMATION

Figure 5. Reference Design Schematic

11

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢉ

ꢀ ꢁꢁꢅ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY

vs

TEMPERATURE

TIMING RESISTANCE

220

215

210

205

1200

1000

800

600

400

200

0

R

= 165 kΩ″

T

F

R = 1 kΩ

C

R

= 220 kΩ

= 50 kΩ

T = 85°C

V

= 15 V

SET

DD

T = 25°C

= 10 V

V

DD

200

195

190

185

180

T = 40°C

= 6 V

V

DD

−50

−25

0

25

50

75

100

125

10

100

1000

RT − Timing Resistance − kΩ

°C

Temperature −

Figure 6

Figure 7

IDD

vs

IDD

vs

OSCILLATOR FREQUENCY, (NO LOAD)

OSCILLATOR FREQUENCY, 1 nF LOAD

25

20

15

12

10

V

DD

= 14 V

V

= 14 V

DD

8

6

4

V

= 10 V

DD

V

DD

= 10 V

V

= 6 V

DD

10

5

V

DD

= 6 V

2

0

10

100

1000

10

100

1000

Frequency − kHz

Figure 8

Figure 9

12

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ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢃꢉ

ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢅ ꢃꢄ ꢃꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

TYPICAL CHARACTERISTICS

DEAD TIME

vs

TIMING RESISTANCE OVER VDD

DEAD TIME

vs

TEMPERATURE

200

180

160

140

120

100

80

160

140

120

100

80

R

= 165 kΩ″

T

F

R = 1 kΩ

C

R

V

= 6 V*

DD

T = 85°C

= 220 kΩ

= 50 kΩ

T = 25°C

SET

V

DD

= 6 V*

V

DD

= 10 V

V

DD

= 14 V

60

V

= 14 V

DD

T = −40°C

40

20

* UCCx8084/6, only

0

10

100

1000

−50

−25

0

25

50

75

100

125

RT − Timing Resistance − kΩ

Temperature −

°C

Figure 10

Figure 11

CONTROL TO CS OFFSET

RAMP HEIGHT

vs

VDD

TEMPERATURE

0.6

0.5

2.0

1.8

1.6

1.4

1.2

1.0

0.8

T

= 25°C

A

(OC Clamped)

R

= 10 Ω

SET

R

= 18 Ω

V

= 0.40 V

SET

CS

0.4

0.3

0.2

0.6

0.4

R

= 50 Ω

SET

V

CS

= 0 V

0.1

0

R

= 100 Ω

SET

0.2

0.0

0

5

10

VDD − Volts

15

−50

−25

0

25

50

75

100

125

Temperature − °C

Figure 12

Figure 13

13

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢇꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢃ ꢉ

ꢀ ꢁꢁꢅ ꢃ ꢄ ꢃ ꢅꢆ ꢀ ꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢈꢆ ꢀꢁ ꢁꢅ ꢃ ꢄ ꢃ ꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

TYPICAL CHARACTERISTICS

RAMP HEIGHT

vs

RAMP HEIGHT

vs

TEMPERATURE

RT

0.7

0.6

T

A

= 25°C

R

= 10 Ω

(OC Clamped)

SET

0.6

0.5

0.4

0.5

0.4

(OC Clamped)

R

= 10 Ω

SET

R

= 18 Ω

SET

R

= 18 Ω

SET

0.3

0.2

0.1

0

0.2

0.1

R

= 50 Ω

SET

R

= 50 Ω

SET

R

= 100 Ω

R

= 100 Ω

SET

0.0

10

100

1000

−50

−25

0

25

50

75

100

125

RT − k

Ω

Temperature −°C

Figure 14

Figure 15

SOFT START

vs

TEMPERATURE

SOFT START

vs

TEMPERATURE

6

100

95

90

85

80

75

UCCx8085 AND UCCx8086

UCCx8083 AND UCCx8084

5

4

3

2

70

65

60

55

50

1

0

−50

−25

0

25

50

75

100

125

−50

−25

0

25

50

75

100

125

°C

Temperature −

°C

Figure 16

Figure 17

14

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ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢃꢉ

ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢅ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢇ ꢆ ꢀꢁꢁ ꢅ ꢃꢄ ꢃ ꢈ ꢆ ꢀꢁ ꢁꢅ ꢃꢄ ꢃꢉ

SLUS488B − SEPTEMBER 2002 − REVISED MAY 2003

TYPICAL CHARACTERISTICS

CS TO OUTX DELAY TIME

vs

TEMPERATURE

150

140

130

120

110

100

90

80

70

60

50

−50

−25

0

25

50

75

100

125

Temperature −

°C

Figure 18


型号：	UCC38086
厂家：	TEXAS INSTRUMENTS
描述：	8-PIN CURRENT MODE PUSH-PULL PWM CONTROLLERS WITH PROGRAMMABLE SLOPE COMPENSATION 8引脚的电流模式推挽PWM具有可编程斜率补偿CONTROLLERS
文件：	总19页 (文件大小：427K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC38086 [TI]

相关型号：

UCC38086D

UCC38086DG4

UCC38086DR

UCC38086DRG4

UCC38086P

UCC38086PG4

UCC38086PW

UCC38086PWG4

UCC38086PWR

UCC3808A-1

UCC3808A-2

UCC3808AD-1