UCC3808AD-1G4 [TI]
具有放电晶体管、12.5/8.3V UVLO、温度范围为 0°C 至 70°C 的低功耗电流模式推挽式 PWM | D | 8 | 0 to 70;型号: | UCC3808AD-1G4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有放电晶体管、12.5/8.3V UVLO、温度范围为 0°C 至 70°C 的低功耗电流模式推挽式 PWM | D | 8 | 0 to 70 信息通信管理 开关 光电二极管 晶体管 |
文件: | 总10页 (文件大小:160K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLUS456D – APRIL 1999 - REVISED AUGUST 2002
D OR N PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
Dual Output Drive Stages in Push-Pull
Configuration
Current Sense Discharge Transistor to
Improve Dynamic Response
1
2
3
4
8
7
6
5
VDD
COMP
OUTA
OUTB
GND
FB
CS
RC
130-µA Typical Starting Current
1-mA Typical Run Current
Operation to 1 MHz
Internal Soft Start
PW PACKAGE
(TOP VIEW)
On-Chip Error Amplifier With 2-MHz Gain
Bandwidth Product
1
8
7
6
5
OUTA
VDD
COMP
FB
OUTB
GND
RC
D
On Chip VDD Clamping
2
3
4
D
Output Drive Stages Capable of 500-mA
Peak-Source Current, 1-A Peak-Sink Current
CS
description
The UCC3808A is a family of BiCMOS push-pull, high-speed, low-power, pulse-width modulators. The UCC3808A
contains all of the control and drive circuitry required for off-line or dc-to-dc fixed frequency current-mode switching
power supplies with minimal external parts count.
The UCC3808A dual output drive stages are arranged in a push-pull configuration. Both outputs switch at half the
oscillator frequency using a toggle flip-flop. The dead time between the two outputs is typically 60 ns to 200 ns
depending on the values of the timing capacitor and resistors, thus limiting each output stage duty cycle to less than
50%.
block diagram
FB
2
COMP
1
CS
3
8
7
VDD
OVERCURRENT
COMPARATOR
22 k
Ω
PEAK CURRENT
COMPARATOR
14 V
0.75 V
2.0 V
0.5 V
2.2 V
S
OUTA
VDD OK
OSCILLATOR
Q
Q
PWM
LATCH
R
S
R
1.2R
Q
Q
S
Q
R
VDD–1 V
T
PWM
COMPARATOR
VDD
0.5 V
R
SOFT START
6
5
OUTB
GND
VOLTAGE
REFERENCE
SLOPE = 1 V/ms
4
Note: Pinout shown is for SOIC and PDIP packages. TSSOP pinout is different.
RC
UDG-00097
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002, Texas Instruments Incorporated
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1
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ꢖ
SLUS456D – APRIL 1999 - REVISED AUGUST 2002
description (continued)
The UCC3808A family offers a variety of package options, temperature range options, and choice of undervoltage
lockout levels. The family has UVLO thresholds and hysteresis options for off-line and battery powered systems.
Thresholds are shown in the table below.
The UCC3808A is an enhanced version of the UCC3808 family. The significant difference is that the A versions
feature an internal discharge transistor from the CS pin to ground, which is activated each clock cycle during the
oscillator dead time. The feature discharges any filter capacitance on the CS pin during each cycle and helps minimize
filter capacitor values and current sense delay.
ORDERING INFORMATION
Packaged Devices
T
= T
J
A
UVLO Option
12.5 V/8.3 V
4.3 V/4.1 V
12.5 V/8.3 V
4.3 V/4.1 V
SOIC (D)
PDIP (N)
TSSOP (PW)
UCC2808AD–1
UCC2808AD–2
UCC3808AD–1
UCC3808AD–2
UCC2808AN–1
UCC2808AN–2
UCC3808AN–1
UCC3808AN–2
UCC2808APW–1
UCC2808APW–2
UCC3808APW–1
UCC3808APW–2
–40°C to 85°C
0°C to 70°C
†
D (SOIC–8) and PW (TSSOP–8) packages are available taped and reeled. Add TR suffix to device type (e.g.
UCC3808ADTR–1) to order quantities of 2500 devices per reel for SOIC-8 and 2000 devices per reel for TSSOP-8.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage (IDD ≤ 10 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OUTA/OUTB source current (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 A
OUTA/OUTB sink current (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 A
Analog inputs (FB, CS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD 0.3 V, not to exceed 6 V
Power dissipation at T = 25°C (N package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
A
Power dissipation at T = 25°C (D package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW
A
Power dissipation at T = 25°C (PW package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mW
A
stg
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to150°C
Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the Power Supply Control Data Book (TI Literature
Number SLUD003) for thermal limitations and considerations of packages.
†
electrical characteristics, T = 0°C to 70°C for the UCC3808A-x, –40°C to 85°C for the UCC2808A-x,
A
VDD = 10 V (see Note 6), 1-µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF T = T , (unless
A
J
otherwise noted)
PARAMETER
Oscillator Section
TEST CONDITIONS
MIN
TYP
MAX UNITS
Oscillator frequency
175
194
0.5
213
kHz
V/V
Oscillator amplitude/VDD
See Note 1
0.44
0.56
NOTES: 1. Measured at RC. Signal amplitude tracks VDD.
6. For UCCx808A–1, set VDD above the start threshold before setting at 10 V.
2
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ꢖ
SLUS456D – APRIL 1999 - REVISED AUGUST 2002
electrical characteristics, T = 0°C to 70°C for the UCC3808A-x, –40°C to 85°C for the UCC2808A-x,
A
VDD = 10 V (see Note 6), 1-µF capacitor from VDD to GND, R = 22 kΩ, C = 330 pF T = T , (unless
A
J
otherwise noted)
Error Amplifier Section
Input voltage
COMP = 2 V
1.95
–1
2
2.05
1
V
Input bias current
Open loop voltage gain
COMP sink current
COMP source current
PWM Section
µA
dB
mA
mA
60
80
2.5
FB = 2.2 V,
FB = 1.3 V,
COMP = 1 V
0.3
–0.2
COMP = 3.5 V
–0.5
Maximum duty cycle
Minimum duty cycle
Current Sense Section
Gain
Measured at OUTA or OUTB
COMP = 0 V
48
49
50
0
%
%
See Note 2
1.9
2.2
0.5
2.5
0.55
200
V/V
V
Maximum input signal
CS to output delay
CS source current
CS sink current
COMP = 5 V
See Note 3
CS from 0 mV to 600 mV
0.45
COMP = 3.5 V,
100
ns
nA
mA
V
–200
5
CS = 0.5 V,
CS = 0 V
RC = 5.5 V
See Note 7
10
0.75
0.8
Over current threshold
COMP to CS offset
Output Section
0.7
0.35
0.8
1.2
V
OUT low level
I = 100 mA
0.5
0.5
25
1
1
V
V
OUT high level
I = –50 mA,
VDD – OUT
Rise time
C
C
= 1 nF
= 1 nF
60
60
ns
ns
L
L
Fall time
25
Undervoltage Lockout Section
UCCx808A–1
UCCx808A–2
UCCx808A–1
UCCx808A–2
UCCx808A–1
UCCx808A–2
See Note 6
11.5
4.1
7.6
3.9
3.5
0.1
12.5
4.3
8.3
4.1
4.2
0.2
13.5
4.5
9
V
V
V
V
V
V
Start threshold
Minimum operating voltage after start
Hysteresis
4.3
5.1
0.3
Soft Start Section
COMP rise time
FB = 1.8 V,
Rise from 0.5 V to 4 V
3.5
20
ms
Overall Section
Startup current
VDD < start threshold
130
1
260
2
µA
mA
V
Operating supply current
VDD zener shunt voltage
FB = 0 V,
IDD = 10 mA
COMP
CS = 0 V
See Note 4
See Note 5 and 6
13
14
15
DV
NOTES: 2. Gain is defined by: A +
,
0 ≤ V ≤ 0.4 V.
CS
DV
CS
3. Parameter measured at trip point of latch with FB at 0 V.
4. Start threshold and zener shunt threshold track one another.
5. Does not include current in the external oscillator network.
6. For UCCx808A–1, set VDD above the start threshold before setting at 10 V.
7. The internal current sink on the CS pin is designed to discharge an external filter capacitor. It is not intended to be a dc sink path.
3
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SLUS456D – APRIL 1999 - REVISED AUGUST 2002
pin assignments
COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the
UCC3808A is a true low-output impedance, 2-MHz operational amplifier. As such, the COMP pin can both source
and sink current. However, the error amplifier is internally current limited, so that zero duty cycle can be externally
forced by pulling COMP to GND.
The UCC3808A family features built-in full-cycle soft start. Soft start is implemented as a clamp on the maximum
COMP voltage.
CS: The input to the PWM, peak current, and overcurrent comparators. The overcurrent comparator is only intended
for fault sensing. Exceeding the overcurrent threshold will cause a soft start cycle. An internal MOSFET discharges
the current sense filter capacitor to improve dynamic performance of the power converter.
FB: The inverting input to the error amplifier. For best stability, keep FB lead length as short as possible and FB stray
capacitance as small as possible.
GND: Reference ground and power ground for all functions. Due to high currents, and high frequency operation of
the UCC3808A, a low impedance circuit board ground plane is highly recommended.
OUTA and OUTB: Alternating high current output stages. Both stages are capable of driving the gate of a power
MOSFET. Each stage is capable of 500-mA peak-source current, and 1-A peak-sink current.
The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the RC
pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two
outputs, along with a slower output rise time than fall time, insures that the two outputs can not be on at the same
time. This dead time is typically 60 ns to 200 ns and depends upon the values of the timing capacitor and resistor.
The high-current-output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output
stage also provides a very low impedance to overshoot and undershoot. This means that in many cases,
external-schottky-clamp diodes are not required.
RC: The oscillator programming pin. The UCC3808A’s oscillator tracks VDD and GND internally, so that variations
in power supply rails minimally affect frequency stability. Figure 1 shows the oscillator block diagram.
Only two components are required to program the oscillator: a resistor (tied to the VDD and RC), and a capacitor (tied
to the RC and GND). The approximate oscillator frequency is determined by the simple formula:
1.41
RC
f
+
OSCILLATOR
where frequency is in Hz, resistance in Ohms, and capacitance in Farads. The recommended range of timing
resistors is between 10 kΩ and 200 kΩ and range of timing capacitors is between 100 pF and 1000 pF. Timing resistors
less than 10 kΩ should be avoided.
For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from VDD
as short as possible, and the leads between timing components and RC as short as possible. Separate ground and
VDD traces to the external timing network are encouraged.
4
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SLUS456D – APRIL 1999 - REVISED AUGUST 2002
pin assignments (continued)
RC
4
1.41
FREQUENCY =
VDD
2
RC
(APPROXIMATE
FREQUENCY)
S
R
Q
OSCILLATOR
OUTPUT
0.2 V
UDG-00095
Figure 1. Block Diagram for Oscillator
NOTE A: The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but both stages are
off during the RC fall time. The output stages switch a 1/2 the oscillator frequency, with ensured duty cycle of < 50% for both outputs.
VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply current
will be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total VDD current
is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the
MOSFET gate charge (Qg), average OUT current can be calculated from:
I
+ Q F, where F is frequency
g
OUT
To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along with
an electrolytic capacitor. A 1-µF decoupling capacitor is recommended.
APPLICATION INFORMATION
A 200-kHz push-pull application circuit with a full-wave rectifier is shown in Figure 2. The output, V , provides 5 V
O
at 50 W maximum and is electrically isolated from the input. Since the UCC3808A is a peak-current-mode controller
the 2N2907 emitter following amplifier (buffers the CT waveform) provides slope compensation which is necessary
for duty ratios greater than 50%. Capacitor decoupling is very important with a single ground IC controller, and a 1
µF is suggested as close to the IC as possible. The controller supply is a series RC for start-up, paralleled with a bias
winding on the output inductor used in steady state operation.
Isolation is provided by an optocoupler with regulation done on the secondary side using the TL431 adjustable
precision shunt regulator. Small signal compensation with tight voltage regulation is achieved using this part on the
secondary side. Many choices exist for the output inductor depending on cost, volume, and mechanicall strength.
Several design options are iron powder, molypermalloy (MPP), or a ferrite core with an air gap as shown here. The
main power transformer has a Magnetics Inc. ER28 size core made of P material for efficient operation at this
frequency and temperature. The input voltage may range from 36 V dc to 72 V dc.
5
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ER28 32CTQ030
8:2
V
O
5 V 50 W
+
µ
EF25 7 H
N
N
µ
F
µ
F
P2
P1
S1
S2
680
0.01
–
+
LOOP B
N
N
BYV
28–200
BYV
28–200
V
µ
F
µ
F
4700
0.47
IN
Ω
Ω
62
62
200 Ω
36 V TO 72 V
1000 pF
1000 pF
LOOP A
–
COMP
4700 pF
Ω
20 k
Ω
51 k
1/4 W
Ω
19.1 k
IRF640
12
IRF640
Ω
10
470 pF
Ω
2.2
DF02SGICT
Ω
2.2
1 mH
3
TL431
1
µ
F
0.1
2
µ
F
µ
F
Ω
19.1 k
10
0.1
Ω
20 k
Ω
2 k
Ω
0.2
VDD OUTA OUTB GND
PRIMARY
GROUND
8
7
6
5
330 pF
UCC3808AD–1
1
2
3
4
Ω
240
COMP FB
CS
RC
RC
Ω
4.99 k
CURRENT
Ω
SENSE
Ω
2.80 k
86.6 k
Ω
4.99 k
H11A1
U3
2K12907
4
5
6
3
2
1
Ω
20 k
µ
0.1 F
330 pF
Ω
432
µ
0.01
1 kV
F
ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆꢇꢈ ꢀꢁꢁ ꢂ ꢃꢄ ꢃ ꢅ ꢆꢂꢈ ꢀꢁꢁ ꢉ ꢃꢄ ꢃ ꢅ ꢆꢇꢈ ꢀꢁꢁ ꢉꢃ ꢄꢃ ꢅꢆ ꢂ
ꢊ ꢋꢌ ꢍꢋ ꢌ ꢎꢏ ꢁꢀꢏ ꢏꢎꢐꢑ ꢒ ꢋꢓ ꢎ ꢍꢀ ꢔꢕꢆꢍꢀ ꢊꢊ ꢍ ꢌꢒ
ꢖ
SLUS456D – APRIL 1999 - REVISED AUGUST 2002
TYPICAL CHARACTERISTICS
IDD
OSCILLATOR FREQUENCY
vs
EXTERNAL RC VALUES
COMP TO CS OFFSET
vs
TEMPERATURE
vs
OSCILLATOR FREQUENCY
14
1000
1.2
1.0
C = 100 pF
12
VDD = 10 V, t = 25
C
IDD
with 1 nF load
C = 220 pF
10
C = 330 pF
100
0.8
8
6
0.6
0.4
C = 1000 pF
10
C = 820 pF
4
C = 560 pF
IDD
0.2
0
without load
2
0
1
–55 –35 –15
5
25
45
65
85 105 125
0
0
200
400
600
800
1000
1200
50
100
150
200
- °C
Temperature
Ω
RT – Timing Resistor – k
Oscillator Frequency – kHz
Figure 3
Figure 4
Figure 5
ERROR AMPLIFIER GAIN AND PHASE
OUTPUT DEAD TIME
vs
EXTERNAL RC VALUES
DEAD TIME
vs
TEMPERATURE
RESPONSE
vs
FREQUENCY
300
250
400
350
300
250
200
150
100
50
90
80
70
60
50
40
180
C = 1000 pF
160
140
120
100
80
VDD = 5 V
VDD = 7.5 V
C = 560 pF
C = 820 pF
C = 330 pF
200
150
Phase
VDD = 10 V
C = 220 pF
30
20
10
60
40
20
100
50
Gain
C = 100 pF
0
0
0
–100
–50
0
50
100
150
1
100
10000
1000000
50
100
150
200
250
Temperature - °C
RT – Timing Resistor – k Ω
Frequency – Hz
Figure 6
Figure 7
Figure 8
CS R
DS(on)
RC R
DS(on)
vs
TEMPERATURE
vs
TEMPERATURE
120
300
250
100
VDD = 5 V
VDD = 5 V
80
60
40
200
150
100
VDD = 7.5 V
VDD = 7.5 V
VDD = 10 V
VDD = 10 V
20
0
50
0
–100
–50
0
50
100
150
–100
–50
0
50
100
150
Temperature - °C
Temperature - °C
Figure 9
Figure 10
7
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
Drawing
HPA00001D
HPA00001DTR
UCC2808AD-1
UCC2808AD-2
UCC2808ADTR-1
UCC2808ADTR-2
UCC2808AN-1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
D
D
D
D
P
8
8
8
8
8
8
8
None
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-NC-NC-NC
75
75
2500
2500
50
Pb-Free
(RoHS)
UCC2808AN-2
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
UCC2808APW-1
UCC2808APW-2
UCC2808APWTR-1
UCC2808APWTR-2
UCC3808AD-1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
PW
PW
PW
PW
D
8
8
8
8
8
8
8
8
8
150
150
2000
2000
75
None
None
None
None
None
None
None
None
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-NC-NC-NC
UCC3808AD-2
SOIC
D
75
UCC3808ADTR-1
UCC3808ADTR-2
UCC3808AN-1
SOIC
D
2500
2500
50
SOIC
D
PDIP
P
Pb-Free
(RoHS)
UCC3808AN-2
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
UCC3808APW-1
UCC3808APW-2
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
8
8
8
8
150
150
None
None
None
None
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
UCC3808APWTR-1
UCC3808APWTR-2
2000
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2005
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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