UCC3811DWTR
更新时间：2024-09-18 18:51:26
品牌：TI
描述：IC,SMPS CONTROLLER,CURRENT-MODE,BICMOS,SOP,16PIN,PLASTIC
概述
规格参数
数据手册UCC3811DWTR 概述
IC,SMPS CONTROLLER,CURRENT-MODE,BICMOS,SOP,16PIN,PLASTIC 开关式稳压器或控制器
UCC3811DWTR 规格参数
| 生命周期： | Obsolete | 包装说明： | SOP, SOP16,.4 |
| Reach Compliance Code： | unknown | 风险等级： | 5.84 |
| 控制模式： | CURRENT-MODE | JESD-30 代码： | R-PDSO-G16 |
| 端子数量： | 16 | 最高工作温度： | 70 °C |
| 最低工作温度： | 最大输出电流： | 0.2 A | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP16,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 认证状态： | Not Qualified |
| 子类别： | Switching Regulator or Controllers | 表面贴装： | YES |
| 最大切换频率： | 1100 kHz | 技术： | BICMOS |
| 温度等级： | COMMERCIAL | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| Base Number Matches： | 1 |
UCC3811DWTR 数据手册
通过下载UCC3811DWTR数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
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ꢀꢁꢁ ꢇ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢇꢃ ꢄꢄ
SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
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FEATURES
DESCRIPTION
D
D
D
D
D
D
D
Single Oscillator Synchronizes Two PWMs
150-µA Startup Supply Current
2-mA Operating Supply Current
Operation to 1 MHz
The UCC3810 and UCC3811 are high-speed
BiCMOS integrated circuits implementing two
synchronized pulse width modulators for use in
off-line and dc-to-dc power supplies. The
UCC381x family provides perfect synchronization
between two PWMs by using the same oscillator.
The oscillator’s sawtooth waveform can be used
for slope compensation if required.
Internal Soft-Start
Full-Cycle Fault Restart
Internal Leading-Edge Blanking of the
Current Sense Signal
Using a toggle flip-flop to alternate between
modulators, the UCC3810 ensures that one PWM
does not slave, interfere, or otherwise affect the
other PWM. This toggle flip- flop also ensures that
each PWM is limited to 50% maximum duty cycle,
insuring adequate off-time to reset magnetic
elements. This device contains many of the same
elements of the UC3842 current mode controller
family, combined with the enhancements of the
UCC3802. This minimizes power supply parts
count. Enhancements include leading edge
blanking of the current sense signals, full cycle
fault restart, CMOS output drivers, and outputs
which remain low even when the supply voltage is
removed.
D
1-A Totem Pole Outputs
D
75-ns Typical Response from Current Sense
to Output
D
D
1.5% Tolerance Voltage Reference
Two UVLO Options
N PACKAGE
(TOP VIEW)
SYNC
CT
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
REF
RT
ENABLE2
FB2
FB1
COMP1
CS1
COMP2
11 CS2
ERROR AMPLIFIER GAIN AND PHASE
OUT1
GND
10 OUT2
vs
9
PWRGND
FREQUENCY
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
CT
RT
FB1
COMP1
CS1
OUT1
GND
VCC
REF
ENABLE2
FB2
COMP2
CS2
OUT2
PWRGND
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Copyright 2002, Texas Instruments Incorporated
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1
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
ORDERING INFORMATION
(1)
PACKAGED DEVICES
UVLO THRESHOLD (V)
T
J
PDIP (N)
START
11.3
8.4
STOP
8.3
SOP (DW)
UCC2810DW (16)
UCC2811DW (16)
UCC3810DW (16)
UCC3811DW (16)
UCC2810N (16)
UCC2811N (16)
UCC3810N (16)
UCC3811N (16)
–40_C to 85_C
0C to 70C
7.0
11.3
8.4
8.3
7.0
(1) All packages are available taped and reeled (indicated by the R suffix on the device type e.g., UCC2810JR)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)(3)
UNIT
V
(2)
Supply voltage , V
CC
11
20
Supply current, I
CC
mA
A
Output peak current, OUT1, OUT2, 5% duty cycle
Output energy, OUT1, OUT2, capacitive load
Analog inputs, FB1, FB2, CS1, CS2, SYNC
±1
20
µJ
V
–0.3 to 6.3
150
Operating junction temperature, T
J
_C
_C
_C
Storage temperature range, T
stg
–65 to 150
300
Lead temperature (soldering, 10 sec)
(1) Currents are positive into, negative out of the specified terminal. All voltages are with respect to GND.
(2) In normal operation, V
is powered through a current-limiting resistor. Absolute maximum of 11 V applies when driven from a low impedance
CC
current does not exceed 20 mA.
such that the V
CC
(3) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
BLOCK DIAGRAM
UDG–92062–1
2
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
ELECTRICAL CHARACTERISTICS
All parameters are the same for both channels, –40_C ≤ T ≤ 85_C for the UCC281x, 0_C ≤ T ≤ 70_C for the
A
A
(1)
UCC381x, V
= 10 V ; R = 150 kΩ, C = 120 pF; no load; T = T ; (unless otherwise specified)
CC
T T A J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
T
T
= 25_C
4.925 5.000 5.075
J
V
CC
Output voltage
V
= full range,
0 mA ≤ I
REF
≤ 5 mA
4.85
5.00
5
5.10
25
J
Load regulation
Line regulation
0 mA ≤ I ≤ 5 mA
REF
mV
UVLO stop threshold voltage,
0.5 V ≤ V ≤ V
12
CC SHUNT
(7)
Output noise voltage
10 Hz < f < 10 kHz,
T
= 25_C
235
5
µV
mV
mA
J
(7)
Long term stability
T
= 125_C,
1000 hours
A
I
Output short circuit current
–8
–25
O(SC)
OSCILLATOR
R
R
= 30 kΩ
C
C
= 120 pF
= 120 pF
860
190
980
220
2.5%
2.5
1100
250
T
T
T
(2)
Oscillator frequency
f
kHz
OSC
= 150 kΩ
T
(7)
Temperature stability
Peak voltage
Valley voltage
0.05
2.45
1.65
30
V
Peak-to-peak amplitude
SYNC threshold voltage
SYNC input current
2.25
0.80
2.65
2.20
SYNC = 5 V
µA
ERROR AMPLIFIER
V
FB input voltage
COMP = 2.5 V
2.44
60
2.50
2.56
V
µA
FB
I
FB input bias current
Open loop voltage gain
±1
FB
73
2
dB
(7)
f
I
I
Unity gain bandwidth
MHz
GAIN
SINK
SRCE
Sink current, COMP
FB = 2.7 V,
FB = 1.8 V,
COMP = 0 V
FB = 1.8 V,
COMP = 1 V
COMP = 4 V
0.3
1.4
–0.5
3.5
–0.8
0%
mA
ms
Source current, COMP
Minimum duty cycle
–0.2
Soft-start rise time, COMP
(1) For UCC3810, adjust V
5
rise from 0.5 V to (REF – 1.5 V)
above the start threshold before setting at 10 V.
4
CC
(2) Oscillator frequency is twice the output frequency. fOSC
+
RT CT
DVCOMP
(3) Current sense gain A is defined by: A +
,
0 V ≤ V ≤ 0.8 V.
CS
DVCS
(4) Parameter measured at trip point of latch with FB = 0 V.
(5) CS blank time is measured as the difference between the minimum non-zero on-time and the CS-to-OUT delay.
(6) Start threshold voltage and V internal zener voltage track each other.
CC
(7) Ensured by design. Not production tested.
3
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
ELECTRICAL CHARACTERISTICS
(1)
–40_C ≤ T ≤ 85_C for the UCC281X, 0_C ≤ T ≤ 70_C for the UCC381X, V
= 10 V ; R = 150 kΩ, C = 120 pF;
A
A
A
CC
T
T
no load; T = T ; all parameters are the same for both channels (unless otherwise specified)
J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT SENSE
(3)
Gain
1.20
0.9
1.55
1.0
1.80
1.1
V/V
V
(4)
Maximum input signal
Input bias current, CS
COMP = 5 V
I
±200
nA
CS
CS steps from 0 V to 1.2 V,
COMP = 2.5 V
Propagation delay time (CS to OUT)
75
ns
V
(5)
Blank time, CS
55
1.55
0.90
Overcurrent threshold voltage, CS
COMP-to-CS offset voltage
1.35
0.45
1.85
1.35
CS = 0 V
PWM
R
R
= 150 kΩ,
= 30 kΩ,
C
C
= 120 pF
= 120 pF
45%
40%
49%
45%
130
50%
48%
T
T
T
(7)
Maximum duty cycle
T
Minimum on-time
CS = 1.2 V,
COMP = 5 V
ns
OUTPUT
I
I
I
I
I
= 20 mA
0.12
0.48
0.7
0.42
1.10
1.2
OUT
OUT
OUT
OUT
OUT
= 200 mA
= 20 mA,
= –20 mA
= –200 mA
V
Low-level output voltage
OL
V
= 0 V
V
CC
0.15
1.2
0.42
2.3
V
OH
High-level output voltage (V
– OUT)
CC
t
t
Rise time, OUT
Fall time, OUT
C
C
= 1 nF
= 1 nF
20
50
R
OUT
OUT
ns
30
60
F
UNDERVOLTAGE LOCKOUT (UVLO)
UCCx810
UCCx811
UCCx810
UCCx811
UCCx810
UCCx811
9.6
7.4
7.1
6
11.3
8.4
8.3
7
13.2
9.4
9.5
8
Start threshold voltage
Stop threshold voltage
Start-to-stop hysteresis
V
1.7
0.65
–20
0.80
3.0
1.40
–35
1.53
4.7
2.15
–55
2.00
ENABLE2 input bias current
ENABLE2 = 0 V
µA
ENABLE2 input threshold voltage
V
(1) For UCC3810, adjust V
CC
above the start threshold before setting at 10 V.
4
(2) Oscillator frequency is twice the output frequency. fOSC
+
RT CT
0 V ≤ V ≤ 0.8 V.
CS
DVCOMP
(3) Current sense gain A, is defined by: A +
,
DVCS
(4) Parameter measured at trip point of latch with FB = 0 V.
(5) CS blank time is measured as the difference between the minimum non-zero on-time and the CS-to-OUT delay.
(6) Start threshold voltage and V internal zener voltage track each other.
CC
(7) Ensured by design. Not production tested.
4
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
ELECTRICAL CHARACTERISTICS
All parameters are the same for both channels, –40_C ≤ T ≤ 85_C for the UCC281x, 0_C ≤ T ≤ 70_C for the
A
A
(1)
UCC381x, V
= 10 V ; R = 150 kΩ, C = 120 pF; no load; T = T ; (unless otherwise specified)
CC
T T A J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OVERALL
Startup current
V
V
V
< Start threshold voltage
0.15
2
0.25
3
CC
CC
CC
Operating supply current, outputs off
Operating supply current, outputs on
= 10 V,
FB = 2.75 V
= 10 V,
FB = 0 V,
mA
3.2
5.1
CS = 0 V,
R = 150 kΩ
T
V
= 10 V,
FB = 0 V,
= 30 kΩ
CC
CS = 0 V,
8.5
12.9
1.2
14.5
14.0
R
T
(6)
VCC internal zener voltage
I
= 10 mA
11.0
0.4
CC
V
VCC internal zener voltage minus start
threshold voltage
(6) Start threshold voltage and V
internal zener voltage track each other.
CC
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5
COMP1
COMP2
O
O
Low impedance output of the error amplifiers.
12
Current sense inputs to the PWM comparators. These inputs have leading edge blanking. For most
applications, no input filtering is required. Leading edge blanking disconnects the CS inputs from all
internal circuits for the first 55 ns of each PWM cycle. When used with very slow diodes or in other
applications where the current sense signal is unusually noisy, a small current-sense R-C filter may
be required.
CS1
6
I
CS2
CT
11
2
I
The timing capacitor of the oscillator. Recommended values of CT are between 100 pF and 1 nF.
Connect the timing capacitor directly across CT and GND.
O
A logic input which disables PWM 2 when low. This input has no effect on PWM 1. This input is inter-
nally pulled high. In most applications it can be left floating. In unusually noisy applications, the input
should be bypassed with a 1-nF ceramic capacitor. This input has TTL compatible thresholds.
ENABLE2
14
I
FB1
FB2
4
I
I
The high impedance inverting inputs of the error amplifiers.
13
To separate noise from the critical control circuits, this part has two different ground connections:
GND and PWRGND. GND and PWRGND must be electrically connected together. However, use
care to avoid coupling noise into GND.
GND
8
–
The high-current push-pull outputs of the PWM are intended to drive power MOSFET gates through
a small resistor. This resistor acts as both a current limiting resistor and as a damping impedance to
minimize ringing and overshoot.
OUT1
OUT2
7
O
O
10
To separate noise from the critical control circuits, this part has two different ground connections:
GND and PWRGND. GND and PWRGND must be electrically connected together.
PWRGND
REF
9
–
The output of the 5-V reference. Bypass REF to GND with a ceramic capacitor ≥ 0.01-µF for best
performance.
15
O
The oscillator charging current is set by the value of the resistor connected from RT to GND. This pin
is regulated to 1 V, but the actual charging current is 10 V/R . Recommended values of R are be-
tween 10 kΩ and 470 kΩ. For a given frequency, higher timing resistors give higher maximum duty
T
T
RT
3
O
cycle and slightly lower overall power consumption.
This logic input can be used to synchronize the oscillator to a free running oscillator in another part.
This pin is edge triggered with TTL thresholds, and requires at least a 10-ns-wide pulse. If unused,
this pin can be grounded, open circuited, or connected to REF.
SYNC
VCC
1
I
I
The power input to the device. This pin supplies current to all functions including the high current
output stages and the precision reference. Therefore, it is critical that VCC be directly bypassed to
PWRGND with an 0.1-µF ceramic capacitor.
16
5
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
APPLICATION INFORMATION
timing resistor
Supply current decreases with increased R by the relationship:
T
11 V
DI
+
CC
R
T
(1)
For more information, see the detailed oscillator block diagram.
leading edge blanking and current sense
Figure 1 shows how an external power stage is connected to the UCC3810/UCC3811. The gate of an external
power N-channel MOSFET is connected to OUT through a small current-limiting resistor. For most applications,
a 10-Ω resistor is adequate to limit peak current and also practical at damping resonances between the gate
driver and the MOSFET input reactance. Long gate lead length increases gate capacitance and mandates a
higher series gate resistor to damp the R-L-C tank formed by the lead, the MOSFET input reactance, and the
device’s driver output resistance.
The UCC3810/UCC3811 features internal leading edge blanking of the current-sense signal on both current
sense inputs. The blank time starts when OUT rises and continues for 55 ns. During that 55 ns period, the signal
on CS is ignored. For most PWM applications, this means that the CS input can be connected to the
current-sense resistor as shown in Figure 1. However, high speed grounding practices and short lead lengths
are still required for good performance.
Figure 1. Detailed Block Diagram
oscillator
The UCC3810/UCC3811 oscillator generates a sawtooth wave at CT. The sawtooth rise time is set by the
resistor from RT to GND. Since R is biased at 1 V, the current through R is 1 V/R . The actual charging current
T
T
T
is 10 times higher. The fall time is set by an internal transistor on-resistance of approximately 100 Ω. During the
fall time, all outputs are off and the maximum duty cycle is reduced to below 50%. Larger timing capacitors
increase the discharge time and reduce frequency. However, the percentage maximum duty cycle is only a
function of the timing resistor R , and the internal 100-Ω discharge resistance.
T
6
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
APPLICATION INFORMATION
error amplifier output stage
The UCC3810 and UCC3811 error amplifiers are operational amplifiers with low-output resistance and
high-input resistance. The output stage of one error amplifier is shown in Figure 3. This output stage allows the
error amplifier output to swing close to GND and as high as one diode drop below 5 V with little loss in amplifier
performance.
Figure 2. Oscillator
Figure 3. Error Amplifier Output Stage
7
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
ERROR AMPLIFIER GAIN AND PHASE
vs
TIMING RESISTANCE
FREQUENCY
Figure 4
Figure 5
MAXIMUM DUTY CYCLE
vs
TIMING RESISTANCE
OSCILLATOR FREQUENCY
vs
TEMPERATURE
Figure 6
Figure 7
8
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SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
MAXIMUM DUTY CYCLE
vs
OSCILLATOR FREQUENCY
FREQUENCY
Figure 8
Figure 9
9
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢂ ꢃꢄꢄ
ꢀꢁ ꢁ ꢇ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢇ ꢃ ꢄꢄ
SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
UDG–94022
Figure 10. Typical Application
10
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢂꢃ ꢄꢄ
ꢀꢁꢁ ꢇ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢇꢃ ꢄꢄ
SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–ā8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
18
20
24
28
0.710
DIM
0.410
0.462
0.510
0.610
A MAX
A MIN
(10,41) (11,73) (12,95) (15,49) (18,03)
0.400
0.453
0.500
0.600
0.700
(10,16) (11,51) (12,70) (15,24) (17,78)
4040000/E 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
11
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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢂ ꢃꢄꢄ
ꢀꢁ ꢁ ꢇ ꢃꢄ ꢅ ꢆ ꢀ ꢁ ꢁꢇ ꢃ ꢄꢄ
SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
J (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
14 LEADS SHOWN
PINS **
14
16
20
DIM
0.310
(7,87)
0.310
(7,87)
0.310
(7,87)
A MAX
B
0.290
(7,37)
0.290
(7,37)
0.290
(7,37)
A MIN
B MAX
B MIN
C MAX
C MIN
14
8
0.785
0.785
0.975
(19,94) (19,94) (24,77)
C
0.755
0.755
0.930
(19,18) (19,18) (23,62)
0.300
(7,62)
0.300
(7,62)
0.300
(7,62)
1
7
0.065 (1,65)
0.045 (1,14)
0.245
(6,22)
0.245
(6,22)
0.245
(6,22)
0.100 (2,54)
0.070 (1,78)
0.020 (0,51) MIN
A
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040083/E 03/99
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, and GDIP1-T20
12
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ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢂꢃ ꢄꢄ
ꢀꢁꢁ ꢇ ꢃꢄ ꢅ ꢆ ꢀ ꢁꢁ ꢇꢃ ꢄꢄ
SLUS162A – FEBRUARY 1999 – REVISED OCTOBER 2002
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.035 (0,89) MAX
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
M
14/18 PIN ONLY
4040049/D 02/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
13
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