UCC3829N-2_技术文档

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

High Speed PWM Controller

PRELIMINARY

FEATURES

DESCRIPTION

•

Compatible with Voltage or Current

Mode Control Methods

The UCC3829 is a BiCMOS High Speed PWM Controller IC. It is opti-

mized for high frequency switched mode power supply applications. The

IC can be used in both voltage mode and current mode control applica-

tions. Care was given to minimizing the propagation delays through the

comparators and logic circuitry while maximizing the bandwidth and slew

rate of the error amplifier. The oscillator frequency and deadtime can be

programmed via two external resistors and a capacitor. The undervolt-

age lockout threshold can be programmed using an external resistor di-

vider. The current limit and overcurrent threshold can be set externally.

The IC is available in push-pull (-1), single ended (-2), or complementary

(-3) output configuration.

•

Practical Operation at Switching

Frequencies to 4MHz

•

50ns Propagation Delay to Output

High Current Complementary

Outputs

•

Programmable Dead Time and

Frequency Oscillator

•

Pulse by Pulse Current Limiting

Fault protection circuitry includes undervoltage detection for the internal

bias supply, and overcurrent detection. The fault detection logic sets a

latch that ensures full discharge of the soft start capacitor before allowing

a restart. While the fault latch is set, the outputs are in a low state. In the

event of continuous faults, the soft start capacitor is fully charged before

discharging to insure that the fault frequency does not exceed the de-

signed soft start period.

Latched Overcurrent Comparator

with Full Cycle Restart

•

Programmable Undervoltage

Lockout (UVLO)

Adjustable Blanking for Leading

Edge Noise Tolerance

BLOCK DIAGRAM

BISYNC

RT1

9

8

18 VDD

V_BIAS

15 OUTA

CT

7

6

CLOCK

>

S

R

Q

T

RT2

14 OUTB

13 PGND

V_BIAS

4V

LEB 19

11 CL+

1.5V

1.2V

RAMP

5

0.9V

12 CL–

PWCONT

EAOUT

NINV

4

3

1

2

1.25V

INV

V_BIAS

14.2V/9V

3V/2.5V

2.1V

SS 10

S

R

Q

1V

17 UVLO

23 VREF

3V

D

REFERENCE

GND 18

UDG-98043

SLUS390 - MARCH 1998

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

ABSOLUTE MAXIMUM RATINGS

ORDERING INFORMATION

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V

Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA

Output Current (OUTA, OUTB, PGND, VCC)

UCC 829

–

DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

Pulsed (0.5µsec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2A

PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.2V

Analog Inputs

INV, NINV, RAMP, SS . . . . . . . . . . . . . . . . . . . . . –0.3 to 7V

CL+, CL-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to 3V

Error Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . . 5mA

Error Amplifier Output Capacitance. . . . . . . . . . . . . . . . . . 20pF

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C

TEMPERATURE & PACKAGE SELECTION

GUIDE TABLE

TEMPERATURE

RANGE

AVAILABLE

PACKAGES

UCC1829-X

UCC2829-X

UCC3829-X

–55°C to +125°C

–40°C to +85°C

0°C to +70°C

J

N, DW, Q

Unless otherwise indicated, voltages are referenced to GND.

Currents are positive into, negative out of the specified terminal.

Consult Packaging Section of Databook for thermal limitations

and considerations of packages.

PART VERSION TABLE

PART NUMBER

UCCX829-1

UCCX829-2

UCCX829-3

OUTPUT

Push-Pull

OUT A/B PHASE

180° Out of Phase

In Phase

OUTPUT FREQUENCY

FCT/2

FCT

Dual Single-Ended

Non-Overlapping Complimentary

OUTB = OUTA

FCT

CONNECTION DIAGRAMS

DIL-20, SOIC-20 (Top View)

N, DW and J Packages

PLCC-20 (Top View)

Q Package

NINV

INV

VREF

LEB

NINV

INV

20 VREF

19 LEB

1

2

3

4

5

6

7

8

9

EAOUT

3

2

1

20 19

18

EAOUT

PWCONT

RAMP

RT2

18 GND

17 UVLO

16 VDD

15 OUTA

14 OUTB

13 PGND

12 CL–

PWCONT

RAMP

RT2

4

5

6

7

8

GND

17

16

15

14

UVLO

VDD

CT

OUTA

OUTB

RT1

9

10 11 12 13

CT

BISYNC

SS

PGND

CL–

RT1

BISYNC

CL+

SS 10

11 CL+

2

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, RT1 = 34.8kΩ, CT = 470pF, RT2 = 392Ω, VDD = 12V,

Over Full Temperature Range and TA = TJ.

PARAMETER

Reference Section

TEST CONDITIONS

MIN

TYP

MAX UNITS

Output Voltage

TJ = 25°C, No Load, Output Off

2.97

2.94

3

3.03

3.06

50

V

Over Temperature, No Load, Output Off

VDD = 5V to 14.5V, Output Off, No Load, (Note 2)

0 < IREF < 5mA

Line Regulation

35

2

mV

V

Load Regulation

Total Output Variation

10

Line, Load, Temperature = 0°C to 70°C, (Note 1)

2.93

2.90

3.07

3.10

Line, Load, Temperature = –55°C to +125°C,

(Note 1)

V

Short Circuit Current

Oscillator Section

Initial Accuracy

VREF = 0

–25

mA

TJ = 25°C

360

320

400

440

480

10

kHz

%

Total Variation

Line, Temperature (Note 1)

TMIN < TA < TMAX (Note 1)

RT1 = 25.7k, CT = 150pF, TJ = 25°C, (Note 1)

Temperature Stability

Initial Accuracy, 1MHz

Total Variation, 1MHz

5

1

0.9

0.8

1.1

1.2

MHz

RT1 = 25.7k, CT = 150pF, Line, Temperature

(Note 1)

Ramp Peak Voltage

Ramp Valley Voltage

Peak To Peak Voltage

BISYNC Output Source Current

BISYNC Output Sink Current

BISYNC Input Threshold

Error Amplifier Section

Input Offset Voltage

Input Bias Current

1.8

2

1

2.2

1.5

V

0.85

1

1.15

–1.5

V

VBISYNC = VDD – 0.5V

VBISYNC = 0.5V

–2

140

1.5

mA

A

60

1

2

V

5

1

mV

µA

nA

dB

µA

V

–1

Input Offset Current

Open Loop Gain

250

70

75

80

CMRR

1.5V < VCM < 4.5V

5V < VDD < 14.5V

VEAOUT = 1V

PSRR

75

Output Sink Current

Output Source Current

Output High Voltage

Output Low Voltage

Gain Bandwidth Product

Slew Rate

300

500

VEAOUT = 4V

–500 –300

5

IEAOUT = –300µA

IEAOUT = 300µA

VDD = 12V, TJ = 25°C

3

0.6

7

1

V

5

MHz

V/µs

1.5

2

PWM Comparator Section

Input Bias Current V(RAMP)

Minimum Duty Cycle

Maximum Duty Cycle (UCCX829-1)

–60

1

0

µA

%

400kHz

400kHz, RT2 Resistor = 200Ω

42.5

85

%

Maximum Duty Cycle (UCCX829-2, -3) 400kHz, RT2 Resistor = 200Ω

Delay to Output

%

50

3

100

–10

ns

Current Limit Fault Section

Soft Start Charge Current

–40

µA

Soft Start Complete Threshold

SS Pin (Note 1)

V

3

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, RT1 = 34.8kΩ, CT = 470pF, RT2 = 392Ω, VDD = 12V,

Over Full Temperature Range and TA = TJ.

PARAMETER

Restart Discharge Current

Restart Threshold

TEST CONDITIONS

MIN

10

TYP

MAX UNITS

40

1.2

1.1

1.4

100

400

µA

V

0.8

1.1

1

Current Limit Threshold

Overcurrent Threshold

Current Limit Delay to Output

Relative to CL–

0.875

1.25

50

V

ns

VDD = 5V

100

Output Section (OUTA, OUTB)

Output Low Saturation

Output High Saturation

UVLO Output Low Saturation

Rise Time

IOUT = 200mA

IOUT = –100mA

At 10mA

0.5

1.0

0.5

40

V

0.1

V

CLOAD = 1nF, TJ = 25°C

VOUT = 0, TJ = 25°C (Note 1)

VOUT = 12V, TJ = 25°C (Note 1)

(Note 1)

20

ns

A

Fall Time

10

20

Output Source Current

Output Sink Current

–0.75

1.5

A

Complementary Delay Time (Delay 2)

(UCCX829 -3 Only)

50

150

ns

Undervoltage Lockout

UVLO Enable Threshold

UVLO Hysteresis

VDD UVLO Enable Threshold

VDD UVLO Hysteresis

Supply Section

2.9

0.3

3

3.1

0.7

14.5

7

V

0.5

13.5

3.5

VDD Range

No Load

4.25

14.5

5

V

Startup Current

VUVLO = 2V, VDD = 13.5V

400kHz, No Load

3

8

mA

IDD

12

Note 1: Guaranteed by design. Not 100% tested in production.

Note 2: Refer to Figure 1.

TYPICAL CHARACTERISTIC CURVES

3.030

3.025

3.020

3.015

3.010

3.005

3.000

2.995

2.990

2.985

2.980

2.975

2.970

3.05

3.04

3.03

3.02

3.01

3

2.99

2.98

2.97

2.96

2.95

-75

-50

-25

0

25

50

75

100

125

TEMPERATURE [°C]

5.0

6.0

7.0

8.0

9.0 10.0 11.0 12.0 13.0 14.0 15.0

VDD [V]

Figure 1. Reference vs. VDD

Figure 2. Reference vs. Temperature

4

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

PIN DESCRIPTIONS

phase. The UCC3829 -3 implements OUTA and OUTB

to be non-overlapping complementary outputs during the

same clock cycle. The output frequency of the

BISYNC: Combination clock output/sync input pin. The

clock signal can be viewed on this pin. If BISYNC is con-

nected to BISYNC of other UCC3829 chips, all the oscil-

lators will run at the highest of all the chips frequencies.

The BISYNC pin has a weak pull down and a strong pull

up.

UCC3829-1 is half that of the UCC3829-2

UCC3829 -3.

and

PGND: Power ground return. The PGND pin should be

used as the return for the VDD bypass capacitor and the

current sense kelvin CL-.

CL+: Current sense input for current limiting. The CL+

and CL- pins are used for current sensing. CL+ is the

current signal while CL- is the kelvin return for the sens-

ing function.

PWCONT: Pulse width control input. This is connected to

the PWM comparator inverting input.

CL–: Current sense input kelvin common.

RAMP: Ramp input . This is connected to the PWM com-

parator non-inverting input through a level shifting volt-

age of approximately 1.25V.

CT: Oscillator timing capacitor. A capacitor connected

between CT and GND is charged by a current source

controlled by RT1. The capacitor is discharged through a

resistor connected between CT and RT2.

RT1: Oscillator charging current programming resistor. A

1V reference at this pin generates a current through a re-

sistor connected between RT1 and GND. This current is

mirrored and ratioed to charge the timing capacitor con-

nected to pin CT.

EAOUT: Error amplifier output. This output is normally

connected directly to the PWCONT pin. It can also be

connected to PWCONT through a resistor divider at-

tenuation network to allow more swing of the error ampli-

fier output. A maximum capacitive load of 20pF with

respect to ground must be observed to insure stability of

the error amplifier.

RT2: Oscillator discharge time programming resistor. The

oscillator (and output) dead time can be programmed via

this pin. The discharge of the timing capacitor CT is de-

termined by an RC discharge using a resistor connected

between RT2 and CT.

GND: Logic and analog ground. The GND pin should be

used for all signal level returns, except the current sense

inputs.

SS: Soft start capacitor pin. A capacitor connected to SS

determines the time the IC takes to soft start. The nomi-

nal SS pin pull up and pull down current is 20µA. The soft

start time delay is approximately calculated as:

INV: Error amplifier inverting input.

LEB: Leading edge blanking programming pin. Connect-

ing a resistor between VREF and LEB and a capacitor

between LEB and GND will program a leading edge

blanking time according to the RC of the resistor/capaci-

tor combination. Connecting the LEB pin to VDD disables

the Leading Edge Blanking function.

CSS • 3V

20 µA

when charging from 0V. After the SS pin reaches the SS

complete threshold of 3V, another SS cycle can be

started. The restart time is approximately:

NINV: Error amplifier non-inverting input.

2 • CSS • 3V

OUTA: Output A. The OUTA pin will pull down with ap-

proximately 1.5A and pull up with approximately 0.75A.

The UCC3829-1 implements push-pull outputs with

OUTA and OUTB active on alternating clock cycles. The

UCC3829-2 implements OUTA and OUTB being in

phase. The UCC3829 -3 implements OUTA and OUTB to

be non-overlapping complementary outputs during the

same clock cycle. The output frequency of the

20 µA

UVLO: Undervoltage lockout programming pin. Connect-

ing a resistor divider between VDD, UVLO, and GND

sets a VDD value at which the UCC3829 chip will be en-

abled. When the voltage on the UVLO pin reaches 3V,

the chip is enabled. When the voltage on UVLO falls be-

low 2.5V, the chip is disabled.

UCC3829-1 is half that of the UCC3829-2

UCC3829 -3.

and

VDD: Voltage supply to IC. VDD is clamped at 14V.

VREF: Voltage reference output and filtering. The voltage

reference output appears on the VREF pin. It is buffered

to drive approximately 5mA and short circuit protected at

approximately 25mA. A bypass capacitor of at least

0.1µF must be connected from VREF to ground.

OUTB: Output B. The OUTB pin will pull down with ap-

proximately 1.5A and pull up with approximately 0.75A.

The UCC3829-1 implements push-pull outputs with

OUTA and OUTB active on alternating clock cycles. The

UCC3829-2 implements OUTA and OUTB being in

5

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

APPLICATION INFORMATION

Functional Programmability

The approximate equation for the falling edge (TF) of the

CT waveform (deadtime period) is:

9.3R^T²

Various features of the UCC3829 are user programma-

ble. RT1 and RT2 allow independent programming for

oscillator rise and fall times within the normal operational

range of the chip. A new feature allows the user to pro-

gram the voltage that flags an undervoltage fault. The

default value of 14V for chip turn-on is selected by tying

the UVLO pin to ground. If the user wants to select

startup voltage then a resistive divider should be tied

from Vdd to ground, with the centerpoint tied to the

UVLO pin. The chip will be enabled when the UVLO pin

reaches 3V, and disabled below 2.5V. Leading edge

blanking can also be optimized to eliminate turn-on noise

when current mode control is used or disabled when de-

sired.

V

PEAK

–

RT 1

T

F

=RT 2

C ln=

T

9.3R^T²

VVALLEY

–

RT 1

Assuming that:

9.3R

^{T 2}<<V^PEAKand

^{T 2}<<V^VALLEY

RT 1

We get a simplified equation:

V

PEAK

TF

=RT 2C ln

T

V

VALLEY

Given a maximum on-time and frequency and assuming

an initial value for either RT2 or CT, you can use the TF

equation to calculate the other. Once you have a value

for CT, you can calculate RT1 using the TR equation.

Oscillator

The oscillator uses an external capacitor CT and two ex-

ternal resistors RT1 and RT2 to generate the clock fre-

quency and dead time. A precise reference voltage is

placed across resistor RT1 to generate a current refer-

ence. The current is then mirrored and used to charge

the capacitor CT from VVALLEY. When a “peak” threshold

is reached, an on chip MOSFET connects the RT2 pin to

GND, discharging CT to a “valley” threshold through an

external resistor RT2. The CT waveform has a linear

ramp shape while charging and an exponential (RC)

slope while discharging. The slope of the charging ramp

is set by the CT, RT1 combination and the slope of the

discharging ramp is set by the values of CT and RT2.

Error Amplifier Section

The Error Amplifier has both inputs and the output

brought out to pins NINV, INV, and EAOUT. The output of

the error amplifier can be connected to the inverting input

of the PWM comparator via the pin PWCONT. This al-

lows inserting attenuation which enables using the full

output swing of the error amplifier. The output of the error

amplifier is forced to follow the soft start waveform during

soft start.

PWM and Output Section

The non-inverted input of the PWM comparator is con-

nected to RAMP. The RAMP can be connected to either

the CT capacitor for voltage mode control, to the current

sense resistor for current mode control, or to a feed for-

ward capacitor for input voltage feed forward control. The

CT waveform can be coupled to RAMP to provide slope

compensation in the current mode case. The MOSFET

switch connected to RAMP provides for the discharge of

the feedforward capacitor. There is a short time constant

(3ns) filter across the inputs of the PWM comparator to

reduce noise.

The approximate equation for the rising edge (TR) of the

CT waveform (maximum on-time period) is:

V

PEAK –

V

VALLEY

TR

=CTRT 1

9.3

The output of the PWM comparator feeds an OR gate

which, together with several other fault signals, sets the

PWM latch. The latch is in turn reset on every dead time

period of the clock waveform. The output of the PWM

latch is OR’ed with the clock and the output of the Fault

Latch (described below) to feed into the pulse steering

Toggle Flip-Flop (TFF). The resulting signal is then

steered according to the output configuration of

UCC3829. The clock output becomes the deadtime be-

tween the outputs.

UDG-97016

Figure 3.

6

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

Output Timing Configurations

Leading Edge Blanking Section

The timing diagram shows the major differences between The Leading Edge Blanking circuit provides a means to

the UCC3829-1, -2 and -3 parts. The output of the insert a blanking period at the beginning of the cycle,

UCC3829-1 is a push-pull configuration with outputs A providing noise pulse elimination for current mode control

and B 180° out of phase and with an output frequency

that is half of the CT’s waveform.

applications. This feature is similar to that of the UC3825

and UC3823A/B controllers. When enabled, an external

resistor is connected from LEB to VREF. An external ca-

pacitor is connected from LEB to either VREF or GND.

During the deadtime, LEB is pulled to GND. At the begin-

ning of the cycle, the pin is released and the capacitor

charges through the resistor toward VREF. At the thresh-

old VREF/2, a comparator senses the voltage and LEB is

removed. The leading edge blanking function can be dis-

abled by connecting LEB to VDD (> VREF). Leading

edge blanking is performed by the same MOSFET switch

connected to RAMP that is used for voltage feed forward

operation.

The UCC3829-2 produces dual outputs that are in phase

and can be used in situations that require high current

drive for single ended designs. A 0.5 resistor should be

added in series with each output before they are con-

nected together. The output pulse frequency is equal to

the CT waveform frequency in this case.

The output drive in the UCC3829-3 has a non-

overlapping complementary configuration. During each

clock cycle Output A produces an output pulse, followed

by a short delay, and then Output B produces an output

pulse. The short delay between Output A and Output B

pulses is tcd, the complementary delay time. This en-

sures that the outputs are never high simultaneously.

Current Timing and Protection

The current limit and overcurrent functions are accom-

plished using the pins CL+ and CL–. These two pins pro-

vide for differential current level sensing, with the trip

points referenced to CL–, rather than GND. The current

limit function provides a pulse by pulse current limiting,

whereas the overcurrent function is considered a fault

condition and initiates a fault logic soft start cycle.

TIMING DIAGRAMS

PWM CNTL

CT

The UCC3829 utilizes differential current sensing and

separate logic and power ground pins to eliminate some

of the noise issues of using current mode control. De-

vices with only one common ground pin for all stated

functions required the combination of power gate drive

current and low-level sensing currents in a common

trace. Since the current signal needed for control is em-

bedded in the power gate drive current, it is not enough

just to separate logic and power ground pins. Differential

sensing in UCC3829 referenced to the negative rail al-

lows the cleanest method of sensing current for use in a

peak current mode controlled power supply utilizing re-

sistive sensing. Current limiting is done on a cycle by cy-

cle basis when the typical threshold of 0.875V is

reached. If the fault level of 1.25V is reached a soft start

cycle is initiated. Internal circuitry insures that soft start

cycles are completed so that fault currents can be con-

trolled.

BISYNC

UCC1829-1

OUT A

UCC1829-1

OUT B

UCC1829-2

OUT A

UCC1829-2

OUT B

Fault Logic Section

UCC1829-3

OUT A

The fault logic detects and handles various fault condi-

tions in the system. The output of the overcurrent com-

parator is logically ORed with the output combination of

the undervoltage detection circuit ORed with the output

of the VREF good circuit. The output of the precision ref-

erence voltage VREF is compared to a level (approxi-

UCC 1829-3

OUT B

tr

tf

tcd

7

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

mately 3 V_BEvoltages) to determine if the reference is

alive. The undervoltage circuit either uses a user pro-

grammed level with a 16% hysteresis or an on threshold

equal to the V_DDclamp voltage and an off threshold of

9V.

sink and turns on a 20µA current source to charge the SS

capacitor.

The under voltage detection is set to a default value of

14V turn on (V_DDclamp active value) and 9V turn off

when the UVLO pin is tied to GND. This default configu-

ration can be overridden by connecting a resistor divider

between V_DDand GND to the UVLO pin. The hysteresis

Once a fault occurs, a soft start cycle takes place. A fault

sets the fault latch. The Q output of the fault latch sets

the RS delay latch and turns on the 20µA soft start dis- for the user set threshold is 16%.

charge current sink. The Q output of the fault latch is

During undervoltage lockout, the self biasing outputs are

gated, however, by the output of the SS complete com-

parator. This insures that a SS cycle cannot start before

the previous one has finished. The soft start capacitor

then is discharged to 1V which is sensed by the RS delay

comparator. The fault latch is then reset. This in turn re-

sets the RS delay latch and turns off the 20µA current

held "OFF" to prevent accidental turn-on of the power

switches.

Supply Section

The incoming voltage supply V_DDis clamped by a shunt

V_DDClamp circuit at 14V.

TYPICAL APPLICATIONS

VIN

DC SOURCE

OR RECTIFIED AC

VOUT

BIAS

SUPPLY

ISOLATED

FEEDBACK

UCC3829-1

UDG-98013

Figure 4. Push-Pull Converter Using UCC3829-1

8

UCC1829-1/-2/-3

UCC2829-1/-2/-3

UCC3829-1/-2/-3

TYPICAL APPLICATIONS (cont.)

VIN

VOUT

UDG-98014

Figure 5. Single Ended Converter with High Power Gate Drive Using UCC3829-2

P/O CT1

V_IN

V_OUT

VDD SUPPLY

P/O CT1

UCC3829-3

COMMON

UDG-98015

Figure 6. Synchronous Rectifier Controller Using UCC3829-3

For additional information, please see U-128 that details

operation and application of some of the features of

UC3823A,B and UC3825A,B PWM Controllers.

UNITRODE CORPORATION

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460

9

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SOIC

Drawing

UCC3829DW-1

UCC3829DW-2

UCC3829DW-3

UCC3829DWTR-1

UCC3829DWTR-2

UCC3829N-1

OBSOLETE

DW

20

TBD

Call TI

DW

UTR

DW

SOIC

PDIP

20

DW

N

UCC3829N-2

N

UCC3829N-3

UTR

UCC3829Q-1

UCC3829Q-2

UCC3829Q-3

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Amplifiers

Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

Logic

Military

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC3829N-2
厂家：	TEXAS INSTRUMENTS
描述：	High Speed PWM Controller 高速PWM控制器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管信息通信管理
文件：	总11页 (文件大小：196K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC3829N-2 [TI]

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