UCC3882PWTR-1G4 [TI]
AVERAGE CURRENT MODE SYNCHRONOUS CONTROLLER WITH 5-BIT DAC; 平均电流模式同步控制器， 5位DAC
| 型号： | UCC3882PWTR-1G4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AVERAGE CURRENT MODE SYNCHRONOUS CONTROLLER WITH 5-BIT DAC |
| 文件： | 总16页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
AVERAGE CURRENT MODE SYNCHRONOUS
CONTROLLER WITH 5-BIT DAC
FEATURES
DESCRIPTION
•
Combined DAC/Voltage Monitor and PWM
The UCC3882 combines high precision reference and
voltage monitoring circuitry with average current
mode PWM synchronous rectification controller
circuitry to power high-end microprocessors with a
minimum of external components. The UCC3882
converts 5 V or 12 V to an adjustable output ranging
from 1.8VDC to 2.05VDC in 50 mV steps and
2.1VDC to 3.5VDC in 100 mV steps with 1% DC
system accuracy.
With Synchronous Rectification Functions
5-Bit Digital-to-Analog (DAC) Converter
1% DAC/Reference Combined Accuracy
•
•
•
Compatible with 5 V and 12 V Systems and 12
V-Only Systems
•
•
Low Offset Current Sense Amplifier
Programmable Oscillator Frequency Practical
to 700 kHz
•
•
•
Foldback Current Limiting
Overvoltage and Undervoltage Fault Windows
2-Ω Totem Pole Outputs with Programmable
Dead Times to Eliminate Cross-Conduction
•
Chip Disable Function
BLOCK DIAGRAM
CAM
4
CAO
6
OVP
OVP (+ 17.5%)
OV
OV (+ 9%)
PWRGD
2
VSNS
1
UV
Current
Amplifier
3 V
UV (−9%)
Q
Voltage
Amplifier
VDRVHI
GATEHI
PGND
19
18
12
VFB 15
Turn
On
S
R
Delay
RT
COMP 16
Anti Cross
Condition
Foldback
Current
Limit
6
ISOUT
VDRVLO
GATELO
10
11
Current Sense
Amplifier
1.37 V
Turn
On
8
7
IS−
IS+
Delay
X16
VSNS
RT
Output Offset
EN
17
9
5 V REF
4.3 V/4.2 V
D0
D1
27
26
VIN
D/C Converter
2 V − 3.5 V, 100 mV
or
UVLO
OSC
VIN
D2 24
D3 23
D4 22
1.3 V − 2.05 V, 50 mV
10.5 V/10 V
5 V
REF
VREF
GND
21
28
13
14
CT RT
20
COMMAND
UDG−97047−1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The DAC output voltage is directly compatible with
Intel’s 5-bit VID code (Table 1) which covers 1.3 V to
2.05 V in 50 mV steps and 2.1 V to 3.5 V in 100 mV
steps. The accuracy of the DAC/reference
combination is better than 1%. Undervoltage lockout
circuitry assures the correct logic states at the
outputs during power up and power down. The
overvoltage and undervoltage comparators monitor
the system output voltage and indicate when it rises
above or falls below its designed value by more than
9%. A second overvoltage comparator digitally forces
GATEHI off and GATELO on when the system output
voltage exceeds its designed value by more than
17.5%.
The voltage and current amplifiers have 2.5 MHz
gain-bandwidth product to satisfy high performance
system requirements. The internal current sense
amplifier permits the use of a low value current sense
resistor, minimizing power loss. The oscillator
frequency is externally programmed with RT and CT.
The foldback circuit reduces the converter short
circuit current limit to 50% of its nominal value when
the
converter
is
short-circuited,
minimizing
component stress and dissipation during abnormal
conditions. The gate drivers are low impedance totem
pole output stages capable of driving large external
MOSFETs. Cross conduction is eliminated internally
by programming the dead time between turn-off and
turn on of the external high side and synchronous
MOSFETs.
For all of the parts, grounding the EN pin disables the
GATEHI and GATELO outputs, shutting down the
power supply. For the 3882, programming a DAC
output voltage below 1.8 V, or programming all of the
VID pins high also disables the GATEHI and
GATELO outputs. For the –1 option parts, the
GATEHI and GATELO outputs are switching, and the
power supply output voltage regulates at the
programmed DAC output voltage for all VID codes.
This device is available in a 28-pin wide body surface
mount package. The UCC3882 is specified for
operation from 0°C to 70°C.
CONNECTION DIAGRAM
N, DW or PW PACKAGES
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSNS
PWRGD
NC
CAM
CAO
OSOUT
IS+
IS−
VIN
VDRVLO
GATELO
PGND
RT
GND
D0
D1
NC
D2
2
3
4
5
6
D3
D4
7
8
VREF
COMMAND
VDRVHI
GATEHI
EN
9
10
11
12
13
14
COMP
VFB
CT
NC − No internal connection
2
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
VDRVHI, GATEHI(2)
–0.3 V to 20 V
–0.3 V to 15 V
–0.3 V to 5.3 V
15 V
VDRVLO, GATELO
All other pins referenced to GND
VIN
Storage Temperature
Junction Temperatur
Lead Temperature (Soldering, 10 sec.)
–65°C to 150°C
–55°C to 150°C.
300°C
(1) Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and
considerations of packages.
(2) 20 V at no load. Derate to 18.5 V when used with capacitive loads of greater than 1000 pF in series with less than 20 Ω .
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VIN = VDRVHI = VDRVLO = 12 V, VSNS = 3.5 V, VD0 = VD1 = VD2 = VD3 = VD4 = 0 V, RT = 13 k,
CT = 1.8 nF, EN = Open, 0°C < TA < 70°C, TA = TJ.
PARAMETER
UNDERVOLTAGE LOCKOUT
VIN UVLO Turn-on Threshold
VIN UVLO Turn-off Threshold
UVLO Threshold Hysteresis
SUPPLY CURRENT
lIN
TEST CONDITIONS
MIN
TYP
MAX
10.8
700
12
UNIT
10.5
10
V
V
9.5
300
500
mV
EN = 0 V
7
mA
DAC/REFERENCE
COMMAND Voltage Accuracy
D0-D4 Voltage High
D0-D4 Input Bias Current
OVP COMPARATOR
Trip Point
10.8 V < VIN < 13.2 V, IREF = 0 mA(1)
DX Pin Floating
–1%
–120
10
1%
5.2
5
V
DX Pin Tied to GND
–70
–20
mA
% Over COMMAND Voltage(2)
% Over COMMAND Voltage(2)
17
20
25
µV
Hysteresis
mV
OV COMPARATOR
Trip Point
5%
9%
20
12%
470
Hysteresis
mV
PWRGD On Resistance
UV COMPARATOR
Trip Point
Ω
% Over COMMAND Voltage(2)
–12%
–80
–9%
20
–5%
Hysteresis
mV
ENABLE PIN
Pull Up Current
VEN = 2.5 V
–50
0
–20
µA
VOLTAGE ERROR AMPLIFIER
Input Offset Voltage
Input Bias Current
VCM = 3 V
–10
10
mV
µA
dB
VCM = 3 V
–0.5
0.5
Open Loop Gain
2.05 V < VCOMP < 3.05 V
10.8 V < VIN < 15 V
90
85
Power Supply Rejection Ratio
Output Sourcing Current
Output Sinking Current
dB
VVFB = 2 V, VCOMMAND = VCOMP = 2.5 V
VVFB = 3 V, VCOMMAND = VCOMP = 2.5 V
–1.6
1
–0.8
mA
mA
(1) This test measures the combined errors of the COMMAND voltage and the voltage amplifier offset voltage. Applies to all DAC codes
from 1.8 V to 3.5 V.
(2) This percentage is measured with respect to the ideal COMMAND voltage programmed by the D0–D4 pins.
3
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, VIN = VDRVHI = VDRVLO = 12 V, VSNS = 3.5 V, VD0 = VD1 = VD2 = VD3 = VD4 = 0 V, RT = 13 k,
CT = 1.8 nF, EN = Open, 0°C < TA < 70°C, TA = TJ.
PARAMETER
CURRENT SENSE AMPLIFIER
Gain
TEST CONDITIONS
MIN
TYP
MAX
UNIT
15
16
60
80
–4
4
17
V/V
dB
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Output Sourcing Current
Output Sinking Current
CURRENT AMPLIFIER
Input Offset Voltage
0 V < VCM < 4.5 V
10.8 V < VIN < 15 V
dB
VIS– = 2 V, VISOUT = VIS+ = 2.5 V
VIS– = 3 V, VISOUT = VIS+ = 2.5 V
–3
mA
Ma
3
VCM = 3 V
1
–0.1
90
mV
µA
dB
V
Input Bias Current
VCM = 3 V
Open Loop Gain
1 V < VCAO < 2.5 V
Output Voltage High
3
Power Supply Rejection Ratio
Output Sourcing Current
Output Sinking Current
OSCILLATOR
10.8 V < VIN < 15 V
80
dB
mA
Ma
VCAM = 2 V, VCAO = VCOMP = 2.5 V
VCAM = 3 V, VCAO = VCOMP = 2.5 V
–7
17
TA = 25°C
324
300
360
360
1.67
1%
396
420
kHz
kHz
V
Initial Accuracy
0°C < TA < 70°C
Valley to Peak Voltage
Frequency Change With Voltage
10.8 V < VIN < 15 V
OUTPUT SECTION (GATEHI AND GATELO)
Output Low Voltage
IGATE = –100 mA
0.2
11.8
20
V
V
Output High Voltage
IGATE = 100 mA
Rise Time
CGATE = 3.3 nF, RSERIES = 10 Ω
CGATE = 3.3 nF, RSERIES = 10 Ω
80
80
ns
ns
Fall Time
15
TURN ON DALAY
GATEHI Turn Off to GATELO Turn On
GATELO Turn Off to GATEHI Turn On
FOLDBACK CURRENT LIMIT
150
135
ns
ns
(3)
VCOMMAND = VSNS, VFB = VCOMMAND– 100mV
1.37
0.71
17
Clamp Level
V
A
(3)
VCOMMAND = 0, VFB = VCOMMAND– 100mV
System Short Circuit Current Limit
VCOMMAND = 2.3 V, VFB = 0 V(4)
14.4
22
(3) This voltage is measured with respect to the COMMAND voltage.
(4) The calculation of this parameter assumes an offchip sense resistor value of 0.005 Ω . This test encompasses all sources of error from
the IC.
PIN DESCRIPTIONS
CAM: This pin is the inverting input to the current
amplifier. The average load current feedback from the
ISOUT pin is applied through a resistor to this pin.
The current loop compensation network is also
connected to this pin (see CAO).
regulates the output voltage of the system. The
voltage at this output ranges from below 0.5 V
(forcing 0% duty cycle) to above 2.5 V forcing
maximum duty cycle. A 3 V clamp circuit prevents the
CAO voltage from rising excessively past the
oscillator peak voltage, for excellent transient
response.
CAO: This pin is the current amplifier output. The
current loop compensation network is connected
between this pin and the CAM pin. The voltage on
this pin is the input to the PWM comparator and
4
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
COMP: This pin is the voltage error amplifier output
voltage. The system voltage compensation network is
applied between COMP and VFB. A 1.37 V clamp
above COMMAND is used to force the power supply
into current limit mode when the output is short
circuited. See the Applications Section for
programming current limit.
overshoot. Good layout techniques should be used to
prevent GATELO from ringing more than 0.3 V below
PGND. The VDRVLO pin provides the power for
GATELO. GATELO is disabled during UVLO
conditions. For the 3882, GATELO is also disabled
when the COMMAND voltage is programmed
between 1.3 V and 1.75 V, or where the D0–D4 pins
are all logic high levels, indicating no processor
present.
COMMAND: This pin is the output of the 5-bit
digital-to-analog (DAC) converter and is the
non-inverting input of the voltage error amplifier. The
voltage on this pin sets the switching regulator output
voltage. The COMMAND voltage is set by the DAC
input pins D0-D4, according to Table 1. The
COMMAND source impedance typically 1.2 kΩ and
must therefore drive only high impedance inputs if
accuracy is to be maintained. Bypass COMMAND
with a 0.01 µF, low ESR, low ESL capacitor for best
circuit noise immunity.
GND: Ground reference for the device. All voltages,
with the exception of the GATE voltages, are
measured with respect to GND. Bypass capacitors on
VIN, VREF, VSNS and COMMAND should be
connected directly to the ground plane near GND.
IS–: This pin is the inverting input to the current
sense amplifier and is connected to the low side of
the average current sense resistor.
IS+: This pin is the non-inverting input to the current
sense amplifier and is connected to the high side of
the average current sense resistor.
CT: This pin is used with RT to program the internal
PWM oscillator frequency. Use
a high quality
capacitor for best oscillator accuracy. See the
Applications Section for programming the oscillator.a
ISOUT: This pin is the output of the current sense
amplifier. The voltage on this pin is equal to the
voltage across the sense resistor multiplied by 16 and
biased up by the COMMAND voltage. This voltage is
used for Average Current mode control and for
current limiting.
D0-D4: These are the digital input control codes for
the DAC (see Table 1). The DAC is comprised of two
ranges set by D4 and with D0 representing the least
significant bit (LSB) and D3, the most significant bit
(MSB). A bit is set low by being connected to GND; a
bit is set high by floating it, or connecting it to a 5 V
source. Each control pin is pulled up to approximately
5V by an internal pull up.i
PGND: This pin provides a dedicated ground for the
output gate drivers. The GND and PGND pins should
be connected externally using a short PC board trace
or plane. Decouple VDRVHI and VDRVLO to PGND
with low ESR capacitor of at least 0.1 µF.
EN: This input is used to disable the GATEHI and
GATELO outputs, resulting in disabling the power
supply. Pulling EN to GND causes the GATEHI and
GATELO outputs to be held low, while floating the pin
or pulling it up to 5V ensures normal operation. EN is
pulled up to 5V internally.
PWRGD: This pin is an open drain output which is
driven low to reset the microprocessor when VSNS
rises above or falls below its nominal value by 9%.
The on resistance of the open-drain switch will be no
higher than 470 Ω. This output should be pulled up to
a logic level voltage and should be programmed to
sink 1 mA or less.
GATEHI: This output provides a low impedance
totem pole driver to drive the high-side external
MOSFET. A series resistor between this pin and the
gate of the external MOSFET is recommended to
prevent gate drive ringing and overshoot. Good layout
techniques should be used to prevent GATEHI from
ringing more than 0.3V below PGND. The VDRVHI
pin provides the power for the GATEHI pin. GATEHI
is disabled during UVLO and overvoltage conditions.
For the 3882, GATEHI is also disabled when the
COMMAND voltage is programmed between 1.3 V
and 1.75 V, or where the D0–D4 pins are all logic
high levels, indicating no processor present.
RT: This pin is used with CT to program the internal
PWM oscillator frequency. It is also used to program
the delay times between the external MOSFET turn
on and turn off periods, which eliminates cross
conduction in those MOSFETs. See the Applications
Section for programming the oscillator and for
controlling cross conduction.
VDRVHI: This pin supplies power to the high side
output driver, GATEHI. Connect VDRVHI to an 18V
or lower source for power supplies converting 12VDC
to lower voltages, and to a 12V source for systems
for power supplies converting 5VDC. This pin should
be bypassed directly to PGND using a low ESR
capacitor.
GATELO: This output provides a low impedance
totem pole driver to drive the low-side synchronous
external MOSFET. A series resistor between this pin
and the gate of the external MOSFET is
recommended to prevent gate drive ringing and
5
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
VDRVLO: This pin supplies power to the low side
output driver, GATELO. VDRVLO is typically
connected to a 12V source, but may be connected to
a 5V source for driving logic level MOSFETs. This pin
should be bypassed directly to PGND using a low
ESR capacitor.
output and enables the GATELO output, forcing 0%
duty cycle on the power supply. This pin is also used
by the foldback current limiting circuitry to indicate
when the output voltage has been short circuited.
VSNS should be decoupled very closely to the IC
with
a capacitor to GND. The OV and UV
comparators’ hysteresis is typically 20mV, requiring
good layout and filtering techniques to insure that
noise and ground-bounce do not inadvertently trip the
OV and UV comparators. It is recommended that an
R-C filter set to approximately Fs/10 be used to filter
noise from the system output, where Fs is the
oscillator frequency.
VIN: This pin supplies power to the chip. Connect
VIN to a stable voltage source that is at least 10.8V
above GND. The GATEHI, GATELO and PWRGD
outputs will be held low until VCC exceeds the upper
undervoltage lockout threshold. This pin should be
bypassed directly to GND.
VFB: This pin is the inverting input to the error
amplifier. This input is connected to COMP through a
feedback network and to the power supply output
through a resistor or a divider network.
DAC INFORMATION
The 5-bit Digital-to-Analog Converter (DAC) is
programmed according to Table 1.The COMMAND
voltage is always active as long as the UCC3882 VIN
pin is above the undervoltage lockout voltage. For the
3882, the output gate drives GATEHI and GATELO
are disabled at certain DAC codes, as shown in
Table 1. Disabling the gate drives disables the power
supply. For the 3882 -1, the GATEHI and GATELO
drives are enabled for all DAC codes. For a given
code, the power supply output regulates at the
corresponding COMMAND voltage.
VREF: This pin provides an accurate 5V reference
and is internally short circuit current limited. VREF
powers the D/A Converter and also provides a
threshold voltage for the UVLO comparator. For best
reference stability, bypass VREF directly to GND with
a low ESR, low ESL capacitor of at least 0.01 µF.
VSNS: This pin is connected to the system output
voltage through a low pass R-C filter. When the
voltage on VSNS rises above or falls below the
COMMAND voltage by 9%, the PWRGD output is
driven low to reset the microprocessor. When the
voltage on VSNS rises above the COMMAND voltage
by 17.5%, the OVP comparator disables the GATEHI
Table 1. Programming the Command Voltage for the UCC3882
Digital Command
Command
Voltage
GATEHI/GATELO
Status
Digital Command
Command
Voltage
GATEHI/GATELO
Status
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
2.050
Note 1 ?
Note 1 ?
Note 1 ?
Note 1 ?
Note 1 ?
Note 1 ?
Note 1 ?
Note 1 ?
Note 1 ?
Note 1 ?
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
3.300
3.400
3.500
Note 1 ?
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
6
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
APPLICATION INFORMATION
This IC is intended to be used in a high performance
power supply to power the Pentium® II or a similar
processor. Figure 1 shows a typical power supply
application circuit which converts +5V to lower
voltages required by the Pentium®II Processor.
For convenience, values are shown in Table 1 for
nominal frequencies from 100 kHz to 700 kHz using
standards resistors and capacitor values.
Table 2. Programming Standard Frequencies
FREQUENCY
(kHz)
RT
(kΩ)
CT
(pF)
Synchronous Switching Delay Time
100
200
300
400
500
600
700
14.7
11.0
10.5
11.3
12.7
10.7
11.0
5600
3900
2700
1800
1200
1200
1000
Figure 2 shows that the fundamental difference
between a Buck and a Synchronous Buck regulator is
the use of a MOSFET rather than a Schottky diode
as the low side or free-wheeling switch.
In order to maintain safe and efficient operation of a
Synchronous Buck regulator, both MOSFETs, Q1 and
Q2, should never be turned on at the same time.
Having both MOSFETs on at the same time results in
cross conduction, which can result in excessively high
power dissipation in one or both MOSFETs. The
UCC3882 has a built in delay between the turn OFF
of one MOSFET and the turn ON of the other
MOSFET. This delay is a controlled delay between
the GATEHI and GATELO drive outputs and is
programmable by the selection of the resistor RT.
Controlling the delay between the gate drive outputs
is only part of the solution. The power supply
designer must also understand intrinsic delays
involving MOSFET turn on, turn off, rise and fall times
in order to insure that there is no cross conduction.
An excessively long delay time between gate drive
signals, or a delay time that is too small, will result in
a inefficient power supply design. The third step in
programming the oscillator is to observe the actual
circuit waveforms to insure that the delay is optimal.
The designer should vary RT and CT accordingly to
adjust the delay time and to program the proper
oscillator frequency.
Using an External Schottky Diode in Parallel
With the Low Side MOSFET
The purpose of using a synchronous buck regulator is
to substitute a low voltage drop MOSFET in place of
a Schottky diode as the low side switch. An external
Schottky diode may still be required however, in order
to reduce the losses due to the reverse recovery of
the low-side MOSFET body diode. Figure 4 illustrates
the effects on power losses due to the non-ideal
nature of a typical MOSFET body diode. IRM is the
peak recovery current of the body diode of Q2 and
ILOUT is the current of the output inductor. Using a
parallel Schottky diode can reduce these losses and
increase circuit efficiency. The size of the diode
should be increased as a function of load current,
input voltage, and operating frequency. The diode
should be as close to the lower MOSFET, Q2, as
possible, to reduce stray inductance.
It is recommended that a value between 10 kΩ and
15 kΩ be used for RT, which minimizes the delay and
can result in the highest efficiency operation. A higher
value of RT will result in a larger delay between the
MOSFET Gate transitions. RT should be between 10
kΩ minimum and 50 kΩ maximum.
Programming the Oscillator
The first step in programming the oscillator is
choosing the value of RT as described above. The
second step is to program the frequency according to
the curves shown in Figure 3, by choosing the
appropriate capacitor value.ransitions. RT should be
between 10 kΩ minimum and 50 kΩ maximum.
7
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
V
P
CC
L1
R1
5 V
IN
Q1
1.6 µH
0.005 Ω
IRL3103
C4
C1
C2
C3
C20
C5
C6
C7
C8
C9
C10
Q2
IRL3103D1
1500 µF
1500 µF 1500 µF
1500 µF
1500 µF 1500 µF
1500 µF 1500 µF 1500 µF 0.1 µF
4.7 µF
R9
3.3 Ω
R10
3.3 Ω
R2
PWRGD
10 KΩ
C14
12 V
IN
0.01 µF
C15
0.1 µF
U1
VSNS
1
2
GND
28
PWRGD
VID0
VID1
NC
CAM
CAO
3
4
5
27 D0
C18
R8
D1
26
25
10 KΩ
1500 pF
NC
C19
R7
VID2
VID3
VID4
D2
24
ISOUT
6
5.6 KΩ
220 pF
23 D3
IS+
IS−
VIN
7
8
D4
22
21
VREF
9
ISHARE
OUTEN
COMMAND
VCRV1
20
19
VDRV2 10
C11
0.1 µF
GATE2
PGND
11
GATE1
EN
18
17
12
13
14
RT
CT
COMP
VFB
16
15
R
T
10 kΩ
C
T
UCC3882
R6
3900 pF
F SWITCH = 225 kHz
100 KΩ
R3
5.62 KΩ
C12
C13
C17
0.01 µF
0.01 µF
R5
365 kΩ
68 pF
UDG−97048−1
Figure 1. Application Circuit – Pentium® II Power Supply
The UCC3882 incorporates short circuit current
foldback, as shown in Figure 6. When the output of
the power supply is short circuited, the output voltage
falls. When the output voltage reaches 1/2 of its
nominal voltage (COMMAND/ 2) then the output
current is reduced. This feature reduces the amount
of current in the MOSFETs and capacitors, and
insures high reliability.
Choosing RSENSE to Set the Current Limit
RSENSE is chosen to limit the maximum (short circuit)
current of the power supply. The short circuit current
equation for the UCC3882 is:
1.37 V
RSENSE 16
ISC +
(1)
and therefore, the value of the sense resistor, for a
chosen short circuit current is:
1.37 V
ISC 16
RSENSE +
(2)
The short circuit current limit does vary slightly as a
function of the switching regulator’s output inductor
value and operating frequency because a high value
of ripple current will reduce the average short circuit
current limit. Figure 5 shows the variation in Isc given
common values for the UCC3882. The UCC3882 is
nominally configured so that a 0.005 mΩ resistor will
set the current limit to approximately 17A.
8
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
capability and their voltage rating. The input
capacitors must handle virtually all of the RMS
current at the switching frequency, even if the circuit
does not have an input inductor. The switching
current in the input capacitors appears as shown in
Figure 7.
L
OUT
V
OUT
V
IN
V
SOURCE
Q1
C
OUT
D2
R
G
Aluminum or tantalum capacitors can be used. The
amount of RMS current in an Electrolytic capacitor
has a strong impact on the reliability and lifetime of
the capacitor. Other factors which affect the life of an
input capacitor are internal heat rise, external airflow,
the amount of time that the circuit operates at
maximum current and the operating voltage. The
curves in Figure 8 show the RMS current handled by
the total input capacitance in typical VRM circuits
powered from 5 V or from 12 V.
High
Drive
L
OUT
V
IN
V
Q1
OUT
V
SOURCE
C
OUT
R
G
Q2
R
G
Low
Drive
High
Drive
L
V
IN
OUT
V
OUT
Q1
V
SOURCE
UDG−97049
Q2 Body
Diode
C
OUT
R
G
Figure 2. Buck vs Synchronous Buck Regulator
High
Drive
800
1 nF
Waveforms Without Reverse Recovery
Waveforms Including Reverse Recovery
Characteristics
700
1.2 nF
600
500
V
1.8 nF
SOURCE
2.7 nF
400
DRAIN
CURRENT
I
2.2 nF
LOUT + IRM
I
LOUT
3.9 nF
300
I
200
LOUT
DIODE
CURRENT
100
5.6 nF
0
IRM
Area Under
This Curve
BODY
DIODE
LOSSES
10
15
20
25
Is Q
RR
RT − Resistor Timing − kW
Figure 3. Programming UCC3882
Oscillator Frequency
Excess Losses Due
to Reverse Recovery
Characteristics in
Body Diode and
MOSFET Q1
Q1
LOSSES
Choosing VDRVLO, VDRVHI and VIN,
T
A
T
B
T
RR
The UCC3882 requires a nominal 12V input supplied
at VIN. VDRVLO and VDRVHI can be set to any
voltage less than 18.5V, and may be set individually.
A power supply deriving its power from +5V should
use +12V at the VDRVHI pin, but may use either +5V
or +12V depending on the drive requirements of the
synchronous low-side MOSFET. A power supply
deriving its power from +12V should use +18V at
VDRVHI in order to provide adequate voltage (6 V)
gate drive to the high-side MOSFET. VIN must be
less than +15V.
UDG−97051
Figure 4. Effects of Reverse Recovery in a
Synchronous Rectifier
Input Capacitors
The input capacitors are chosen primarily based on
their switching frequency RMS current handling
9
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
6.5
10
9
8
7
6
5
4
3
2
1
0
400 kHz, 3 mH
V
= 5 V, V = 1.8 V
OUT
IN
V
= 5 V, V
= 2.8 V
IN
OUT
6
5.5
V
= 12 V, V
OUT
= 2.8 V
IN
200 kHz, 3 mH
300 kHz, 1.5 mH
400 kHz, 1.5 mH
V
= 12 V, V = 1.8 V
OUT
5
IN
Choose the type and number of the input capacitors based
on these curves by choosing the input voltage and nominal
output Voltage. Example: For a 5 V input, 1.8 V outout power
supply with a load of 15 Amperes, the input capacitors
ahould be chosen for 7.5 Amperes RMS current.
4.5
200 kHz, 1.5 mH
4
10
11
12
13
14
15
16
17
18
19
20
13
14
15
16
17
18
19
20
Short Circuit Current − A
Load Current − A
Figure 5. Short Circuit Current Limit vs RSENSE for
Various Frequency and Inductor Values
Figure 8. Load Current vs RMS Current for Input
Capacitors – Pentium® II Family
100
80
Demonstration Kit Design and Performance
A demonstration circuit was built based on the
UCC3882 and utilizing an Intel VRM 8.1 form factor
connector. The schematic is shown in Figure 9 and
the list of materials in Table 3. The circuit is
configured for the following operating parameters:
60
•
•
•
•
Switching Frequency = 225 kHz
Rated Output Current = 15 A
Short Circuit Current = 17 A Nominal
Output Voltage: 1.8 V to 2.8 V Configured by VID
Code.
40
20
0
0
20
40
60
80
100
•
•
•
Airflow: 100 LFM
Temperature: 0°C to 60°C
Regulation: Per Intel VRM 8.1 DC-DC Converter
Design Guidelines
Short Circuit Current − %
Figure 6. Short circuit Foldback Reduces Stress
on Circuit Components by Reducing Short Circuit
Current
Figure 17–Figure 19 show the performance of the
circuit.
V
IN
ON
0
V
REPPLE
V
I
C
I
OFF
D • Ts
(I−D) • Ts
2
2
• (I−D)
RMS CAPACITOR CURRENT
I
• D+I
ON
OFF
UDG−96216
Figure 7. Input Capacitors Current Waveform
10
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
Table 3. List of Materials
REF
U1
DESCRIPTION
Unitrode UCC3882 DAC/PWM
PACKAGE
SOIC-28 WIDE
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
SPRAGUE Size A,
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
10x20mm Radial Can
1206 SMD
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C17
C18
C19
C20
CT
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
Sprague/Vishay 595D475X0016A2B, 4.7 µF 16 V Tantalum
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
0.10 µF Ceramic
0.10 µF Ceramic
1206 SMD
0.01 µF Ceramic
0603 SMD
0.01 µF Ceramic
0603 SMD
0.01 µF Ceramic
0603 SMD
0.10 µF Ceramic
1206 SMD
68 pF NPO Ceramic
0603 SMD
1000 pF Ceramic
0603 SMD
220 pF NPO Ceramic
0603 SMD
Sanyo 6MV1500GX, 1500 µF, 6.3 V, Aluminum Electrolytic
3900pF Ceramic
10x20mm Radial Can
0603 SMD
J1
AMP 532956-7 40 Pin Connector
Toroid T51-52C, 5 Turns #16AWG, 1.6 µH
International Rectifier IRL3103, 30 V, 56 A
International Rectifier IRL3103D1, 30 V, 56 A
5 mΩ, PCB Resistor
40 Pin
L1
Toroid
Q1
TO-220AB, layed down
TO-220AB, layed down
Copper Trace
0603 SMD
Q2
R01
R02
R03
R05
R06
R07
R08
R09
R10
10 kΩ, 5%, 1/16 Watt
5.62 kΩ, 1%, 1/16 Watt
0603 SMD
365 kΩ, 1%, 1/16 Watt
0603 SMD
100 kΩ, 5%, 1/16 Watt
0603 SMD
5.6 kΩ, 5%, 1/16 Watt
0603 SMD
10 kΩ, 5%, 1/16 Watt
0603 SMD
3.3 Ω, 5%, 1/16 Watt
0603 SMD
3.3 Ω, 5%, 1/16 Watt
0603 SMD
11
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
V
P
CC
A10
B11
A12
B13
A14
B15
5 V
IN
L1
R1
Q1
1.6 µH
0.005 Ω
IRL3103
A16
B17
A18
B19
A20
C1
C2
C3
C20
C4
C5
C6
C7
C8
C9
C10
Q2
IRL3103D1
1500 µF 1500 µF 1500 µF 1500 µF 4.7 µF
1500 µF 1500 µF 1500 µF 1500 µF 1500 µF
0.1 µF
A1
B1
A2
B2
A3
R10
3.3 Ω
R2
B10
A11
C14
10 kΩ
R9
0.01 µF
3.3 Ω
B12
A13
B14
A15
B16
A17
B18
A19
B20
B9 PWRGD
C15
U1
0.1 µF
1
2
VSNS
PWRGD
NC
GND
28
A4 12 V
IN
B4
3
4
C18
R8
CAM
10 kΩ
1500 pF
A7 VIDO
27
26
D0
D1
CAO
5
6
B7 VID1
C19
220 pF
R7
ISOUT
25 NC
5.6 kΩ
A8 VID2
24 D2
7
8
IS+
IS−
B8 VID3
A9 VID4
23
D3
D4
22
VREF
VIN
9
21
A6 ISHARE
20 COMMAND
VDRV2
10
C11
19
VDRV1
0.1 µF
GATE2
11
18 GATE1
17 EN
PGND 12
RT 13
B6 OUTEN
B3 NC
A5 NC
B5 NC
COMP
16
R
T
CT
14
10 kΩ
C
T
VFB
15
UCC3882
3900 pF
R6
C12
0.01 µF
C13
0.01 µF
F
SWITCH = 225 kHz
100 kΩ
R3
C17
5.62 kΩ
R5
365 kΩ
68 pF
UDG−97140
Figure 9. Reference Design – UCC3882 5-Bit Synchronous Wectifier PWM Controller for the Intel
Pentium®II Processor
12
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
Figure 10. Demo Board
Figure 11. COMP Silkscreen
Figure 12. COMP Side
Figure 13. GND Layer
Figure 14. PWR Layer
Figure 15. Solder Side
Figure 16. Drill Drawing
13
UCC3882/-1
www.ti.com
SLUS294A–MARCH 1999–REVISED OCTOBER 2005
Figure 17. Transient Response to 15.2A Step Load Channel 2 Scale is 50 mV/A
95
90
85
80
75
70
65
60
55
50
9
8
7
6
5
4
3
2
1
0
Efficiency
Power Dissipation
0
5
10
15
DC Load Current − A
Figure 18. 13. UCC3882 Demo Kit Efficiency
5
3
1
−1
−3
−5
0
2
4
6
8
10
12
14
16
Load Current − A
Figure 19. Load Regulation
14
PACKAGE OPTION ADDENDUM
www.ti.com
19-Oct-2005
PACKAGING INFORMATION
Orderable Device
UCC3882DW-1
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
28
28
28
28
28
28
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3882DW-1G4
UCC3882DWTR-1
UCC3882PW
SOIC
SOIC
DW
DW
PW
PW
PW
20 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TSSOP
TSSOP
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
UCC3882PWTR-1
UCC3882PWTR-1G4
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
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to Customer on an annual basis.
Addendum-Page 1
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相关型号：
UCC3885D
IC 0.5 A SWITCHING CONTROLLER, 400 kHz SWITCHING FREQ-MAX, PDSO14, Switching Regulator or Controller
TI
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