UCC3917J [TI]
Positive Floating Hot-Swap Power Manager;
| 型号： | UCC3917J |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Positive Floating Hot-Swap Power Manager |
| 文件： | 总9页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
application
INFO
UCC1917
UCC2917
UCC3917
available
Positive Floating Hot Swap Power Manager
FEATURES
DESCRIPTION
• Manages Hot Swap of 15V and
The UCC3917 family of positive floating hot swap managers provides complete
power management, hot swap, and fault handling capability. The voltage limita-
tion of the application is only restricted by the external component voltage limi-
tations. The IC provides its own supply voltage via a charge pump off of VOUT.
The onboard 10V shunt regulator protects the IC from excess voltage. The IC
also has catastrophic fault indication to alert the user that the ability to shut off
the output NMOS has been bypassed. All control and housekeeping functions
are integrated and externally programmable. These include the fault current
level, maximum output sourcing current, maximum fault time, soft start time,
and average NMOS power limiting.
Above
• Precision Fault Threshold
• Programmable Average Power
Limiting
• Programmable Linear Current
Control
• Programmable Overcurrent Limit
• Programmable Fault Time
The fault level across the current sense amplifier is fixed at 50mV to minimize
total drop out. Once 50mV is exceeded across the current sense resistor, the
fault timer will start. The maximum allowable sourcing current is programmed
with a voltage divider from the VREF/CATFLT pin to generate a fixed voltage
on the MAXI pin. The current level at which the output appears as a current
source is equal to VMAXI divided by the current sense resistor. If desired, a con-
trolled current startup can be programmed with a capacitor on MAXI.
• Internal Charge Pump to Control
External NMOS Device
• Fault Output and Catastrophic
Fault Indication
• Fault Mode Programmable to
Latch or Retry
When the output current is below the fault level, the output device is switched
on with full gate drive. When the output current exceeds the fault level, but is
less than maximum allowable sourcing level programmed by MAXI, the output
remains switched on, and the fault timer starts charging CT. Once CT charges
to 2.5V, the output device is turned off and attempts either a retry sometime
later or waits for the state on the LATCH pin to change if in latch mode. When
the output current reaches the maximum sourcing current level, the output de-
vice appears as a current source.
• Shutdown Control
• Undervoltage Lockout
BLOCK DIAGRAM
VDD
13
LATCH
16
V
1
3
PLIM
DD
UVLO
>10V=ENABLE
< 6V=DISABLE
V
DD
5V
40µA
VDD
40µA
DISABLE
SHTDWN 12
VOUT
OUTPUT
VOUT
OUTPUT
LOW
VOUT
FLTOUT 11
5V
C1P
8
OVER
CURRENT
REFERENCE
50mV
COMPARATOR
LOGIC
SUPPLY
2
4
SENSE
VOUT
ON-TIME
DELAY
C1N
C2P
C2N
7
6
5
10 CT
4V
200mV
9
15
VREF/CATFLT
14
MAXI
UDG-99055
VSS
SLUS203A - AUGUST 1999
UCC1917
UCC2917
UCC3917
ABSOLUTE MAXIMUM RATINGS
CONNECTION DIAGRAM
IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
SHTDWN Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –500µA
LATCH Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –500µA
VREF Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –500µA
PLIM Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
MAXI Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of package.
DIL-16, SOIC-16 (Top View)
J or N Package, D Package
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C for the UCC3917, –40°C to 85° for the
UCC2917 and –55°C to 125°C for the UCC1917, CT = 4.7nF. TA = TJ. All voltages are with respect to VOUT. Current is positive
into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
VDD Section
IDD
From VOUT (Note 1)
3.0
7.9
5.5
–6
5
11
9.7
7.5
–4
mA
V
UVLO Turn On Threshold
UVLO Off Voltage
8.8
6.5
–5
V
VSS Regulator Voltage
Fault Timing Section
Overcurrent Threshold
V
TA = 25°C
47.5
46
50
50
53
54
mV
mV
nA
µA
V
Over Operating Temperature
Overcurrent Input Bias
CT Charge Current
50
500
–28
4.5
VCT = 1V
–78
3.4
–50
CT Catastrophic Fault Threshold
CT Fault Threshold
2.25
0.32
1.7
2.5
0.5
2.7
2.75
0.62
3.7
V
CT Reset Threshold
Output Duty Cycle
V
Fault Condition
%
Output Section
Output High Voltage
IOUT = 0
6
5
8
7
10
9
V
V
V
V
V
IOUT = –500µA
IOUT = 0
Output Low Voltage
0
0.05
0.5
0.9
IOUT = 500µA
IOUT = 1mA
0.1
0.5
Linear Current Section
Sense Control Votlage
MAXI = 100mV
MAXI = 400mV
MAXI = 200mV
85
100
400
50
115
430
500
mV
mV
nA
370
Input Bias
SHUTDOWN Section
Shutdown Threshold
Input Current
2.0
24
2.4
40
2.8
60
V
SHTDWN = 0V
2
µA
ns
Shutdown Delay
100
500
UCC1917
UCC2917
UCC3917
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C for the UCC3917, –40°C to 85° for
the UCC2917 and –55°C to 125°C for the UCC1917, CT = 4.7nF. TA = TJ. All voltages are with respect to VOUT. Current is
positive into and negative out of the specified terminal.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
LATCH Section
Latch Threshold
Input Current
1.7
24
2
2.3
60
V
LATCH = 0V
40
µA
Fault Out Section
Fault Output High
Fault Output Low
6
8
10
V
V
0.01
0.05
Power Limiting Section
VSENSE Regulator Voltage
Duty Cycle Control
IPLIMIT = 64µA
IPLIMIT = 64µA
IPLIMIT = 1mA
4.5
0.6
5
5.5
1.7
0.2
V
%
%
1.2
0.1
0.045
VREF/CATFLT Section
VREF Regulator Voltage
Fault Output Low
4.5
5
5.5
0.50
70
V
V
IVREF/CATFLT = 5mA
0.22
40
Output Sink Current
VCT = 5V, VVREF/CATFLT = 5V
Relative to MAXI
15
mA
mV
Overload Comparator Threshold
110
200
290
Note 1: Set by user with RSS
.
PIN DESCRIPTIONS
age on MAXI divided by the current sense resistor. If de-
sired, a controlled current start up can be programmed
with a capacitor on MAXI (to VOUT), and a programmed
start delay can be achieved by driving the shutdown with
an open collector/drain device into an RC network.
C1N: Negative side of the upper charge pump capacitor.
C1P: Positive side of the upper charge pump capacitor.
C2N: Negative side of the lower charge pump capacitor.
C2P: Positive side of lower charge pump capacitor.
OUTPUT: Gate drive to the NMOS pass element.
CT: A capacitor is connected to this pin to set the fault
time. The fault time must be more than the time to
charge the external load capacitance (see Application In-
formation).
PLIM: This feature ensures that the average external
NMOS power dissipation is controlled. A resistor is con-
nected from this pin to the drain of the external NMOS
pass element. When the voltage across the NMOS ex-
ceeds 5V, current will flow into PLIM which adds to the
fault timer charge current, reducing the duty cycle from
the 3% level.
FLTOUT: This pin provides fault output indication. Inter-
face to this pin is usually performed through level shift
transistors. Under a non-fault condition, FLTOUT will pull
to a high state. When a fault is detected by the fault timer
or the under voltage lockout, this pin will drive to a low
state, indicating the output NMOS is in the off state.
SENSE: Input voltage from the current sense resistor.
When there is greater than 50mV across this pin with re-
spect to VOUT, a fault is sensed, and CT starts to
charge.
LATCH: Pulling this pin low causes a fault to latch until
this pin is brought high or a power on reset is attempted.
However, pulling this pin high before the reset time is
reached will not clear the fault until the reset time is
reached. Keeping LATCH high will result in normal oper-
ation of the fault timer. Users should note there will be an
RC delay dependent upon the external capacitor at this
pin.
SHTDWN: This pin provides shutdown control. Interface
to this pin is usually performed through level shift transis-
tors. When shutdown is driven low, the output disables
the NMOS pass device.
VDD: Power to the I.C. Is supplied by an external current
limiting resistor on initial power-up or if the load is
shorted. As the load voltages rises (VOUT), a small
amount of power is drawn from VOUT by an internal
charge pump. The charge pump’s input voltage is regu-
lated by an on-chip 5V zener. Power to VDD is supplied
MAXI: This pin programs the maximum allowable sour-
cing current. Since VREF/CATFLT is a regulated volt-
age, a voltage divider can be derived to generate the
program level for MAXI. The current level at which the
output appears as a current source is equal to the volt-
3
UCC1917
UCC2917
UCC3917
PIN DESCRIPTIONS (cont.)
by the charge pump under normal operation (i.e., exter- NMOS pass device, this pin pulls to a low state when CT
nal FET is on).
charges about the catastrophic fault thershold. A
possible application for this pin is to trigger the shutdown
of an auxilliaty FET in series with the main FET for
redundency.
VOUT: Ground reference for the IC.
VREF/CATFLT: This pin primarily provides an output ref-
erence for the programming of MAXI. Secondarily, it pro-
vides catastrophic fault indication. In a catastrophic fault,
when the IC unsuccessfully attempts to shutdown the
VSS: Negative reference out of the chip. Normally cur-
rent fed via a resistor to ground.
UDG-96265-1
Figure 1. Fault timing circuitry for the UCC3917, including power limit and overload.
APPLICATION INFORMATION
Note that under normal fault conditions where the output
Fault Timing
current is just above the fault level, VOUT ≅ VIN, IPL = 0,
and the CT charging current is just I1.
Fig. 1 shows the detailed circuitry for the fault timing func-
tion of the UCC3917. For simplicity, we first consider a
typical fault mode where the overload comparator and the
current source I3 do not come into play. A typical fault oc-
curs once the voltage across the current sense resistor,
RS, exceeds 50mV. This causes the over current com-
parator to trip and the timing capacitor to charge with cur-
rent source I1 plus the current from the power limiting
amplifier, or PLIM amplifier. The PLIM amplifier is de-
signed to only source current into the CT pin once the
voltage across the output FET exceeds 5V. The current
IPL is related to the voltage across the FET with the fol-
lowing expression:
During a fault, CT will charge at a rate determined by
the internal charging current and the external timing ca-
pacitor, CT. Once CT charges to 2.5V, the fault com-
parator switches and sets the fault latch. Setting the
fault latch causes both the output to switch off and the
charging switch to open. CT must now discharge with
current source I2 until 0.5V is reached. Once the voltage
at CT reaches 0.5V, the fault latch resets (assuming
LATCH is high, otherwise the fault latch will not reset
until the LATCH pin is brought high or a power-on reset
occurs) which re-enables the output and allows the fault
circuitry to regain control of the charging switch. If a fault
is still present, the overcurrent comparator will close the
charging switch causing the cycle to repeat. Under a
constant fault the duty cycle is given by:
(VIN – VOUT) – 5V
IPL
=
RPL
4
UCC1917
UCC2917
UCC3917
APPLICATION INFORMATION (cont.)
1.5µA
IPL + I1 IPL + 50µA
I2
PFET AVG = (VIN – VOUT) •IMAX •Duty Cycle
Duty Cycle =
≅
1.5µA
= (VIN – VOUT) •IMAX
•
IPL + 50µA
where IPL is 0µA under normal operations (see Fig. 2).
Where (VIN – VOUT) >> 5V,
VIN – VOUT
However, under large transients, average power dissipa-
tion can be limited using the PLIM pin. A proof follows,
average dissipation in the pass element is given by:
IPL
≅
RPL
I
OUT
I
MAX
I
FAULT
OUTPUT
CURRENT
I
O(nom)
t
V
CT
2.5V
C
VOLTAGE
T
(WITH RESPECT TO V
)
OUT
0.5V
0V
t
V
OUT
V
IN
OUTPUT VOLTAGE
(WITH RESPECT TO GND)
0V
t
t0
t1 t2
t3
t4
t5
t6 t7 t8
t9 t10
UDG-99147
t0: Safe condition - output current is nominal, output t5 = t3: Illustrates 3% duty cycle.
voltage is at the positive rail, VIN.
t6 = t4:
t1: Fault control reached - output current rises above
the programmed fault value, CT begins to charge with ≅
50µA.
t7: Output short circuit - if VOUT is short circuited to
ground, CT charges at a higher rate depending upon
the values for VIN and RPL
.
t2: Maximum current reached - output current reaches
the programmed maximum level and becomes a con-
t8: Fault occurs - output is still short circuited, but the
occurrence of a fault turns the FET off so no current is
conducted.
stant current with value IMAX
.
t3: Fault occurs - CT has charged to 2.5V, fault output
goes low, the FET turns off allowing no output current to
flow, VOUT discharges to ground.
t9 = t4: Output short circuit released, still in fault
mode.
t10 = t0: Fault released, safe condition - return to nor-
mal operation of the circuit breaker.
t4: Retry - CT has discharged to 0.5V, but fault current
is still exceeded, CT begins charging again, FET is on,
VOUT rises to VIN.
Note that t6 – t5 ≅ 36 • (t5 – t4).
Figure 2. Nominal timing diagram.
5
UCC1917
UCC2917
UCC3917
APPLICATION INFORMATION (cont.)
IOVERLOAD =IMAX + 200mV / RS
and where IPL >> 50µA, the duty cycle can be approxi-
mated as:
Once the overcurrent comparator trips the UCC3917 will
enter programmed fault mode (hiccup or latched). It
should be noted that on subsequent retries during Hic-
cup mode or if a short should occur when the UCC3917
is actively limiting the current, the output current will not
exceed IMAX. In the event that the external FET does
not respond during a fault the UCC3917 will set the
VREF/CATFLT pin low to indicate a catastrophic failure.
1.5µA •RPL
VIN −VOUT
.
Therefore the average power dissipation in the MOSFET
can be approximated by:
1.5µA •RPL
VIN - VOUT
PFET AVG = (VIN - VOUT) •IMAX
•
Selecting the Minimum Timing Capacitance
=IMAX •1.5µA •RPL
To ensure that the IC will startup correctly the designer
must ensure that the fault time programmed by CT ex-
ceeds the startup time of the load. The startup time
(TSTART) is a function of several components; load resis-
tance and load capacitance, soft start components R1,
R2 and CSS, the power limit current contribution deter-
mined by RPL, and CIN.
Notice that since (VIN – VOUT) cancels, average power
dissipation is limited in the NMOS pass element (see Fig.
3). Also, a value for RPL can be roughly determined from
this approximation.
PFET AVG
RPL
=
IMAX •I.5µA
For a parallel capacitor-constant current load:
(1)
CLOAD •VIN
RPL = INF
TSTART
=
IMAX –ILOAD
For a parallel R-C load :
TSTART
IMAX = 4A
RPL = 10M
RPL = 5M
=
(2)
VIN
–RLOAD •CLOAD • ln 1–
IMAX •RLOAD
RPL = 2M
RPL = 1M
If the power limit function is not be used then CT(min)
can be easily found:
RPL = 200k
RPL =500k
ICH •TSTART
(3)
CT (min)=
dVCT
where dVCT is the hysteresis on the fault detection cir-
cuitry. During operation in the latched fault mode config-
uration dVCT = 2.5V. When the UCC3917 is configured
for the hiccup or retry mode of fault operation
dVCT=2.0V.
Figure 3. Plot of average power vs. FET voltage
for increasing values of RPL
.
Overload Comparator
The overload comparator provides protection against a
shorted load during normal operation when the external
N-channel FET is fully enhanced. Once the FET is fully
enhanced the linear current amplifier essentially saturates
and the system is in effect operating open loop. Once the
FET is fully enhanced the linear current amplifier requires
a finite amount of time to respond to a shorted output
possibly destroying the external FET. The overload com-
parator is provided to quickly shutdown the external
MOSFET in the case of a shorted output (if the FET is
fully enhanced). During an output short CT is charged by
I3 at ~ 1mA. The current threshold for the overload com-
parator is a function of IMAX and a fixed offset and is de-
fined as:
If the power limit function is used the CT charging cur-
rent becomes a function of ICH + IPL. And CT(min) is
found from:
6
UCC1917
UCC2917
UCC3917
APPLICATION INFORMATION (cont.)
CT (min) ≅
(4) Please note that the actual on-time in hiccup mode
threshold current 60µA. For example, if the minimum
when operating into a short is defined by:
–t
LOAD •CLOAD
VIN –IMAX •RLOAD • 1–eR
CT •dVCT
(8)
T (on) =
seconds
ICH + IPL pk
( )
I
+
CH
RPL
where dVCT ~2.0V and
VIN
(9)
IPL pk =
A
( )
RPL
dt
•
dVCT
Selecting Other External Components
Other external components are necessary for correct
operation of the IC. Referring to the application diagram
I
(PK)
PL
at the back of the data sheet, resistors RSENSE, RSS
R1, R2 and R3 are required and follow certain equations
with a brief description following where applicable:
,
V
OUT
I
VIN-V
PL
PL
50mV
RSENSE
=
(Sense Resistor)
IFAULT
VIN – 5V
5mA
RSS
GND)
=
(Connected between VSS and
T
START
VIN –10
5mA
R3 =
(Used in series with a diode to
connect VIN to VDD)
Figure 4. Relationship between IPL, VOUT and TSTART
.
(R1+R2)> 20kΩ (Current limit out of VREF)
Since IPL is a function of the output voltage, VOUT, which
varies over time, equation 4 must be integrated to solve
for CT(min). However equation 4 can be easily approxi-
mated if the output voltage slews. If the output voltage
slews linearly then the CT charge current contribution
from the power limit circuitry is shown to be at a peak
when VOUT = 0V and at 0A when VOUT=VIN-VPL, where
VPL is the power limit voltage threshold. IPL is shown in
Fig. 4 below.
Lastly, the external capacitors used for the charge pump
are required and need to equal 0.1µF, i.e. CIN = CH =
C1 = C2 = 0.1µF.
LEVEL Shift Circuitry (Optional)
The UCC3917 can be used in many systems without
logic command or diagnostic feedback. If a system re-
quires control from low-voltage logic or feedback to
low-voltage logic, then level shifting circuits are required.
The level shift circuits in Fig. 5A and Fig. 5B show ways
to interface to LATCH and SHTDWN and the level shift
circuits in Fig. 6 show ways of interfacing from FLTOUT
to low-voltage logic.
Where IPL is defined as:
VIN –V
–VPL
(5)
(
≡
)
OUT
IPL
RPL
In Fig. 5A, resistor R limits the level shift current. Select
R so that the current in the level shift circuit never ex-
ceeds the absolute maximum current in the logic com-
mand inputs, 500µA. For example, if the maximum
supply voltage for the system is 75V, select
The average IPL current for the interval (0, TSTART) from
Fig. 4 is defined as:
2
(6)
VIN –V
(
)
PL
IPL AVG ≡
(
)
2•RPL •VIN
75V
R >
=150k Ω.
Equation 4 can now be simplified to:
500µA
ICH + IPL AVG
(7)
(
)
•TSTART
CT min ≅
R must also be chosen so that the minimum current in
the level shift circuit exceeds the worst case logic
( )
dVCT
7
UCC1917
UCC2917
UCC3917
APPLICATION INFORMATION (cont.)
R
TO
UCC3917
supply voltage for the system is 25V, choose
25V
C
R >
= 416k Ω.
SHTDWN
OR
60µA
LATCH
VOUT
The capacitor C shown on the output of this circuit is
useful to filter the level shift output and prevent false
triggering from noise. The minimum recommended ca-
pacitor value is 100pF. Larger capacitors will result in
better noise immunity and longer delay to logic com-
mand.
(A)
TO
UCC3917
SHTDWN
OR
C
LATCH
The circuit in Fig. 5B accomplished the same function as
the circuit in Fig. 5A, using different components. In this
circuit, select resistor R so that the transistor draws
enough current to exceed the 60µA logic threshold but
doesn’t exceed the 500µA maximum logic input current.
For example, if the input circuit is 5V logic, then
VOUT
R
UDG-99148
(B)
Figure 5. Potential level shift circuitry
to interface to LATCH and SHTDWN on the
V
V
V
DD
DD
DD
13
13
13
R1
LOCAL
VDD
11 FLTOUT
11 FLTOUT
LOCAL
VDD
LOCAL
VDD
11 FLTOUT
R1
R1
LOCAL
LOCAL
FAULT
LOCAL
FAULT
FAULT
R2
R2
R2
(A)
(B)
(C)
Figure 6. Potential level shift circuitry to interface to FLTOUT on the UCC3917.
8
UCC1917
UCC2917
UCC3917
APPLICATION INFORMATION (cont.)
V
IN
D1
R3
LATCH
16
VDD
13
R
PL
PLIM
V
1
3
DD
UVLO
>10V=ENABLE
< 6V=DISABLE
V
DD
5V
40µA
VDD
40µA
DISABLE
SHTDWN 12
FLTOUT 11
OUTPUT
VOUT
VOUT
OUTPUT
LOW
C
IN
VOUT
C1P
8
5V
OVER
CURRENT
REFERENCE
50mV
C1
10V SHUNT
REGULATOR
COMPARATOR
SENSE
VOUT
C1N
7
2
4
ON-TIME
DELAY
LOGIC
SUPPLY
R
SENSE
C2P
6
CT
C
T
C2
10
C2N
5
4V
200mV
9
15
14
VSS
MAXI
C
VREF/CATFLT
H
R1
R2
R
SS
C
SS
OUTPUT
UDG-99056
Figure 7. Positive floating hot swap power manager UCC1917, UCC2917 and UCC3917.
SAFETY RECOMMENDATIONS
Although the UCC3917 is designed to provide system device such as a fuse should be placed in series with
protection for all fault conditions, all integrated circuits can the power device. The UCC3917 will prevent the fuse
ultimately fail short. For this reason, if the UCC3917 is in- from blowing for virtually all fault conditions, increasing
tended for use in safety critical applications where UL or system reliability and reducing maintenance cost, in ad-
some other safety rating is required, a redundant safety dition to providing the hot swap benefits of the device.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
9
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