UCC3952DP-4 [TI]

Enhanced Single Cell Lithium-Ion Battery Protection IC; 增强的单节锂离子电池保护IC
UCC3952DP-4
型号: UCC3952DP-4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Enhanced Single Cell Lithium-Ion Battery Protection IC
增强的单节锂离子电池保护IC

电池
文件: 总5页 (文件大小:38K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
UCC3952-1/-2/-3/-4  
Enhanced Single Cell Lithium-Ion Battery Protection IC  
FEATURES  
DESCRIPTION  
Protects sensitive Lithium Ion cells  
from over-charging and  
over-discharging  
The UCC3952 is a monolithic BiCMOS lithium-ion battery protection circuit  
that is designed to enhance the useful operating life of one cell recharge-  
able battery pack. Cell protection features consist of internally trimmed  
charge and discharge voltage limits, discharge current limit with a delayed  
shutdown and an ultra low current sleep mode state when the cell is dis-  
charged. Additional features include an on chip MOSFET for reduced exter-  
nal component count and a charge pump for reduced power losses while  
charging or discharging a low cell voltage battery pack. This protection cir-  
cuit requires one external capacitor and is able to operate and safely shut-  
down in the presence of a short circuit condition.  
Dedicated for one cell applications  
Integrated low impedance MOSFET  
switch and sense resistor  
Precision trimmed overcharge and  
overdischarge voltage limits  
Extremely low power drain  
3A current capacity  
Overcurrent and Short Circuit  
Protection  
Reverse Charger Protection  
Thermal Protection  
APPLICATION DIAGRAM  
PACK+  
1
TCLK  
16  
15  
3k  
+
CBPS  
2
N/C  
0.1µF  
3
4
5
6
7
8
BNEG  
BNEG  
BNEG  
BNEG  
BNEG  
N/C 14  
PACK– 13  
PACK– 12  
PACK– 11  
PACK– 10  
CHARGER  
LOAD  
9
BNEG  
PACK–  
UDG-98205  
SLUS400A - FEBRUARY 2000  
UCC3952-1/-2/-3/-4  
CONNECTION DIAGRAMS  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage (PACK+ to BNEG) . . . . . . . . . . . . . . . . . . . . 7V  
Maximum Forward Voltage (PACK+ to PACK–) . . . . . . . . . 16V  
Maximum Reverse Voltage  
SOIC-16 (TOP VIEW)  
DP Package  
(where PACK+ to BNEG = 5V). . . . . . . . . . . . . . . . . . . . . 8V  
Maximum Cell Continuous Charge Current. . . . . . . . . . . . . . 3A  
Junction Temperature. . . . . . . . . . . . . . . . . . . . 55°C to 150°C  
Storage Temperature Range . . . . . . . . . . . . . . –40°C to 125°C  
TCLK  
N/C  
16 PACK+  
15 CBPS  
14 N/C  
1
2
3
4
5
6
7
8
Currents are positive into, negative out of the specified termi-  
nal. Consult Packaging Section of Databook for thermal limita-  
tions and considerations of packages. All voltages are  
referenced to GND.  
N/C  
SUB  
13 SUB  
SUB  
12 SUB  
BNEG  
BNEG  
BNEG  
11 PACK–  
10 PACK–  
TSSOP-16 (TOP VIEW)  
PW Package  
9
PACK–  
TCLK  
N/C  
1
2
3
4
5
6
7
8
16 PACK+  
15 CBPS  
14 N/C  
BNEG  
BNEG  
BNEG  
BNEG  
BNEG  
BNEG  
BCC-18 (TOP VIEW)  
GSH Package  
PACK–  
PACK–  
13  
12  
N/C TCLK  
PACK+ N/C  
17  
11 PACK–  
10 PACK–  
18  
N/C  
1
16  
2
CBPS 15  
N/C 14  
9
PACK–  
3
4
5
6
BNEG  
BNEG  
BNEG  
BNEG  
8
PACK– 13  
PACK– 12  
PACK– 11  
7
10  
PACK– PACK–  
9
BNEG BNEG  
Consult factory for GSH package availability.  
ELECTRICAL CHARACTERISTICS: Temperature Range: –20°C < TA < 70°C, Unless otherwise stated. All voltages are  
with respect to BNEG. TA = TJ  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
State Transition Threshold Section  
NORM to OV (VOV  
OV to NORM (VOVR)  
NORM to OV (VOV  
OV to NORM (VOVR)  
NORM to OV (VOV  
OV to NORM (VOVR)  
NORM to OV (VOV  
OV to NORM (VOVR)  
)
UCC3952-1  
UCC3952-1  
UCC3952-2  
UCC3952-2  
UCC3952-3  
UCC3952-3  
UCC3952-4  
UCC3952-4  
4.15  
3.85  
4.20  
3.90  
4.25  
3.95  
4.30  
4.00  
4.20  
3.90  
4.25  
3.95  
4.30  
4.00  
4.35  
4.05  
4.25  
3.95  
4.30  
4.00  
4.35  
4.05  
4.40  
4.10  
V
V
V
V
V
V
V
V
)
)
)
2
UCC3952-1/-2/-3/-4  
ELECTRICAL CHARACTERISTICS: Temperature Range: –20°C < TA < 70°C, Unless otherwise stated. All voltages are  
with respect to BNEG. TA = TJ  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
State Transition Threshold Section (cont.)  
OV Delay Time (TOV  
NORM to UV (VUV  
)
1
2
sec  
V
)
UCC3952-1, UCC3952-2, UCC3952-3,  
UCC3952-4  
2.25  
2.35  
2.65  
25  
2.45  
UV to NORM (VUVR)  
UCC3952-1, UCC3952-2, UCC3952-3,  
UCC3952-4  
2.55  
10  
2.75  
40  
V
Overdischarge Delay Time (TOD  
)
ms  
Short Circuit Protection Section  
ITHLD  
TDLY  
Discharge current limit, PACK+ = 3.7V  
3.0  
1
4.5  
2.5  
A
Discharge current delay, PACK+ = 3.7V, I = 6A  
ms  
M  
RRESET  
Discharge current reset resistance,  
PACK+ = 4.0  
7.5  
Bias Section  
IDD  
Normal operating current. VUV < VPACK < VOV  
Operating current in overvoltage VOV < VPACK  
Shutdown operating current VPACK < VUV  
5
8
µA  
µA  
µA  
V
11  
24  
2.5  
1.7  
VMIN  
Minimum cell voltage when all circuits are  
guaranteed to be fully functional  
FET Switch Section  
VPACK  
VPACK  
RON  
PACK+ > VOV, I(SWITCH) = 1mA to 2A  
Battery overcharged state switch permits  
discharge current only.  
100  
400  
mV  
mV  
mΩ  
PACK+ = 2.5V, I(SWITCH) = –1mA to –2A  
Battery overdischarged state switch permits  
charge current only.  
–600 –100  
50  
In Normal Mode (when not in OV or UV). This  
value includes package and bondwire resistance.  
PACK+ = 2.5V  
75  
Thermal Shutdown Section  
TS  
Thermal shutdown temperature. (Note 1)  
135  
°C  
Note 1. This parameter is guaranteed by design. Not 100% tested in production.  
PIN DESCRIPTIONS  
give the battery pack user appropriate access to the bat-  
tery. In an over-charged state, only discharge current is  
permitted. In an over-discharged state, only charge cur-  
rent is permitted.  
BNEG: Connect the negative terminal of the battery to  
this pin.  
PACK+: Connect to the positive terminal of the battery.  
This pin is available to the user.  
SUB: (DP Package Only) Do not connect. These pins  
must be electrically isolated from all other pins. These  
pins may be soldered to isolated coppper pads for  
heatsinking. However, most applications do not require  
heatsinking.  
CBPS: This power supply bypass pin is connected to  
PACK+ through an internal 10K resistor. An external  
0.1 F capacitor must be connected between this pin and  
BNEG.  
PACK–: The negative terminal of the battery pack (nega-  
tive terminal available to the user). The internal FET  
switch connects this terminal to the BNEG terminal to  
TCLK: Production Test Mode pin. This pin is used to  
provide a high frequency clock to the IC during produc-  
tion testing. In an application this pin may be left uncon-  
nected, or tied to BNEG.  
3
UCC3952-1/-2/-3/-4  
APPLICATION INFORMATION  
PACK+ 16  
10K  
V
UV  
CBPS 15  
V
UVR  
4-1  
MUX  
T
DEL  
OV  
STATE  
MACHINE  
LOGIC  
V
1SEC  
OVR  
THRESHOLD  
COMPARATOR  
TCLK  
N/C  
1
2
3
4
5
6
7
8
9
V
OV  
1.5V  
T
SEL  
DEL  
UV  
CLK  
10mS  
BNEG  
BNEG  
BNEG  
BNEG  
BNEG  
BNEG  
PACK–  
SYSTEM  
CLOCK  
GENERATOR  
TDLS  
1mS  
SETD  
V
PUMP  
50mV  
2M  
RST  
50mV  
THERMAL  
SHUTDOWN  
PACK– 10  
PACK– 11  
PACK– 12  
PACK– 13  
PACK– 14  
UDG-98209  
PW package shown  
Figure 1. Detailed block diagram.  
APPLICATION INFORMATION  
Fig. 1 shows a detailed block diagram of the UCC3952.  
nects the load from the battery pack and enters a super  
low power mode. The pack will remain in this state until it  
detects the application of a charger, at which point  
charging is enabled. The requirement of two consecutive  
readings below the UV threshold filters out momentary  
drops in cell voltage due to load transients, preventing  
nuisance trips.  
Battery Voltage Monitoring  
The battery cell voltage is sampled every 8ms by con-  
necting a resistor divider across it and comparing the re-  
sulting voltage to a precision internal reference voltage.  
Under normal conditions (cell voltage is below Over Volt-  
age threshold and above Under Voltage threshold), the  
UCC3952 consumes less than 10 A of current and the  
internal MOSFET is fully turned on with the aid of a  
charge pump.  
If the cell voltage exceeds the Over Voltage threshold for  
1sec, charging is disabled, however discharge current is  
still allowed. This feature of the IC is explained further in  
the section on Controlled Charge/Discharge Mode.  
When the cell voltage falls below the Under Voltage  
threshold for two consecutive samples, the IC discon-  
4
UCC3952-1/-2/-3/-4  
APPLICATION INFORMATION (cont.)  
Over Current Monitoring and Protection  
across the MOSFET to 100mV. When a light load is ap-  
plied to the part, the loop adjusts the impedance of the  
MOSFET to maintain 100mV across it. As the load in-  
creases, the impedance of the MOSFET is decreased to  
maintain the 100mV control. At heavy loads (still below  
“over-current” limit level), the loop will not maintain regu-  
lation and will drive the gate of the MOSFET to the bat-  
tery voltage (not the charge-pump output voltage). The  
MOSFET RDS(on) in the over-voltage state will be higher  
than RDS(on) during normal operation. The voltage drop  
(and associated power loss) across the internal MOSFET  
in this mode of operation is still significantly lower than  
the typical solution of two external back-to-back  
MOSFETs, where the body diode is conducting.  
Discharge current is continuously monitored via an inter-  
nal sense resistor. In the event of excessive current, an  
Over Current condition is declared if the high current  
(over 3A) persists for over 1ms. This delay allows for  
charging of the system bypass capacitors without trip-  
ping the overcurrent. A 0.1 F capacitor on the CBPS pin  
provides momentary holdup for the IC to assure proper  
operation in the event that a hard short suddenly pulls  
the cell voltage below the minimum operating voltage.  
Once an Over Current condition has been declared, the  
internal MOSFET turns off. The only way to return the  
pack to normal operation is to remove the load by un-  
plugging the pack from the system. The overcurrent is re-  
set when an internal pull down brings PACK(–) to within  
50mV of BNEG. At this point, the pack returns to its nor-  
mal state of operation.  
When the chip senses an under-voltage condition, it dis-  
connects the load from the battery pack and shuts itself  
down to minimize current drain from the battery. Several  
circuits remain powered and will detect placement of the  
battery pack into a charger. Once the charger presence  
is detected, the linear loop is activated and the chip al-  
lows charging current into the battery. This linear control  
mode of operation is in effect until the battery voltage  
reaches a level of VUVR, at which time normal operation  
is resumed.  
Controlled Charge/Discharge Mode  
When the chip senses an over-voltage condition, it pre-  
vents any additional charging, but allows discharge. This  
is accomplished by activating a linear control loop which  
controls the gate of the MOSFET based on the differen-  
tial voltage across its drain to source terminals. The lin-  
ear loop attempts to regulate the differential voltage  
UNITRODE CORPORATION  
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054  
TEL. (603) 424-2410 • FAX (603) 424-3460  
5

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