UCC3957MTR-1G4_技术文档

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

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FEATURES

DESCRIPTION

D

Three- or Four-Cell Operation

Two-Tier Overcurrent Limiting

The UCC3957 is a BiCMOS three- or four-cell

lithium-ion battery pack protector designed to

operate with external P-channel MOSFETs.

Utilizing external P-channel MOSFETs provides

the benefits of no loss-of-system ground in an

overdischarge state, and protects the IC as well as

battery cells from damage during an overcharge

state. An internal state machine runs continuously

to protect each lithium-ion cell from overcharge

and overdischarge. A separate overcurrent-

protection block protects the battery pack from

excessive discharge currents.

30-µA Typical Supply-Current Consumption

3.5-µA Typical Supply Current in Sleep Mode

Smart Discharge Minimizes Losses in

Overcharge Mode

6.5-V to 20-V VDD Supply Range

Highly Accurate Internal Voltage Reference

Externally Adjustable Delays in Overcurrent

Controller

If any cell voltage exceeds the overvoltage

threshold, the appropriate external P-channel

MOSFET is turned off, preventing further charge

current. An external N-channel MOSFET is

required to level shift to this high-side P-channel

MOSFET. Discharge current can still flow through

the second P-channel MOSFET. Likewise, if any

cell voltage falls below the undervoltage limit, the

second P-channel MOSFET is turned off and only

charge current is allowed. Such a cell-voltage

condition causes the chip to go into low-power

sleep mode. Attempting to charge the battery

pack wakes up the chip. A cell-count pin (CLCNT)

is provided to program the IC for three- or four-cell

operations.

D

Detection of Loss-of-Cell Sense Connections

M PACKAGE

(TOP VIEW)

VDD

CLCNT

WU

DVDD

AVDD

CDLY2

DCHG

CHG

1

2

3

4

5

6

7

8

16

15

14

13

12

11

AN1

AN2

A two-tiered overcurrent controller and external

current shunt protect the battery pack from

excessive discharge currents. If the first

overcurrent threshold level is exceeded, an

internal timing circuit charges an external

capacitor to provide a user programmable

blanking time. If at the end of the blanking time the

overcurrent condition still exists, the external

discharge FET is turned off for a period 17 times

longer than the first blanking period, and then the

discharge FET is turned back on. If at any time a

second higher overcurrent threshold is exceeded

for more than a user programmable time, the

discharge FET is turned off, and remains off for the

same period as the first tier off time. This two tiered

overcurrent-protection scheme allows for

charging capacitive loads while retaining effective

short-circuit protection.

AN3

AN4

10 CDLY1

CHGEN

BATLO

9

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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1

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

block diagram

VDD

CLCNT

WU

1

2

3

4

5

6

7

8

16 DVDD

15 AVDD

14 CDLY2

CELL

VOLTAGE

SELECT

STATE

MACHINE

REFERENCE

VOLTAGE

SELECT AND

COMPARE

REF

CLOCK

DCHG

AN1

13

S

R

Q

UV

SLEEP

AN2

12 CHG

11 AN4

VDD

+

AN3

AN4

10 CDLY1

OVERCURRENT

CONTROLLER

BATLO

9

CHGEN

UDG–00129

†‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V

Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Input voltage: (WU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 V

(AN1, AN2, AN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VAN4 – VDD

(CLCNT, CHGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V

Input voltage range (BATLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.5 V

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

J

Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. Consult

Packaging Information section of the Portable Products Databook (TI Literature No. SLUD001) for thermal limitations and considerations of

packages. All voltages are referenced to the AN4 terminal.

AVAILABLE OPTIONS

†

PACKAGED DEVICES

SSOP (M)

T

A

NORMAL TO OVERCHARGE VOLTAGE (V)

4.25 4.30

UCC3957M–1 UCC3957M–2 UCC3957M–3 UCC3957M–4

4.20

4.35

–20°C to 70°C

†

The M package is available taped and reeled. Add TR suffix to device type (e.g.

UCC3957M–1TR) to order quantities of 2500 devices per reel.

2

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

electrical characteristics over recommended operating free-air temperature range, VDD = 16 V,

–20_C < T < 70_C, T = T . (unless otherwise noted)

A

J

supply

PARAMETER

TEST CONDITIONS

MIN

TYP

5.0

30

MAX UNIT

VDD

IDD

Minimum VDD

Supply current

5.5

40

V

µA

V

min

I

Sleep-mode supply current

Input voltage for WU

VDD = 10.4 V

See Note 2

3.5

7.5

20

SL

V

IN

output

PARAMETER

TEST CONDITIONS

MIN

TYP

70

MAX UNIT

Driving-logic low,

Driving-logic high,

Driving-logic low,

Driving-logic high,

V

O

V

O

V

O

V

O

= 1 V

40

100

–3

µA

mA

µA

I

DCHG output current

DCHG

= (VDD – 1)

= 1 V

–13

70

40

100

–3

CHG ouput current

CHG

= (VDD – 1V)

–15

mA

state transitions

PARAMETER

TEST CONDITIONS

See Note 1

MIN

4.15

3.95

4.20

4.00

4.25

4.05

4.30

4.10

2.5

2.2

8

TYP

4.20

4.00

4.25

4.05

4.30

4.10

4.35

4.15

2.6

MAX UNIT

V

Normal to overcharge voltage

Overcharge to normal voltage

Normal to overcharge voltage

Overcharge to normal voltage

Normal to overcharge voltage

Overcharge to normal voltage

Normal to overcharge voltage

Overcharge to normal voltage

Undercharge to normal voltage

Normal to undercharge voltage

Overvoltage to CHG delay

Undervoltage to DCHG Delay

Cell sample rate

4.25

4.05

4.30

4.10

4.35

4.15

4.40

4.20

2.7

V

OV

UCC3957–1

UCC3957–2

UCC3957–3

UCC3957–4

OVR

OV

See Note 1

V

OVR

OV

V

OVR

OV

V

OVR

UV

V

2.3

2.4

V

UVR

td

OV

td

UV

17

23

ms

mV

V

8

17

23

t

S

4

8.5

11.5

25

V

SM

V

WU

V

CE

Smart discharge threshold

Wakeup input threshold

BATLO voltage

4

15

With respect to VDD

50

230

1.3

750

2.6

Charge-enable input threshold

0.8

short-circuit protection

PARAMETER

First-tier threshold level

TEST CONDITIONS

MIN

120

275

30

TYP

150

375

50

MAX UNIT

V

190

450

70

mV

ms

µs

CL1

BATLO

Second-tier threshold level

First-tier blanking time

Restart time

CL2

BATLO

t

CDLY1 = 0.1 µF

CDLY2 = 10 pF

B1

300

100

500

400

700

600

RST

B2

Second-tier blanking time

NOTE 1: Other overvoltage or undervoltage thresholds are available. Please consult the factory.

2: Refer to Figure 6, for WU leakage characteristics.

3

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

AN1

NO.

4

I

Connects to the negative terminal of the top battery cell and the positive terminal of the second battery cell.

Connects to the bottom terminal of the second battery cell and the top terminal of the third battery cell.

AN2

AN3

5

6

Connects to the bottom terminal of the third battery cell and the top terminal of the fourth battery cell in a four

cell stack. In a three cell pack it connects to the bottom terminal of the third battery and to AN4.

I

AN4

7

Connects to the bottom terminal of the battery stack and the top of the current sense resistor.

AVDD

15

Internal analog supply bypass cap pin. Connect a 0.1-µF capacitor between this pin and AN4. This pin is

nominally 7.3 V.

O

I

BATLO

8

9

Connects to the bottom of the current sense resistor and the negative terminal of the battery pack.

CHGEN

The charge enable input for the protection IC. This point must be driven high to DVDD or AVDD to allow

charging of the battery pack. This pin has a very weak pulldown.

I

CDLY1

10

Delay control pin for the short-circuit protection feature. A capacitor connected between this point and AN4

determines the time delay from when an overcurrent situation is detected to when the FET is turned off. This

capacitor also controls the hiccup mode timeout period.

O

I

CDLY2

CLCNT

14

2

An external cap can be tied between this pin and AN4 to extend the blanking time on the second current limit

tier.

This pin programs the IC for three or four cell operation. Tying this pin low (to AN4) sets four cell operation,

while tying it high (to DVDD or AVDD) sets three cell operation. This pin is internally pulled low, so open cir-

cuit conditions always result in four-cell mode.

DCHG

CHG

13

12

16

This pin is used to prevent overdischarge. If the state machine indicates that any cell is undervoltage, this pin

is driven high with respect to chip substrate so that the external P-channel MOSFET prevents further dis-

charge. If all cell voltages are above the minimum threshold, this pin is driven low.

O

This pin is used to control an external N-channel MOSFET, which in turn drives a P-channel MOSFET. If at

least one cell voltage is over the overvoltage threshold, this pin is driven low with respect to AN4. If all cell

voltages are below this threshold, this pin is driven high.

DVDD

Internal digital supply bypass capacitor pin. Connect a 0.1-µF capacitor between this pin and AN4. This pin is

nominally 7.3V.

O

I

VDD

WU

1

3

Supply voltage to the IC. Connect this point to the top of the lithium-ion battery stack.

This pin is used to provide a wakeup signal to the IC during sleep mode. Connect this pin to the drain of the

N-channel level shift MOSFET.

I

4

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

APPLICATION INFORMATION

overview

The UCC3957 provides complete protection against overdischarge, overcharge and overcurrent for a three-

or four-cell lithium-ion battery pack. It uses a flying capacitor technique to sample the voltage across each

battery cell and compare it to a precision reference. If any cell is in overvoltage or undervoltage, the

internal-state machine takes the appropriate action to prevent further charge or discharge. High-side P-channel

MOSFETs are used to independently control charge and discharge current. Figure 1 shows a three-cell

lithium-ion protector application diagram with the optional charge-enable switch. In this application, the diode

D1 protects the MOSFET Q2 from inductive kick at turn-off.

R1

1 MΩ

PACK (+)

Q3

Q1

2N7002

IFR7416

CHARGE

D1

1 A, 50 V

Q2

IFR7416

DISCHARGE

C1

0.1 µF

VDD

1

2

3

4

5

6

7

8

16

DVDD

C2

0.1 µF

LI–ION

C5

4.7 µF

25 V

BATTERY

STACK

CLCNT

WU

AVDD 15

CDLY2 14

C3

OPTIONAL

+

13

DCHG

AN1

AN2

AN3

AN4

CHG 12

AN4 11

C4

0.022 µF

CDLY1 10

R

SENSE

0.025 Ω

PACK (–)

BATLO CHGEN

9

S1

CLOSE TO ENABLE CHARGING

UDG–98016

Figure 1. Three-Cell Lithium-Ion Protector Application Diagram

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

APPLICATION INFORMATION

overview (continued)

Figure 2 shows a four-cell protector with optional components to protect the charge FET from excessive

gate-to-source transients. In this application, the Zener diode VR1 and the resistor R2 are optional. They protect

the MOSFET Q1 from excessive open-circuit charger voltage. Diode D1 protects MOSFET Q2 from inductive

kick during turn-off.

VR1 18 V

PACK (+)

R1 1 MΩ

R2

10 kΩ

Q1

IFR7416

CHARGE

D1

1 A, 50 V

Q3

2N7002

Q2

IFR7416

DISCHARGE

C5

C1

0.1 µF

4.7 µF

25 V

VDD

CLCNT

WU

1

2

3

4

5

6

7

8

16

DVDD

C2

0.1 µF

LI–ION

BATTERY

STACK

AVDD 15

CDLY2 14

C3

OPTIONAL

+

13

AN1

AN2

AN3

AN4

DCHG

CHG 12

AN4 11

C4

0.022 µF

CDLY1 10

R

SENSE

0.025 Ω

BATLO CHGEN

9

PACK (–)

UDG–98017

Figure 2. Four-Cell Lithium-Ion Protector Application Diagram

connecting the cell stack

When connecting the cell stack to the circuit, it is important to do so in the proper order. First, the bottom of the

stack should be connected to AN4 . Next, the top of the stack should be connected to VDD. The cell taps can

then be connected to AN1, AN2, and AN3 in any order.

choosing three or four cells

For three-cell packs, the cell-count pin (CLCNT) should be connected to the DVDD pin, and the AN3 pin should

be tied to the AN4 pin. For four-cell applications, the CLCNT pin should be grounded (to AN4) and the AN3 pin

is connected to the positive terminal of the bottom cell in the stack.

6

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

APPLICATION INFORMATION

undervoltage protection

When any cell is found to be overdischarged (below the normal-to-undercharge threshold), the state machine

turns off both high-side FETs and enters the sleep mode, where current consumption drops to about 3.5 µA.

It remains in sleep mode until the application of a charger is sensed by the wakeup pin (WU) being raised above

VDD.

charging

Once a charger has been applied, the charge FET is turned on as long as the charge-enable input pin (CHGEN)

is pulled up to the DVDD pin. If the CHGEN input is left open (or connected to AN4), the charge FET remains

off.

During charge, the charge and discharge FETs cycle on and off while the device is in the sleep state

(undercharge mode), until the cell voltages are all above the undercharge-to-normal threshold. Once the cell

voltages are above this threshold, the device enters the normal state and the FETs remain on continuously.

While the device is charging and in undercharge mode, there is an approximate on time of 8 ms corresponding

to one sampling period, with a very short off time corresponding to undercharge-voltage detect and sleep-mode;

once WU is pulled back up to PACK(+), wake-up detect again occurs, and a new sampling period/charge cycle

is initiated.

open wire protection

The UCC3957 provides protection against broken-cell sense connections within the pack. If the sense

connection to one of the cells (pins AN1, AN2, or AN3) should become disconnected, weak internal-current

sources make the cells that are connected to that wire appear to be in overcharge and charging of the pack is

prevented.

overvoltage protection and the smart discharge feature

If any cell is charged to a voltage exceeding the normal-to-overcharge threshold, the charge FET is turned off,

preventing further charge current. Hysteresis keeps the charge FET off until the cell voltages have dropped

below the overcharge-to-normal threshold. In most protector designs, the charge FET is held off completely

within this voltage band. During this time, discharge current must be conducted through the body diode of the

charge FET. This forward voltage drop can be as high as 1 V, causing significant power dissipation in the charge

FET and wasting precious battery power.

The UCC3957 has a unique smart discharge feature that allows the charge FET to return to on mode (for

discharge only) while still in the overcharge hysteresis band. This greatly reduces power dissipation in the

charge FET. This is accomplished by sensing the voltage drop across the current-sense resistor. If this drop

exceeds 15 mV (corresponding to 0.6 A of discharge current using a .025 Ω sense resistor), the charge FET

is turned back on. This threshold assures that only discharge current is conducted. In an example using a

20-mW FET with a 1-V body diode drop and a 1-A load, the power dissipation in Q1 would be reduced from 1

W to 0.02 W.

NOTE: A similar technique is not used during charge (when the discharge MOSFET is off due to

cells being in undervoltage) because the charge current should be low while the cells are in

undervoltage.

7

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SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

APPLICATION INFORMATION

protection against a runaway charger

The use of a small N-channel level shifter (Q3 in the application diagrams) allows the IC to interface with the

high-side charge FET (Q1), even in the presence of a runaway charger. Only the drain-source voltage rating

of the charge FET limits the charge voltage that the protection circuit can withstand. The wakeup (WU) pin is

designed to handle input voltages greater than VDD, as long as the current is limited. In the examples shown,

the charge FET’s gate-source resistor (R1) provides this current limiting. Note that in Figure 2, a resistor and

zener (R2 and VR1) have been added to protect Q1 against any possibility of a voltage transient exceeding its

maximum gate-source rating.

overcurrent protection

The UCC3957 protects the battery pack from an overload or a hard short circuit using a two-tier overcurrent

protection scheme. The overcurrent protection is designed to go into a hiccup mode when the voltage drop

across an external-sense resistor (connected to the AN4 and BATLO pins) exceeds a certain threshold. In this

mode, the discharge FET is periodically turned off and on until the fault is removed. Once the fault is removed,

normal operation is automatically resumed.

To facilitate charging large capacitive loads, there are two overcurrent threshold voltages, each with its own

user-programmable time delay. This two-tier approach provides fast response to short circuits, while enabling

the battery pack to provide short-duration surge currents. It also facilitates the charging of large filter caps

without causing nuisance overcurrent trips.

The first-tier threshold is 150 mV nominal, corresponding to 6 A using a .025-Ω sense resistor as shown in the

examples of Figure 1 and Figure 2. If the pack-discharge current exceeds this amount for a period of time,

determined by the capacitor on the CDLY1 pin, it then enters the hiccup mode. The first-tier hiccup duty cycle

is fixed at approximately 6%, minimizing power dissipation in the event of a sustained overload. The absolute

on and off times of the discharge FET (Q2) are controlled by the CDLY1 capacitor. A curve relating the delay

(on time) to this capacitor value is shown in Figure 4. The off time is approximately 17 times longer than the on

time.

The second-tier overcurrent threshold is nominally 375 mV, corresponding to 15 A using a .025-Ω sense resistor.

If the pack current exceeds this value for a period of time, determined by the capacitor on the CDLY2 pin, it then

enters the hiccup-mode with a much lower duty cycle, typically less than 1%. The relationship of this time delay

(on time) to the CDLY2 capacitor value is shown in the curve of Figure 5. The off time during this hiccup mode

is still determined by the CDLY1 capacitor, as previously described. This technique greatly reduces the stress

and power dissipation in the FETs during short-circuit conditions.

In the examples shown in Figure 1 and Figure 2 (with CDLY1 = .022 µF), the first-tier overcurrent on time is

approximately 10 msec, while the off time is approximately 170 msec, resulting in a 5.9% duty cycle for currents

over 6 A (but less than 15 A). If no CDLY2 capacitor is used, the second-tier on time is less than 200 µsec

(assuming no stray capacitance), resulting in a duty cycle of about 0.1% for currents over 15 A. If CDLY2 = 22pF,

the typical on time for currents exceeding 15 A is approximately 800 µsec, resulting in a duty cycle of 0.5%.

8

www.ti.com

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢉ

ꢈ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢂ

ꢈ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢊ

SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

APPLICATION INFORMATION

protecting against inductive kick at turn-off

In the case of a short circuit, the di/dt that occurs when the discharge FET is turned off can result in a significant

voltage undershoot at the pack output due to stray inductance. This undershoot can potentially exceed the

breakdown voltage rating of the discharge FET. A clamp diode (D1 in Figure 1, Figure 2, and Figure 3), or a

capacitor across the pack output, protects against this possibility. A diode also provides protection from a

reverse-polarity charger.

During turn-off, a voltage overshoot can occur at the top of the cell stack, due to wiring inductance and the cells’

internal equivalent series inductance (ESL). During very high di/dt conditions, such as occurs when turning off

in response to a short circuit, this voltage overshoot can be significant and potentially damage the IC or the

discharge FET (Q2). For this reason, it is strongly recommended that a capacitor (C5) be placed across the cell

stack, from VDD to AN4, and that stray inductance be minimized in the battery-current path. Additional methods

to reduce di/dt across the cell stack are discussed in the following section.

controlling discharge FET turn-on and turn-off times

Slew-rate limiting the pack output voltage at turn-on greatly reduces the surge current into large capacitive

loads.

This allows the designer to select shorter overcurrent-delay times, minimizing the stress on Q1 and Q2 in the

event of a shorted pack output. A simple method of implementing slew-rate limiting is shown in Figure 3. It

consists of an RC network (R3 and C6) between gate and drain of the discharge FET (Q2) to control its turn-on

time. This circuit relies on the relatively high-sink impedance (about 20 kΩ) of the UCC3957’s DCHG output.

The values shown for R3 and C6 provide a pack output voltage rise time of about 4.5 ms when the discharge

FET (Q2) is turned on. Note that the addition of R3 and C6 has made it possible to eliminate the CDLY2

capacitor, for the quickest response to a true short circuit. While this circuit does not prevent a large surge current

when inserting a live battery pack into a highly-capacitive load, it does allow it to restart (after one hiccup cycle)

if this initial surge-current trips the overcurrent protection.

Increasing the turn-off time of the discharge FET (Q2) reduces the inductive kick that results during turn-off after

an overcurrent condition. This is accomplished by adding a resistor (R4) in series with the DCHG output. This

reduction of di/dt at turn-off minimizes the need for a capacitor across the battery stack. It is recommended that

this resistor value not exceed a few hundred Ohms, in which case the ability to turn off quickly enough into a

short may be compromised.

Due to the relatively low-charge currents (typically a few Amperes max), controlling the turn-on and turn-off

times of the charge FET is not beneficial. In fact, the turn-off time of the charge FET is slow due to the large value

of R1, the gate-to-source resistor.

9

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ꢀ ꢁꢁꢂ ꢃ ꢄ ꢅ ꢆꢇꢈ ꢀ ꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢉ ꢈ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢂ ꢈ ꢀꢁ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢊ

SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

APPLICATION INFORMATION

controlling discharge FET turn-on and turn-off times

Figure 3 shows a four-cell protector with slew-rate limiting the discharge FET. In this application, VR1 and R2

are optional, They protect Q1 from excessive open-circuit charger voltage. R3 and C6 are chosen based on

capacitive load that must be driven. R4 minimizes inductive kick at turn-off.

VR1 18 V

PACK (+)

R1 1 MΩ

R2

10 kΩ

Q1

IFR7416

CHARGE

D1

1 A, 50 V

R3 1 kΩ

Q3

2N7002

C6

0.22 µF

R4

100 Ω

Q2

IFR7416

DISCHARGE

C5

4.7 µF

25 V

C1

0.1 µF

VDD

1

2

3

4

5

6

7

8

16

DVDD

C2

0.1 µF

LI–ION

BATTERY

STACK

CLCNT

WU

AVDD 15

CDLY2 14

C3

OPTIONAL

+

13

AN1

AN2

AN3

AN4

DCHG

CHG 12

AN4 11

C4

0.022 µF

CDLY1 10

R

SENSE

0.025 Ω

BATLO CHGEN

9

PACK (–)

UDG–98018

Figure 3. Four-Cell Lithium-Ion Protector Application Diagram

10

www.ti.com

ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢈ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆꢉ ꢈ ꢀꢁꢁ ꢂ ꢃꢄ ꢅ ꢆꢂ ꢈ ꢀꢁ ꢁꢂ ꢃꢄ ꢅꢆ ꢊ

SLUS236B – JANUARY 1999 – REVISED SEPTEMBER 2002

TYPICAL CHARACTERISTICS

TYPICAL TIER-TWO OVERCURRENT DELAY TIME

TYPICAL TIER-ONE OVERCURRENT DELAY TIME

vs

DELAY CAPACITANCE

1000

1400

1200

100

10

1

1000

800

Off-time

600

400

Delay

200

0

0.1

0

10

20

30

40

0.001

0.01

0.1

C

– Delay Capacitance – pF

CDLY2

C

– Delay Capacitance – µF

Figure 4

CDLY1

Figure 5

WU LEAKAGE CURRENT

vs

INPUT VOLTAGE

70

60

50

Maximum

Typical

40

30

20

Minimum

10

0

14

16

18

20

22

24

26

V

WU

– Wake-Up Input Voltage – V

Figure 6

11

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2009

PACKAGING INFORMATION

Orderable Device

UCC3957M-1

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SSOP/

QSOP

DBQ

16

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3957M-1G4

UCC3957M-2

SSOP/

QSOP

DBQ

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3957M-2G4

UCC3957M-3

SSOP/

QSOP

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3957M-3G4

UCC3957M-4

SSOP/

QSOP

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

UCC3957M-4G4

UCC3957MTR-1

UCC3957MTR-1G4

UCC3957MTR-2

UCC3957MTR-2G4

UCC3957MTR-3

UCC3957MTR-3G4

UCC3957MTR-4

UCC3957MTR-4G4

SSOP/

QSOP

75 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

TBD

Call TI

SSOP/

QSOP

TBD

Call TI

SSOP/

QSOP

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

SSOP/

QSOP

2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jul-2009

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2009

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCC3957MTR-2

UCC3957MTR-3

UCC3957MTR-4

SSOP/

QSOP

DBQ

16

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

SSOP/

QSOP

SSOP/

QSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jul-2009

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCC3957MTR-2

UCC3957MTR-3

UCC3957MTR-4

SSOP/QSOP

DBQ

16

2500

346.0

29.0

Pack Materials-Page 2

IMPORTANT NOTICE

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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型号：	UCC3957MTR-1G4
厂家：	TEXAS INSTRUMENTS
描述：	4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16, GREEN, PLASTIC, QSOP-16 信息通信管理光电二极管过电流保护
文件：	总18页 (文件大小：552K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC3957MTR-1G4 [TI]

相关型号：

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