UCC3972_技术文档

UCC1972/3

UCC2972/3

UCC3972/3

BiCMOS Cold Cathode Fluorescent Lamp Driver Controller

FEATURES

DESCRIPTION

• 1mA Typical Supply Current

Design goals for a Cold Cathode Fluorescent Lamp (CCFL) converter used

in a notebook computer or portable application include small size, high effi-

ciency, and low cost. The UCC3972/3 CCFL controllers provide the neces-

sary circuit blocks to implement a highly efficient CCFL backlight power

supply in a small footprint 8 pin TSSOP package. The BiCMOS controllers

typically consume less than 1mA of operating current, improving overall

system efficiency when compared to bipolar controllers requiring 5mA to

10mA of operating current.

• Accurate Lamp Current Control

• Analog or Low Frequency Dimming

Capability

• Open Lamp Protection

• Programmable Startup Delay

• 4.5V to 25V Operation

External parts count is minimized and system cost is reduced by integrat-

ing such features as a feedback controlled PWM driver stage, open lamp

protection, startup delay and synchronization circuitry between the buck

and push-pull stages. The UCC3972/3 include an internal shunt regulator,

allowing the part to operate with input voltages from 4.5V up to 25V. The

part supports both analog and externally generated low frequency dimming

modes of operation.

• PWM Frequency Synchronized to

External Resonant Tank

• 8 Pin TSSOP and SOIC Packages

Available

• Internal Voltage Clamp Protects

Transformer from Over-voltage

(UCC3973)

The UCC3973 adds a programmable voltage clamp at the BUCK pin. This

feature can be used to protect the transformer from overvoltage during

startup or when an open lamp occurs. Transformer voltage is controlled by

reducing duty cycle when an over-voltage is detected.

TYPICAL APPLICATION CIRCUIT

C6 27pF

UCC3972 NO INTERNAL VOLTAGE CLAMP

INTERNAL VOLTAGE CLAMP LIMITS TRANSFORMER

VOLTAGE AT START-UP OR DURING FAULT

T1

UCC3973

SYSTEM VOLTAGE

(4.5V TO 25V)

R2 1k

C5 0.1µF

R1

1kΩ

UCC3972/3

VDD

D1

R10

R11

8

C1

6.8µF

Q2

VBAT

2

1

C2

1µF

LAMP

HV

C7

0.1µF

Q3

6

5

3

GND

L1

68µH

LAMP

LV

BUCK

MODE

COMP

ANALOG

DIMMING

C3

1µF

R6 75Ω

OUT

FB

7

4

R5 10k

R4 750

R3 68k

LOW FREQUENCY DIMMING

68k

D2

C4 33nF

D

R

LFD

0V-5V LOW FREQUENCY CONTROL SIGNAL

UDG-99154

SLUS252A - JANUARY 2000

UCC1972/3

UCC2972/3

UCC3972/3

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27V

VDD Maximum Forced Current . . . . . . . . . . . . . . . . . . . . 30mA

Maximum Forced Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 17V

BUCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5V to VBAT

MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 4.0V

MODE Maximum Forced Current . . . . . . . . . . . . . . . . . . 300µA

Operating Junction Temperature . . . . . . . . . . –55°C to +150°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

TSSOP-8 (TOP VIEW)

PW Package

Unless otherwise indicated, currents are positive into, negative

out of the specified terminal. Pulse is defined as less than 10%

duty cycle with a maximum duration of 500µs. Consult Pack-

aging Section of Databook for thermal limitations and consider-

ations of packages. All voltages are referenced to GND.

DIL-8 (TOP VIEW)

J, N Packages

OUT

VDD

1

2

3

4

8

7

6

5

GND

MODE

FB

BUCK

VBAT

COMP

ELECTRICAL CHARACTERISTICS: Unless otherwise specified these specifications hold for T_A=0°C to +70°C for the

UC3972/3, –40°C to +85°C for the UC2972/3, and –55°C to +125°C for the UC1972/3; T_A=T_J; VDD=VBAT=VBUCK=12V;

MODE=OPEN. For any tests with VBAT>17V, place a 1k resistor from VBAT to VDD.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Input supply

VDD Supply Current

VBAT Supply Current

VDD = 12V

VBAT = 25V

VBAT = 12V

VBAT = 25V

1

7

1.5

10.5

60

mA

µA

V

30

70

18

4

140

19

VDD Regulator Turn-on Voltage

VDD UVLO Threshold

UVLO Threshold Hysteresis

Output Section

I_SOURCE= 2mA to 10mA

Low to high

17

3.6

100

4.4

300

V

200

mV

Pull Down Resistance

Pull Up Resistance

Output Clamp Voltage

Output Low

I_SINK= 10mA to 100mA

I_SOURCE= 10mA to 100mA

VBAT = 25V, Shunt Regulator on

MODE = 0.5V, I_SINK= 1mA

CL = 1nF, Note 1

25

50

18

0.2

Ω

V

16

0.05

200

V

Rise Time

ns

Fall Time

CL = 1nF, Note 1

2

UCC1972/3

UCC2972/3

UCC3972/3

ELECTRICAL CHARACTERISTICS: Unless otherwise specified these specifications hold for T_A=0°C to +70°C for the

UC3972/3, –40°C to +85°C for the UC2972/3, and –55°C to +125°C for the UC1972/3; T_A=T_J; VDD=VBAT=VBUCK=12V;

MODE=OPEN. For any tests with VBAT>17V, place a 1k resistor from VBAT to VDD.

PARAMETER

Oscillator Section

TEST CONDITIONS

MIN

TYP

MAX UNITS

Minimum Frequency

BUCK = VBAT– 2, V_BAT= 12V to 25V,

T_A= –40°C to +85°C

52

44

66

80

kHz

BUCK = VBAT–2, V_BAT= 12V to 25V

T_A= –55°C to +125°C

Maximum Synchronizable Frequency

Maximum Duty Cycle

BUCK = VBAT, V_BAT= 12V to 25V

T_A= –40°C to +85°C

160

145

220

280

BUCK = VBAT, V_BAT= 12V to 25V

T_A= –55°C to +125°C

FB = 1V, T_A< 0°C

FB = 1V, T_A= 0°C to 70°C

FB = 2V

84

92

%

µA

A

95

Minimum Duty Cycle

0

BUCK Input Bias Current

BUCK = VBAT = 12V

BUCK = VBAT = 25V

40

80

–1

90

110

–0.3

Zero Detect Threshold

Measured at BUCK w/respect to VBAT,

VBAT=12V to 25V, T_A< 0°C

–2.4

–2.0

V

Measured at BUCK w/respect to VBAT,

VBAT=12V to 25V, T_A= 0°C to 70°C

–1

–0.3

V

Error Amplifier

Input Voltage

COMP = 2V, T_A= 0°C to +70°C

COMP = 2V

1.465

1.455

–2

1.5

2

1.535

1.545

10

V

Line Regulation

mV

nA

dB

V

Input Bias Current

–500 –100

Open Loop Gain

COMP = 0.5V to 3.0V

FB = 1V

60

80

3.7

0.15

–1.2

4

Output High Voltage

Output Low Voltage

Output Source Current

Output Sink Current

Output Source Current

Output Sink Current

Unity Gain Bandwidth

Mode Select

3.3

4.1

FB = 2V

0.35

–0.4

V

FB = 1V, COMP = 2V

FB = 2V, COMP = 2V

FB = 1V, COMP = 2V, MODE = 0.5V

FB = 2V, COMP = 2V, MODE = 0.5V

T_J= 25C, Note 1

mA

µA

MHz

2

–1

1

2

Output Enable Threshold

Open Lamp Detect Enable Threshold

Mode Output Current

MODE Clamp Voltage

Open Lamp

0.85

2.75

15

1

3

1.15

3.25

25

V

MODE = 0.5V

20

3.7

µA

V

MODE = OPEN

3.3

4

Open Lamp Detect Threshold

Measured at BUCK with respect to VBAT,

VBAT=12V to 25V

–8

–7

–9

–6

V

Over-voltage Clamp Threshold (UCC3973) Measured at BUCK with respect to VBAT,

–10.3

–7.7

VBAT=12V to 25V, I_FB= 100µA

Note 1. Guaranteed by design. Not 100% tested in production.

3

UCC1972/3

UCC2972/3

UCC3972/3

PIN DESCRIPTIONS

BUCK: Senses the voltage on the top side of the induc- GND: Ground reference for the IC.

tor feeding the resonant tank. The voltage at this point

MODE: The voltage on this pin is used to control start-up

and various modes of operation for the part (refer to the ta-

ble in the block diagram).

is used to synchronize the internally generated ramp

and to detect whether an open lamp condition exists.

An open lamp condition exists when this voltage is be-

low the specified threshold for seven clock cycles. If the

MODE pin is held below the open lamp detect enable

threshold, this protective feature is disabled.

When the voltage is below 1V, OUT is forced low, open

lamp detection is disabled and the error amplifier is

tri-stated.

When the voltage is between 1V and 3V, OUT is enabled

and the error amplifier output is connected to COMP.

Open lamp detection is still disabled and a constant 20µA

current is sourced from this pin. Placing an appropriate

value external capacitor between this pin and ground al-

lows the user to disable open lamp detection for a set pe-

riod of time at start-up to allow the lamp to strike.

On the UCC3973, this pin is also used to sense an

over-voltage across the transformer primary. If the volt-

age at this pin exceeds the clamp threshold, current will

be sourced fron the FB pin.

COMP: Output of the error amplifier.Compensation

components set the bandwidth of the entire system and

are normally connected between COMP and FB. The

error amplifier averages lamp current against a fixed in-

ternal reference. The resulting voltage on the COMP

pin is compared to an internally generated ramp, set-

ting the PWM duty cycle. During UVLO, this pin is ac-

tively pulled low.

When MODE reaches 3V, open lamp detection is enabled

and normal operation is activated.

OUT: Drives the buck regulator N-channel MOSFET. OUT

turn-on is synchronized to twice the tank resonant fre-

quency. OUT is actively pulled low when in UVLO, an

open lamp condition has been detected or MODE is less

than 1V.

FB: This pin is the inverting input to the error amplifier.

On the UCC3973, current is sourced form this pin if the

clamp threshold is exceeded at the BUCK pin (see be-

low). The sourced current will reduce OUT duty cycle to

control transformer primary voltage. The source current

is disabled on the UCC3972.

VBAT: Positive input supply to power stage. This voltage

is required by internal control circuitry to provide

open-lamp detection and synchronization. Operating range

is from 4.5V to 25V.

VDD: This pin connects to the battery voltage from which

the CCFL inverter will operate. If the potential on VBAT

can exceed 18V in the application, a series resistor must

be placed between VBAT and this pin (see applications

section). The voltage at the VDD pin will then be regulated

to 18V. This pin should be bypassed with a minimum ca-

pacitance of 0.1µF.

800

600

400

200

0

8.7

9.2

9.7

VBAT - VBUCK

Clamp current vs. tank voltage for UCC3973.

4

UCC1972/3

UCC2972/3

UCC3972/3

BLOCK DIAGRAM

VBAT

2

OVER-VOLTAGE

CLAMP COMPARATOR

9.0V

+

–

TO S3

UVLO

4.0V/3.8V

VDD

8

UVLO=1

VREF

OPEN LAMP DETECT

COMPARATOR

18V

3V REF

7.0V

S2

3 BIT

+

UP-DOWN

COUNTER

–

1

BUCK

66kHz-200kHz

OSCILLATOR

ZERO DETECT

COMPARATOR

FROM MODE SELECT

1.0V

+

–

SYNC

VDD

UVLO

R

S

RAMP OUT

Q

R

UVLO

7

OUT

0.2V

+

OUTPUT OFF

PWM

S Q

(FROM MODE SELECT)

–

6

GND

FROM

CLAMP

COMP

VDD

20µA

I

CLAMP

ERROR

AMPLIFIER

S1

*MODE

SELECT

1.5V

+

–

MODE

5

S3

4

FB

(ALWAYS OPEN ON UCC3972)

3

UDG-98154

COMP

*MODE

Output

Open Lamp

Detection

S2

Error Amplifier Output

S1

<1V

1V< MODE< 3V

>3V

OFF

ON

DISABLED

ENABLED

OPEN

CLOSED

DISCONNECTED FROM COMP

CONNECTED TO COMP

OPEN

CLOSED

APPLICATION INFORMATION

Introduction

backlight converter must produce the high voltage

needed to strike and operate the lamp. Although CCFLs

can be operated with a DC voltage, a symmetrical AC

operating voltage is recommended to maintain the rated

life of the lamp. Sinusiodal voltage and current lamp

waveforms are also recommended to achieve optimal

electrical to light conversion and to reduce high voltage

electromagnetic interference (EMI). A topology that pro-

vides these requirements while maintaining efficient op-

eration is presented below.

Cold Cathode Fluorescent Lamps (CCFL) are frequently

used as the backlight source for Liquid Crystal Displays

(LCDs). These displays are found in numerous applica-

tions such as notebook computers, portable instrumenta-

tion, automotive displays, and retail terminals.

Fluorescent lamps provide superior light output effi-

ciency, making their use ideal for power sensitive porta-

ble applications where the backlight circuit can consume

a significant portion of the battery’s capacity. The

5

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

Circuit Operation

The resonant tank consisting of C_RESand T1 produces

sinusoidal currents (I_RES) and voltages and is fed by a

controlled DC current (I_BUCK) from the buck stage. Note

that the BUCK node voltage is ½ the primary tank volt-

age, as VBAT is located at the center tap of the trans-

former. The high turns ratio transformer (T1) amplifies

the sinusoidal tank voltage to produce a sinusoidal sec-

ondary voltage that is divided between the lamp and bal-

last capacitor.

A current fed push-pull topology is used to power the

CCFL backlight shown in Fig. 1. This topology accommo-

dates a wide input voltage and dimming range while re-

taining sinusoidal operation of the lamp. The converter

consists of a resonant push-pull stage, a high voltage

output stage, and a buck pre-stage used to regulate cur-

rent in the converter.

Referring to Fig. 1, the push-pull stage consists of C_RES

,

Transistors Q1 and Q2 are driven out of phase at 50 per-

cent duty cycle with an auxiliary winding on T1. The

winding provides a floating AC voltage source at the res-

onant frequency that is used to drive the transistor bases

alternately on and off. One leg of the auxiliary winding is

tied to the input voltage through base resistor R_B, which

is sized to provide sufficient base current to the transis-

tors. The transistors channel the buck inductor current

into opposing ends of the tank at the resonant frequency,

supplying energy for the lamp and system losses.

Q1, Q2, R_B, and T1’s primary and auxiliary windings.

The output stage consists of C_BALLAST, the lamp, the

current sense resistor R_S, and T1’s secondary. The reso-

nant frequency of the tank is set by the primary induc-

tance of T1, along with the resonant capacitor (C_RES),

and the reflected secondary impedance. The secondary

impedance includes the lamp, the ballast capacitor

(C_BALLAST), the distributed winding capacitance of T1,

and the stray capacitance which forms between the

lamp, lamp wires, and the backlight reflector. Since the

lamp impedance is nonlinear with operating current, the

tank resonant frequency will vary slightly with load (typi-

cally 1.5:1).

The buck power stage consists of inductor L_BUCK

,

MOSFET switch S_BUCK, and flyback diode D_BUCK. In or-

der to prevent interactions between multiple switching

RESONANT PUSH-PULL STAGE

OUTPUT STAGE

C

T1 PRIMARY

VBAT

BALLAST

T1 SECONDARY

CCFL

I

VBAT

R

LAMP

C

RES

VBAT

FB

I

B

RES

T1

AUXILIARY

R

S

Q2

Q1

V

BUCK

VBAT

L

BUCK

VBAT

D

BUCK

I

BUCK

Q1

ON

Q2

ON

Q1

ON

Q2

ON

S

VBUCK

GND

BUCK

OUT

BUCK STAGE

UDG-98157

Figure 1. Push-pull, output, and buck stages.

6

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

frequencies, the UCC3972/3 synchronizes the buck fre- lamp, providing a high impedance sinusoidal current

quency to the frequency of the push-pull stage. The tra- source with which to drive the CCFL. This approach im-

ditional buck topology is inverted to take advantage of proves the optical efficiency of the system, as capacitive

the lower R_DS(on)characteristics of an N-Channel leakage effects are minimized due to reduced harmonic

MOSFET switch (S_BUCK). With a sinusoidal voltage content in the voltage waveforms. Unfortunately, from an

across the tank, the resulting output of the buck stage electrical efficiency standpoint, an increased tank voltage

(V_BUCK) becomes a full-wave rectified voltage referenced produces increased flux losses in the transformer and in-

to VBAT as shown in Fig. 1.

creased circulating currents in the tank. In practice, the

voltage drop across the ballast capacitor is selected to

be approximately twice the lamp voltage (750V in our

case) at rated lamp current. Assuming a 50kHz resonant

frequency and 5mA operating current, a ballast capaci-

tance of 22pF is selected. Since the lamp and ballast ca-

pacitor impedance are 90 degrees out of phase, the

vector sum of lamp and capacitor voltages determine the

secondary voltage on the transformer.

Lamp current is sensed directly with R_Sand a parallel di-

ode on each half cycle. The resulting voltage across the

sense resistor R_Sis kept at a 1.5V average by the error

amplifier, which in turn controls the duty cycle of S_BUCK

.

The buck converter typically operates in continuous cur-

rent mode but can operate with discontinuous current as

the CCFL is dimmed.

Design Procedure

2

(2)

V_SEC

=

V

(

+ V

(

LAMP

)

CB

A notebook computer backlight circuit will be presented

here to illustrate a design based on the UCC3972/3 con-

troller. The converter will be designed to drive a single

cold cathode fluorescent lamp (CCFL) with the following

specifications:

The resulting secondary voltage at rated lamp current is

820V. Since the capacitor dominates the secondary im-

pedance, the lamp current maintains a sinusiodal shape

despite the non-linear behavior of the lamp. As the CCFL

is dimmed, lamp voltage begins to dominate the second-

ary impedance and current becomes less sinusiodal.

Transformer secondary voltage is reduced, however, so

high frequency capacitive losses are less pronounced.

The value of ballast capacitor has no effect on current

regulation since the average lamp current is sensed di-

rectly by the controller.

Table 1. Lamp Specifications

Lamp Length

Lamp Diameter

Striking Voltage (20°C)

Operating Voltage (5mA)

Full Rated Current

Full Rated Power

250mm (10”)

6mm

1000V (PEAK)

375V (RMS)

5mA

1.9W

Once the ballast capacitor is selected, the resonant fre-

quency of the push-pull stage can be determined from

the transformer’s inductance (L), turns ratio (N), and the

selection of resonating capacitor (C_RES).

Input Voltage Range:

The notebook computer will be powered by a 4 cell Lith-

ium-Ion battery pack with an operational voltage range of

10V to 16.8V. When the pack is being charged, the back

light converter is powered from an AC adapter whose DC

output voltage can be as high as 22V.

F_RESONANT

=

(3)

1

2π L_PRIMARY

C

(

+ N ²•C_BALLAST

(

))

RES

Resonant Tank and Output Circuit

The selection of components to be used in the resonant

tank of the converter is critical in trading off the electrical

and optical efficiencies of the system. The value of the

output circuit’s ballast capacitor plays a key role in this

trade-off. The voltage across the ballast capacitor is a

function of the resonant frequency and secondary lamp

current:

Output distortion is minimized by keeping the independ-

ent resonant frequencies of the primary and secondary

circuits equal. This is achieved by making the resonant

capacitor equal to the ballast capacitance times the turns

ratio squared:

2

C_RES=N ²•C_BALLAST= 67 • 22pF = 0.1µF

(4)

( )

I_LAMP

(1)

V_CB

=

The resulting resonant frequency is about 50kHz, this

frequency will vary depending upon the lamp load and

amount of stray capacitance in the system. Since the

UCC3972/3 has an internal oscillator, it is important that

2• π •C_BALLAST•F_RESONANT

A voltage drop across C_BALLASTmany times the lamp

voltage will make the secondary current insensitive to

distortions caused by the non-linear behavior of the

7

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

the operating frequencies of a particular design are ternate half cycles (i.e. only ½ of the primary winding sees

within the synchronizable frequencies of the controller.

the buck current depending upon which transistor is on).

Maximum resonant current is equal to:

Component Selection for the Resonant Tank and

Output Circuit

V_PRIMARY

L_PRIMARY

C_RES

820

44

0.1

(6)

I_RES

=

= 600mA

Since high efficiency is a primary goal of the backlight

converter design, the selection of each component

must be carefully evaluated. Losses in the ballast ca-

67 •

pacitor are usually insignificant, however, its value de- Buck inductor current is calculated in the next section.

termines the tank voltage which influences the losses in Secondary current is simply the lamp current, the second-

the resonant capacitor and transformer. Since the reso-

nant capacitor has high circulating currents, a capacitor

with low dissipation factor should be selected. Power

loss in the resonant tank capacitor will be:

ary winding has 176 of resistance.

Core losses are a function of core material, cross sectional

area of the core, operating frequency, and transformer

voltage. For ferrite material, the hysteresis core losses in-

crease with voltage by a cubed factor; for a given core

cross sectional area, doubling the tank voltage will cause

the losses to increase by a factor of 8. This makes the se-

lection of the ballast capacitor a critical decision for effi-

ciency.

(5)

C_{RES _LOSS}watts =

(

)

2

V

(

• 2π •F_RESONANT•C_RES•DissipationFactor

)

TANK

Polypropylene foil film capacitors give the lowest loss;

metalized polypropylene or even NPO ceramic may

give acceptable performance in a lower cost surface

mount (SMT) package. Table 2 gives possible choices

for the resonant and high voltage ballast capacitors.

Other elements influencing the resonant tank and output

circuit efficiency include the push-pull transistors, the base

drive and sense resistors, as well as the lamp. High gain

low V_CESATbipolar transistor such as Zetek’s FZT849 al-

low high efficiency operation of the push-pull stage. These

SOT223 package parts have a typical current transfer ratio

(h_FE) of 200 and a forward drop (V_CESAT) of just 35mV at

500mA. Rohm’s 2SC5001 transistors provide similar per-

formance. For low power, size sensitive applications, a

SOT23 transistor is available from Zetek (FFMT619) with

approximately twice the forward drop at 500mA. The base

drive resistor R_Bis sized to provide full V_CEsaturation for

all operating conditions assuming a worst case h_FE. For

efficiency reasons, the base resistor should be selected to

have the highest possible value. A 1k resistor was se-

lected in this application. Losses scale with buck voltage

as:

The transformer is physically the largest component in

the converter, making the tradeoff of transformer size

and efficiency a critical choice. The transformer’s effi-

ciency will be determined by a combination of wire and

core losses. A Coiltronics transformer (CTX110600)

was chosen for this application because of its small

size, low profile, and overall losses of about 5% at 1W.

Low profile CCFL transformers are also available from

Toko (847)-297-0070 in Mt. Prospect, IL or Sumida

(408)-982-9660 in Santa Clara, CA.

Wire losses are determined by the RMS current and

the ESR of the windings. The primary winding resis-

tance for the Coiltronics transformer is 0.16 . The

RMS current of the primary winding includes the sinu-

soidal resonant current and the DC buck current on al-

V ²

(7)

BUCK

R_{B(LOSS )}

=

R_B

Table 2. Capacitor selection

Capacitance Type

Manufacturer

Ballast Capacitor

Series

Dissipation Factor

(1kHz)

Cera-Mite (414) 377-3500

NOVA-CAP (805) 295-5920

Murata Electronics

High Voltage Disk Capacitor (3kV)

SMT 1808 (3kV)

564C

COG

GHM

Resonant Capacitor

Wima (914)347-2474

Polypropylene foil film FKP02

Metalized Polypropylene

SMT Metalized polyphenylene-sulfide

SMT Ceramic

FKP02

MKP2

MKI

CHE

COG

0.0003

0.0005

0.0015

0.0006

0.001

Paccom (800)426-6254

NOVA-CAP

8

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

The current sense resistor R_Sprovides direct control of

lamp current. Since the current sense resistor voltage is

controlled to a 1.5V reference, its power loss is inversely

proportional to its value at a given lamp current.

(9)

V_SEC• 2

N • π

V_{BUCK _AVE}=V_BAT

820 • 2

−

=V_BAT

−

=V_BAT− 5.5•Volts

67 • π

Synchronizing the Stages

The approximate on time using the maximum 22V input

voltage (V_{BUCK_AVE}= 16.4), a 100kHz switching fre-

quency (two times the resonant frequency), and ignoring

the diode drop can be calculated from the following:

An internal comparator at the BUCK node is used to syn-

chronize the PWM buck frequency to twice the resonant

tank frequency. Synchronization is accomplished with

sync pulse that is generated each time the BUCK node

voltage is within 1.0V of VBAT; the UCC3972/3 uses this

sync pulse to reset the PWM oscillator’s saw-tooth ramp.

The sync circuit will operate with typical PWM frequen-

cies between 66kHz and 200kHz, corresponding to a

33kHz to 100kHz tank frequency.

VBAT −V_{BUCK _AVE}

t_ON

(10)

=

T −t_ON

V_{BUCK _AVE}

The resulting on time is 2.5µs. A 150 H inductor will re-

sult in a peak to peak ripple current of 280mA. Average

inductor current (with maximum lamp current) can be cal-

culated by taking the lamp power divided by the tank effi-

ciency and the RMS buck voltage.

Buck Stage Design

The PWM output controls current in the buck inductor.

The UCC3972/3’s buck power stage differs from a tradi-

tional buck topology in a few respects:

I_BUCK

=

(11)

V

•I_LAMP

Efficiency









375 • 0.005 • 2 • 67

0.8 • 820

2•N

LAMP

• The topology is inverted using a ground referenced

N-Channel MOSFET rather than a VDD referenced

P-Channel.







 •

=

V









SEC

= 380mA

• The output voltage is a full wave rectified sinewave at

The resulting inductor ripple is less than 50%. A list of

possible inductors are given below along with ESR and

current rating (losses in the inductor are calculated with

RMS current).

the switching frequency, rather than DC.

Referring back to Fig. 1, when OUT turns S_BUCKon, the

BUCK node voltage V_BUCKis placed across the inductor.

This voltage is typically positive and current ramps up in

the inductor (it is possible for the BUCK node voltage to

go negative if VBAT is low and the lamp current is near

The choice of a MOSFET for the buck switch should take

into consideration conduction and switching losses. The

R_DS(on)and gate charge are typically at odds, however,

where minimizing one will typically result in the other in-

creasing. An International Rectifier IRFL014 was se-

lected (SOT-223 package) in this application with a gate

charge of 11nC and R_DS(on)of 0.2 . A Schottky diode

should be used for the buck diode in order to minimize

forward drop.

maximum).

When

S_BUCK

is

turned

off,

VBAT-V_BUCK+V_DBUCKis placed across the inductor with

opposite polarity. As with any buck converter, the

volt-seconds across the inductor must be reversed on

each switching cycle to maintain constant current. The

duty cycle (D) relationship is complicated somewhat by

the fact the output voltage is changing within a switching

cycle. The equations below determine the relationship

between on and off times in continuous conduction mode

where T is the switching period, D = t_ON/T, and t_OFF= T-

Table 3. Inductor Suppliers

t_ON

.

t_ON

T

Vendor

L

Part Number ESR Current

Rating

(8)

V_BUCK•dt = VBAT −V

+V_D•dt

(

∫

t_ON

)

BUCK

∫

Coilcraft

(847) 639-6400

150µH DO3316-154 0.38

1A

0

Coiltronics (407)

241-7876

Sumida

(847) 956-0666

150µH CTX150-4 0.175 0.72A

Selecting the buck inductor:

Maximum ripple current in the inductor occurs when fre-

quency and duty cycle are at a minimum, which corre-

sponds to VBAT and lamp current being a maximum.

The average value of V_BUCKat rated lamp current is

equal to:

150µH CDR125-151 0.4

0.85A

0.4A

Toko (847) 297-0070 150µH 646CY-151 0.73

9

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

Dimming Techniques

Analog Dimming:

A control circuit that implements analog dimming with a

potentiometer (R_ADJ) is shown in Fig. 2. When the sec-

ondary has a positive polarity current, D1 is reversed bi-

ased and lamp current is sensed directly through R_Land

R_ADJ. When the current reverses direction, D1 conducts

and the voltage on the sense node V_Xis clamped to the

forward drop of the diode. The resulting waveform at V_X

is a half wave rectified sinusoid whose voltage is propor-

tional to lamp current.

V_D

2

_^π



(12)

1.5 +



Figure 3. Analog dimming control from micro-

processor.





I_LAMP

=

2 R + R_ADJ

(

)

L

Low Frequency Dimming (LFD):

Analog dimming techniques described previously can

provide excellent dimming over a 10:1 range, depending

upon the physical layout and the amount of stray capaci-

tance in the backlight's secondary circuitry. Beyond this

level the lamp may begin to exhibit the "thermometer ef-

fect" causing uneven illumination across the tube.

V_X

C_FB

0V

V_X

C

BALLAST

R_FB

R_ADJ

FB

1.5V

COMP

D1

Low frequency dimming (LFD) is accomplished by oper-

ating the lamp at rated current and gating the lamp on

and off at a low frequency. Since the lamp is operated at

full intensity when on, the system layout has little effect

on dimming performance. The average lamp intensity is

a function of the duty cycle and period of the gating sig-

nal. The duty cycle can be controlled to a low minimum

value, allowing a very wide dimming range. Low fre-

quency dimming can be implemented by summing a

PWM signal into the feedback node to turn the lamp off

as shown in Fig. 4. A 68k resistor is used for R_FBand

R_LFD, C_FBis reduced to 6.8nF to speed up the lamp

re-strike. The repetition rate of the signal should be

greater than 120Hz to avoid visible flicker.

R_L

Figure 2. Analog dimmer with potentiometer.

This voltage is averaged by the feedback components

(R_FB, C_FB) and held to 1.5V by the error amplifier when

the control loop is active. The resulting voltage at the

output of the error amplifier (COMP) sets the duty cycle

of PWM stage. Average lamp current is controlled by ad-

justing R_ADJto the appropriate value. Resistor R_Lsets

the high current level of the lamp.

Analog Dimming by PWM or D/A Control Signal:

Analog dimming control of the lamp can be achieved by

providing a digital pulse stream (or DC control voltage)

from the system microprocessor as shown in Fig. 3. For

this technique, the lamp current sense resistor (R1) is

fixed and the V_Xnode voltage is averaged against the

digital pulse stream of the microprocessor. The averag-

ing circuit consists of R2, R3, and C_FB. A higher average

value from the pulse stream will result in less average

lamp current. The frequency of the digital pulse stream

should be high enough to maintain a constant DC value

across the feedback capacitor. If a D/A converter is avail-

able in the system, a DC output can be used in place of

Figure 4. Low frequency dimming by forcing lamp

current off through the FB pin.

the pulse stream.

10

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

Referring to Fig. 5, at time t0 the control signal is trolling the duty cycle with a timer routine within the LCD’s

brought low and the voltage in the resonant tank begins software program.

to build. At time t1 there is sufficient voltage for the

LFD waveforms at 200Hz and 50% duty cycle are shown

lamp to strike and the feedback loop controls the lamp

in Fig. 6a. Fig. 6b show a time expanded photo of the

at rated current using a fixed current sense resistor.

same waveforms. Channel 1 is lamp voltage at 500V /div,

When the LFD signal is brought low at time T2, the

Channel 2 is lamp current at 20mA / div, and Channel 3 is

COMP output is low and the OUT pin stops switching.

the LFD control voltage. Since the photos are from a digi-

The resonant tank voltage decays until the lamp extin-

tal oscilloscope, alias exists in the waveforms.

guishes. If the on time were extended to t3 the average

Lamp Current Control Loop

lamp intensity would be increased accordingly, the next

low frequency cycle begins at time t4.

The current control loop for the CCFL circuit is discussed

in detail in Unitrode Application Note U-148 and is briefly

repeated here for completeness. A block diagram for the

current control loop is shown in Fig. 7.

The PWM modulator small signal gain is inversely propor-

tional to the internal saw tooth ramp and proportional to

the input voltage (the inductor’s current slope increases as

VBAT increases). The resonant tank and buck inductor

form a RLC filter at the center point of the push pull trans-

former. The effective L of the filter is dominated by buck in-

ductor and the effective C is approximately 8 times the

resonant capacitor (C_RES) value. This occurs because the

reflected ballast capacitance is equal to C_RESand the

equivalent capacitance at the push-pull center point is four

times the capacitance across the tank. The equivalent re-

sistance at the push-pull center point is equal to ¼ the

tank voltage squared divided by the lamp power. The cor-

ner frequency and Q of the filter are:

LAMP

VOLTAGE

LAMP

CURRENT

LFD

5V

CONTROL

SIGNAL

ON

OFF

0V

t0 t1

t2

t3

t4

Figure 5. Low frequency dimming timing waveforms.

The time relationship between the resonant and gating

frequency has been exaggerated so that the sinusoidal

waveforms can be depicted. In order to avoid visible

lamp flicker, the low frequency gating rate (t0-t4) should

be greater than 100Hz. To prevent “beat” frequency in-

terference, it may be advantageous to synchronize the

gating frequency to a multiple of the monitor scan rate

of the LCD display. This can be accomplished by con-

1

(13)

F_CORNER

=

²π ^L_BUCK• 8•C_RES

2πF_FILTERL_BUCK

(14)

Q =

R_FILTER

Figure 6b. Time expanded showing lamp strike and

feedback delay.

Figure 6a. LFD at 50% duty cycle.

11

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

C

FB

ERROR

AMPLIFIER

PWM

MODULATOR

VBAT

TRANSFORMER

SECONDARY

IMPEDANCE

2 POLE

RLC

FILTER

2N

S

2

R

+X

C

N

LAMP

V

P

SAW

1.5V

R

FB

0.5R

S

Figure 7. Current control loop block diagram.

The resulting gain of the filter is unity below the 15kHz

corner frequency, peaking up at the corner frequency

with Q, and rolling off with a 2-pole response above the

corner frequency. As shown in Fig. 7, the transformer

turns ratio provides a voltage gain and the output circuit

(whose impedance includes the lamp and ballast capaci-

tor) converts the voltage into a current. The current

sense resistor produces a voltage on each half cycle,

leaving the error amplifier as the final gain block.

Striking the Lamp

Before the lamp is struck, the lamp presents an imped-

ance much larger than the ballast capacitor and the full

output voltage of the transformer secondary is across the

lamp. Since the buck converter must reverse the

volt-seconds on the buck inductor, the average tank volt-

age at the primary can be no greater than the DC input

voltage. This constraint along with the turns ratio of the

push-pull transformer sets the peak voltage available to

strike the lamp:

Loop gain is greatest at minimum lamp current and maxi-

mum input voltage. With a 22V input, a 2V saw-tooth,

and 1:67 turns transformer, the low frequency voltage

gain of the PWM, RLC filter, and Transformer is 1500.

With a 375V lamp and 1mA of lamp current (using a

22pF ballast capacitor and 50kHz switching frequency)

the secondary impedance is 400k . R_SENSEat 1mA is

4k (equation 12), resulting in a low frequency power

loop gain of 7.5. The error amplifier is configured as an

integrator, giving a single pole roll-off and a high gain at

DC. A 68k resistor and 33nF capacitor give a 70Hz

crossover frequency for the feedback network, yielding a

maximum crossover frequency of 500Hz for the total loop

avoiding stability problems with the Q of the resonant

tank. For 5mA of lamp current with a 22V input the total

loop crossover is 200Hz, for low frequency dimming ap-

plications C_FBcan be reduced to 6.8nF with no instability

(1kHz crossover).

V_STRIKE=N_S:P• π •V_INPUT

(15)

The Coiltronics transformer has a 67:1 turns ratio, giving

2100 peak volts available to strike the lamp with the mini-

mum 10V input. In our example this is more than suffi-

cient for the 1000V required to strike the lamp. With the

22V maximum charger input, the available striking volt-

age could theoretically reach 5000V! The possibility of

breaking down the transformer’s secondary insulation

becomes a real concern at this voltage.

Voltage Clamp Circuit (UCC3972)

An external voltage clamp circuit consisting of D4, Q4,

R7, R8, and R9 can be added to the typical application

circuit as shown in Fig. 8. This circuit limits the maximum

transformer voltage during startup, allowing an extended

time period for striking the lamp while protecting the

transformer from over voltage. For fixed input voltage de-

signs, this circuit is optional since the transformer turns

can be optimized at one voltage.

12

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

VBAT

2

T1

C5

LAMP

R9

D4

D

CLAMP

Q2

R7

Q1

D2

R4

R3

R8

V

Q4

2N3906

BUCK

UCC3972 EXTERNAL

VOLTAGE CLAMP

L1

4

UDG-99161

FB

Figure 8. Optional voltage clamp circuit. For UCC3972. (Not required for UCC3973)

The clamp circuit works as follows: An optional zener diode D_CLAMPcan be added to either

If the voltage at the base of Q4 is equal to the zener (D4) UCC3972 or UCC3973 designs as shown in Fig. 8. The

voltage plus the V_BEof Q4, the clamp circuit will activate zener provides a high speed clamp when power is ini-

limiting the voltage in the resonant tank. When the clamp tially applied to the circuit and before the voltage clamp

activates, Q4 is turned on and additional current (set by can regulate the feedback loop. D_CLAMPcan be a small

R9) is allowed into the feedback capacitor. The peak 250mW zener since it will only conduct for a few reso-

clamp voltage is given by:

V_CLAMP=V_IN–V_BUCK

R7 + R8

nant cycles before the voltage clamp takes effect.

D_CLAMP’s value should be a few volts greater than the

voltage clamp.

=

(16a)

• V

(

+V_BEQ4PEAK

)

ZENER

Setting the Time Period for Blanking Open Lamp De-

tection

R7

Internal Voltage Clamp Circuit for UCC3973

A capacitor on the MODE pin of the UCC3972/3 is used

The over-voltage function is provided internally on the to blank the open lamp protection circuitry during the ini-

UCC3973. As shown in the block diagram of the tial lamp startup. When the IC is initially powered-up, a

UCC3972/3, an internal comparitor monitors the instanta-

neous voltage between VBAT and BUCK. If this voltage

exceeds the over-voltage clamp level (9V nominal), a

current will be sourced from the FB pin to reduce duty cy-

cle. The source current level increases with over-voltage,

but is typically 100µA at the threshold voltage. As with

the Open Lamp Trip Level, the Voltage Clamp Threshold

is programmed with external resistors R10 and R11.

20 A current out of the MODE pin charges the capacitor

C_MODEfrom ground potential. Since the PWM output is

disabled when the MODE pin is between 0V-1V, open

lamp blanking occurs as C_MODEis charged from 1V-3V,

giving a soft start period of:

C_MODE

(17)

T_SS

=

•SEC

10µF

R10 + R11













(16b)

The time required for lamp strike is application depend-

ent, and a 10 F capacitor allows 1 second in which to

strike the lamp. Fig. 9 shows the voltage at the V_BUCK

node with a 20V input and a 13.5V peak level for the

internal voltage clamp (UCC3972 requires and external

clamp) under an open lamp fault condition. After the 1

second period, the open lamp detection circuit trips and

the UCC3972/3 shuts down until power is cycled on the

chip.

V_CLAMP

=

• 9V

PEAK

R10

A 2k resistor for R10 and a 1k resistor for R11 will result

in a peak (VBAT–V_BUCK) level of 13.5V. With a 1:67

turns ration transformer, the secondary voltage will be

clamped to 1280 V_RMS

.

The FB pin source current is disabled in the UCC3972.

13

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

suring the converter would shut down after the one sec-

ond blank time if a true open lamp existed. If the open

lamp voltage is increased, the peak clamp circuit voltage

(equation 16) would need to be increased accordingly. A

peak VBAT-Vbuck voltage of 10.5V has been set for

open lamp detection in this example. (R10 = 2k,

R11 = 1k).

Voltage Regulator

The UCC3972/3 controller contains an internal 18V

shunt regulator that provides a 5% accurate voltage

clamp for the MOSFET gate drive while allowing the con-

troller to operate in applications with input voltages up to

25V. Since only the VBAT and BUCK pins are rated for

25V, the shunt regulator limits the voltage on the VDD

and OUT pins to 18V. The MODE, CS, and COMP pin

voltages are typically less than 5V. If the UCC3972/3 is

to be used in an application with input voltages greater

than 18V, a resistor from VBAT to VDD is required to

limit the current into the VDD pin. The resistor should be

sized to allow sufficient current to operate the controller

and drive the external MOSFET gate, while minimizing

the voltage drop across the resistor. A bypass capacitor

should be connected at the VDD pin to provide a con-

stant operating voltage.

Figure 9. V_BUCKand MODE pin voltages during an

open lamp fault start-up.

Normal Startup

In practice, the lamp will typically strike in much less than

1 second (usually within the first few cycles) and the volt-

age at the transformer voltage will collapse to below the

open lamp trip level. Difficulty in striking the lamp usually

results from one or a combination of the following:

Selecting the Shunt Resistor:

The first step in selecting the shunt resistor is to deter-

mine the current requirements for the application. With a

100kHz switching frequency and a maximum gate

charge of 11nC for the IRFL014 , the gate drive circuit

requires 1.1mA of average current. The UCC3972/3 re-

quires an additional maximum quiescent current of

1.5mA. The shunt resistor must therefore supply 2.6mA

of current over the operating voltage of the part.

• Insufficient transformer turns ratio or input voltage.

• Increase in required striking voltage at cold

temperature.

• The lamp has set for a long period of time.

• Transformer secondary voltage is reduced due to

voltage division between parasitic secondary

capacitance and the ballast capacitor.

The application’s maximum input voltage is 22V. With a

regulator clamp voltage of 18V, the maximum value for

the shunt resistor becomes 1.5k [(22-18)V/2.6mA]. This

resistor will minimize losses at maximum input voltage,

but could produce a 4V drop (from VBAT to VDD) even

when the regulator is not clamped. This drop reduces the

available gate drive voltage, leaving only 6V with the

minimum input voltage of 10V. Since the efficiency of the

shunt regulator is not of primary importance when the

charger is running, a smaller value of shunt resistor is se-

lected to improve the available gate drive voltage. A

470 shunt resistor will produce a maximum 1.2V drop

from VBAT to VDD when the shunt regulator is not

clamped. When the regulator is clamped at 18V and the

charger voltage is at its maximum of 22V, the power

across the shunt resistor will be 35mW [(4V x 4V)/470].

Setting the Open Lamp Trip Level

The buck voltage is monitored by an internal 7V com-

parator to detect an open lamp. The actual trip voltage

across the resonant tank is set with an external resistor

divider R10 and R11.

V_OPENLAMP=V_IN–V_BUCK

(18)

R10 + R11













=

• 7V PEAK

R10

R10 and R11 should be in the 1kΩ-5k range, to guar-

antee sharp zero crossing edges at the buck pin of the

IC. In most applications the peak clamp voltage would be

set to a higher level than the open lamp trip voltage, en-

14

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

Low Current Shutdown Circuit:

VIN: 5V-25V

Since the shunt regulator circuitry needs to remain ac-

tive, even when the MODE pin is less than 1V and the

output is not switching, a low current shutdown is not

provided in the UCC3972/3. The following is a simple

on/off control requiring only two transistors with internal

bias resistors to disconnect V_INproviding a low current

shutdown. VBAT and BUCK pins will consume a small

current in this mode because they have 430k of internal

resistance.

SOT23

or

SOT323

47K

22K

PNP

OFF / ON

CONTROL

0V-5V

22K

47K

470

NPN

UCC3972

VDD

8

Cold Cathode Lamp Characteristics

1µF

Before beginning a CCFL converter design, it is impor-

tant to become familiar with the characteristics of the

lamp. The lamp presents a non-linear load to the con-

verter resulting in unique voltage vs. current (VI) charac-

teristics. The length, diameter, and physical construction

of the lamp determine its performance, and thus impact

the design of the converter. Fig. 11 shows the VI charac-

teristics collected from various lengths of 6mm diameter

lamps, where Fig. 12 shows the characteristics of several

3mm-diameter lamps.

6

5

GND

MODE

10uF

Part Numbers (Motorola)

NPN sot-23:

NPN sot-323: MUN5234T1

It is interesting to note how the operating and striking

voltages (V_STRIKE) of the lamps are related to length as

well as lamp diameter. Since equal length CCFLs of dif-

ferent diameters have about the same lumens per watt

efficiency, the smaller diameter lamps actually produce

more light when driven at a given current since they op-

MMUN2234LT1

PNP sot-23:

MMUN2134LT1

PNP sot-323: MUN5134T1

Figure 10. Optional low current shutdown circuit.

erate at a higher voltage. The lamps have regions of voltage to keep the lamp operating over the whole range

positive and negative resistance with the voltage peaking of operating current, this requirement becomes more dif-

at 4mA for the 6mm diameter lamps and at 1mA for the ficult with longer length and smaller diameter lamps.

3mm diameter lamps.

Since the lamp characteristics will vary with the manufac-

turing technique, it is a good idea to collect data from

several lamp manufacturers and to include design mar-

gin for process variations.

In order to successfully dim the lamp, the converter’s res-

onant tank and step up transformer must provide enough

Figure 11. 6mm lamp characteristics (20°C).

Figure 12. 3mm lamp characteristics (20°C).

15

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

Since a fluorescent lamp is a pressurized gas filled tube less pronounced as the lamp is over-driven as shown in

(usually Argon and Mercury vapor), it shouldn’t be sur- Fig. 15. The expected life of the lamp will also degrade,

prising that temperature plays a major role in the lamp as illustrated in Fig. 16, when the lamp is operated above

characteristics. Fig. 13 depicts the variations in striking rated current.

and operating voltage for a 150 x 3mm lamp over tem-

perature, illustrating the importance of taking tempera-

ture effects into account when designing the converter.

Cold Cathode Fluorescent Lamp Efficiency

Trade-Offs

Although CCFLs offer high output light efficiency com-

pared to other lamp types such as incandescent, only a

percentage of the input energy is converted to light. As il-

lustrated in Fig. 17, 35% of the energy is lost in the elec-

trodes, 26% as conducted heat along the tube. A portion

of the Ultra Violet energy gets converted into visible light

by the lamp phosphor, where the remainder is converted

into radiated heat. Finally, Mercury atoms convert 3% of

the initial energy into visible light. The result is typically

15% overall electrical to optical energy conversion in the

lamp.

The lumen output of the backlight system is temperature

dependent as well, and may need to be accounted for in

applications requiring tight lumens regulation over a wide

temperature range. Fig. 14 shows the temperature ef-

fects on lumens for the lamp operated at 5mA.

Since lamp current is roughly proportional to luminosity, it

may be tempting to operate the lamp at a RMS current

higher than specified in the manufacturer’s data sheet.

While the lamp will continue to operate tens of percent

above the rated current, the luminosity gain becomes

Striking Voltage

5mA

140

120

100

80

1200

1000

800

600

400

200

0

60

40

20

0

20

40

60

0

20

40

60

80

AMBIENT TEMPERATURE (°C)

Figure 13. Temperature effects on voltage.

Figure 14. Temperature effects on lumens.

120

100

80

60

40

20

0

100

5mA

RATED

LAMP

10

1

50

75

100

125

150

175

200

0

2

4

6

8

10

% RATED LAMP CURRENT

LAMP CURRENT (mA)

Figure 15. Lumens output versus current.

Figure 16. Lamp life versus current.

16

UCC1972/3

UCC2972/3

UCC3972/3

APPLICATION INFORMATION (cont.)

In a practical backlight design, the physical spacing be- since capacitive reactance decreases as frequency in-

tween the lamp and high voltage secondary wiring with creases. This is why a pure sinusoid gives the best elec-

respect to the foil reflector and LCD frame can be tight. trical to optical efficiency, minimizing harmonic losses.

With this tight spacing, distributed stray capacitance will Sinusoidal waveforms require more circulating current in

form as shown in Fig. 17. The stray capacitance causes the resonant tank, however, lowering the electrical effi-

leakage currents from the high voltage secondary to cir- ciency of the converter.

cuit ground. Although the current through stray capaci-

The trade-off of electrical and optical efficiencies must be

tance doesn’t directly translate into losses, the extra

optimized to achieve the best design. System electrical

current through the transformer, primary resonant tank,

efficiencies of 75-85% are easily achievable in a typical

and switching devices does. A poor layout with exces-

UCC3972/3 based design while still maintaining good

sive stray capacitance can reduce system efficiency by

optical conversion. Efficiencies will vary with external

tens of percent. High frequency harmonics in the sec-

component selection, input voltage, and lamp power. Fig.

ondary voltage waveform impact efficiency even further,

18 and 19 show system electrical efficiencies versus in-

put voltage and output power for the 375V lamp design.

C

BALLAST

LAMP POWER 100%

C

STRAY

L

A

M

P

POSITIVE COLUMNS 65%

Hg VISIBLE

LIGHT 3%

C

ELECTRODE

LOSS 35%

HEAT LOSS

26%

UV RADIATION

36%

STRAY

VISIBLE LIGHT

15%

HEAT LOSS 85%

C

STRAY

UDG-98165

Figure 17. Lamp and stray capacitor losses.

Figure 18. Design example efficiency vs. input

voltage at 2W.

Figure 19. Design efficiency vs. output power.

UNITRODE CORPORATION

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 • FAX (603) 424-3460

17


型号：	UCC3972
厂家：	TEXAS INSTRUMENTS
描述：	BiCMOS Cold Cathode Fluorescent Lamp Driver Controller 的BiCMOS冷阴极荧光灯驱动器控制器驱动器控制器
文件：	总17页 (文件大小：310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC3972 [TI]

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UCC3972PWG4

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UCC3973

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