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UCD3138128, UCD3138A64

SLUSBZ8A –JUNE 2014–REVISED SEPTEMBER 2014

UCD3138x Highly-Integrated Digital Controller For Isolated Power

1 Features

– Low IC Standby Power

•

Primary Side Voltage Sensing

1

•

64 kB and 128 kB Program Flash Derivative of

UCD3138 Family

Current Share (Average & Master/Slave)

Feature Rich Fault Protection Options

–

2-32 kB or 4-32 kB Program Flash Memory

Banks

–

7 Analog / 4 Digital Comparators,

Cycle-by-Cycle Current Limiting

Supports Execution From 1 Bank, While

Programming Another

Programmable Blanking Time and Fault

Counting

Capability to Update Firmware Without

Shutting Down the Power Supply

–

External Fault Inputs

Additional Communication Ports Compared to

the UCD3138 (+1 SPI, +1 I2C)

•

Synchronization of DPWM Waveforms Between

Multiple UCD3138x Devices

Boot Flash Based Dual Memory Image

Support for ‘On the Fly’ Firmware Updates

15 channel, 12 bit, 267 ksps General Purpose

ADC

•

Digital Control of up to 3 Independent Feedback

Loops

•

Internal Temperature Sensor

Fully Programmable High-Performance 31.25

MHz, 32-bit ARM7TDMI-S Processor

–

Dedicated PID Based Hardware

2-pole/2-zero Configurable, Non-Linear Control

–

64 kB Program Flash (2-32 kB Banks)

2 kB Data Flash with ECC

Up to 16 MSPS Error A/D Converter (EADC)

–

Configurable Resolution (min: 1mV/LSB)

8 kB Data RAM

Up to 8x Oversampling and Adaptive Sample

Positioning

4 kB Boot ROM Enables Firmware Boot-Load

•

Communication Peripherals,

–

Hardware Based Averaging (up to 8x)

14 bit Effective Reference DAC

–

2 - I²C/PMBus interfaces

2 - UARTs, 1 - SPI

•

Up to 8 High Resolution Digital Pulse Width

Modulated (DPWM) Outputs

•

Timer Capture with Selectable Input Pins

80-pin QFP Package

–

250 ps Pulse Width Resolution

Operating Temperature: –40°C to 125°C

4 ns Frequency and Phase Resolution

Adjustable Phase Shift and Dead-bands

Cycle-by-Cycle Duty Cycle Matching

Up to 2 MHz Switching Frequency

2 Applications

•

Power Supplies and Telecom Rectifiers

Power Factor Correction

•

Configurable Trailing/Leading/Triangular

Modulation

Isolated DC-DC Modules

Phase Shifted Full Bridge with Peak Current Mode

Control, LLC, HSFB, Forward, etc.

•

RTC support

Configurable Feedback Control

Typical Applications and Tools

–

Voltage, Average Current and Peak Current

Mode Control

Best in Class Firmware

Development Tools

–

Constant Current, Constant Power

UCD3138A64

UCD3138128

•

Configurable FM, Phase Shift Modulation and

PWM

Advanced Configuration &

Advanced Topology Control

Fast, Automatic and Smooth Mode Switching

Debug Tools

V_IN

Q1

Q3

Transformer

L_K

L_R

–

Frequency Modulation and PWM

Phase Shift Modulation and PWM

Q2

V_IN

L^M

C_O

esr

Q₁

Q₂

Q4

SR₂

n₂

C_R

L₀

L

n

M

1

•

High Efficiency and Light Load Management

C₀

+ Forward, Flyback,

Half-bridge, etc...

Q₃

Q₄

SR₁

–

Burst Mode & Ideal Diode Emulation

Synchronous Rectifier Soft On/Off

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

UCD3138128, UCD3138A64

SLUSBZ8A –JUNE 2014–REVISED SEPTEMBER 2014

www.ti.com

Table of Contents

9.1 Overview ................................................................. 17

9.2 Functional Block Diagram ....................................... 18

9.3 Feature Description................................................. 19

9.4 Device Functional Modes........................................ 44

9.5 Register Maps......................................................... 53

1

2

3

4

5

6

7

8

Features.................................................................. 1

Applications ........................................................... 1

Revision History..................................................... 2

Description ............................................................. 3

Product Family Comparison................................. 4

Product Feature Overview .................................... 5

Pin Configuration and Functions......................... 6

Specifications......................................................... 8

8.1 Absolute Maximum Ratings ..................................... 8

8.2 Handling Ratings....................................................... 8

8.3 Recommended Operating Conditions....................... 9

8.4 Thermal Information.................................................. 9

8.5 Electrical Characteristics........................................... 9

8.6 Timing Characteristics............................................. 11

8.7 PMBUS/SMBUS/IC Timing².................................... 12

8.8 Timing Requirements.............................................. 12

9.6 Synchronous Rectifier MOSFET Ramp And IDE

Calculation ............................................................... 56

10 Applications and Implementation...................... 57

10.1 Application Information.......................................... 57

10.2 Typical Application ............................................... 58

11 Power Supply Recommendations ..................... 69

12 Layout................................................................... 69

12.1 IC Grounding and Layout Guidelines.................... 69

12.2 Layout Examples................................................... 70

13 Device and Documentation Support ................. 72

13.1 Device Support...................................................... 72

13.2 Documentation Support ........................................ 72

13.3 Trademarks........................................................... 74

13.4 Electrostatic Discharge Caution............................ 74

13.5 Glossary................................................................ 74

8.9 Power On Reset (POR) / Brown Out Detect

(BOD)....................................................................... 14

8.10 Typical Clock Gating Power Savings.................... 15

8.11 Typical Characteristics.......................................... 16

Detailed Description ............................................ 17

14 Mechanical, Packaging, and Orderable

9

Information ........................................................... 74

3 Revision History

Changes from Original (June 2014) to Revision A

Page

•

Added device UCD313128 .................................................................................................................................................... 1

Changed Feature From: "64 kB Program Flash Derivative.." To: "64 kB and 128 kB Program Flash Derivative..." ............. 1

Changed Feature From: 2-32 kB Program Flash Memory Banks To: 2-32 kB or 4-32 kB Program Flash Memory Banks .. 1

Added Feature: "Boot Flash Based Dual Memory..." ............................................................................................................. 1

Changed Feature From: 4 kB Data RAM To: 8 kB Data RAM .............................................................................................. 1

Changed Feature From: "8 kB Boot ROM Enables..." To: "4 kB Boot ROM Enables..." ....................................................... 1

Changed From: UCD3138A64 to UCD3138x throughout the document................................................................................ 3

Changed the Product Family Comparison table..................................................................................................................... 4

Deleted table: Summary Of Key Differences Between UCD3138x & UCD3138.................................................................... 5

Changed title From: POWER ON RESET AND BROWN OUT (V33D pin, See Figure 3) To: POWER ON RESET

AND BROWN OUT (V33A pin, See Figure 3)...................................................................................................................... 10

•

Changed title From: POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3) To: POWER ON RESET

AND BROWN OUT (V33A pin, See Figure 3)...................................................................................................................... 12

•

Changed From: V33D To: V33A in the definitions list following Figure 3 ........................................................................... 14

Changed paragraph 2 of the Memory section From: 2048x32-bit Boot ROM To: 1024x32-bit Boot ROM ........................ 17

Changed text in the Memory section description From: The availability of 64 kB of program Flash memory in 2-32

kB banks, enables the designers to implement dual images To: The availability of 64 kB or 128 kB of program Flash

memory in 2-32 kB or 4-32 kB banks, enables the designers to implement multiple images.............................................. 17

•

Added a 2 new paragraphs to the end of the Memory section description.......................................................................... 17

Changed the Memory Map (After Reset Operation) to include Program Flash 2 and Program Flash 3 ............................ 53

Changed the Memory Map (Normal Operation) to include Program Flash 2 and Program Flash 3 ................................... 53

Added Figure 36 .................................................................................................................................................................. 55

2

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4 Description

The UCD3138 family is a digital power supply controller from Texas Instruments offering superior levels of

integration and performance in a single chip solution. The UCD3138x, in comparison to Texas Instruments

UCD3138x digital power controller offers 64 kB of program Flash memory in UCD3138A64 (128 KB in

UCD3138128) and additional options for communication such as SPI and a second I²C port. o The availability of

of program Flash memory in multiple 32 kB banks enables designers to implement dual images of firmware (e.g.

one main image + one back-up image) in the device and provides the option to execute from either of the banks

using appropriate algorithms. It also creates the unique opportunity for the processor to load a new program and

subsequently execute that program without interrupting power delivery. This feature allows the end user to add

new features to the power supply in the field while eliminating any down-time required to load the new program.

The flexible nature of the UCD3138 family makes it suitable for a wide variety of power conversion applications.

In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance

of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network

infrastructure space. The UCD3138 family is a fully programmable solution offering customers complete control

of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to

simplifying our customer’s development effort through offering best in class development tools, including

application firmware, Code Composer Studio^TMsoftware development environment, and TI’s Fusion Power

Development GUI which enables customers to configure and monitor key system parameters.

At the core of the controller are the Digital Power Peripherals (DPP). Each DPP implements a high speed digital

control loop consisting of a dedicated Error Analog to Digital Converter (EADC), a PID based 2 pole - 2 zero

digital compensator and DPWM outputs with 250ps pulse width resolution. The device also contains a 12-bit, 267

ksps general purpose ADC with up to 15 channels, timers, interrupt control, PMBus, I²C, SPI and UART

communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-

time monitoring, configures peripherals and manages communications. The ARM microcontroller executes its

program out of programmable flash memory as well as on chip RAM and ROM.

In addition to the DPP, specific power management peripherals have been added to enable high efficiency

across the entire operating range, high integration for increased power density, reliability, and lowest overall

system cost and high flexibility with support for the widest number of control schemes and topologies. Such

peripherals include: light load burst mode, synchronous rectification, LLC and phase shifted full bridge mode

switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current

constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing,

secondary side input voltage sensing, high resolution current sharing, hardware configurable soft start with pre

bias, as well as several other features. Topology support has been optimized for voltage mode and peak current

mode controlled phase shifted full bridge, single and dual phase PFC, bridgeless PFC, hard switched full bridge

and half bridge, active clamp forward converter, two switch forward converter and LLC half bridge and full bridge.

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

12.00 mm × 12.00 mm

UCD3138128

UCD3138A64

TQFP (80)

(1) For detailed ordering information please check the Mechanical, Packaging, and Orderable Information section at the end of this

datasheet.

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6 Product Feature Overview

FEATURE

UCD3138x 80 PIN

ARM7TDMI-S Core Processor

31.25 MHz

High Resolution DPWM Outputs (250ps Resolution)

8

Number of High Speed Independent Feedback Loops (# Regulated Output Voltages)

3

12-bit, 267ksps, General Purpose ADC Channels

15

Digital Comparators at ADC Outputs

4

Flash Memory (Program) (UCD3138A64)

64 kB

Flash Memory (Program) (UCD3138128)

128 kB

Flash Memory (Data)

2 kB

Flash Security

√

RAM

8 kB

DPWM Switching Frequency

up to 2 MHz

Programmable Fault Inputs

4

High Speed Analog Comparators with Cycle-by-Cycle Current Limiting

7

UART (SCI)

2

PMBus

1

I²C

1

SPI

1

Timers

4 (16 bit) and 2 (24 bit)

Timer PWM Outputs

Timer Capture Inputs

Watchdog

4

2

√

On Chip Oscillator

Power-On Reset and Brown-Out Detector

Sync IN and Sync OUT Functions

Total GPIO (includes all pins with multiplexed functions such as, DPWM, Fault Inputs, SCI, etc.)

External Interrupts

43

1

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7 Pin Configuration and Functions

12mm × 12mm TQFP

80 Pins

Bottom View

1

2

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

AD13

AD12

DGND

V33D

3

AD10

BP18

4

AD07

V33DIO

DGND

5

AD06

6

AD04

FAULT3

FAULT2

SPI_MISO

SPI_MOSI

SPI_CLK

SPI_CS

7

AD03

8

V33DIO

9

DGND

10

11

12

13

14

15

16

17

18

19

20

/RESET

PWM2

PWM3

TCAP0/TCAP1

TMS

TCAP1/TCAP0

ADC_EXT_TRIG

PMBUS_CLK

PMBUS_DATA

PMBUS_ALERT

PMBUS_CTRL

I2C_CLK

I2C_DATA

TDI/TCAP0/TCAP1

TDO/TCAP0/TCAP1

TCK/RTC_IN/RTC_OUT

FAULT1

FAULT0

EXT_INT

DGND

Additional pin functionality is specified in the following table.

Pin Functions

ALTERNATE ASSIGNMENT

CONFIGURABLE

AS A GPIO?

NAME

PRIMARY ASSIGNMENT

NO. 1

NO. 2

1

2

3

AD13

AD12

AD10

12-bit ADC, Ch 13, comparator E, I-share

12-bit ADC, Ch 12

DAC output

12-bit ADC, Ch 10

12-bit ADC, Ch 7, Connected to comparator F and reference to

comparator G

4

AD07

DAC output

5

6

7

8

AD06

12-bit ADC, Ch 6, Connected to comparator F

12-bit ADC, Ch 4, Connected to comparator D

12-bit ADC, Ch 3, Connected to comparator B and C

Digital I/O 3.3V core supply

DAC output

AD04

AD03

V33DIO

6

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Pin Functions (continued)

ALTERNATE ASSIGNMENT

CONFIGURABLE

AS A GPIO?

NAME

PRIMARY ASSIGNMENT

NO. 1

NO. 2

9

DGND

RESET

PWM2

PWM3

TCAP1

Digital ground

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

Device Reset Input, active low

General purpose PWM 2

General purpose PWM 3

Timer Capture Input

Yes

TCAP0

ADC_EXT_TRIG

PMBUS_CLK

PMBUS_DATA

PMBUS_ALERT

PMBUS_CTRL

I2C_CLK

I2C_DATA

DGND

ADC conversion external trigger input

PMBUS Clock (Open Drain)

PMBus data (Open Drain)

PMBus Alert (Open Drain)

PMBus Control (Open Drain)

I2C Clock

I2C Data

Digital ground

DPWM0A

DPWM0B

DPWM1A

DPWM1B

DPWM2A

DPWM2B

DPWM3A

DPWM3B

GPIOA

DPWM 0A output

Yes

DPWM 0B output

DPWM 1A output

DPWM 1B output

DPWM 2A output

DPWM 2B output

DPWM 3A output

DPWM 3B output

General Purpose I/O Pin

DPWM Synchronize pin

SCI TX 0

GPIOB

GPIOC

GPIOD

SYNC

SCI_TX0

SCI_RX0

SCI_TX1

SCI_RX1

PWM0

SCI RX 0

SCI TX 1

SCI RX 1

General purpose PWM 0

General purpose PWM 1

Digital ground

PWM1

DGND

EXT_INT

FAULT0

FAULT1

TCK⁽¹⁾

External Interrupt

Yes

External fault input 0

External fault input 1

JTAG TCK (for manufacturer test only)

JTAG TDO (for manufacturer test only)

JTAG TDI (for manufacturer test only)

JTAG TMS (for manufacturer test only)

Timer Capture Input

RTC_IN

TCAP0

RTC_OUT

TCAP1

TDO⁽¹⁾

TDI⁽¹⁾

TCAP1

TMS⁽¹⁾

TCAP0

TCAP1

SPI_CS

SPI Chip Select

SPI_CLK

SPI_MOSI

SPI_MISO

FAULT2

FAULT3

DGND

SPI Clock

SPI Master Output Slave Input

SPI Master Input Slave Output

External fault input 2

External fault input 3

Digital ground

V33DIO

Digital I/O 3.3V core supply

1.8V Bypass (For internal use only, do not load)

Digital 3.3V core supply

Digital ground

BP18

V33D

DGND

RSVD

Internal use only. Tie to BP18.

RTC external clock input

RTC_IN_1_8

(1) Fusion Digital Power based debug tools are recommended instead of JTAG.

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Pin Functions (continued)

ALTERNATE ASSIGNMENT

NO. 1 NO. 2

CONFIGURABLE

AS A GPIO?

NAME

PRIMARY ASSIGNMENT

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

AGND

EAP0

EAN0

EAP1

EAN1

EAP2

EAN2

AGND

V33A

AD00

AD01

AD02

AD05

AD14

AD08

AD09

AD11

AGND

Analog ground

Channel #0, differential analog voltage, positive input

Channel #0, differential analog voltage, negative input

Channel #1, differential analog voltage, positive input

Channel #1, differential analog voltage, negative input

Channel #2, differential analog voltage, positive input

Channel #2, differential analog voltage, negative input

Analog ground

Analog 3.3V supply

12-bit ADC, Ch 0, Connected to current source

12-bit ADC, Ch 1, Connected to current source

12-bit ADC, Ch 2, Connected to comparator A, I-share

12-bit ADC, Ch 5

12-bit ADC, Ch 14

12-bit ADC, Ch 8

12-bit ADC, Ch 9

12-bit ADC, Ch 11

Analog ground

8 Specifications

(1)

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

–0.3

-0.3

MAX

3.8

2.5

0.3

3.0

V33D

V33D to DGND

V33DIO to DGND

V33A to AGND

BP18 to DGND

Ground difference

V

V33DIO

V33A

BP18

|DGND – AGND|

RTC_IN_1_8/RSVD

-0.3

–0.3

–40

All Pins, excluding

AGND⁽²⁾

Voltage applied to any pin

Junction Temperature

3.8

V

T_OPT

125

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Referenced to DGND

8.2 Handling Ratings

MIN

MAX

UNIT

T_stg

Storage temperature range

–55

150

°C

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

pins⁽¹⁾

–2000

–500

2000

500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8

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8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

3.0

1.6

-40

TYP

3.3

1.8

-

MAX UNIT

V33D

V33DIO

V33A

BP18

T_J

Digital power

3.6

2.0

125

V

Digital I/O power

Analog power

V

1.8 V digital power

Junction temperature

V

°C

8.4 Thermal Information

THERMAL METRIC⁽¹⁾

80-PIN QFN

47.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJCtop

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

7.8

24.4

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

24.0

R_θJCbot

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T_J= –40°C to 125°C (unless otherwise noted)

PARAMETER

SUPPLY CURRENT

TEST CONDITION

MIN

TYP

MAX

UNIT

Measured on V33A. The device is

powered up but all ADC12 and EADC

sampling is disabled

I33A⁽¹⁾

6.3

mA

All GPIO and communication pins are

open

I33DIO⁽¹⁾

I33D⁽¹⁾

0.35

69

mA

ROM program execution

The device is in ROM mode with all

DPWMs enabled and switching at 2

MHz. The DPWMs are all unloaded.

I33

93

100

mA

ERROR ADC INPUTS EAP, EAN

EAP – AGND

–0.15

–0.256

–256

0.8

1.998

1.848

248

V

EAP – EAN

V

Typical error range

AFE = 0

mV

MΩ

μA

AFE = 3

1

2

4

8

1.20

2.30

4.45

9.10

AFE = 2

1.7

EAP – EAN Error voltage digital resolution

AFE = 1

3.55

6.90

0.5

AFE = 0

R_EA

Input impedance (See Figure 9)

AGND reference

I_OFFSETInput offset current (See Figure 9)

–5

5

16

10

-6

4

Input voltage = 0 V at AFE = 0

Input voltage = 0 V at AFE = 1

Input voltage = 0 V at AFE = 2

Input voltage = 0 V at AFE = 3

–16

–10

–6

mV

EADC Offset

–4

15.62

5

Sample Rate

MHz

Analog Front End Amplifier Bandwidth

100

(1) Characterized by design and not production tested.

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Electrical Characteristics (continued)

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T_J= –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

See Figure 10

MIN

TYP

MAX

21

UNIT

V/V

Gain

Minimum output voltage

EADC DAC

DAC range

1

A₀

mV

0

1.6

V

VREF DAC reference resolution

10 bit, No dithering enabled

With 4 bit dithering enabled

1.56

97.6

mV

μV

VREF DAC reference resolution

INL

–1.5

–1.0

1.58

1.5

2.1

LSB

V

DNL

DAC reference voltage

1.61

ADC12

I_BIAS

Bias current for PMBus address pins

Measurement range for voltage monitoring

Internal ADC reference voltage

9.5

0

10.5

2.5

μA

V

–40°C to 125°C

–40°C to 25°C

25°C to 125°C

2.475

2.500

–0.7

2.53

V

Change in Internal ADC reference from

25°C reference voltage⁽¹⁾

mV

-6

ADC12 INL integral nonlinearity⁽²⁾

ADC12 DNL differential nonlinearity⁽²⁾

ADC Zero Scale Error

-7.5/+2.9

–0.7/+3.2

±5

LSB

mV

nA

ADC_SAMPLING_SEL = 6 for all

ADC12 data, 25 °C to 125 °C

–7

7

35

ADC Full Scale Error

–35

±20

Input bias

2.5 V applied to pin

200

Input leakage resistance⁽²⁾

Input Capacitance⁽²⁾

ADC_SAMPLING_SEL= 6 or 0

1

MΩ

pF

10

DIGITAL INPUTS/OUTPUTS⁽³⁾⁽⁴⁾

DGND

+ 0.25

V_OL

V_OH

Low-level output voltage⁽⁵⁾

I_OH= 4 mA, V33DIO = 3 V

I_OH= –4 mA, V33DIO = 3 V

V

V33DIO

– 0.6

(5)

High-level output voltage

V_IH

V_IL

I_OH

I_OL

High-level input voltage

Low-level input voltage

Output sinking current

Output sourcing current

V33DIO = 3 V

2.1

V

1.1

4

mA

–4

SYSTEM PERFORMANCE

Processor master clock (MCLK)

Digital filter delay⁽⁶⁾

31.25

250

MHz

MCLKs

MHz

t_Delay

(1 clock = 32ns)

6

f_(PCLK)

Internal oscillator frequency

240

238

9.7

260

Current share current source (See

Figure 28)

I_SHARE

259

μA

kΩ

R_SHARECurrent share resistor (See Figure 28)

POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)

10.3

VGH

VGL

V_res

Voltage good High

Voltage good Low

2.7

2.5

0.8

V

Voltage at which IReset signal is valid⁽²⁾

(2) Characterized by design and not production tested.

(3) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.

(4) On the 40 pin package V33DIO is connected to V33D internally.

(5) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop

specified. Maximum sink current per pin = –6 mA at V_OL; maximum source current per pin = 6 mA at V_OH

.

(6) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which

has no variation associated with it, must be accounted for when calculating the system dynamic response.

10

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Electrical Characteristics (continued)

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T_J= –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Internal signal warning of brownout

conditions

Brownout

2.9

V

TEMPERATURE SENSOR⁽²⁾

V_TEMP

Voltage range of sensor

Volts/°C

1.46

2.44

V

mV/ºC

ºC/LSB

ºC

Voltage resolution

Temperature resolution

Accuracy⁽²⁾⁽⁷⁾

6.3

0.0969

±5

Degree C per bit

-40°C to 125°C

–10

–40

10

Temperature range

I_TEMP

-40°C to 125°C

125

ºC

Current draw of sensor when active

Trimmed 25°C reading

30

μA

V_AMB

ANALOG COMPARATOR

DAC Reference DAC Range

Ambient temperature

1.87

V

0

2.5

V

Reference Voltage

2.478

2.5 2.513

V

Bits

INL⁽²⁾

DNL⁽²⁾

7

bits

LSB

mV

mA

mV

–0.42

0.06

–5.5

0.5

0.21

0.12

19.5

1

Offset

Reference DAC buffered output load⁽⁸⁾

Buffer offset (-0.5 mA)

Buffer offset (1.0 mA)

8.3

17

RTC INTERFACE

f_RTCRTC external input frequency

10

MHz

(7) Ambient temperature offset value from the TEMPSENCTRL register should be used to meet accuracy.

(8) Available from reference DACs for comparators D, E, F and G.

8.6 Timing Characteristics

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T_J= –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

250

3.9

MAX

UNIT

ns

EADC DAC

t

Settling Time

From 10% to 90%

ADC12

ADC single sample conversion time⁽¹⁾

ADC_SAMPLING_SEL= 6 or 0

μs

SYSTEM PERFORMANCE

Total time is: TWD x

(WDCTRL.PERIOD+1)

TWD Watchdog time out resolution

10.5

100

13.3

17

6

ms

ns

Time to disable DPWM output based on

active FAULT pin signal

High level on FAULT pin

66

1

Flash Read

MCLKs

t_Delay

Digital filter delay⁽²⁾

(1 clock = 32ns)

T_J= 25°C

Retention period of flash content (data

retention and program)

years

ms

Program time to erase one page or block in

data flash or program flash

20

50

Program time to write one word in program

flash

µs

(1) Characterized by design and not production tested.

(2) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which

has no variation associated with it, must be accounted for when calculating the system dynamic response.

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Timing Characteristics (continued)

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T_J= –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

µs

Program time to write one word in data

flash

40

Sync-in/sync-out pulse width

Sync pin

256

ns

POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)

Time delay after Power is good or

RESET* relinquished

t_POR

1

ms

I_RESETgoes from a low state to a high

state. This is approximately equivalent

to toggling the external reset pin from

low to high state.

The time it takes from the device to exit a

reset state and begin executing the boot

flash.⁽¹⁾

t_EXC1

0.5

I_RESETgoes from a low state to a high

state. This is approximately equivalent

to toggling the external reset pin from

low to high state.

The time it takes from the device to exit a

reset state and begin executing program

flash bank 0 (32 kB).⁽¹⁾

t_EXC2

3

6

ms

μs

I_RESETgoes from a low state to a high

state. This is approximately equivalent

to toggling the external reset pin from

low to high state.

The time it takes from the device to exit a

reset state and begin executing the total

program flash (64 kB).⁽¹⁾

t_EXCT

TEMPERATURE SENSOR⁽¹⁾

t_ON

Turn on time / settling time of sensor

100

7

ANALOG COMPARATOR

Bits

bits

LSB

INL⁽³⁾

DNL⁽³⁾

–0.42

0.06

0.21

0.12

Time to disable DPWM output based on 0

V to 2.5 V step input on the analog

90

150

ns

comparator.⁽³⁾

(3) Characterized by design and not production tested.

8.7 PMBUS/SMBUS/IC Timing²

The timing characteristics and timing diagram for the communications interface that supports I²C, SMBus, and

PMBus in Slave or Master mode are shown in the Timing Requirements, Figure 1, and Figure 2. The numbers in

the Timing Requirements are for 400 kHz operating frequency. However, the device supports two speeds,

standard (100 kHz) and fast (400 kHz).

8.8 Timing Requirements

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

Typical values at T_A= 25°C and VCC = 3.3 V (unless otherwise noted)

f_SMB

f_I2C

SMBus/PMBus operating frequency

I²C operating frequency

Slave mode, SMBC 50% duty cycle

Slave mode, SCL 50% duty cycle

100 400

kHz

Bus free time between start and

stop⁽¹⁾

t_(BUF)

1.3

µs

t_(HD:STA)

t_(SU:STA)

t_(SU:STO)

t_(HD:DAT)

t_(SU:DAT)

Hold time after (repeated) start⁽¹⁾

Repeated start setup time⁽¹⁾

Stop setup time⁽¹⁾

0.6

0

µs

ns

ms

µs

Data hold time

Receive mode

Data setup time

100

35

t_(TIMEOUT)Error signal/detect⁽²⁾

t_(LOW)Clock low period

1.3

(1) Fast mode, 400 kHz

(2) The device times out when any clock low exceeds t_(TIMEOUT)

.

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Timing Requirements (continued)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNIT

t_(HIGH)

Clock high period⁽³⁾

35

ms

Cumulative clock low slave extend

time⁽⁴⁾

t_(LOW:SEXT)

25

ms

20 + 0.1

Cb⁽⁵⁾

t_f

Clock/data fall time

Rise time t_r= (V_ILmax– 0.15) to (V_IHmin+ 0.15)

Fall time t_f= 0.9 VDD to (V_ILmax– 0.15)

300

ns

20 + 0.1

Cb⁽⁵⁾

t_r

Clock/data rise time

300

400

ns

C_b

Total capacitance of one bus line

pF

(3) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This

specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).

(4) t_(LOW:SEXT)is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(5) C_b(pF)

Figure 1. IC/SMBUS/PMBUS Timing Diagram²

Figure 2. Bus Timing In Extended Mode

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8.9 Power On Reset (POR) / Brown Out Detect (BOD)

V33D

3.3 V

Brown Out

VGH

VGL

Vres

t

t_POR

IReset

t

undefined

Figure 3. Power On Reset (POR) / Brown Out Reset (BOR)

VGH –

VGL –

This is the V33A threshold where the internal power is declared good. The UCD3138x comes out

of reset when above this threshold.

This is the V33A threshold where the internal power is declared bad. The device goes into reset

when below this threshold.

V_res

I_Reset

t_POR

–

This is the V33A threshold where the internal reset signal is no longer valid. Below this threshold

the device is in an indeterminate state.

–

This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding

the reset pin on the IC low.

–

The time delay from when VGH is exceeded to when the device comes out of reset.

Brown

Out –

This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an

interrupt can be triggered if enabled.

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8.10 Typical Clock Gating Power Savings

6.00

5.00

4.00

3.00

2.00

1.00

0.00

DPWM

ADC12

Front-end Control Peak Current

Mode

Timer

Filter

Constant

Power/Constant

Current

SCI

GIO

C001

Module

The CLKGATECTRL register provides control bits that can enable or disable the clock to several peripherals

such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.

By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in

order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current

consumption of the device. The power savings chart displays the power savings per module. For example there

are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.

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8.11 Typical Characteristics

ADC12 Measurement Temperature Sensor Voltage

2.1

2.6

2.4

2.2

2.0

1.8

1.6

1.4

2

1.9

1.8

1.7

1.6

−60 −40 −20

0

20 40 60 80 100 120 140 160

Temperature (°C)

−40

−20

0

20

40

60

Temperature (°C)

80

100

120

G006b

G005a

Figure 5. ADC12 Measurement Temperature Sensor Voltage

vs. Temperature

Figure 4. EADC LSB Size With 4x Gain (Mv) vs. Temperature

ADC12 2.5-V Reference

ADC12 Temperature Sensor Measurement Error

8

2.515

2.510

2.505

2.500

6

4

2

2.495

2.490

2.485

0

−2

−4

2.480

2.475

−40

−20

0

20

40

60

Temperature (°C)

80

100

120

−40

−20

0

20

40

60

80

100

120

G002b

Temperature (°C)

G003b

Figure 7. ADC12 Temperature Sensor Measurement Error

vs. Temperature

Figure 6. ADC12 2.5-V Reference vs. Temperature

2.08

2.06

3 σ

1 σ

AVG

-1 σ

-3 σ

2.04

2.02

2

1.98

1.96

1.94

1.92

-100

-50

0

50

100

150

200

Temperature (°C)

Figure 8. Oscillator Frequency (2MHz Reference, Divided Down From 250MHz) vs. Temperature

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9 Detailed Description

9.1 Overview

9.1.1 ARM Processor

The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit

microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where

two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set. The

Thumb instructions allow for higher code density equivalent to a 16-bit microprocessor, with the performance of

the 32-bit microprocessor.

The three-staged pipelined ARM processor has fetch, decode and execute stage architecture. Major blocks in

the ARM processor include a 32-bit ALU, 32 x 8 multiplier, and a barrel shifter.

9.1.2 Memory

The UCD3138x (ARM7TDMI-S) is a Von-Neumann architecture, where a single bus provides access to all of the

memory modules. All of the memory module addresses are sequentially aligned along the same address range.

This applies to program flash, data flash, ROM and all other peripherals.

Within the UCD3138 family architecture, there is a 1024x32-bit Boot ROM that contains the initial firmware

startup routines for PMBUS communication and non-volatile (FLASH) memory download. This boot ROM is

executed after power-up-reset checks if there is a valid FLASH program written. If a valid program is present, the

ROM code branches to the main FLASH-program execution. If there is no valid program, the device waits for a

program download through the PMBus.

The UCD3138 family also supports customization of the boot program by allowing an alternative boot routine to

be executed from program FLASH. This feature enables assignment of a unique address to each device;

therefore, enabling firmware reprogramming even when several devices are connected on the same

communication bus.

There are three separate flash memory areas present inside the device. There are 2-32 kB program flash blocks

and 1-2 kB data flash area. The 32 kB program areas are organized as 8 k x 32 bit memory blocks and are

intended to be for the firmware programs. The blocks are configured with page erase capability for erasing blocks

as small as 1 kB per page, or with a mass erase for erasing the entire 32 kB array. The flash endurance is

specified at 1000 erase/write cycles and the data retention is good for 100 years. The 2 kB data flash array is

organized as a 512 x 32 bit memory (32 byte page size). The data flash is intended for firmware data value

storage and data logging. Thus, the Data flash is specified as a high endurance memory of 20 k cycles with

embedded error correction code (ECC).

For run time data storage and scratchpad memory, a 8 kB RAM is available. The RAM is organized as a 2 k x 32

bit array.

The availability of 64 kB or 128 kB of program Flash memory in 2-32 kB or 4-32 kB banks, respectively enables

the designers to implement multiple images of firmware (e.g. one main image + one back-up image) in the device

and the flexibility to execute from either of the banks using appropriate algorithms. It also creates the unique

opportunity for the processor to load a new program and subsequently execute that program without interrupting

power delivery. This feature allows the end user to add new features to the power supply while eliminating any

down-time required to load the new program.

The UCD3138128 adds two additional 32 kB program flash blocks. On the UCD3138128, the boot ROM supports

a dual image configuration where each image contains 64 kB. If the first 64kB has an invalid program, the boot

ROM will check for a valid program in the second 64kB and jump there. The boot ROM also supports a

configuration with a single program occupying the entire 128 kB.

For the UCD3138128, on the fly updates are supported through boot ROM while UCD3138A64 on the fly

updates are supported through boot flash. Detailed procedures can be found in SLUUB54

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9.2 Functional Block Diagram

Loop MUX

DPWM0A

EAP0

PID Based

Filter 0

Front End 0

EAN0

DPWM0

DPWM1

DPWM2

DPWM3

DPWM0B

DPWM1A

EAP1

PID Based

Filter 1

Front End 1

EAN1

DPWM1B

DPWM2A

DPWM2B

DPWM3A

PID Based

Filter 2

Front End 2

AFE

Constant Power Constant

Current

2^3-AFE

DPWM3B

SYNC

EAP2

Front End Averaging

Digital Comparators

EADC

2^AFE

X

Avg()

EAN2

SAR/Prebias

Ramp

DAC0

Input Voltage Feed Forward

A₀

Filter x

CPCC

G

Value

Dither

Abs()

Peak Current Mode

Control Comparator

PMBUS_ALERT

PMBUS_CTRL

PMBUS_DATA

PMBUS_CLK

PWM0

Advanced Power Control

Mode Switching, Burst Mode, IDE,

Synchronous Rectification soft on & off

PMBus/I²C

ADC_EXT

AD[14:0]

ADC12 Control

Sequencing, Averaging,

Digital Compare, Dual

Sample and hold

PWM1

ADC12

Timers

PWM2

AD00

AD01

4 ± 16 bit (PWM)

2 ± 24 bit (TCAP)

PWM3

Internal Temperature

Sensor

TCAP0

TCAP1

AD02

AD13

Current Share

Analog, Average, Master/Slave

AGND

Oscillator

SCI_TX1

SCI_RX0

SCI_TX1

SCI_RX1

EXT_INT

FAULT0

FAULT1

FAULT2

FAULT3

GPIO[A..D]

/RESET

UART0

UART1

ARM7TDMI-S

32 bit, 31.25 MHz

Analog

Comparators

AD02

AD03

Memory

DFLASH 2 kB

RAM 8 kB

A

B

ROM 4 kB

PFLASH

64 kB (UCD3138A64)

or

GPIO

Control

C

128 kB (UCD3138128)

AD04

AD13

AD06

AD07

Fault MUX &

Control

Bank 0

32 kB

Bank 1

32 kB

D

V33D

V33DIO

BP18

Cycle by Cycle

Current Limit

E

Bank 3

32 kB

Bank 4

32 kB

Power and

1.8 V Voltage

Regulator

Digital

Comparators

TCK

F

DGND

V33A

Power On Reset

JTAG

TDI

G

TMS

Brown Out Detection

AGND

TDO

SPI_MISO

SPI_MOSI

SPI_CLK

SPI_CS

RTC_IN_1_8

RTC_IN

SPI

Real Time

Clock

RTC_OUT

I2C_DATA

I2C_CLK

PMBus/I²C

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9.3 Feature Description

9.3.1 System Module

The System Module contains the interface logic and configuration registers to control and configure all the

memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address decoder,

memory management controller, system management unit, central interrupt unit, and clock control unit.

9.3.1.1 Address Decoder (DEC)

The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory map

addresses are selectable through configurable register settings. These memory selects can be configured from 1

kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM execution, which is then

configured by the ROM code to the application setup. During access to the DEC registers, a wait state is

asserted to the CPU. DEC registers are only writable in the ARM privilege mode for user mode protection.

9.3.1.2 Memory Management Controller (MMC)

The MMC manages the interface to the peripherals by controlling the interface bus for extending the read and

write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of address space

decoding.

9.3.1.3 System Management (SYS)

The SYS unit contains the software access protection by configuring user privilege levels to memory or

peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal address or

access conditions. A clock control setup for the processor clock (MCLK) speed, is also available.

9.3.1.4 Central Interrupt Module (CIM)

The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports

two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of

interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table. This numerical index

value indicates the highest precedence channel with a pending interrupt and is used to locate the interrupt vector

address from the interrupt vector table. Interrupt channel 0 has the lowest precedence and interrupt channel 31

has the highest precedence. To remove the interrupt request, the firmware should clear the request as the first

action in the interrupt service routine. The request channels are maskable, allowing individual channels to be

selectively disabled or enabled.

Table 1. Interrupt Priority Table

MODULE COMPONENT OR

REGISTER

NAME

DESCRIPTION

PRIORITY

BRN_OUT_INT

EXT_INT

Brownout

Brownout interrupt

0 (Lowest)

External Interrupts

Watchdog Control

Interrupt on external input pin

Interrupt from watchdog exceeded (reset)

1

2

WDRST_INT

Wake-up interrupt when watchdog equals half of set watch

time

WDWAKE_INT

Watchdog Control

3

SCI_ERR_INT

SCI_RX_0_INT

SCI_TX_0_INT

SCI_RX_1_INT

SCI_TX_1_INT

PMBUS_INT

UART or SCI Control

UART or SCI error Interrupt. Frame, parity or overrun

UART0 RX buffer has a byte

4

5

UART0 TX buffer empty

6

UART1 RX buffer has a byte

7

UART1 TX buffer empty

8

PMBus related interrupt

9

DIG_COMP_SPI_I2C_INT 12-bit ADC Control, SPI, I²C

Digital comparator, SPI and I²C interrupt

10

“Prebias complete”, “Ramp Delay Complete”, “Ramp

Complete”, “Load Step Detected”,

FE0_INT Front End 0

11

“Over-Voltage Detected”, “EADC saturated”

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Feature Description (continued)

Table 1. Interrupt Priority Table (continued)

MODULE COMPONENT OR

REGISTER

NAME

DESCRIPTION

PRIORITY

“Prebias complete”, “Ramp Delay Complete”, “Ramp

Complete”, “Load Step Detected”,

FE1_INT

Front End 1

12

“Over-Voltage Detected”, “EADC saturated”

“Prebias complete”, “Ramp Delay Complete”, “Ramp

Complete”, “Load Step Detected”,

FE2_INT

Front End 2

13

“Over-Voltage Detected”, “EADC saturated”

PWM3_INT

16-bit Timer PWM 3

16-bit Timer PWM 2

16-bit Timer PWM 1

16-bit timer PWM 0

24-bit Timer Control

16-bit Timer PWM3 counter overflow or compare interrupt

16-bit Timer PWM2 counter Overflow or compare interrupt

16-bit Timer PWM1 counter overflow or compare interrupt

16-bit Timer PWM0 counter overflow or compare interrupt

24-bit Timer counter overflow interrupt

14

15

16

17

18

19

20

21

22

PWM2_INT

PWM1_INT

PWM0_INT

OVF24_INT

CAPTURE_1_INT

Reserved for future use

CAPTURE_0_INT

COMP_0_INT

24-bit Timer capture 1 interrupt

24-bit Timer Control

24-bit Timer capture 0 interrupt

24-bit Timer compare 0 interrupt

Constant Power Constant Current Mode switched in CPCC module Flag needs to be read for

CPCC_RTC_INT

ADC_CONV_INT

23

24

or Real Time Clock Output

details. RTC timer output generates an interrupt.

12-bit ADC Control

ADC end of conversion interrupt

Analog comparator interrupts, Over-Voltage detection,

Under-Voltage detection,

FAULT_INT

Fault Mux Interrupt

25

LLM load step detection

DPWM3

DPWM2

DPWM3

DPWM2

Same as DPWM1

26

27

1) Every (1-256) switching cycles

2) Fault Detection

DPWM1

28

3) Mode switching

DPWM0

Same as DPWM1

29

30

EXT_FAULT_INT

SYS_SSI_INT

External Faults

System Software

Fault pin interrupt

System software interrupt

31 (highest)

9.3.2 Peripherals

9.3.2.1 Digital Power Peripherals

At the core of the UCD3138x controller are 3 Digital Power Peripherals (DPP). Each DPP can be configured to

drive from one to eight DPWM outputs. Each DPP consists of:

•

Differential input error ADC (EADC) with sophisticated controls

Hardware accelerated digital 2-pole/2-zero PID based filter

Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are capable of

supporting functions like input voltage feed forward, current mode control, and constant current/constant power,

etc.. The simplest configuration is shown in the following figure:

EAP

DPWMA

Digital

PWM

Error ADC

(Front End)

Filter

DPWMB

EAN

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9.3.2.1.1 Front End

Figure 9 shows the block diagram of the front end module. It consists of a differential amplifier, an adjustable

gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging filters and a precision

high resolution set point DAC reference. The programmable gain amplifier in concert with the EADC and the

adjustable digital gain on the EADC output work together to provide 9 bits of range with 6 bits of resolution on the

EADC output. The output of the Front End module is a 9 bit sign extended result with a gain of 1 LSB / mV.

Depending on the value of AFE selected, the resolution of this output could be either 1, 2, 4 or 8 LSBs. In

addition Front End 0 has the ability to automatically select the AFE value such that the minimum resolution is

maintained that still allows the voltage to fit within the range of the measurement. The EADC control logic

receives the sample request from the DPWM module for initiating an EADC conversion. EADC control circuitry

captures the EADC-9-bit-code and strobes the filter for processing of the representative error. The set point DAC

has 10 bits with an additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be

driven from a variety of sources to facilitate things like soft start, nested loops, etc. Some additional features

include the ability to change the polarity of the error measurement and an absolute value mode which

automatically adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration. In this mode topologies like

the phase shifted full bridge converter can be controlled to maintain transformer flux balance. The internal DAC

can be ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This

eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is a unity

gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified in the

Electrical Characteristics table.

EAP

Front End Differential

Amplifier

R_EA

I_OFFSET

AGND

EAN

R_EA

I_OFFSET

AGND

Figure 9. Input Stage Of EADC Module

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AFE_GAIN

2^3-AFE_GAIN

EAP0

6 bit ADC

8mV/LSB

2^AFE_GAIN

EAN0

Signed 9 bit result

(error) 1 mV /LSB

EADC

X

Averaging

SAR/Prebias

Ramp

Filter x

CPCC

DAC0

A₀

10 bit DAC

1.5625mV/LSB

ꢁ

Value

Dither

4 bit dithering gives 14 bits of effective resolution

97.65625ꢀV/LSB effective resolution

Absolute Value

Calculation

10 bit result

1.5625mV/LSB

Peak Current

Detected

Peak Current Mode

Comparator

Figure 10. Front End Module

9.3.2.1.2 DPWM Module

The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B. Multiple

DPWM modules within the UCD3138x system can be configured to support all key power topologies. DPWM

modules can be used as independent DPWM outputs, each controlling one power supply output voltage rail. It

can also be used as a synchronized DPWM—with user selectable phase shift between the DPWM channels to

control power supply outputs with multiphase or interleaved DPWM configurations.

The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width

modulated outputs for the power stage switches. The filter calculates the necessary duty ratio as a 24-bit number

in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This

duty ratio value is used to generate the corresponding DPWM output ON time. The resolution of the DPWM ON

time is 250 psec.

Each DPWM module can be synchronized to another module or to an external synchronization signal. An input

SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four DPWM

modules—occur when the ramp timer crosses a programmed threshold. This allows the phase of the DPWM

outputs for multiple power stages to be tightly controlled.

The DPWM logic takes the output of the filter and converts it into the correct DPWM output for several power

supply topologies. It provides for programmable dead times and cycle adjustments for current balancing between

phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can

provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to several

fault handling circuits. Some of the control for these fault handling circuits is in the DPWM registers. Fault

handling is covered in the Fault Mux section.

Each DPWM module supports the following features:

•

Dedicated 14 bit time-base with period and frequency control

Shadow period register for end of period updates.

Quad-event control registers (A and B, rising and falling) (Events 1-4)

–

Used for on/off DPWM duty ratio updates.

•

Phase control relative to other DPWM modules

Sample trigger placement for output voltage sensing at any point during the DPWM cycle.

Support for 2 independent edge placement DPWM outputs (same frequency or period setting)

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•

Dead-time between DPWM A and B outputs

High Resolution PWM capability – 250 ps

Pulse cycle adjustment of up to ±8.192 µs ( 32768 × 250 ps)

Active high/ active low output polarity selection

Provides events to trigger both CPU interrupts and start of ADC12 conversions.

9.3.2.1.3 DPWM Events

Each DPWM can control the following timing events:

1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in relationship

to the DPWM period. The programmed value set in the register should be one fourth of the value calculated

based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the circuitry runs at one fourth

of the DPWM clock (PCLK = 250MHz max). When this sample trigger count is equal to the DPWM Counter,

it initiates a front end calculation by triggering the EADC, resulting in a CLA calculation, and a DPWM

update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.

2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).

3. Period–low resolution switching period count. (count of PCLK cycles)

4. Event 1–count offset for rising DPWM A event. (PCLK cycles)

5. Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are for

high resolution control. Upper 14 bits are the number of PCLK cycle counts.

6. Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution control.

Upper 14 bits are the number of PCLK cycle counts.

7. Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution control.

Upper 14 bits are the number of PCLK cycle counts.

8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.

Basic comparisons between the programmed registers and the DPWM counter can create the desired edge

placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.

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Multi Mode Open Loop

Start of Period

Period

Period Counter

DPWM Output A

Event 1

Event 2 (High Resolution)

Cycle Adjust A (High Resolution)

Sample Trigger 1

To Other

Modules

Blanking A Begin

Blanking A End

DPWM Output B

Event 3 (High Resolution)

Event 4 (High Resolution)

Cycle Adjust B (High Resolution)

Sample Trigger 2

Blanking B Begin

To Other

Modules

Blanking B End

Phase Trigger

Events which change with DPWM mode:

DPWM A Rising Edge = Event 1

DPWM A Falling Edge = Event 2 + Cycle Adjust A

DPWM B Rising Edge = Event 3

DPWM B Falling Edge = Event 4 + Cycle Adjust B

Phase Trigger = Phase Trigger Register value

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,

Blanking B End

The drawing above is for multi-mode, open loop. Open loop means that the DPWM is controlled entirely by its

own registers, not by the filter output. In other words, the power supply control loop is not closed.

The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking signals are

used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional DPWM

modes are described below.

24

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9.3.2.1.4 High Resolution DPWM

Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of PWM

edges, the UCD3138x DPWM can generate waveforms with resolutions as small as 250 ps. This is 16 times the

resolution of the clock driving the DPWM module.

This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz each.

9.3.2.1.5 Over Sampling

The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample the

error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the sample trigger

register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8 times per PWM period.

Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the sampling register. The “01”

setting triggers 2X over sampling, the “10” setting triggers 4X over sampling, and the “11” triggers over sampling

at 8X.

9.3.2.1.6 DPWM Interrupt Generation

The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in the

period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower interrupt

service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12 trigger for sequence

synchronization. Table 2 outlines the divide ratios that can be programmed.

9.3.2.1.7 DPWM Interrupt Scaling/Range

Table 2. DPWM Interrupt Divide Ratio

NUMBER OF 32

INTERRUPT

DIVIDE

SETTING

INTERRUPT

DIVIDE

COUNT

INTERRUPT

DIVIDE

COUNT (HEX)

SWITCHING PERIOD

FRAMES (assume

1MHz loop)

MHZ

PROCESSOR

CYCLES

1

2

0

1

00

01

03

07

0F

1F

2F

3F

4F

5F

7F

9F

BF

DF

FF

1

2

32

64

3

4

128

4

7

8

256

5

15

31

47

63

79

95

127

159

191

223

255

16

32

48

64

80

96

128

160

192

224

256

512

6

1024

1536

2048

2560

3072

4096

5120

6144

7168

8192

7

8

9

10

11

12

13

14

15

9.3.3 Automatic Mode Switching

Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware

intervention. This is useful to increase efficiency and power range. The following paragraphs describe phase-

shifted full bridge and LLC examples.

9.3.3.1 Phase Shifted Full Bridge Example

In phase shifted full bridge topologies, efficiency can be increased by using pulse width modulation, rather than

phase shift, at light load. This is shown below:

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DPWM3A

(QB1)

DPWM3B

(QT1)

DPWM2A

(QT2)

DPWM2B

(QB2)

VTrans

DPWM1B

(QSYN1,3)

DPWM0B

(QSYN2,4)

IPRI

Figure 11. Phase-Shifted Full Bridge Waveforms

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L1

T1

Q7

+12V

Q6

Q5

C1

RL

VBUS

I_pri

PRIM

CURRENT

ORING

CTL

T2

VOUT

C2

R2

D1

T1

QT2

QB2

QT1

VA

Lr

Current

Sensing

QB1

D2

DPWM0B

DPWM1B

Vref

DPWM0

Duty for mode

switching

Vout

Iout

CPCC

<

EADC0

EADC1

CLA0

DPWM1

DPWM2

CLA1

DPWM2A

DPWM2B

Load Current

DPWM3A

DPWM3B

I_pri

EADC2

DPWM3

PCM

AD00

ISOLATED

GATE Transformer

ACFAIL_IN

FAULT 0

FAULT 1

FAULT 2

SYNCHRONOUS

GATE DRIVE

AD01

AD02/CMP0

AD03/CMP1/CMP2

AD04/CMP3

AD05/CMP4

AD06/CMP5

AD07/CMP6

AD08

ACFAIL_OUT

FAILURE

I_SHARE

Vout

FAULT

GPIO1

GPIO2

GPIO3

ORING_CRTL

ON/OFF

Iout

I_pri

CBC

temp

P_GOOD

Vin

VA

WD

ARM7

AD09

PMBus

UART0

RST

OSC

Primary

UART1

Memory

Figure 12. Secondary-Referenced Phase-Shifted Full Bridge Control With Synchronous Rectification

9.3.3.2 LLC Example

In LLC, three modes are used. At the highest frequency, a pulse width modulated mode (Multi Mode) is used. As

the frequency decreases, resonant mode is used. As the frequency gets still lower, the synchronous MOSFET

drive changes so that the on-time is fixed and does not increase. In addition, the LLC control supports cycle-by-

cycle current limiting. This protection function operates by a comparator monitoring the maximum current during

the DPWMA conduction time. Any time this current exceeds the programmable comparator reference the pulse is

immediately terminated. Due to classic instability issues associated with half-bridge topologies it is also possible

to force DPWMB to match the truncated pulse width of DPWMA. Here are the waveforms for the LLC:

PWM

Mode

LLC Mode

fr

fs= fr_max

fs< fr

fs> fr

Q1T

Q1B

QSR1

QSR2

Tr= 1/fr

I_SEC(t)

Figure 13. LLC Waveforms

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VBUS

Q1T

I_LR(t)

Transformer

QSR2

LRES

LK

NS

Driver

DPWM1B

I_SEC(t)

Oring Circuitry

RLRES

Q1B

I_LM(t)

LM

V_OUT

NP

RF1

RF2

AD03

COUT1

COUT2

EAP0

V_OUT(t)

VBUS

ESR1

ESR2

CF

QSR1

EAN0

AD04

CRES

RS

Driver

DPWM1A

CS

CRES

V_CR(t)

RS1

RS2

ADC13

EAP1

Driver

DPWM0B

DPWM0A

Figure 14. Secondary-Referenced Half-Bridge Resonant LLC Control With Synchronous Rectification

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9.3.3.3 Mechanism For Automatic Mode Switching

The UCD3138x allows the customer to enable up to two distinct levels of automatic mode switching. These

different modes are used to enhance light load operation, short circuit operation and soft start. Many of the

configuration parameters for the DPWM are in DPWM Control Register 1. For automatic mode switching, some

of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.

If automatic mode switching is enabled, the filter duty signal is used to select which of these three registers is

used. There are 4 registers which are used to select the points at which the mode switching takes place. They

are used as shown below.

Automatic Mode Switching

With Hysteresis

Filter Duty

Full Range

Auto Config High

High – Upper Threshold

High – Lower Threshold

Auto Config Mid

Low – Upper Threshold

Low – Lower Threshold

Control

Register 1

0

Figure 15. Automatic Mode Switching

As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config

Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Auto

Config Mid until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is

close to a mode switching point.

9.3.4 DPWMC, Edge Generation, Intramux

The UCD3138x has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB

waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux.

DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the Blanking A

end time.

The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses

them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each

edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it.

The options are:

0 = DPWM(n) A Rising edge

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1 = DPWM(n) A Falling edge

2 = DPWM(n) B Rising edge

3 = DPWM(n) B Falling edge

4 = DPWM(n+1) A Rising edge

5 = DPWM(n+1) A Falling edge

6 = DPWM(n+1) B Rising edge

7 = DPWM(n+1) B Falling edge

Where “n" is the numerical index of the DPWM module of interest. For example n=1 refers to DPWM1.

The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit.

The IntraMux is controlled by the Auto Config registers. Intra Mux is short for intra multiplexer. The IntraMux

takes signals from multiple DPWMs and from the Edge Gen and combines them logically to generate DPWMA

and DPWMB signals This is useful for topologies like phase-shifted full bridge, especially when they are

controlled with automatic mode switching. Of course, it can all be disabled, and DPWMA and DPWMB will be

driven as described in the sections above. If the Intra Mux is enabled, high resolution must be disabled, and

DPWM edge resolution goes down to 4 ns.

Here is a drawing of the Edge Gen/Intra Mux:

A/B/C (N)

A/B/C (N+1)

INTRAMUX

C (N+2)

C (N+3)

PWM A

PWM B

EDGE GEN

A(N)

B(N)

EGEN A

EGEN B

A(N+1)

B(N+1)

B SELECT

A SELECT

A ON SELECT

A OFF SELECT

B ON SELECT

B OFF SELECT

Figure 16. Edge Generation / IntraMux

Here is a list of the IntraMux modes for DPWMA:

0 = DPWMA(n) pass through (default)

1 = Edge-gen output, DPWMA(n)

2 = DPWNC(n)

3 = DPWMB(n) (Crossover)

4 = DPWMA(n+1)

5 = DPWMB(n+1)

6 = DPWMC(n+1)

7 = DPWMC(n+2)

8 = DPWMC(n+3)

and for DPWMB:

0 = DPWMB(n) pass through (default)

1 = Edge-gen output, DPWMB(n)

2 = DPWNC(n)

3 = DPWMA(n) (Crossover)

4 = DPWMA(n+1)

5 = DPWMB(n+1)

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6 = DPWMC(n+1)

7 = DPWMC(n+2)

8 = DPWMC(n+3)

The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply:

DPWM(n)

DPWM3

DPWM0

DPWM1

DPWM2

DPWM(n+1)

DPWM(n+2)

DPWM(n+3)

9.3.5 Filter

The UCD3138x filter is a PID filter with many enhancements for power supply control. Some of its features

include:

•

Traditional PID Architecture

Programmable non-linear limits for automated modification of filter coefficients based on received EADC error

Multiple coefficient sets fully configurable by firmware

Full 24-bit precision throughout filter calculations

Programmable clamps on integrator branch and filter output

Ability to load values into internal filter registers while system is running

Ability to stall calculations on any of the individual filter branches

Ability to turn off calculations on any of the individual filter branches

Duty cycle, resonant period, or phase shift generation based on filter output.

Flux balancing

Voltage feed forward

Here is the first section of the Filter :

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Limit Comparator

Limit 6

Limit 5

…..

PID Filter Branch Stages

Kp Coef

Limit 0

Coefficient

select

EADC_DATA

Xn

<>

16

24

9

24

X

P

Xn-1 Reg

9

Ki Coef

9

Ki High

Clamp

Optional

Selected

by

24

16

24

9

24

9

+

Ki_yn reg

X

I

KI_ADDER_

MODE

24

Ki Low

Kd alpha

9

24

Kd coef

Kd yn_reg

24

X

32

9

Round

24

16

24

X_n–X_n+1

9

24

-

X

Clamp

+

D

Figure 17. First Section of the Filter

The filter input, Xn, generally comes from a front end. Then there are three branches, P, I. and D. Note that the D

branch also has a pole, Kd Alpha. Clamps are provided both on the I branch and on the D alpha pole.

The filter also supports a nonlinear mode, where up to 7 different sets of coefficients can be selected depending

on the magnitude of the error input Xn. This can be used to increase the filter gain for higher errors to improve

transient response.

Here is the output section of the filter (S0.23 means that there is 1 sign bit, 0 integer bits and 23 fractional bits).:

Filter Yn

Clamp High

Yn Scale

Shifter

24

P

I

24

S0.23

26

Filter Yn

Saturate

Yn

Clamp

+

D

S2.23

S0.23

Filter Yn

Clamp Low

All are S0.23

Figure 18. Output Section of the Filter

This section combines the P, I, and D sections, and provides for saturation, scaling, and clamping.

There is a final section for the filter, which permits its output to be matched to the DPWM:

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Filter Output

Clamp High

Round to

18 bits,

Truncate

low 4 bits

Filter Period

Bits [17:4]

Filter YN

24 S0.23

38

18

14

X

Clamp to

Positive

Round to

S14.23

14.4

14.0

Filter YN (Duty %)

18

Filter Duty

14.4

38

18 bits,

Clamp to

Positive

18

Clamp

X

24

S0.23

S14.23

14.4

KCompx 14.0

14

14.0

KCompx

DPWMx Period

Loop_VFF

14

DPWMx Period 14.0

Filter Output

Clamp Low

14.0

PERIOD_MULT_SEL

Resonant Duty

OUTPUT_MULT_SEL

Figure 19. Final Section for the Filter

This permits the filter output to be multiplied by a variety of correction factors to match the DPWM Period, to

provide for Voltage Feed Forward, or for other purposes. After this, there is another clamp. For resonant mode,

the filter can be used to generate both period and duty cycle.

9.3.5.1 Loop Multiplexer

The Loop Mux controls interconnections between the filters, front ends, and DPWMs. Any filter, front end, and

DPWM can be combined in a variety of configurations.

It also controls the following connections:

•

DPWM to Front End

Front End DAC control from Filters or Constant Current/Constant Power Module

Filter Special Coefficients and Feed Forward

DPWM synchronization

Filter to DPWM

The following control modules are configured in the Loop Mux:

•

Constant Power/Constant Current

Cycle Adjustment (Current and flux balancing)

Global Period

Light Load (Burst Mode)

Analog Peak Current Mode

9.3.5.2 Fault Multiplexer

In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the

UCD3138x provides an extensive array of multiplexers that are united under the name Fault Mux module.

The Fault Mux Module supports the following types of mapping between all the sources of fault and all the

different fault response mechanisms inside each DPWM module.

•

Many fault sources may be mapped to a single fault response mechanism. For instance an analog

comparator in charge of over voltage protection, a digital comparator in charge of over current protection and

an external digital fault pin can be all mapped to a Fault-A signal connected to a single FAULT MODULE and

shut down DPWM1-A.

•

A single fault source can be mapped to many fault response mechanisms inside many DPWM modules. For

instance an analog comparator in charge of over current protection can be mapped to DPWM-0 through

DPWM-3 by way of several fault modules.

Many fault sources can be mapped to many fault modules inside many DPWM modules.

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CBC_PWM_AB_EN

FAULT MUX

DPWM

Bit20 in DPWMCTRL0

CYCLE BY CYCLE

ANALOG PCM

FAULT- CBC

AB FLAG

FAULT MODULE

DISABLE PWM A AND B

CBC_FAULT_EN

Bit30 in DPWMFLTCTRL

FAULT- AB

FAULT-A

FAULT-B

AB FLAG

FAULT MODULE

DISABLE PWM A AND B

DCOMP– 4X

EXT GPIO– 4X

ACOMP – 7X

A FLAG

FAULT MODULE

DISABLE PWM A ONLY

B FLAG

FAULT MODULE

DISABLE PWM B ONLY

ALL_FAULT_EN

DPWM_EN

Bit0 in DPWMCTRL0

Bit 31 in DPWMFLTCTRL

Figure 20. Fault Mux Module

The Fault Mux Module provides a multitude of fault protection functions within the UCD3138x high-speed loop

(Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly configurable

fault generation based on digital comparators, high-speed analog comparators and external fault pins. Each of

the fault inputs to the DPWM modules can be configured to one or any combination of the fault events provided

in the Fault Mux Module.

Each one of the DPWM engines has four fault modules. The modules are called CBC fault module, AB fault

module, A fault module and B fault module.

The internal circuitry in all the four fault modules is identical, and the difference between the modules is limited to

the way the modules are attached to the DPWMs.

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FAULT FLAG

FAULT IN

FAULT MODULE

Figure 21. Fault Module

All fault modules provide immediate fault detection but only once per DPWM switching cycle. Each one of the

fault modules own a separate max_count and the fault flag will be set only if sequential cycle-by-cycle fault count

exceeds max_count.

Once the fault flag is set, DPWMs need to be disabled by DPWM_EN going low in order to clear the fault flags.

Please note, all four Fault Modules share the same DPWM_EN control, all fault flags (output of Fault Modules)

will be cleared simultaneously.

All four Fault Modules share the same global FAULT_EN as well. Therefore a specific Fault Module cannot be

enabled/ disabled separately.

FAULT - CBC

CLIM

CYCLE BY CYCLE

Figure 22. Cycle-By-Cycle Block

Unlike Fault Modules, only one Cycle by Cycle block is available in each DPWM module.

The Cycle by Cycle block works in conjunction with CBC Fault Module and enables DPWM reaction to signals

arriving from the Analog Peak current mode (PCM) module.

The Fault Mux Module supports the following basic functions:

•

4 digital comparators with programmable thresholds and fault generation

Configuration for 7 high speed analog comparators with programmable thresholds and fault generation

External GPIO detection control with programmable fault generation

Configurable DPWM fault generation for DPWM Current Limit Fault, DPWM Over-Voltage Detection Fault,

DPWM A External Fault, DPWM B External Fault and DPWM IDE Flag

•

Clock Failure Detection for High and Low Frequency Oscillator blocks

Discontinuous Conduction Mode Detection

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HFO/LFO

Fail Detect

DCM Detection

Analog Comparator 0

Control

Analog

Comparator 0

Digital Comparator 0

Control

Front End

Control 0

Analog Comparator 1

Control

Analog

Comparator 1

Digital Comparator 1

Control

Front End

Control 1

Analog Comparator 2

Control

Analog

Comparator 2

Digital Comparator 2

Control

Analog Comparator 3

Control

Analog

Comparator 3

Front End

Control 2

Digital Comparator 3

Control

Analog Comparator 4

Control

Analog

Comparator 4

fault[2:0]

External GPIO

Detection

Analog Comparator 5

Control

Analog

Comparator 5

DPWM 0

Fault Control

DPWM 1

Fault Control

DPWM 2

Fault Control

DPWM 3

Fault Control

Analog Comparator 6

Control

Analog

Comparator 6

DPWM 0

DPWM 1

DPWM 2

DPWM 3

Analog Comparator

Automated Ramp

Figure 23. Fault Mux Block Diagram

9.3.6 Communication Ports

9.3.6.1 SCI (UART) Serial Communication Interface

maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous

A

Receiver/Transmitter (UART) interfaces are included within the device for asynchronous start-stop serial data

communication (see the pin out sections for details). Each interface has a 24 bit pre-scaler for supporting

programmable baud rates, a programmable data word and stop bit options. Half or full duplex operation is

configurable through register bits. A loop back feature can also be setup for firmware verification. Both SCI-TX

and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being used.

9.3.6.2 PMBUS/I²C

The UCD3138x has two independent interfaces which both support PMBus and I²C in master and slave modes.

Only one of the interfaces has control of the address pin current sources as well as support for the optional

Control and Alert lines described in the PMBus specification. Other than these differences, the interfaces are

identical.

The PMBus/I²C interface is designed to minimize the processor overhead required for interface. It can

automatically detect and acknowledge addresses. It handles start and stop conditions automatically, and can

clock stretch until the processor has time to poll the PMBus status. It will automatically receive and send up to 4

bytes at a time. It can automatically verify and generate a PEC. This means that a write byte command can be

received by the processor with only one function call. There is no need for any interrupts at all with this

PMBus/I²C interface. If it is polled every few milliseconds, it will work perfectly.

The interface also supports automatic ACK of two independent addresses. If both PMBus/I²C interfaces are used

at the same time a total of 4 independent addresses can be automatically detected.

Example: PMBus Address Decode via ADC12 Reading

The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address decoding.

At power-up the device applies I_BIASto each address detect pin and the voltage on that pin is captured by the

internal 12-bit ADC.

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Vdd

AD00,

AD01

On/Off Control

I

BIAS

Resistor to

set PMBus

Address

To ADC Mux

Figure 24. PMBUS Address Detection Method

PMBus/I²C address 0x7E is a reserved address and should not be used in a system using the UCD3138x. This

address is used for manufacturing test.

9.3.6.3 SPI

The SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length

(1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used

for communication between the UCD3138x and external peripherals. Typical applications include an interface to

external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI EPROMs and

analog-to-digital converters. The SPI allows serial communication with other SPI devices through a 3-pin or 4-pin

mode interface. The SPI typically is configured as a master for communicating to external EEPROM.

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SCS

t_CSS

t_WH

t_WL

t_CSH

SCK

t_SU

t_H

MISO

MOSI

VALID IN

t_V

t_HO

VALID OUT

P_SCK

t_WH

t_WL

t_SU

t_H

t_V

t_HO

t_CSS

Period SCK

2 ICLK

1/2 P_SCK

2 ns (typical)

4 ns (typical)

2 ns (typical)

1 P_SCK

SCK High Time

SCK Low Time

Data in setup

Data in hold

Ouput Valid

Ouput Data Hold

Chip Select Setup

t_CSH

Chip Select Hold

1 P_SCK

Figure 25. SPI Timing Diagram

9.3.7 Real Time Clock

The UCD3138x has an internal real time clock (RTC) function that can track time in seconds, minutes, hours and

days. This function requires an external precision 10 MHz clock.

•

Firmware writable time/day register which tracks the total number of days.

–

The day counter will be able to count 4 years worth of days.

Years and months and leap year calculation must be calculated in firmware.

•

Firmware programmable frequency correction of ±200 ppm in 0.8 ppm steps

The RTC function can provide interrupts to the IRQ or FIQ at 1, 10, 30, and 60 second intervals.

The clock from the RTC driver can be driven to an external pin through an internal multiplexor

The clock for the RTC function can come from an external clock through a dedicated GPIO pin.

9.3.8 Timers

External to the Digital Power Peripherals there are 3 different types of timers in UCD3138x. They are the 24-bit

timer, 16-bit timer and the watchdog timer

9.3.8.1 24-Bit Timer

There is one 24 bit timer which runs off the Interface Clock. It can be used to measure the time between two

events, and to generate interrupts after a specific interval. Its clock can be divided down by an 8-bit pre-scalar to

provide longer intervals. The timer has two compare registers (Data Registers). Both can be used to generate an

interrupt after a time interval. . Additionally, the timer has a shadow register (Data Buffer register) which can be

used to store CPU updates of the compare events while still using the timer. The selected shadow register

update mode happens after the compare event matches.

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The two capture pins TCAP0 and TCAP1 are inputs for recording a capture event. A capture event can be set

either to rising, falling, or both edges of the capture pin signal. Upon this event, the counter value is stored in the

corresponding capture data register. Five Interrupts from the 24 bit timer can be set, which are the counter

rollover event (overflow), capture events 0 and 1, and the two comparison match events. Each interrupt can be

disabled or enabled.

9.3.8.2 16-Bit PWM Timers

There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a

8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for

generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register)

which can be used to store CPU updates of compare events while still using the timer. The selected shadow

register update mode happens after the compare event matches.

The counter reset can be configured to happen on a counter roll over, a compare equal event, or by a software

controlled register. Interrupts from the PWM timer can be set due to the counter rollover event (overflow) or by

the two comparison match events. Each comparison match and the overflow interrupts can be disabled or

enabled.

Upon an event comparison, the PWM pin can be configured to set, clear, toggle or have no action at the output.

The value of PWM pin output can be read for status or simply configured as General Purpose I/O for reading the

value of the input at the pin.

9.3.8.3 Watchdog Timer

A watchdog timer is provided on the device for ensuring proper firmware loop execution. The timer is clocked off

of a separate low speed oscillator source. If the timer is allowed to expire, a reset condition is issued to the ARM

processor. The watchdog is reset by a simple CPU write bit to the watchdog key register by the firmware routine.

On device power-up the watchdog is disabled. Yet after it is enabled, the watchdog cannot be disabled by

firmware. Only a device reset can put this bit back to the default disabled state. A half timer flag is also provided

for status monitoring of the watchdog.

9.3.9 General Purpose ADC12

The ADC12 is a 12 bit, high speed analog to digital converter, equipped with the following options:

•

Typical conversion speed of 267 ksps

Conversions can consist from 1 to 16 ADC channel conversions in any desired sequence

Post conversion averaging capability, ranging from 4X, 8X, 16X or 32X samples

Configurable triggering for ADC conversions from the following sources: firmware, DPWM rising edge,

ADC_EXT_TRIG pin or Analog Comparator results

•

Interrupt capability to embedded processor at completion of ADC conversion

Six digital comparators on the first 6 channels of the conversion sequence using either raw ADC data or

averaged ADC data

•

Two 10 µA current sources for excitation of PMBus addressing resistors

Dual sample and hold for accurate power measurement

Internal temperature sensor for temperature protection and monitoring

The control module (ADC12 Contol Block Diagram) contains the control and conversion logic for auto-

sequencing a series of conversions. The sequencing is fully configurable for any combination of 16 possible ADC

channels through an analog multiplexer embedded in the ADC12 block. Once converted, the selected channel

value is stored in the result register associated with the sequence number. Input channels can be sampled in any

desired order or programmed to repeat conversions on the same channel multiple times during a conversion

sequence. Selected channel conversions are also stored in the result registers in order of conversion, where the

result 0 register is the first conversion of a 16-channel sequence and result 15 register is the last conversion of a

16-channel sequence. The number of channels converted in a sequence can vary from 1 to 16.

Unlike EADC0 through EADC2, which are primarily designed for closing high speed compensation loops, the

ADC12 is not usually used for loop compensation purposes. The EADC converters have a substantially faster

conversion rate, thus making them more attractive for closed loop control. The ADC12 features make it best

suited for monitoring and detection of currents, voltages, temperatures and faults. Please see the Typical

Characteristics plots for the temperature variation associated with this function.

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ADC12 Block

ADC12 Registers

ADC

Averaging

12-bit SAR

ADC

S/H

ADC

Channels

ADC12

Control

Digital

Comparators

ADC Channel

ADC External Trigger (from pin)

Analog

Comparators

DPWM

Modules

Figure 26. ADC12 Control Block Diagram

9.3.10 Miscellaneous Analog

The Miscellaneous Analog Control (MAC) Registers are a catch-all of registers that control and monitor a wide

variety of functions. These functions include device supervisory features such as Brown-Out and power saving

configuration, general purpose input/output configuration and interfacing, internal temperature sensor control and

current sharing control.

The MAC module also provides trim signals to the oscillator and AFE blocks. These controls are usually used at

the time of trimming at manufacturing; therefore this document will not cover these trim controls.

9.3.11 Brownout

Brownout function is used to determine if the device supply voltage is lower than a threshold voltage, a condition

that may be considered unsafe for proper operation of the device.

The brownout threshold is higher than the reset threshold voltage; therefore, when the supply voltage is lower

than brownout threshold, it still does not necessarily trigger a device reset.

The brownout interrupt flag can be polled or alternatively can trigger an interrupt to service such case by an

interrupt service routine. Please see the Power On Reset (POR) / Brown Out Reset (BOR) section.

9.3.12 Global I/O

Up to 32 pins in UCD3138x can be configured in the Global I/O register to serve as a general purpose input or

output pins (GPIO). This includes all digital input or output pins except for the RESET pin.

The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins,

EADC analog input pins and the RESET pin. Additional digital pins not listed in this register can be configured

through their local configuration registers.

There are two ways to configure and use the digital pins as GPIO pins:

1. Through the centralized Global I/O control registers.

2. Through the distributed control registers in the specific peripheral that shares it pins with the standard GPIO

functionality.

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The Global I/O registers offer full control of:

1. Configuring each pin as a GPIO.

2. Setting each pin as input or output.

3. Reading the pin’s logic state, if it is configured as an input pin.

4. Setting the logic state of the pin, if it is configured as an output pin.

5. Connecting pin/pins to high rail through internal push/pull drivers or external pull up resistors.

The Global I/O registers include Global I/O EN register, Global I/O OE Register, Global I/O Open Drain Control

Register, Global I/O Value Register and Global I/O Read Register.

The following is showing the format of Global I/O EN Register (GLBIOEN) as an example:

BIT NUMBER

Bit Name

Access

31:0

GLOBAL_IO_EN

R/W

Default

0000_0000_0000_0000_0000_0000_0000_0000

Bits 29-0: GLOBAL_IO_EN – This register enables the global control of digital I/O pins

0 = Control of IO is done by the functional block assigned to the IO (Default)

1 = Control of IO is done by Global IO registers.

PIN NUMBER

BIT

PIN_NAME

UCD3138x

11

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

PWM2

PWM3

12

FAULT3

ADC_EXT_TRIG

TCK

55

14

45

TDO

46

TMS

48

TDI

47

SCI_TX1

SCI_TX0

SCI_RX1

SCI_RX0

TCAP0

37

35

38

36

49

PWM1

40

PWM0

39

TCAP1

13

I2C_DATA

PMBUS_CTRL

PMBUS_ALERT

EXT_INT

FAULT2

FAULT1

FAULT0

SYNC

20

18

17

42

54

44

43

8

34

7

DPWM3B

DPWM3A

DPWM2B

DPWM2A

DPWM1B

DPWM1A

DPWM0B

DPWM0A

29

6

28

5

27

4

26

3

25

2

24

1

23

0

22

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9.3.13 Temperature Sensor Control

Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities. The

internal temperature sensor is disabled by default.

Temperature

Calibration

ADC 12

Temperature

Sensor

CH15

Figure 27. Internal Temp Sensor

Temperature sensor is calibrated at room temperature (25 °C) via a calibration register value.

The temperature sensor is measured using ADC12 (via Ch15). The temperature is then calculated using a

mathematical formula involving the calibration register (this effectively adds a delta to the ADC measurement).

The temperature sensor can be enabled or disabled.

9.3.14 I/O Mux Control

I/O Mux Control register may be used in order to choose a single specific functionality that is desired to be

assigned to a physical device pin for your application. See the UCD3138x programmer's manual for details on

the available configurations.

9.3.15 Current Sharing Control

UCD3138x provides three separate modes of current sharing operation.

•

Analog bus current sharing

PWM bus current sharing

Master/Slave current sharing

AD02 has a special ESD protection mechanism that prevents the pin from pulling down the current-share bus

if power is missing from the UCD3138x

The simplified current sharing circuitry is shown in the drawing below. The digital pulse connected to SW3

transforms SW3 into a pulse-width-modulated current source. Details on the frequency and resolution of this

feature are in the digital power fusion peripherals manual.

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3.3 V

I_SHARE

SW3

Digital

3.3 V

3.3V

ESD

AD13

ESD

3.2 kΩ

400 Ω

250 Ω

AD02

SW2

SW1

ESD

250 Ω

EXT CAP

R_SHARE

ADC12 and

CMP

ADC12 and

CMP

Figure 28. Simplified Current Sharing Circuitry

FOR TEST ONLY,

ALWAYS KEEP 00

CURRENT SHARING MODE

CS_MODE

EN_SW1

EN_SW2

DPWM

Off or Slave Mode (3-state)

PWM Bus

00

00 (default)

0

1

0

1

0

01

10

11

ACTIVE

Off or Slave Mode (3-state)

Analog Bus or Master

0

The period and the duty of 8-bit PWM current source and the state of the SW1 and SW2 switches can be

controlled through the current sharing control register (CSCTRL).

9.3.16 Temperature Reference

The temperature reference register (TEMPREF) provides the ADC12 count when ADC12 measures the internal

temperature sensor (channel 15) during the factory trim and calibration.

This information can be used by different periodic temperature compensation routines implemented in the

firmware. But it should not be overwritten by firmware, otherwise this factory written value will be lost until the

device is reset.

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9.4 Device Functional Modes

9.4.1 DPWM Modes Of Operation

The DPWM is a complex logic system which is highly configurable to support several different power supply

topologies. The discussion below will focus primarily on waveforms, timing and register settings, rather than on

logic design.

The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts over

again.

The DPWM logic causes transitions in many digital signals when the period counter hits the target value for that

signal.

9.4.1.1 Normal Mode

In Normal mode, the Filter output determines the pulse width on DPWM A. DPWM B fits into the rest of the

switching period, with a dead time separating it from the DPWM A on-time. It is useful for buck topologies,

among others. Here is a drawing of the Normal Mode waveforms:

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Device Functional Modes (continued)

Normal Mode Closed Loop

Start of Period

Period

Period Counter

Filter controlled edge

DPWM Output A

Event 1

Filter Duty (High Resolution)

Cycle Adjust A (High Resolution)

Adaptive Sample Trigger A

Adaptive Sample Trigger B

Sample Trigger 1

Blanking A Begin

To Other

Modules

Blanking A End

DPWM Output B

Event 3 – Event 2 (High Res)

Event 4 (High Res)

Sample Trigger 2

Blanking B Begin

Blanking B End

Phase Trigger

To Other

Modules

Events which change with DPWM mode:

DPWM A Rising Edge = Event 1

DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A

Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or

Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register

DPWM B Rising Edge = Event 1 + Filter Duty + Cycle Adjust A + (Event 3 – Event 2)

DPWM B Falling Edge = Event 4

Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B

Begin, Blanking B End

Figure 29. Normal Mode - Closed Loop

Cycle adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be

used for functions like current balancing. The Adaptive Sample Triggers can be used to sample in the middle of

the on-time (for an average output), or at the end of the on-time (to minimize phase delay) The Adaptive Sample

Register provides an offset from the center of the on-time. This can compensate for external delays, such as

MOSFET and gate driver turn on times.

Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning

of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges

are dynamic, so blanking is more difficult.

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Device Functional Modes (continued)

Cycle Adjust B has no effect in Normal Mode.

9.4.1.2 Phase Shifting

In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The phase

shift signal has two possible sources. It can come from the Phase Trigger Register. This provides a fixed value,

which is useful for an application like interleaved PFC.

The phase shift value can also come from the filter output. In this case, the changes in the filter output causes

changes in the phase relationship of two DPWM modules. This is useful for phase shifted full bridge topologies.

The following figure shows the mechanism of phase shift:

Phase Shift

DPWM0 Start of Period

Period Counter

DPWM1 Start of Period

Period Counter

Phase Trigger = Phase Trigger Register value or Filter Duty

Figure 30. Phase Shifting

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Device Functional Modes (continued)

9.4.1.3 DPWM Multiple Output Mode

Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral

to drive two phases with the same pulse width, but with a time offset between the phases, and with different

cycle adjusts for each phase.

The Multi-Mode diagram is shown in Figure 31.

Multi Mode Closed Loop

Start of Period

Period

Period Counter

Filter controlled edge

DPWM Output A

Event 1

Filter Duty (High Resolution)

Cycle Adjust A (High Resolution)

Adaptive Sample Trigger A

Adaptive Sample Trigger B

Sample Trigger 1

Blanking A Begin

To Other

Modules

Blanking A End

DPWM Output B

Event 3 (High Resolution)

Filter Duty (High Resolution)

Cycle Adjust B (High Resolution)

Sample Trigger 2

Blanking B Begin

Blanking B End

To Other

Modules

Phase Trigger

Events which change with DPWM mode:

DPWM A Rising Edge = Event 1

DPWM A Falling Edge = Event 1 + Filter Duty + Cycle Adjust A

Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register or

Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register

DPWM B Rising Edge = Event 3

DPWM B Falling Edge = Event 3 + Filter Duty + Cycle Adjust B

Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B

Begin, Blanking B End

Figure 31. DPWM Multi-Mode Close Loop

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Device Functional Modes (continued)

Event 2 and Event 4 are not relevant in Multi mode.

DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse

width operation is possible. DPWMA cannot cross over the period boundary.

Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking

this rising edge.

And, of course, Cycle Adjust B is usable on DPWM B.

9.4.1.4 DPWM Resonant Mode

This mode provides a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the

switching frequency changes, the dead times between the pulses remain the same.

The equations for this mode are designed for a smooth transition from PWM mode to resonant mode, as

described in the LLC Example section. Here is a diagram of this mode:

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Device Functional Modes (continued)

Resonant Symmetrical Closed Loop

Start of Period Start of Period

Filter Period

Period Counter

Filter controlled edge

DPWM Output A

Event 1

Filter Duty – Average Dead Time

Adaptive Sample Trigger A

Adaptive Sample Trigger B

Sample Trigger 1

Blanking A Begin

To Other

Modules

Blanking A End

DPWM Output B

Event 3 - Event 2

Period Register – Event 4

Sample Trigger 2

Blanking B Begin

Blanking B End

Phase Trigger

To Other

Modules

Events which change with DPWM mode:

Dead Time 1 = Event 3 – Event 2

Dead Time 2 = Event 1 + Period Register – Event 4)

Average Dead Time = (Dead Time 1 + Dead Time 2)/2

DPWM A Rising Edge = Event 1

DPWM A Falling Edge = Event 1 + Filter Duty – Average Dead Time

Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register

Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register

DPWM B Rising Edge = Event 1 + Filter Duty – Average Dead Time + (Event 3 – Event 2)

DPWM B Falling Edge = Filter Period – (Period Register – Event 4)

Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin,

Blanking B End

Figure 32. DPWM Resonant Symmetrical Mode

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Device Functional Modes (continued)

The Filter has two outputs, Filter Duty and Filter Period. In this case, the Filter is configured so that the Filter

Period is twice the Filter Duty. So if there were no dead times, each DPWM pin would be on for half of the

period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both

DPWM pins. Therefore, both pins will have the same on-time, and the dead times will be fixed regardless of the

period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. This is the

only edge for which the blanking signals can be used easily.

9.4.2 Triangular Mode

Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM

pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode,

only DPWM-B is available. Here is a diagram for Triangular Mode:

Triangular Mode Closed Loop

Start of Period

Period

Start of Period

Period Counter

DPWM Output A

Sample Trigger 1

Blanking A Begin

Blanking A End

To Other

Modules

Filter controlled edge

DPWM Output B

Cycle Adjust A (High Resolution)

Cycle Adjust B (High Resolution)

Filter Duty/2 (High Resolution)

Period/2

Sample Trigger 2

Blanking B Begin

Blanking B End

To Other

Phase Trigger

Modules

Events which change with DPWM mode:

DPWM A Rising Edge = None

DPWM A Falling Edge = None

Adaptive Sample Trigger = None

DPWM B Rising Edge = Period/2 - Filter Duty/2 + Cycle Adjust A

DPWM B Falling Edge = Period/2 + Filter Duty/2 + Cycle Adjust B

Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B

Begin, Blanking B End

Figure 33. Triangular Mode

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Device Functional Modes (continued)

All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not

needed. It is very easy to put a fixed sample trigger exactly in the center of the FET on-time, because the center

of the on-time does not move in this mode.

9.4.3 Leading Edge Mode

Leading edge mode is similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the

rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge

stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the Leading Edge Mode:

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Device Functional Modes (continued)

Leading Edge Closed Loop

Start of Period

Period

Period Counter

DPWM Output A

Event 1

Filter Duty (High Resolution)

Cycle Adjust A (High Resolution)

Adaptive Sample Trigger A

Adaptive Sample Trigger B

Sample Trigger 1

Blanking A Begin

To Other

Modules

Blanking A End

DPWM Output B

Event 2 - Event 3 (High Resolution)

Event 4 (High Resolution)

Sample Trigger 2

Blanking B Begin

Blanking B End

Phase Trigger

To Other

Modules

Events which change with DPWM mode:

DPWM A Falling Edge = Event 1

DPWM A Rising Edge = Event 1 - Filter Duty + Cycle Adjust A

Adaptive Sample Trigger A = Event 1 - Filter Duty + Adaptive Sample Register or

Adaptive Sample Trigger B = Event 1 - Filter Duty/2 + Adaptive Sample Register

DPWM B Rising Edge = Event 4

DPWM B Falling Edge = Event 1 - Filter Duty + Cycle Adjust A -(Event 2 – Event 3)

Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B

Begin, Blanking B End

Figure 34. Leading Edge Mode

As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are

mainly useful for the edges at the beginning and end of the period.

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9.5 Register Maps

9.5.1 CPU Memory Map And Interrupts

When the device comes out of power-on-reset, the data memories are mapped to the processor as follows:

9.5.1.1 Memory Map (After Reset Operation)

ADDRESS

SIZE (BYTES)

MODULE

0x0000_0000 – 0x0003_FFFF

In 32 repeated blocks of 8 k each

32 X 8 k

Boot ROM

0x0004_0000 – 0x0004_7FFF

0x0004_8000 – 0x0004_FFFF

0x0005_0000_0x0005_7FFF

0x0006_9800 – 0x0006_9FFF

0x0006_A000 – 0x0006_BFFF

32 k

2 k

Program Flash 0

Program Flash 1

Program Flash 2

Program Flash 3

Data Flash

8 k

Data RAM

9.5.1.2 Memory Map (Normal Operation)

Just before the boot ROM program gives control to flash program, the ROM configures the memory as follows:

ADDRESS

SIZE (BYTES)

MODULE

Boot ROM

0x0002_0000 – 0x0002_1FFF

0x0000_0000 – 0x00000_07FFF

0x0000_8000 – 0x08000_0FFFF

0x0000_8000 - 0x10000_17FFF

0x0000_8000 - 0x18000_1FFFF

0x0006_9800 – 0x0006_9FFF

0x0006_A000 – 0x0006_BFFF

8 k

32 k

2 k

Program Flash 0 (or 1)

Program Flash 1 (or 0)

Program Flash 2 (or 0 for UCD3138128 only)

Program Flash 3 (or 1 for UCD3138128 only)

Data Flash

8 k

Data RAM

9.5.1.3 Memory Map (System And Peripherals Blocks)

ADDRESS

SIZE

256

MODULE

Loop Mux

0x0012_0000 - 0x0012_00FF

0x0013_0000 - 0x0013_00FF

0x0014_0000 - 0x0014_00FF

0x0015_0000 - 0x0015_00FF

0x0016_0000 - 0x0016_00FF

0x0017_0000 - 0x0017_00FF

0x0018_0000 - 0x0018_00FF

0x0019_0000 - 0x0019_00FF

0x001A_0000 - 0x001A_00FF

0x001B_0000 – 0x001B_00FF

0x001C_0000 - 0x001C_00FF

0x001D_0000 - 0x001D_00FF

0x001E_0000 - 0x001E_00FF

0xFFF7_E400 - 0xFFF7_34FF

0xFFF7_EC00 - 0xFFF7_ECFF

0xFFF7_ED00 - 0xFFF7_EDFF

0xFFF7_F000 - 0xFFF7_F0FF

0xFFF7_F600 - 0xFFF7_F6FF

0xFFF7_F700 - 0xFFF7_F7FF

Fault Mux

ADC

DPWM 3

Filter 2

DPWM 2

Front End/Ramp Interface 2

Filter 1

DPWM 1

Front End/Ramp Interface 1

Filter 0

DPWM 0

Front End/Ramp Interface 0

RTC

UART 0

UART 1

Miscellaneous Analog Control

PMBus/I²C Interface (1)

PMBus/I²C Interface (2)

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ADDRESS

SIZE

256

23

MODULE

GIO

0xFFF7_FA00 - 0xFFF7_FAFF

0xFFF7_FD00 - 0xFFF7_FDFF

0xFFFF_FD00 - 0xFFFF_FDFF

0xFFFF_FE00 - 0xFFFF_FEFF

0xFFFF_FF20 - 0xFFFF_FF37

0xFFFF_FFD0 - 0xFFFF_FFEC

Timer

MMC

DEC

CIM

28

SYS

The registers and bit definitions inside the System and Peripheral blocks are detailed in the programmer’s

manuals.

9.5.2 Boot ROM

The device incorporates a 8 kB boot ROM. This boot ROM includes support for:

•

Program download through the PMBus

Device initialization

Examining and modifying registers and memory

Verifying and executing program flash automatically

Jumping to a customer defined boot program

Checksum evaluation to support using the program flash as a single 64 kB block or as 2-32 kB blocks.

The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on

the program flash. If the first 2 kB of program FLASH 0 has a valid checksum, the program branches to location

0 in Program FLASH 0. This permits the use of a custom boot program. If the first checksum fails, it performs

some additional checksum calculations to determine where the valid program is located. This permits full

automated program memory checking, when there is no need for a custom boot program. The complete decision

tree is located in Figure 35. Additionally, the part can support two separate programs in block 0 and block 1

through a custom boot-flash routine.

Device Reset

Does PFLASH 0 have a

BRANCH instruction at the

beginning?

Yes

No

Is there a valid checksum on

the first 2 kB of PFLASH 0,

all 32 kB of PFLASH 0,

all 64 kB of PFLASH 0 & 1?

Yes

No

Stay in ROM

BRANCH to

Program Flash 0

Figure 35. Check Sum Evaluation Flowchart, 64 kB

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Device Reset

Does PFLASH 0 have a

BRANCH instruction at the

beginning?

Yes

No

Is there a valid checksum on

the first 2 kB of PFLASH 0,

all 32 kB of PFLASH 0,

all 64 kB of PFLASH 0 & 1

or 128 kB of PFLASH 0, 1, 2 and 3?

Does PFLASH 2 have a

BRANCH instruction at the

beginning?

Yes

No

Yes

Is there a valid checksum on

all 64 kB of PFLASH 2 &3?

Yes

No

BRANCH to

Stay in ROM

Program Flash 0

BRANCH to

Program Flash 2

Figure 36. Check Sum Evaluation Flowchart, 128 kB

If none of the checksums are valid, the Boot ROM stays in control, and accepts commands via the PMBus

interface. These functions can be used to read and write to all memory locations in the device. Typically they are

at address 11 and are used to download a program to Program Flash, and to command its execution.

9.5.3 Customer Boot Program

As described above, it is possible to generate a user boot program using 2 kB or more of the Program Flash.

This can support things which the Boot ROM does not support, including:

•

Program download via UART – useful especially for applications where the UCD3138A64 or UCD3138128 is

isolated from the host (e.g., PFC)

•

Encrypted download – useful for code security in field updates.

PMBus download at different addresses

Different command formats

9.5.4 Flash Management

The device offers a variety of features providing for easy prototyping and easy flash programming. At the same

time, high levels of security are possible for production code, even with field updates. Standard firmware will be

provided for storing multiple copies of system parameters in data flash. This minimizes the risk of losing

information if data-flash programming is interrupted.

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9.6 Synchronous Rectifier MOSFET Ramp And IDE Calculation

The device has built in logic for optimizing the performance of the synchronous rectifier MOSFETs. This comes in

two forms:

•

Synchronous Rectifier MOSFET ramp for softly turning on and off the MOSFETs

Ideal Diode Emulation (IDE) calculation

When starting up a power supply, It is not uncommon for there to already be a voltage present on the output –

this is called pre-bias. It can be very difficult to calculate the ideal synchronous rectifier MOSFET on-time for this

case. If it is not calculated correctly, it may pull down the pre-bias voltage, causing the power supply to sink

current. To avoid this, the synchronous rectifier MOSFETs are not turned on until after the power supply has

ramped up to the nominal output voltage. The synchronous rectifier MOSFETs are then turned on slowly in order

to avoid an output voltage glitch. The synchronous rectifier MOSFET ramp logic can be used to turn them on at a

rate well below the bandwidth of the filter.

In discontinuous mode, the ideal on-time for the synchronous rectifier MOSFETs is a function of V_in, V_out, and the

primary side duty cycle (D). The IDE logic in the UCD3138x takes V_inand V_outdata from the firmware and

combines it with D data from the filter hardware. It uses this information to calculate the ideal on-time for the

synchronous rectifier MOSFETs.

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10 Applications and Implementation

10.1 Application Information

The UCD3138x has an extensive set of fully-programmable, high-performance peripherals that make it suitable

for a wide range of power supply applications. In order to make the part easier to use, TI has prepared an

extensive set of materials to demonstrate the features of the device for several key applications. In each case the

following items are available:

1. Full featured EVM hardware that demonstrates classic power supply functionality.

2. An EVM user guide that contains schematics, bill-of-materials, layout guidance and test data showcasing the

performance and features of the device and the hardware.

3. A firmware programmers manual that provides a step-by-step walk through of the code.

Table 3. Application Information

APPLICATION

EVM DESCRIPTION

This EVM demonstrates a PSFB DC-DC power converter with digital control using the UCD3138x device. Control is

implemented by using PCMC with slope compensation. This simplifies the hardware design by eliminating the need

for a series blocking capacitors and providing the inherent input voltage feed-forward that comes from PCMC. The

controller is located on a daughter card and requires firmware in order to operate. This firmware, along with the entire

source code, is made available through TI. A free, custom function GUI is available to help the user experiment with

the different hardware and software enabled features. The EVM accepts a DC input from 350 VDC to 400 VDC, and

outputs a nominal 12 VDC with full load output power of 360 W, or full output current of 30 A.

Phase shifted full

bridge

This EVM demonstrates an LLC resonant half-bridge DC-DC power converter with digital control using the

UCD3138x device. The controller is located on a daughter card and requires firmware in order to operate. This

firmware, along with the entire source code, is made available through TI. A free, custom function GUI is available to

help the user experiment with the different hardware and software enabled features. The EVM accepts a DC input

from 350 VDC to 400 VDC, and outputs a nominal 12 VDC with full load output power of 340 W, or full output current

of 29 A.

LLC resonant

converter

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10.2 Typical Application

This section summarizes the PSFB EVM DC-DC power converter.

L1

T1

Q7

+12V

Q6

Q5

C1

RL

VBUS

I_pri

PRIM

ORING

CTL

CURRENT

T2

VOUT

C2

R2

D1

T1

QT2

QB2

QT1

VA

Lr

Current

Sensing

QB1

D2

Vref

DPWM0

DPWM0B

DPWM1B

Duty for mode

switching

Vout

CPCC

<

EADC0

EADC1

CLA0

DPWM1

DPWM2

Iout

CLA1

DPWM2A

DPWM2B

Load Current

DPWM3A

DPWM3B

I_pri

EADC2

PCM

DPWM3

AD00

AD01

ISOLATED

GATE Transformer

ACFAIL_IN

FAULT0

FAULT1

FAULT2

SYNCHRONOUS

GATE DRIVE

ACFAIL_OUT

FAILURE

AD02/CMP0

AD03/CMP1/CMP2

AD04/CMP3

AD05/CMP4

AD06/CMP5

AD07/CMP6

AD08

I_SHARE

Vout

FAULT

UCD3138

GPIO1

GPIO2

GPIO3

ORING_CRTL

ON/OFF

Iout

I_pri

CBC

temp

P_GOOD

Vin

VA

WD

ARM7

AD09

PMBus

UART0

RST

OSC

Primary

UART1

Memory

Figure 37. Phase-Shifted Full-Bridge

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Typical Application (continued)

10.2.1 Design Requirements

Table 4. Input Characteristics

PARAMETER

CONDITIONS

MIN

TYP

MAX UNIT

ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.

V_in

Input voltage range

Max input voltage

Input current

Normal Operating

Continuous

350

385

420

V

V_inmax

I_in

Vin=350V, Full Load

1.15

30

A

I_stby

V_on

V_hys

Input no load current Output current is 0A

mA

V

V_inDecreasing (input voltage is detected on secondary side)

340

360

Under voltage lockout

V_inIncreasing

V

Table 5. Output Characteristics

PARAMETER

CONDITIONS

MIN

TYP

MAX UNIT

ALL SPECIFICATIONS at Vin=400V and 25°C AMBIENT UNLESS OTHERWISE NOTED.

V_O

Output voltage setpoint

Line regulation

No load on outputs

12

V

Reg_line

All outputs; 360 ≤ V_in≤ 420; I_O= I_Omax

All outputs; 0 ≤ I_O≤ I_Omax; V_in= 400 V

5Hz to 20 MHz

0.5

1

%

Reg_load

Load regulation

Ripple and noise⁽¹⁾

V_n

I_O

η

100

mVpp

A

Output current

0

30

Efficiency at phase-shift mode

Efficiency at PWM ZVS mode

Efficiency at hard switching mode

Output adjust range

Vo = 12 V, Io = 15 A

93%

90%

η

V_adj

11.4

12.6

V

Transient response

overshoot/undershoot

V_tr

50% Load Step at 1AµS, min load at 2A

±0.36

t_settling

t_start

Transient response settling time

Output rise time

100

50

µS

mS

%

10% to 90% of Vout

At Startup

Overshoot

2

fs

Switching frequency

Current sharing accuracy

Loop phase margin

Loop gain margin

Over V_inand I_Oranges

50% - full load

150

±5

kHz

%

I_share

φ

10% - Full load

45

degree

dB

G

10

(1) Ripple and noise are measured with 10µF Tantalum capacitor and 0.1µF ceramic capacitor across output.

10.2.2 Detailed Design Procedure

10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration

Overview

The hardware configuration of the UCD3138x PCMC PSFB converter contains two critical elements that are

highlighted in the subsequent sections.

•

DPWM initialization - This section will highlight the key register settings and considerations necessary for the

UCD3138x to generate the correct MOSFET waveforms for this topology. This maintains the proper phase

relationship between the MOSFETs and synchronous rectifiers as well as the proper set up required to

function correctly with PCMC.

•

PCMC initialization - This section will discuss the register settings and hardware considerations necessary to

modulate the DPWM pins with PCMC and internal slope compensation.

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10.2.2.2 DPWM Initialization for PSFB

The UCD3138x DPWM peripheral provides flexibility for a wide range of topologies. The PSFB configuration

utilizes the Intra-Mux and Edge Generation Modules of the DPWM. For a diagram showing these modules, see

the UCD3138x Digital Power Peripherals Manual.

Here is a schematic of the power stage of the PSFB:

L1

T1

VOUT

Q6

VBUS

I_pri

PRIM

CURRENT

Q5

T2

R2

D1

D2

QT2

QB2

QT1

QB1

Lr

T1

ISOLATED

GATE Transformer

SYNCHRONOUS

GATE DRIVE

Figure 38. Schematic – PSFB Power Stage

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Here is an overview of the key PSFB signals:

3 A – QB1

( DPWM1C)

3 B – QT1

( DPWM2C)

2 A – QT2

( EDGEGEN)

X1

Y3

2 B – QB2

( EDGEGEN)

X3

Y2

Transformer

Voltage

X2

1 B –

QSYN 1,3

Y1

0 B –

QSYN 2,4

DPWM3AF

DPWM3BF

DPWM 2AF

DPWM 2BF

Current

Peak Level

X1, X2 ,X3 and Y1 , Y2 , Y3 are sets of moving edges

All other edges are fixed .

Figure 39. Key PSFB Signals

10.2.2.3 DPWM Synchronization

DPWM1 is synchronized to DPWM0, DPWM2 is synchronized to DPWM1, and DPWM3 is synchronized to

DPWM2, ½ period out of phase using these commands:

Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //configured to slave

Dpwm2Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm3Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; // configured to slave

Dpwm0Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm1Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

Dpwm2Regs.DPWMPHASETRIG.all = PWM_SLAVESYNC;

LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0; // Slave to dpwm-0

LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 1; // Slave to dpwm-1

LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2; // Slave to dpwm-2

If the event registers on the DPWMs are the same, the two pairs of signals will be symmetrical. All code

examples are taken from the PSFB EVM code, unless otherwise stated.

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10.2.2.4 Fixed Signals to Bridge

The two top signals in the above drawing have fixed timing. The DPWM1CF and DPWM2CF signals are used for

these pins. DPWMCxF refers to the signal coming out of the fault module of DPWMx, as shown inFigure 40.

Figure 40. Fixed Signals to Bridge

These signals are actually routed to pins DPWM3A and 3B using the Intra Mux with these statements:

Dpwm3Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 7; // Send DPWM1C

Dpwm3Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 8; // Send DPWM2C

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Since these signals are really being used as events in the timer, the #defines are called EV5 and EV6. Here are

the statements which initialize them:

// Setup waveform for DPWM-C (re-using blanking B regs)

Dpwm2Regs.DPWMBLKBBEG.all = PWM2_EV5 + (4 *16);

Dpwm2Regs.DPWMBLKBEND.all = PWM2_EV6;

Period End

Controlled by DPWM1 Blanking register

Period Start

Blank B Begin

Blank B End

3 A – QB1

Even 6

Even 5

( DPWM1C)

3 B – QT1

Even 6

Even 5

( DPWM 2C)

Blank B Begin

Blank B End

Controlled by DPWM2 Blanking register

Figure 41. Blank B Timing Information

The statements for DPWM1 are the same. Remember that DPWMC reuses the Blank B registers for timing

information.

10.2.2.5 Dynamic Signals to Bridge

DPWM0 and 1 are set at normal mode. PCMC triggering signal (fault) chops DPWM0A and 1A cycle by cycle.

The corresponding DPWM0B and 1B are used for synchronous rectifier MOSFET control. The same PCMC

triggering signal is applied to DPWM2 and DPWM3. Both of these are set to normal mode as well. DPWM2 and

3 are chopped and their edges are used to generate the next two dynamic signals to the bridge. They are

generated using the Edge Generator Module in DPWM2. The Edge Generator sources are DPWM2 and

DPWM3. The edges used are:

DPWM2A turned on by a rising edge on DPWM2BF

DPWM2A turned off by a falling edge on DPWM3AF

DPWM2B turned on by a rising edge on DPWM3BF

DPWM2B turned off by a falling edge on DPWM2AF

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Period Start

Period End

3 A – QB1

( DPWM 1C)

3 B – QT1

( DPWM 2C)

2 A – QT2

( EDGEGEN )

2 B – QB2

( EDGEGEN )

Y3

X3

1A

1 B –

QSYN 1,3

Y2

Y1

X2

0A

0 B –

QSYN 2,4

X1

DPWM 3AF

DPWM 3BF

DPWM 2AF

DPWM 2BF

Current

Peak Level

Chopping point

X1 , X2 , X3 and Y1 , Y2 , Y3 are sets of moving edges

All other edges are fixed .

Figure 42. Dynamic Signals to Bridge

The Edge Generator is configured with these statements:

Dpwm2Regs.DPWMEDGEGEN.bit.A_ON_EDGE = 2;

Dpwm2Regs.DPWMEDGEGEN.bit.A_OFF_EDGE = 5;

Dpwm2Regs.DPWMEDGEGEN.bit.B_ON_EDGE = 6;

Dpwm2Regs.DPWMEDGEGEN.bit.B_OFF_EDGE = 1;

Dpwm2Regs.DPWMCTRL0.bit.PWM_A_INTRA_MUX = 1; // EDGEGEN-A out the A output

Dpwm2Regs.DPWMCTRL0.bit.PWM_B_INTRA_MUX = 1; // EDGEGEN-B out the B output

Dpwm2Regs.DPWMEDGEGEN.bit.EDGE_EN = 1;

The EDGE_EN bits are set for all 4 DPWMs. This is done to ensure that all signals have the same timing delay

through the DPWM.

The finial 6 gate signals are shown in Figure 43.

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Period Start

Period End

3 A – QB1

( DPWM 1C)

3 B – QT1

( DPWM 2C)

2 A – QT2

( EDGEGEN )

2 B – QB2

( EDGEGEN )

Y3

X3

1 B –

QSYN 1,3

Y2

Y1

X2

X1

0 B –

QSYN 2,4

Peak Level

Current

Chopping point

Figure 43. Final 6 Gate Signals

Note how the falling edge of DPWM2AF aligns with the X1 edge, and how the rising edge of DPWM2BF aligns

with the X3 edge. The falling edges on DPWM2AF and DPWM3AF are caused by the peak detection logic. This

is fed through the Cycle By Cycle logic. The Cycle By Cycle logic also has a special feature to control the rising

edges of DPWM2BF (X1 and X3) and DPWM3BF (Y1 and Y3). It uses the value of Event3 – Event2 to control

the time between the edges. The same feature is used with DPWM0 and DPWM1 to control the X2 and Y2

signals. Using the other 2 DPWMs permits these signals to have a different dead time.

The same setup can be used for voltage mode control. In this case, the Filter output sets the timing of the falling

edge on DPWMxAF.

All DPWMs are configured in Normal mode, with CBC enabled. If external slope compensation is used,

DPWM1A and DPWM1B are used to reset the external compensator at the beginning of each half cycle. If no

PCMC event occurs, the values of Events 2 and 3 determine the locations of the edges, just as in open loop

mode.

10.2.3 System Initialization for PCM

PCM (Peak Current Mode) is a specialized configuration for the UCD3138x which involves several peripherals.

This section describes how it works across the peripherals.

10.2.3.1 Use of Front Ends and Filters in PSFB

All three front ends are used in PSFB. The same signals are used in the same places for both PCMC and

voltage mode. The same hardware can be used for both control modes, with the mode determined by which

firmware is loaded into the device. FE0 and FE1 are used with their associated filters, but Filter 2 is not used at

all.

FE0 – Vout – voltage loop

FE1 – Iout – current loop

FE2 – Ipri – PCM

In PCMC mode, FE2 is used for PCMC, and the voltage loop is normally used to provide the start point for the

compensation ramp. If the CPCC firmware detects a need for constant current mode, it switches to the current

loop for the start point.

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10.2.3.2 Peak Current Detection

Peak current detection involves all the major modules of the DPPs, the Front End, Filter, Loop Mux, Fault Mux

and the DPWMs. A drawing of the major elements is shown in Figure 44.

Ipri

PCM

Comparator

Loop

Mux

Fault

Mux

DPWM

Voltage Loop

Filter

Loop

Mux

Ramp

Module

Loop

Mux

Vout

Front

End

Figure 44. Peak Current Detection Function

All signals without arrows flow from left to right. The voltage loop is used to select a peak current level. This level

is fed to the Ramp module to generate a compensation ramp. The compensation ramp is compared to the

primary current by the PCMC comparator in the Front End. When the ramp value is greater than the primary

current, the APCMC signal is sent to the DPWM, causing the events described in the previous sections.

The DPWM frame start and output pin signals can be used to trigger the Ramp Module. In this case, unlike in the

case of other ramp module functions, each DPWM frame triggers the start of the ramp. The ramp steps every 32

ns.

The Filter is configured normally, there is no real difference for PCMC. The PCM_FILTER_SEL bits in the

LoopMux.PCMCTRL register are used to select which filter is connected to the ramp module:

LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL =0; //select filter0

With Firmware Constant Power/Constant current, Filter 1 and Front End 1 are used as a current control loop,

with the EADCDAC set to high current. If the voltage loop value becomes higher than the current loop value,

then Filter 1 is used to control the PCM ramp start value:

LoopMuxRegs.PCMCTRL.bit.PCM_FILTER_SEL =1;

S P A C E //select filter1 for slope compensation source

In the ramp module, there are 2 bitfields in the RAMPCTRL register which must be configured. The

PCM_START_SEL must be set to a 1 to enable the Filter to be used as a ramp start source. The RAMP_EN bit

must be set, of course.

The DAC_STEP register sets the slope of the compensation ramp. The DAC value is in volts, of course, so it is

necessary to calculate the slope after the current to voltage conversion. Here is the formula for converting from

millivolts per microsecond to DACSTEP.

m = compensation slope in millivolts per microsecond

ACSTEP = 335.5 × M

In C, this can be written:

#define COMPENSATION_SLOPE 150 //compensation slope in millivolts per microsecond

#define DACSTEP_COMP_VALUE ((int) (COMPENSATION_SLOPE*335.5) )

S P A C E //value in DACSTEP for desired compensation slope

S P A C E FeCtrl0Regs.DACSTEP.all = DACSTEP_COMP_VALUE;

It may also be necessary to set a ramp ending value in the RAMPDACEND register.

66

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In addition, it is necessary to set the D2S_COMP_EN bit in the EADCCTRL register. This is for enabling the

differential to single ended comparator function. The front end diagram leaves it out for simplicity, but the

connection between the DAC and the EADC amplifier is actually differential. The PCMC comparator, however, is

single ended. So a conversion is necessary as shown in Figure 45.

AFE_GAIN

2^3-AFE_GAIN

6 bit ADC

8mV/LSB

EAP0

2^AFE_GAIN

EAN0

Signed 9 bit result

(error) 1 mV /LSB

EADC

X

Averaging

SAR/Prebias

Ramp

Filter x

CPCC

DAC0

10 bit DAC

1.5625mV/LSB

Σ

Value

Differential to

Single Ended

Dither

4 bit dithering gives 14 bits of effective resolution

97.65625μV/LSB effective resolution

Absolute Value

Calculation

10 bit result

1.5625mV/LSB

Peak Current

Detected

Peak Current Mode

Comparator

Figure 45. Differential to Single-Ended Comparator Function

The EADC_MODE bit in EADCCTRL should be set to a 5 for peak current mode.

The peak current detection signal next goes to the Loop Mux. The Fault Mux has only 1 APCM input, but there

are 3 front ends. So the PCM_FE_SEL bits in APCMCTRL must be used to select which front end is used:

LoopMuxRegs.APCMCTRL.bit.PCM_FE_SEL = 2; // use FE2 for PCM */

The PCM_EN bit must also be set.

LoopMuxRegs.APCMCTRL.bit.PCM_EN = 1; // Enable PCM

Next the Fault Mux is used to enable the APCM bit to the CLIM/CBC signal to the DPWM. There are 4

DPWMxCLIM registers, one for each DPWM. The ANALOG_PCM_EN bit must be set in each one to connect the

PCM detection signal to the CLIM/CBC signal on each DPWM. For the latest configuration information on all of

these bits, consult the appropriate EVM firmware. To avoid errors, it is best to configure your hardware design

using the same DPWMs, filters, and front ends for the same functions as the EVM.

DPWM timing is used to trigger the start of the ramp. This is selected by the FECTRLxMUX registers in the Loop

Mux. DPWMx_FRAME_SYNC_EN bits, when set, cause the ramp to be triggered at the start of the DPWM

period.

10.2.3.3 Peak Current Mode (PCM)

There is one peak current mode control module in the device however any front end can be configured to use

this module.

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10.2.4 Application Curves

30A Load

syncFETs off

1A-16A-1A

Vin =385V

Figure 47. V_OUTSoft Start

Figure 46. Load Transient

Kp =14000

Ki =300

Kd =2000

Alpha = –2

Figure 48. Bode Plot

68

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11 Power Supply Recommendations

•

Both 3.3 VD and 3.3 VA should have a local 4.7 µF capacitor placed as close as possible to the device pins

•

BP18 should have a 1 µF capacitor.

12 Layout

12.1 IC Grounding and Layout Guidelines

•

Two grounds are recommended: AGND (analog) and DGND (digital)

–

AGND plane should be just large enough to connect to all required components.

Power ground (PGND) can be independent or combined with DGND

The power pad of the driver IC should be tied to DGND

•

RSVD must be tied to BP18.

All analog signal filter capacitors should be tied to AGND

–

If the gate driver device, such as UCD27524 or UCD27511/7 driver is used, the filter capacitor for the

current sensing pin can be tied to DGND for easy layout

•

All digital signals, such as GPIO, PMBus and PWM are referenced to DGND.

The RESET pin capacitor (0.1 µF) should be connected to DGND. If the RESET pin is unused it is

recommended to tie the pin to 3.3 V through 220 Ω.

•

All filter and decoupling capacitors should be placed close to UCD3138x as possible

–

Resistor placement is less critical and can be moved a little further away

The DGND and AGND net-short resistor MUST be placed right between one UCD3138x’s DGND pin and one

AGND pin. Ground connections to the net short element should be made by a large via (or multiple paralleled

vias) for each terminal of the net-short element.

•

If a gate driver device such as UCC27524 or UCC27511/7 is on the control card and there is a PGND

connection, a net-short resistor should be tied to the DGND plane and PGND plane by multiple vias. In

addition the net-short element should be close to the driver IC.

Configure all unused GPIO as inputs and connect them to ground. Alternatively unused GPIOs can be

configured to outputs and set to a logic level of 0.

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12.2 Layout Examples

Figure 49. Layout Example

70

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Layout Examples (continued)

UCD3138A64/UCD3138128

Figure 50. Layout Example

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13 Device and Documentation Support

13.1 Device Support

13.1.1 Development Support

The application firmware for the UCD3138x is developed on Texas Instruments Code Composer Studio (CCS)

integrated development environment.

Device programming, real time debug and monitoring/configuration of key device parameters for certain power

topologies are all available through Texas Instruments’ FUSION_DIGITAL_POWER_DESIGNER Graphical User

Interface (http://www.ti.com/tool/fusion_digital_power_designer). The FUSION_DIGITAL_POWER_DESIGNER

software application uses the PMBus protocol to communicate with the device over a serial bus using an

interface adaptor known as the USB-TO-GPIO, available as an EVM from Texas Instruments

(http://www.ti.com/tool/usb-to-gpio). PMBUS-based real-time debug capability is available through the ‘Memory

Debugger’ tool within the Device GUI module of the FUSION_DIGITAL_POWER_DESIGNER GUI, which

represents a powerful alternative over traditional JTAG-based approaches’.

The software application can also be used to program the devices, with a version of the tool known as

FUSION_MFR_GUI optimized for manufacturing environments (http://www.ti.com/tool/fusion_mfr_gui). The

FUSION_MFR_GUI tool supports multiple devices on a board, and includes built-in logging and reporting

capabilities.

13.2 Documentation Support

13.2.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 6. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

UCD3138A64

UCD3138128

Click here

13.2.2 Related Documentation

In terms of reference documentation, the following programmer’s manuals are available offering detailed

information regarding the application and usage of UCD3138x digital controller:

1. UCD3138064 or UCD3138128 Programmer's Manual

2. UCD3138 Digital Power Peripheral Programmer's Manual Key topics covered in this manual include:

–

Digital Pulse Width Modulator (DPWM)

–

Modes of Operation (Normal/Multi/Phase-shift/Resonant etc)

Automatic Mode Switching

DPWMC, Edge Generation & Intra-Mux

–

Front End

–

Analog Front End

Error ADC or EADC

Front End DAC

Ramp Module

Successive Approximation Register Module

–

Filter

–

Filter Math

Loop Mux

–

Analog Peak Current Mode

72

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–

Constant Power/Constant Current (CPCC)

Automatic Cycle Adjustment

–

Fault Mux

–

Analog Comparators

Digital Comparators

Fault Pin functions

DPWM Fault Action

Ideal Diode Emulation (IDE), DCM Detection

Oscillator Failure Detection

–

Register Map for all of the above peripherals in UCD3138A64 or UCD3138128

3. UCD3138 Monitoring and Communications Programmer’s Manual

Key topics covered in this manual include:

–

ADC12

–

Control, Conversion, Sequencing & Averaging

Digital Comparators

Temperature Sensor

PMBUS Addressing

Dual Sample & Hold

–

Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating)

PMBUS Interface

General Purpose Input Output (GPIO)

Timer Modules

PMBus

Register Map for all of the above peripherals in UCD3138A64

4. UCD3138 ARM and Digital System Programmer’s Manual

Key topics covered in this manual include:

–

Boot ROM & Boot Flash

–

BootROM Function

Memory Read/Write Functions

Checksum Functions

Flash Functions

Avoiding Program Flash Lock-Up

–

ARM7 Architecture

–

Modes of Operation

Hardware/Software Interrupts

Instruction Set

Dual State Inter-working (Thumb 16-bit Mode/ARM 32-bit Mode)

–

Memory & System Module

–

Address Decoder, DEC (Memory Mapping)

Memory Controller (MMC)

Central Interrupt Module

Register Map for all of the above peripherals in UCD3138A64 or UCD3138128

5. FUSION_DIGITAL_POWER_DESIGNER for UCD31XX Isolated Power Applications – User Guide

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13.2.2.1 References

1. UCD3138064 Programmer’s Manual (Literature Number: SLUUAD8 )

2. UCD3138 Digital Power Peripherals Programmer’s Manual (Literature Number:SLUU995)

3. UCD3138 Monitoring & Communications Programmer’s Manual (Literature Number:SLUU996)

4. UCD3138 ARM and Digital System Programmer’s Manual (Literature Number:SLUU994)

5. FUSION_DIGITAL_POWER_DESIGNER for Isolated Power Applications (Literature Number: SLUA676)

6. Code Composer Studio Development Tools v3.3 – Getting Started Guide, (Literature Number: SPRU509H)

7. ARM7TDMI-S Technical Reference Manual

8. System Management Bus (SMBus) Specification

9. PMBus™ Power System Management Protocol Specification

10. UCD3138128 Programmers Manual (Literature Number: SLUUB54)

In addition to the tools and documentation described above, for the most up to date information regarding

evaluation modules, reference application firmware and application notes/design tips, please visit

http://www.ti.com/product/UCD3138A64.

13.3 Trademarks

PMBus is a trademark of SMIF, Inc.

All other trademarks are the property of their respective owners.

13.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

6-Sep-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCD3138128PFCR

UCD3138A64PFCR

TQFP

PFC

80

1000

330.0

24.4

15.0

1.5

20.0

24.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Sep-2014

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

UCD3138128PFCR

UCD3138A64PFCR

TQFP

PFC

80

1000

367.0

45.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996

PFC (S-PQFP-G80)

PLASTIC QUAD FLATPACK

0,27

0,17

M

0,50

60

0,08

41

40

61

80

21

0,13 NOM

1

20

Gage Plane

9,50 TYP

12,20

SQ

11,80

0,25

14,20

SQ

0,05 MIN

0°–7°

13,80

0,75

0,45

1,05

0,95

Seating Plane

0,08

1,20 MAX

4073177/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	UCD3138128_15
厂家：	TEXAS INSTRUMENTS
描述：	UCD3138x Highly-Integrated Digital Controller For Isolated Power CD
文件：	总80页 (文件大小：2743K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCD3138128_15 [TI]

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