UCD7242MRSJREP [TI]
数字双路同步降压功率驱动器，UCD7242-EP | RSJ | 32 | -55 to 125;
| 型号： | UCD7242MRSJREP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 数字双路同步降压功率驱动器，UCD7242-EP | RSJ | 32 | -55 to 125 驱动 CD 开关 驱动器 |
| 文件： | 总34页 (文件大小：1813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
数字双路同步降压功率驱动器
查询样片: UCD7242-EP
1
特性
•
•
•
具有针对双路同步降压转换器的驱动器的全集成电
源开关
支持国防、航空航天、和医疗应用
•
受控基线
同一组装和测试场所
一个制造场所
完全兼容 TI 整合数字电源 (Fusion Digital Power)
控制器，如 UCD92xx 系列
•
•
•
•
•
•
宽输入电压范围：4.75V 至 18V
运行低至具有一个外部偏置电源的 2.2V 输入
每通道高达 10A 输出电流
支持军用（-55°C 至 125°C）温度范围
延长的产品生命周期
•
•
•
•
•
•
•
延长的产品变更通知
工作开关频率 2 MHz
产品可追溯性
具有电流限值标记的高侧电流限值
来自 VIN 的板载经稳压 6V 驱动器电源
过热保护
T
MON
V
IN
PWM-B
SRE-B
FLT-B
PWM-A
SRE-A
FLT-A
热感测输出 - 电压与芯片温度成比例
欠压闭锁 (UVLO) 和过压闭锁 (OVLO) 确保适当的
驱动电压
V
DIS
GG
•
•
符合 RoHS 环保标准
I
-A
I
-B
MON
MON
精确的芯片上电流感测 (±5%)
BST-A
BST-B
应用范围
BSW-A
SW-A
BSW-B
SW-B
•
•
数控同步降压功率级
针对台式机、服务器、电信和笔记本处理器的高电
流双相位电压调整模块和企业级降压稳压器
(VRM/EVRD) 稳压器
PGND
PGND
GND BP3
V
GG
说明
UCD7242 是一款可驱动两个独立降压电源的完整电源系统（请见 图 1）。 在一个单片解决方案中完全集成高侧金
属氧化物半导体场效应晶体管 (MOSFET)，低侧 MOSFET，驱动器，电流感测电路以及必要的保护功能，以最大
限度地减小尺寸和提高效率。 驱动器电路可在同步降压电路中为高侧 NMOS 开关和低侧 NMOS 同步整流器提供
高充电及放电电流。 MOSFET 栅极可由内部经稳压 VGG 电源驱动至 +6.25V 电压。 可禁用内部 VGG 稳压器，以
允许用户提供一个独立的栅极驱动电压。 这种高灵活性支持 2.2V 至 18V 宽电源转换输入电压范围。内部欠压闭锁
(UVLO) 逻辑可在允许芯片工作之前确保 VGG 良好。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
版权 © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SLVSBY2
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
说明（继续）
同步整流器使能 (SRE) 引脚在 PWM 信号为低电平时控制低侧 MOSFET 是否打开。 当 SRE 为高电平时，此部件
针对所有负载以连续传导模式运行。 在这个模式下，此驱动逻辑模块使用脉宽调制 (PWM) 信号来控制高侧与低侧
栅极驱动信号。 还优化了死区时间以防止交叉传导。 当 SRE 为低电平时，此部件在轻负载时运行在断续传导模式
下。 在这个模式下，低侧 MOSFET 始终保持关闭。
板载比较器监控流经高侧开关的电流，以保护功率级不受突发高电流负载的影响。 针对高侧比较器设置消隐延迟，
以避免与开关边沿噪声同时发生故障报告。 如果发生过流故障，高侧 FET 被关闭并且故障标志 (FLT) 被置为有效
以警告控制器。
由一个高精度集成电流感测元件测量和监控 MOSFET 电流。 这个方法在大多数负载范围内提供 ±5% 的精度。
IMON 引脚上的控制器可使用这个被放大的信号。
一个片载温度感测将芯片温度转换为供控制器使用的 TMON 上的电压。 如果芯片温度超过 170°C，此温度传感器发
起一个暂停输出切换的热关断并且将 FLT 标志置位。 当芯片温度下降到低于热滞后频带时，正常运行恢复。
VIN
VIN
VIN
TMON
30
31
32
19
27
28
29
VIN
UCD7242
PWM-B
SRE-B
FLT-B
PWM-A
SRE-A
FLT-A
1
2
9
26
25
18
Thermal
Sense
Drive
Logic
Drive
Logic
VIN
VGG
Generator
IMON-B
BST-B
IMON-A
BST-A
Current
Sense
Processor
Current
Sense
Processor
7
3
20
24
VIN
VIN
BSW-B
SW-B
BSW-A
SW-A
4
23
14
Driver
Driver
Driver
Driver
VOUT-B
VOUT-A
13
PGND
PGND
10
11
12
15
16
17
VDD LDO
8
21
GND
6
22
VGG DIS BP3
5
Testmode
VGG
Short
图 1. 典型应用电路和方框图
2
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
ORDERING INFORMATION
ORDERABLE PART
TOP SIDE
MARKING
TJ
PIN COUNT
SUPPLY
PACKAGE
VID NUMBER
NUMBER
–55°C to 125°C
32-pin
UCD7242MRSJREP
Reel of 2500
QFN
UCD7242EP
V62/14601-01XE
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
RATING
–0.3 to 20
VALUE
VIN
Supply voltage
V
V
V
V
V
V
V
V
V
DC
AC(2)
–0.3 to SW + 7
BST
Boot voltage
34
VGG, VGG_DIS
BP3
Gate supply voltage
Logic supply voltage
7
4
DC
AC(2)
–2 to VIN + 1
34
SW, BSW
Switch voltage
TMON, IMON, Testmode
Analog outputs
Digital I/O’s
–0.3 to 3.6
–0.3 to 5.5
PWM-A, PWM-B, SRE-A,
SRE-B, FLT-A, FLT-B
TJ
Junction temperature
–55 to 150
–55 to 150
2000
°C
°C
V
Tstg
Storage temperature
ESD rating
HBM: Human Body model
CDM: Charged device model
500
V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive
into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of
packages.
(2) AC levels are limited to within 5 ns.
THERMAL INFORMATION
UCD7242-EP
THERMAL METRIC(1)
RSJ
32 PINS
40.7
17.8
12
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
°C/W
ψJT
0.1
ψJB
11.9
0.3
θJCbot
(1) 有关传统和全新热度量的更多信息，请参阅 IC 封装热度量 应用报告 （文献号：ZHCA543）。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的规定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环
境热阻抗。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI 标准 G30-
88 中找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结至电路板的热阻。
(5) 结至顶部的特征参数，( ψJT)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
(6) 结至电路板的特征参数，(ψJB)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI
标准 G30-88 中找到了内容接近的说明。
间距
Copyright © 2013, Texas Instruments Incorporated
3
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
2.2
TYP
12
MAX
UNIT
V
VIN
VIN
VGG
TJ
Power input voltage (internally generated VGG
)
18
18
Power input voltage (externally generated VGG
Externally supplied gate drive voltage
Operating junction temperature range
Switching frequency
)
12
V
4.75
–55
300
6.2
V
125
°C
kHz
fs
750
2000
ELECTRICAL CHARACTERISTICS
VIN = 12V; 1μF from BP3 to GND, 0.22μF from BST to BSW, 4.7μF from VGG to PGND, TA = TJ = –55°C to 125°C (unless
otherwise noted)
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
SUPPLY SECTION
Outputs not switching, VIN = 2.2 V,
PWM(INH) = LOW, SRE(INL) = HIGH,
VGG_DIS = HIGH, VGG = 5V
6
6
mA
mA
Supply current
Outputs not switching, VIN = 18 V,
PWM(INH) = LOW, SRE(INL) = HIGH,
VGG_DIS = LOW
GATE DRIVE UNDER VOLTAGE LOCKOUT
VGG
UVLO ON
BP3 Rising
BP3 Falling
4.0
3.8
V
V
UVLO OFF
UVLO hysteresis
200
mV
VGG SUPPLY GENERATOR
VGG
VIN = 7 to 18 V
5.2 6.25
6.8
V
VGG drop out
VIN = 4.75 to 7 V, IVGG < 50 mA
850
mV
BP3 SUPPLY VOLTAGE
BP3
IDD = 0 to 10 mA
3.14
3.3 3.45
V
INPUT SIGNAL (PWM, SRE)
VIH
VIL
Positive-going input threshold voltage
2.1
1.2
2.3
1.9
V
V
Negative-going input threshold voltage
3-state Condition
1
1.4
V
tHLD_R 3-state hold-off time
VPWM = 1.65 V
VPWM = 5.0 V
VPWM = 3.3 V
VPWM = 0 V
275
133
66
–66
1
ns
IPWM
Input current
Input current
μA
μA
VSRE = 5.0 V
VSRE = 3.3 V
VSRE = 0 V
ISRE
1
1
VGG DISABLE (VGG_DIS)
Input resistance to AGND
VGG_DIS
45
100
550
150
1.6
kΩ
V
Threshold
Hysteresis
1.35
mV
FAULT FLAG (FLT)
FLT Output High Level
FLT Output Low Level
IOH = 2 mA
IOL = –2 mA
2.7
V
V
0.6
4
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V; 1μF from BP3 to GND, 0.22μF from BST to BSW, 4.7μF from VGG to PGND, TA = TJ = –55°C to 125°C (unless
otherwise noted)
PARAMETER
TEST CONDITION
MIN TYP MAX UNIT
CURRENT LIMIT
Over current threshold
12
15 18.5
80
A
Tfault_HS delay until HS FET off(1)
Tfault_FF delay until FLT asserted(1)
Propagation delay from PWM to reset FLT(1) 1st falling edge of PWM without a fault event
ns
ns
ns
ns
100
100
High side blanking time(1)
CURRENT SENSE AMPLIFIER
Gain
Over currents during this period will not be detected
60
IMON/ IOUT, (see Figure 14 )
17
5
20
26 μA/A
Bandwidth(1)
kHz
THERMAL SENSE
Thermal shutdown(1)
170
20
°C
°C
Thermal shutdown hysteresis(1)
Temperature Sense T(1)
Temperature Sense T Offset(1)
POWER MOSFETS
Gain, TJ = –20°C to 125°C
10
mV/°C
mV
TJ = 0°C, –100 μA ≤ ITMON ≤ 100 μA
470
Propagation delay from PWM to switch node
going high
32
ns
High side MOSFET RDS(ON)
15.5
6.5
5
mΩ
mΩ
Low side MOSFET RDS(ON)
High side MOSFET turn on – Dead Time(1)
Low side MOSFET turn on – Dead Time(1)
10
11
ns
ns
6
(1) As designed and characterized. Not 100% tested in production. These specifications apply for –40°C ≤ TJ ≤ 125°C.
Copyright © 2013, Texas Instruments Incorporated
5
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
DEVICE INFORMATION
PINOUT
PINOUT
(TOP VIEW)
PINOUT
(BOTTOM VIEW)
29
30
31 32
27 28
32 31
30
29
28 27
VIN
VIN
1
2
3
4
5
6
7
8
9
26
26
25
24
23
22
21
20
19
18
PWM_A
PWM_B
SRE_B
BST_B
BSW_B
VGG
1
2
3
4
5
6
7
8
9
25 SRE_A
24 BST_A
Special
6mm x 6mm
QFN
BSW_A
BP3
23
22
21
20
19
18
VGG_DIS
Pkg Code: RSJ
AGND
IMON_A
TMON
IMON_B
testmode
FLT_A
PGND
FLT_B
PGND
10 11
12
13
14
15
16 17
17 16
15
14
13
12
11 10
PIN FUNCTIONS
UCD7242 –BUCK POWER STAGE
FUNCTION
High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A
QFN
PIN NAME I/O
Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of
the high side MOSFET and the low side MOSFET when SRE-B is high.
1
PWM-B
I
PWM = high
PWM = low
PWM = 1.65 V
HS = off, LS = off
HS = off, LS = off
SRE = high
SRE = low
HS = on, LS = off
HS = on, LS = off
HS = off, LS = on
HS = off, LS = off
Synchronous Rectifier Enable input for the B-channel. High impedance digital input capable of
accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate
anti-cross-conduction delay is used during synchronous mode.
2
SRE-B
I
Connection for the B-channel charge pump capacitor that provides a floating supply for the high side
driver. Connect a 0.22μF ceramic capacitor from this pin to BSW-B (pin 4).
3
4
BST_B
BSW-B
I
I
Connection for B-channel charge pump capacitor. Internally connected to SW-B.
Gate drive voltage for the power MOSFETs. For VIN ≥ 4.75V, the internal VGG generator can be used.
For VIN < 4.75 V, this pin should be driven from an external bias supply. When externally driven,
VGG_DIS must be tied to VGG. In all cases, bypass this pin with a 4.7μF (min), 10V (min) ceramic
capacitor to PGND.
5
6
VGG
I/O
I
When tied to VGG, disables the on-chip VGG generator to allow gate drive voltage to be supplied from
an external source. This is required when VIN is < 4.75V. To use the internal VGG generator, tie to
GND.
VGG_DIS
MOSFET current sense monitor output. Provides a current source output that is proportional to the
current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
7
8
IMON-B
O
I
testmode
Test mode only. Tie to GND.
6
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
PIN FUNCTIONS (continued)
UCD7242 –BUCK POWER STAGE
QFN
PIN NAME I/O
FUNCTION
Fault flag for the B-channel. This signal is a 3.3V digital output which is latched high when the current
in the B-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor will initiate a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
9
FLT-B
O
10, 12, 15, 17
11, 16
PGND
NC
–
–
Shared power ground return for the buck power stage
No internal connection. It is recommended that these pins be tied to PGND.
Switching node of the B-channel buck power stage and square wave input to the buck inductor.
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
13
14
SW-B
SW-A
–
–
Switching node of the A-channel buck power stage and square wave input to the buck inductor.
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
Fault flag for the A-channel. This signal is a 3.3V digital output which is latched high when the current
in the A-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor initiates a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
18
FLT-A
O
Temperature sense pin. The voltage on this pin is proportional to the die temperature. The gain is
10mV/°C. At TJ = 0°C, the output voltage has an offset of 0.47V. When the die temperature reaches
the thermal shutdown threshold, this pin is pulled to BP3 and the power FETs are switched off. When
the die temperature falls below the thermal hysteresis band, the FLT flag clears and normal operation
resumes.
19
20
TMON
O
O
MOSFET current sense monitor output. Provides a current source output that is proportional to the
current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
IMON -A
21
22
23
24
GND
BP3
–
O
–
Analog ground return.
Output of internal 3.3V LDO regulator for powering internal logic circuits. Bypass this pin with 1μF
(min) to GND. This LDO is supplied by the VGG pin.
BSW-A
BST-A
Connection for A-channel charge pump capacitor. Internally connected to SW-A.
Connection for the A-channel charge pump capacitor that provides a floating supply for the high side
driver. Connect a 0.22μF ceramic cap from this pin to BSW-A (pin 23).
–
Synchronous Rectifier Enable input for the A-channel. High impedance digital input capable of
accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate
anti-cross-conduction delay is used during synchronous mode.
25
SRE-A
I
I
High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A
Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of
the high side MOSFET and the low side MOSFET when SRE-A is high.
26
PWM -A
PWM = high
PWM = low
PWM = 1.65 V
HS = off, LS = off
HS = off, LS = off
SRE = high
SRE = low
HS = on, LS = off
HS = on, LS = off
HS = off, LS = on
HS = off, LS = off
27, 29, 30, 32
28, 31
VIN
NC
–
–
Input Voltage to the buck power stage and driver circuit
No internal connection. It is recommended that these pins be tied to VIN.
Copyright © 2013, Texas Instruments Incorporated
7
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
90
85
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 8 V
s I
O
O
O
O
O
= 3.3 V, f = 750 kHz, V = 8 V
s
I
= 3.3 V, f = 1 MHz, V = 8 V
80
75
s
I
= 2 V, f = 500 kHz, V = 8 V
s
I
= 2 V, f = 750 kHz, V = 8 V
s
I
V
V
= 2 V, f = 1 MHz, V = 8 V
s I
O
= 1.2 V, f = 500 kHz, V = 8 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 8 V
s I
= 1.2 V, f = 1 MHz, V = 8 V
s
I
0
2
4
6
8
10
Load - A
Figure 2.
UCD7242
3
2.5
2
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 8 V
s I
O
O
O
O
O
= 3.3 V, f = 750 kHz, V = 8 V
s
I
= 3.3 V, f = 1 MHz, V = 8 V
s
I
= 2 V, f = 500 kHz, V = 8 V
s
I
= 2 V, f = 750 kHz, V = 8 V
s
I
V
V
= 2 V, f = 1 MHz, V = 8 V
s I
O
= 1.2 V, f = 500 kHz, V = 8 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 8 V
s I
= 1.2 V, f = 1 MHz, V = 8 V
s
I
1.5
1
0.5
0
0
2
4
6
8
10
Load - A
Figure 3.
8
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
90
85
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 10 V
s I
O
O
O
O
O
80
75
70
= 3.3 V, f = 750 kHz, V = 10 V
s
I
= 3.3 V, f = 1 MHz, V = 10 V
s
I
= 2 V, f = 500 kHz, V = 10 V
s
I
= 2 V, f = 750 kHz, V = 10 V
s
I
V
V
= 2 V, f = 1 MHz, V = 10 V
s I
O
= 1.2 V, f = 500 kHz, V = 10 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 10 V
s I
= 1.2 V, f = 1 MHz, V = 10 V
s
I
0
2
4
6
8
10
Load - A
Figure 4.
UCD7242
3
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 10 V
s I
O
O
O
O
O
= 3.3 V, f = 750 kHz, V = 10 V
s
I
= 3.3 V, f = 1 MHz, V = 10 V
s
I
2.5
2
= 2 V, f = 500 kHz, V = 10 V
s
I
= 2 V, f = 750 kHz, V = 10 V
s
I
V
V
= 2 V, f = 1 MHz, V = 10 V
s I
O
= 1.2 V, f = 500 kHz, V = 10 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 10 V
s I
= 1.2 V, f = 1 MHz, V = 10 V
s
I
1.5
1
0.5
0
0
2
4
6
8
10
Load - A
Figure 5.
Copyright © 2013, Texas Instruments Incorporated
9
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
90
85
80
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 12 V
s I
O
O
O
O
O
= 3.3 V, f = 750 kHz, V = 12 V
s
I
75
70
65
= 3.3 V, f = 1 MHz, V = 12 V
s
I
= 2 V, f = 500 kHz, V = 12 V
s
I
= 2 V, f = 750 kHz, V = 12 V
s
I
V
V
= 2 V, f = 1 MHz, V = 12 V
s I
O
= 1.2 V, f = 500 kHz, V = 12 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 12 V
s I
= 1.2 V, f = 1 MHz, V = 12 V
s
I
0
2
4
6
8
10
Load - A
Figure 6.
UCD7242
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 12 V
s I
3
O
O
O
O
O
= 3.3 V, f = 750 kHz, V = 12 V
s
I
= 3.3 V, f = 1 MHz, V = 12 V
s
I
= 2 V, f = 500 kHz, V = 12 V
s
I
2.5
2
= 2 V, f = 750 kHz, V = 12 V
s
I
V
V
= 2 V, f = 1 MHz, V = 12 V
s I
O
= 1.2 V, f = 500 kHz, V = 12 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 12 V
s I
= 1.2 V, f = 1 MHz, V = 12 V
s
I
1.5
1
0.5
0
0
2
4
6
8
10
Load - A
Figure 7.
10
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242
90
85
80
75
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 14 V
s I
O
O
O
O
O
= 3.3 V, f = 750 kHz, V = 14 V
s
I
= 3.3 V, f = 1 MHz, V = 14 V
s
I
70
65
60
= 2 V, f = 500 kHz, V = 14 V
s
I
= 2 V, f = 750 kHz, V = 14 V
s
I
V
V
= 2 V, f = 1 MHz, V = 14 V
s I
O
= 1.2 V, f = 500 kHz, V = 14 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 14 V
s I
= 1.2 V, f = 1 MHz, V = 14 V
s
I
0
2
4
6
8
10
Load - A
Figure 8.
UCD7242
V
V
V
V
V
= 3.3 V, f = 500 kHz, V = 14 V
s I
O
O
O
O
O
= 3.3 V, f = 750 kHz, V = 14 V
3
s
I
= 3.3 V, f = 1 MHz, V = 14 V
s
I
= 2 V, f = 500 kHz, V = 14 V
s
I
= 2 V, f = 750 kHz, V = 14 V
s
I
2.5
2
V
V
= 2 V, f = 1 MHz, V = 14 V
s I
O
= 1.2 V, f = 500 kHz, V = 14 V
O
O
O
s
I
V
V
= 1.2 V, f = 750 kHz, V = 14 V
s I
= 1.2 V, f = 1 MHz, V = 14 V
s
I
1.5
1
0.5
0
0
2
4
6
8
10
Load - A
Figure 9.
Copyright © 2013, Texas Instruments Incorporated
11
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
UCD7242 1 Rail Operating
50
f
= 2000 kHz
s
f
40
30
20
10
0
= 1500 kHz
s
f
= 1000 kHz
s
f
= 500 kHz
s
f
= 0 kHz
s
4
4.5
5
5.5
6
6.5
V
- V
GG
Figure 10. VGG Supply Current with 1 Rail Operating and 1 Rail Off
UCD7242 2 Rail Operating
f
= 2000 kHz
= 1500 kHz
s
f
80
s
60
40
f
= 1000 kHz
s
f
= 500 kHz
s
20
0
f
= 0 kHz
s
4
4.5
5
5.5
6
6.5
V
- V
GG
Figure 11. VGG Supply Current with 2 Rails Operating
12
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
TYPICAL CHARACTERISTICS (continued)
Inductor used in the following plots is a 0.47μH BI Technologies inductor (HM72A). All data taken at room ambient.
Continuous Operation at IOUT = 10A
10
7
5
T
= 150°C
J
3
2
T
= 140°C
J
T
J
= 130°C
= 120°C
T
J
1
0
T
= 110°C
70
J
20
30
50
100
Duty Cycle - %
Figure 12.
Figure 12 shows the mean time to failure (MTTF) for an output load current of 10A on a single output, or an
output load current of 10A on both outputs.
Copyright © 2013, Texas Instruments Incorporated
13
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
DETAILED DESCRIPTION
PWM INPUT
The PWM input pin accepts the digital signal from the controller that represents the desired high-side FET on
time. This input is designed to accept 3.3V logic levels, but is also tolerant of 5V input levels. The SRE pin sets
the behavior of the PWM pin. When the SRE pin is asserted high, the device is placed in synchronous mode. In
this mode, the timing duration of the high-side gate drive and the low-side gate drive are both controlled by the
PWM input signal. When PWM is high, the high-side MOSFET is on and the low-side MOSFET is off. When
PWM is low, the high-side MOSFET is off and the low-side MOSFET is on. An optimized anti-cross-conduction
delay is introduced to ensure the proper FET is turned off before the other FET is turned on. When the SRE pin
is asserted low, the device is placed in non-synchronous mode. In this mode the PWM input only controls the
high-side MOSFET. When PMW is high, the high-side MOSFET is on. The low side FET is always held off.
The PWM input supports a 3-state detection feature. It can detect if the PWM input signal has entered a 3-state
mode. When 3-state mode is detected, both the high-side and low-side MOSFETs are held off. To support this
mode, the PWM input pin has an internal pull-up resistor of approximately 50kΩ to 3.3V and a 50kΩ pull-down
resistor to ground. During normal operation, the PWM input signal swings below 0.8V and above 2.5V. If the
source driving the PWM pin enters a 3-state or high impedance state, the internal pull-up/pull down resistors will
tend to pull the voltage on the PWM pin to 1.65V. If the voltage on the PWM pin remains within the 0.8V to 2.5V
3-state detection band for longer than tHLD_R, 3-state detection hold-off time, then the device enters 3-state mode
and turns both MOSFETs off. This behavior occurs regardless of the state of the SRE pin. When exiting 3-state
mode, PWM should first be asserted low and SRE High. This ensures that the bootstrap capacitor is recharged
before attempting to turn on the high-side FET. The logic threshold of this pin typically exhibits 900mV of
hysteresis to provide noise immunity and ensure glitch-free operation.
SRE INPUT
The SRE (Synchronous Rectifier Enable) pin is a high impedance digital input. It is designed to accept 3.3V logic
levels, but is also tolerant of 5V levels. When asserted high, the operation of the low-side synchronous rectifier
FET is enabled. The state of the low-side MOSFET is governed by the PWM input. When SRE is asserted low,
the low-side FET is continuously held low, keeping the FET off. While held off, current flow in the low-side FET is
restricted to its intrinsic body diode. The logic threshold of this pin typically exhibits 900mV of hysteresis to
provide noise immunity and ensure glitch-free operation.
VIN
VIN supplies power to the internal circuits of the device. The input power is conditioned by an internal linear
regulator that provides the VGG gate drive voltage. A second regulator that operates off of the VGG rail produces
an internal 3.3V supply that powers the internal analog and digital functional blocks. The VGG regulator produces
a nominal 6.2V. The output of the VGG regulator is monitored by the Under-Voltage Lock Out (UVLO) circuitry.
The device will not attempt to produce gate drive pulses until the VGG voltage is above the UVLO threshold. This
ensures that there is sufficient voltage available to drive the power FETs into saturation when switching activity
begins. To use the internal VGG regulator, VIN should be at least 4.7V. When performing power conversion with
VIN values less than 4.7V, the gate drive voltage must be supplied externally. (See VGG and VGG DIS sections
for details.)
VGG
The VGG pin is the gate drive voltage for the high current gate driver stages. For VIN ≥ 4.75V, the internal VGG
generator can be used. For VIN < 4.75 V, this pin should be driven from an external bias supply. When using the
internal regulator, the VGG_DIS pin should be tied low. When using an external VGG, VGG_DIS must be tied to
VGG. Current is drawn from the VGG supply in fast, high-current pulses. A 4.7μF ceramic capacitor (10V
minimum) should be connected from the VGG pin to the PGND pin as close as possible to the package. Whether
internally or externally supplied, the voltage on the VGG pin is monitored by the ULVO circuitry. The voltage must
be higher than the UVLO threshold before power conversion can occur. The average current drawn from the VGG
supply is dependant on the switching frequency, the absolute value of VGG and the total gate charge of the power
FETs inside the device.
14
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
VGG_DIS
This pin, when asserted high, disables the on-chip VGG linear regulator. When tied low, the VGG linear regulator
is used to derive VGG from VIN. This pin is designed to be permanently tied high or low depending on the power
architecture being implemented. It is not intended to be switched dynamically while the device is in operation.
SW
The SW pin is the switching node of the power conversion stage. When configured as a synchronous buck, the
voltage swing on SW normally traverses from slightly below ground to above VIN. Parasitic inductance in the
high-side FET conduction path and the output capacitance (Coss) of the low side FET form a resonant circuit
than can produce high frequency ( > 100MHz) ringing on this node. The voltage peak of this ringing will exceed
VIN. Care must be taken not to exceed the maximum voltage rating of this pin. The main areas available to
impact this amplitude are: the driver voltage magnitude (VGG) and the parasitic source and return paths for the
MOSFET (VIN, PGND). In some cases, a series resistor and capacitor snubber network connected from this pin
to PGND can be helpful in damping the ringing and decreasing the peak amplitude. In general this should not be
necessary due to the integrated nature of this part.
BST
The BST pin provides the drive voltage for the high-side FET. A bootstrap capacitor is connected from this pin to
the BST-SW node. Internally, a diode connects the BST pin to the VGG supply. In normal operation, when the
high side FET is off and the low-side FET is on, the SW node is pulled to ground and, thus, holds one side of the
bootstrap capacitor at ground potential. The other side of the bootstrap capacitor is clamped by the internal diode
to VGG. The voltage across the bootstrap capacitor at this point is the magnitude of the gate drive voltage
available to switch-on the high-side FET. The bootstrap capacitor should be a low ESR ceramic type, a minimum
value of 0.22μF is recommended.
In order to ensure that the bootstrap capacitor has sufficient time to recharge, the steady-state duty cycle must
not exceed what is shown in Figure 13. The curve in Figure 13 is for CBST= 0.22µF. Different values of CBST will
have different DMAX limitations.
96
94
92
90
88
86
0.6
0.8
1
1.2
1.4
1.6
- Switching Frequency - MHz
1.8
2
f
s
Figure 13.
BST-SW
Electrically this node is the same as the SW pin. However, it is physically closer to the BST pin so as to minimize
parasitic inductance effects of trace routing to the BST capacitor. Keeping the external traces short should
minimize turn on and off times.
This pin is not sized for conducting inductor current and should not be tied to the SW pin. It is only for the BST
pin capacitor connection.
Copyright © 2013, Texas Instruments Incorporated
15
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
IMON
MOSFET current sense monitor output. This pin provides a current source output that is proportional to the
current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should be
connected to a resistor to GND to produce a voltage proportional to the power-stage load current. For example, a
value of 10kΩ to ground produces a voltage of 2.0V when the power stage current is 10A.The accuracy of the
reported current is a function of the peak to peak ripple current in the inductor (ΔI). The nominal behavior is
described by Equation 1. The plot illustrates the possible variability in the sensed current as a function of load for
a ΔI=4A. If no PWM is detected for 8µs IMON will report 0V.
ì
μA
A
μA
A
ü
ΔI
2
20
I
OUT
If IOUT ³
ï
ï
ï
ï
I
MON(IOUT,DI)=
í
ï
ý
ï
μA
A
ΔI
2
10
I
OUT +5
DI
If IOUT <
ï
î
ï
þ
(1)
200
175
150
125
100
75
50
25
DI = 4 A
0
0
1
2
3
4
5
6
7
8
9
10
I
(A)
OUT
Figure 14. Sensed Current Variability
TMON
The voltage on this pin is proportional to the die temperature with a gain of 10 mV/°C and an offset voltage of
0.47 V at TJ = 0°C (Equation 2):
10mV
TMON(TJ) = 0.47 V +
TJ
( )
°C
(2)
16
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110 120130
- Junction Temperature - °C
T
J
Figure 15. Typical Characteristics
If the junction temperature exceeds approximately 170°C, the device will enter thermal shutdown. This will assert
the FLT pin, both MOSFETs will be turned off and the switch node will go high impedance. When the junction
temperature cools by approximately 20°C, the device will exit thermal shutdown and resume switching as
directed by the PWM and SRE pins. During a thermal shutdown event, the voltage on the Temp pin is driven to
3.3V.
FLT
This signal is a 3.3V digital output which is latched high when the current in the high-side FET exceeds the
current limit trip point. When tripped, high-side FET drive pulses are truncated to limit output current. FLT is
cleared on the falling edge of the first PWM pulse without a fault. Additionally, if the die temperature exceeds
170°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag.
Normal operation resumes when the die temperature falls below the thermal hysteresis band. The FLT flag will
clear after a PWM pulse occurs without a fault. Current limit is ignored during the high side blanking time. If an
over current event occurs during the blanking time the part will not initiate current limit for ~50ns.
PWM
ILIMIT
IL
HS
LS
FLT
Figure 16. FLT Signal
Copyright © 2013, Texas Instruments Incorporated
17
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
APPLICATION INFORMATION
A partial schematic of a power supply application using the UCD7242 power stage is provided below. Although
not shown the IC controlling the output is from the UCD92XX family of digital controllers.
Vin
+
330 mF
26 PWM-A
25 SRE-A
18 FLT-A
20 IMON-A
Vin 29
NC 28
PWM1
SRE1
FF1
EAp1
22 mF 25 V
10 W
Vin 27
800 nH
CS1
SW-A 14
BST-A 24
BSW-A 23
PGND 15
NC 16
Vout1
+
1
2
9
7
PWM-B
SRE-B
FLT-B
PWM2
SRE2
FF2
RBIAS
0.22 mF
47 mF
330 mF
GND
CS2
IMON-B
10 W
Temp
19 TMON
PGND 17
Vin 30
EAn1
EAp2
NC 31
10 kW
10 kW
1 mF
UCD7242
22 mF 25 V
10 W
Vin 32
800 nH
22 BP3
SW-B 13
Vout2
+
21 AGND
BST-B
3
4
RBIAS
0.22 mF
47 mF
330 mF
BSW-B
5
6
8
VGG
PGND 10
NC 11
GND
4.7 mF
VGG DIS
Test
10 W
PGND 12
EAn2
PRE-BIAS OPERATION
The UCD7242 has no problem starting up into pre-biased output voltages. However, when one channel is held in
tri-state and the second channel is actively switching, the tri-stated channel may generate a DC voltage through
weak capacitive coupling between SW-A and SW-B. This coupling comes principally from the close proximity of
the switch nodes on the silicon and the PWB layout.
There are several options to address this concern.
1. The device(s) that the UCD7242 is powering on a 3-stated channel has a known current draw at sub-
regulation voltage levels. This current draw may be sufficient to hold the voltage down.
2. Instead of holding the off channel in a 3-state condition, drive PWM actively low. This forces the synchronous
rectifier to turn on and prevent the pre-bias voltage from rising. If this option is elected, it is important to verify
that there are no other sources of leakage in the system.
3. Add a small load resistor, RBIAS. In most cases a value of 1kΩ should keep the output voltage below 200mV.
Some experimentation may be needed to determine the appropriate value. In many cases, the feedback
divider may provide a sufficient load.
It is important that VBIAS be less than or equal to the steady state output voltage during regulation. If this
condition is not enforced the controller in charge of regulating this rail will be unable to start up. If start up is
forced, damage may result.
18
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
OPERATING FREQUENCY
Switching frequency is a key place to start the design of any DC/DC converter. This will set performance limits on
things such as: maximum efficiency, minimum size, and achievable closed loop bandwidth. A higher switching
frequency is, generally, going to yield a smaller design at the expense of a lower efficiency. The size benefit is
principally a result of the smaller inductor and capacitor energy storage elements needed to maintain ripple and
transient response requirements. The additional losses result from a variety of factors, however, one of the
largest contributors is the loss incurred by switching the MOSFETs on and off. The integrated nature of the
UCD7242 makes these losses drastically smaller and subsequently enables excellent efficiency from a few
hundred kHz up to the low MHz. For a reasonable trade off of size versus efficiency, 750kHz is a good place to
start.
VGG
If 4.75V < VIN ≤ 6V a simple efficiency enhancement can be achieved by connecting VGG_DIS and VGG directly to
VIN. This allows the solution to bypass the drop out voltage of the internal VGG linear regulator, subsequently
improving the enhancement of the MOSFETs. When doing this it is critical to make sure that VGG never exceeds
the absolute maximum rating of 7V.
INDUCTOR SELECTION
There are three main considerations in the selection of an inductor once the switching frequency has been
determined. Any real world design is an iterative trade off of each of these factors.
1. The electrical value which in turn is driven by:
(a) RMS current
(b) The maximum desired output ripple voltage
(c) The desired transient response of the converter
2. Losses
(a) Copper (PCu
(b) Core (Pfe)
)
3. Saturation characteristics of the core
INDUCTANCE VALUE
The principle equation used to determine the inductance is:
diL (t)
vL (t) = L
dt
(3)
(4)
During the on time of the converter the inductance can be solved to be:
V
- VOUT
D
IN
L =
DI
¦s
Where:
VIN
VOUT
fs
Input Voltage
Output voltage
Switching frequency
D
Duty cycle (VOUT/VIN for a buck converter)
The target peak to peak inductor current.
ΔI
In general, it is desirable to make ΔI large to improve transient response and small to reduce output ripple
voltage and RMS current. A number of considerations go into this however, ΔI = 0.4 IOUT results in a small ILRMS
without an unnecessary penalty on transient response. It also creates a reasonable ripple current that most
practical capacitor banks can handle. Here IOUT is defined as the maximum expected steady state current.
Plugging these assumptions into the above inductance equation results in:
Copyright © 2013, Texas Instruments Incorporated
19
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
V
- V
OUT
D
IN
L = 5
2 ´ I
¦s
OUT
(5)
For example, plotting this result as a function of VIN and VOUT results in:
Figure 17. Inductance vs. VIN and VOUT
In this graph IOUT is 10A, the switching frequency is 750kHz and the inductor ΔI is 4A. If the switching frequency
is cut in half then the resulting inductance would be twice the value shown. Notice that the maximum inductance
occurs at the maximum VIN and VOUT shown on the plot. In general, this inductance value should be used in
order to keep the inductor ripple current from becoming too large over the range of supported VIN and VOUT
.
INDUCTOR LOSSES AND SATURATION
The current rating of an inductor is based on two things: the current necessary to raise the component
temperature by 40°C and the current level necessary to reduce the inductance to 80% of its initial value
(1)
(saturation current ). The current rating is the lower of these two numbers. Both of these factors are influenced
by the choice of core material. Popular materials currently in use are: ferrite, powdered alloy and powdered iron.
Ferrite is regarded as the highest performance material and as such is the lowest loss and the highest cost. Solid
ferrite all by itself will saturate with a relatively small amount of current. This can be addressed by inserting a gap
into the core. This, in effect, makes the inductor behave in a linear manner over a wide DC current range.
However, once the inductance begins to roll off, these gapped materials exhibit a “sharp” saturation
characteristic. In other words, the inductance value reduces rapidly with increases in current above the saturation
level. This small inductance that results, can produce dangerously high current levels.
(1) Although “saturation current” is standard terminology among many inductor vendors, technically saturation does not occur until the
relative permeability of the core is reduced to approximately 1. This is a value much larger than what is typically seen on data sheets.
20
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
Powdered iron has the advantage of lower cost and a soft saturation characteristic; however, its losses can be
very large as switching frequencies increase. This can make it undesirable for a UCD7242 based application
where higher switching frequency may be desired. It’s also worth noting that many powdered iron cores exhibit
an aging characteristic where the core losses increase over time. This is a wear-out mechanism that needs to be
considered when using these materials.
The powdered alloy cores bring the soft saturation characteristics of powdered iron with considerable
improvements in loss without the wear-out mechanism observed in powdered iron. These benefits come at a cost
premium.
In general the following relative figure of merits can be made:
Ferrite
High
Powdered Alloy
Medium
Powdered Iron
Cost
Loss
Low
High
Soft
Low
Medium
Saturation
Rapid
Soft
When selecting an inductor with an appropriate core it’s important to have in mind the following:
1. ILRMS, maximum RMS current
2. ΔI, maximum peak to peak current
3. IMAX, maximum peak current
The RMS current can be determined by Equation 6:
DI2
2
ILRMS
=
IOUT
+
12
(6)
When the 40% ripple constraint is used at maximum load current, this equation simplifies to: ILRMS≈IOUT
.
It is widely recognized that the Steinmetz equation (Pfe) is a good representation of core losses for sinusoidal
stimulation. It is important to recognize that this approximation applies to sinusoidal excitation only. This is a
reasonable assumption when working with converters whose duty cycles are near 50%, however, when the duty
cycle becomes narrow this estimate may no longer be valid and considerably more loss may result.
β
Pƒe = k × ƒα × BAC
(7)
(7)
The principle drivers in this equation are the material and its respective geometry (k, α, β), the peak AC flux
density (BAC) and the excitation frequency (ƒ). The frequency is simply the switching frequency of the converter
while the constant k, can be computed based on the effective core volume (Ve) and a specific material constant
(kƒe).
k = kƒe × Ve
(8)
(8)
The AC flux density (BAC) is related to the conventional inductance specifications by the following relationship:
DI
´ N 2
L
B
=
AC
A
e
(9)
Where L is the inductance, Ae, is the effective cross sectional area that the flux takes through the core and N is
the number of turns.
Some inductor manufactures use the inductor ΔI as a figure of merit for this loss, since all of the other terms are
a constant for a given component. They may provide a plot of core loss versus ΔI for various frequencies where
ΔI can be calculated as:
V
- VOUT
D
IN
DI =
L
¦s
(10)
IMAX has a direct impact on the saturation level. A good rule of thumb is to add 15% of head room to the
maximum steady state peak value to provide some room for transients.
ΔI
æ
ö
÷
ø
I
= 1.15 × I
ç OUT
+
MAX
2
è
(11)
21
For example for a 10A design has the following:
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
IOUT
ILRMS
ΔI
10A
10A
4A
IMAX
13.8A
Armed with this data one can now approach the inductor data sheet to select a part with a “saturation” limit
above 13.8A and current “heating” limit above 10A. Furthermore, total losses can be estimated based on the
datasheet DCR value (ILRMS 2DCR) and the core loss curves for a given frequency and ΔI.
INPUT CAPACITANCE
Due to the non-zero impedance of the power planes of the input voltage rail, it is necessary to add some local
capacitance near the UCD7242 to ensure that the voltage at this node is quiet and stable. The primary things to
consider are:
1. The radiated fields generated by the di/dt and dv/dt from this node
2. RMS currents capability needed in the capacitors
3. The AC voltage present and respective susceptibility of any device connected to this node
DI2
2
IOUT ´ D ´ (1 - D) +
ICINRMS
=
´ D
12
(12)
As a point of reference if ΔI=0.4 IOUT this places the worst case ICINRMS at approximately 5A. This corresponds to
a duty cycle of approximately 50%. Other duty cycles can result in a significantly lower RMS current.
A good input capacitor would be a 22μF X5R ceramic capacitor. Equally important as selecting the proper
capacitor is placing and routing that capacitor. It is crucial that the decoupling be placed as close as possible to
both the power pin (VIN) and ground (PGND). It is important to recognize that each power stage should have its
own local decoupling. One 22μF capacitor should be placed across each VIN and PGND pair. The proximity of
the capacitance to these pins will reduce the radiated fields mentioned above.
OUTPUT CAPACITANCE
The goal of the output capacitor bank is to keep the output voltage within regulation limits during steady state
and transient conditions.
The total AC RMS current flowing through the capacitor bank can be calculated as:
DI
I
=
COUTRMS
12
(13)
For a single type of output capacitor the output ripple voltage wave form can be approximated by the following
equation:
t
1
VOUT (t) = IC (t) ´ esr +
IC (t ) ´ dt
C
ò
0
(14)
(15)
(16)
Where:
DI ´ ¦s
ì
DI
D
´ t -
t<
ï
ï
í
D
2
¦
s
IC (t) =
æ
ç
è
ö
÷
ø
DI ´ ¦s
D
DI
ï
´
t -
+
otherwise
ï
1 - D
¦
2
s
î
After substitution and simplification yields
ì
t ´ ΔI ´
¦
´ t - D
ΔI ´ 1- 2 ´ D
DI ´ ¦
æ
ç
è
(
2 × D
)
(
)ö
÷
æ
ç
è
DIö
1
D
s
s
esr´
´ t -
+
´
-
t<
ï
ï
í
ï
÷
D
2
C
12 ´ ¦s
¦
s
ø
ø
VOUT (t) =
æ DI ´ ¦s
æ
ö
÷
ö
÷
ø
æ DI ´ (¦s ´ t -1) ´ (D - ¦s ´ t)- DI ´ (1- 2 ´ D)ö
D
DI
1
esr´
´ t -
+
+
´
otherwise
ç
è
ç
è
÷
ø
ç
ï
1- D
¦
2
C
2 ´ 1- D ´ ¦s
12 ´ ¦s
(
)
è
s ø
î
22
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
The term in this equation multiplied by the esr gives the ripple voltage component due to esr and the term
multiplied by 1/C gives the ripple voltage component due to the change in charge on the capacitor plates. In the
case were the esr component dominates the peak to peak output voltage can be approximated as:
VPPesr ≉ ΔI × esr
(17)
(17)
When the charge term dominates the peak to peak voltage ripple becomes:
DI
V
»
PPQ
8 ´ C ´ ¦
s
(18)
It is tempting to simply add these two results together for the case where the voltage ripple is significantly
influenced by both the capacitance and the esr. However, this will yield an overly pessimistic result, in that it
does not account for the phase difference between these terms.
Using the ripple voltage equations and the RMS current equation should give a design that safely meets the
steady state output requirements. However, additional capacitance is often needed to meet transient
requirements and the specific local decoupling requirements of any IC that is being powered off of this voltage.
This is not just a function of the capacitor bank but also the dynamics of the control loop. See the UCD9240
Compensation Cookbook for additional details.
DECOUPLING
It is necessary that VGG and BP3 have their own local capacitance as physically close as possible to these pins.
The VGG capacitor should be connected as close as possible to pin 5 and PGND with a 4.7μF ceramic capacitor.
The BP3 capacitor should be connected as close as possible to pin 22 and AGND with a 1μF ceramic capacitor.
The UCD7242 also supports the ability to operate from input voltages down to 2.2V. In these cases an additional
supply rail must be connected to VGG and VGG_DIS must be shorted to VGG. Potential external bias supply
generators for low VIN operation: TPS63000, TPS61220. The amount of current required for this supply is
dependant on the VGG voltage, the switching frequency and the number of active channels used in the UCD7242.
When both sides are active, use Figure 11: VGG Supply Current with 2 Rails Operating for current draw
estimates. If only one side is active, use Figure 10: VGG Supply Current with 1 Rail Operating and 1 Rail Off.
CURRENT SENSE
An appropriate resistor must be connected to the current sense output pins to convert the IMON current to a
voltage. In the case of the UCD9XXX digital controllers, these parts have a full scale current monitor range of 0V
to 2V. It is desirable to maximize this range to make full use of the current monitoring resolution inside the
controller. In order to ensure that current sensing will occur all the way to IMAX=10A a 1.8V target is chosen. In
this case a resistor 9.09kΩ would work.
VMON
RMON
=
m A
IMAX ´ 20
A
(19)
In some applications it may be necessary to filter the IMON signal. The UCD7242 IMON pin is a current source
output, so a capacitor to ground in parallel with the current-to-voltage conversion resistor is all that is required.
As a rule of thumb, placing the corner frequency of the filter at 20% of the switching frequency should be
sufficient.
For example, if the switching frequency is 500kHz or higher the ripple frequency will be easily rejected with a
corner frequency of approximately 100kHz. With a 100kHz pole point, the filter time constant is 1.6µs. A fast
current transient should be detected within 4.8µs.
1
C
=
MON
2 × p × R
× 20%×f
s
MON
(20)
20A Power Stage
It is possible to configure the UCD7242 to supply 20A by tying the outputs of two power stages together. When
doing this it is required that the PWM pulse widths of the two PWM input signals be identical. The best way to do
this is to drive PWM-A and PWM-B from the same signal. This ensures that balanced volt seconds will be
applied to the external SW pins.
Copyright © 2013, Texas Instruments Incorporated
23
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
Vin
www.ti.com.cn
+
330uF
26 PWM-A
25 SRE-A
18 FLT-A
20 IMON-A
Vin 29
NC 28
PWM1
SRE1
EAp1
22uF 25V
10r0
Vin 27
800nH
CS1
SW-A 14
BST-A 24
BSW-A 23
PGND 15
NC 16
Vout1
GND
+
1
2
9
7
PWM-B
SRE-B
FLT-B
0.22uF
47uF
SN74LVC1G32
330uF
FF1
IMON-B
10r0
Temp
19 TMON
PGND 17
Vin 30
EAn1
NC 31
4k99
UCD7242
22uF 25V
Vin 32
800nH
22 VDD
SW-B 13
1uF
21 AGND
BST-B
3
4
0.22uF
BSW-B
5
6
8
VGG
PGND 10
NC 11
4.7uF
VGG DIS
Test
PGND 12
Figure 18. 20A Design
Layout Recommendations
The primary thermal cooling path is from the VIN, GND, and the SW “stripes” on the bottom of the package. Wide
copper traces should connect to these nodes. 1-ounce copper should be the minimum thickness of the top layer;
however, 2-ounce copper is better. Multiple thermal vias should be placed near the GND stripes that connect to a
PCB ground plane. There is room to place multiple 10-mil (0.25mm) diameter vias next to the VIN and GND
stripes under the package.
For input bypassing, the 22µF input ceramic capacitors should be connected as close as possible to the VIN and
GND stripes. If possible, the input caps should be placed directly under the UCD7242 using multiple 10-mil vias
to bring the VIN and GND connections to the back side of the board. Minimizing trace inductance in the bypass
path is extremely important to reduce the amplitude of ringing on the switching node.
24
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
VIN
C32
22uF 25V
1210
TP31
CS3
TP32
FF3
TP33 TP34
SRE3 PWM3
26 PWM-A
25 SRE-A
18 FF-A
Vin 29
Vin 28
PWM3
SRE3
FF3
C8
EAp3
L1
800nH
HM00-08822LF
12.5 x 10.5mm
TB4
1x2
R30
10r0
0603 0.2
22uF 25V
1210
TP46
SW3
TP40
Vout3
Vin 27
CS3
20 Isense-A
SW-A 14
BST-A 24
BSW-A 23
PGND 15
PGND 16
PGND 17
Vin 30
Vout3
GND
C9
C10
+
RBIAS
1
2
9
7
PWM-B
SRE-B
FF-B
PWM4
SRE4
FF4
C27
0.22uF
0603
47uF
1210
330uF
10mm x
12.5mm
R31
10r0
0603
CS4
T2
Isense-B
TP41
GND
19 Tsense
EAn3
EAp4
T2
TP35
CS4
TP36
FF4
TP37
SRE4
TP38
PWM4
TP39
C28
U5
L2
800nH
HM00-08822LF
12.5 x 10.5mm
Vin 31
TB5
1x2
UCD7242
R32
10r0
0603 0.2
22uF 25V
1210
TP47
SW4
TP42
Vout4
6x6 QFN
Pkg RSJ
Vin 32
R36
10k0
0603
R35
10k0
0603
SW-B 13
Vout4
GND
C11
C12
+
RBIAS
C31
1uF
0603
22 BP3
21 AGND
BST-B
3
4
C29
0.22uF
0603
47uF
1210
330uF
10mm x
12.5mm
BSW-B
VGG DIS
TP44
6
5
8
VGG DIS
VGG
PGND 10
PGND 11
PGND 12
VGG
TP45
R33
10r0
0603
TP43
GND
R37
10k0
0603
C30
4.7uF
0805
Test
EAn4
Figure 19. Schematic Fragment from 4-Output EVM
Copyright © 2013, Texas Instruments Incorporated
25
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
Output
cap
PGND
PGND
VIN
Input
caps
PGND
PGND
Output
cap
Figure 20. Top Layer
26
Copyright © 2013, Texas Instruments Incorporated
UCD7242-EP
www.ti.com.cn
ZHCSBS3 –OCTOBER 2013
Note how the ground
end of the VIN and
VOUT caps and the
PGND stripes of the
UCD7242 are all tied
together with multiple
vias.
Note: This is the primary heat dispersal layer as well as the major return-current path.
Figure 21. Layer 2 - Power GND Plane
Figure 22. Layer 3
Copyright © 2013, Texas Instruments Incorporated
27
UCD7242-EP
ZHCSBS3 –OCTOBER 2013
www.ti.com.cn
C32 is another VIN
bypass cap
placed directly
under the part.
Note use of
multiple vias to tie
directly to the VIN
and PGND
stripes.
Figure 23. Bottom Layer (X-ray View)
28
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
2500
(1)
(2)
(3)
(4/5)
(6)
UCD7242MRSJREP
V62/14601-01XE
ACTIVE
VQFN-HR
VQFN-HR
RSJ
32
32
RoHS-Exempt
& Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
UCD7242
EP
ACTIVE
RSJ
RoHS-Exempt
& Green
NIPDAU
UCD7242
EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明