UCD9244MRGCTEP_技术文档

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

UCD9244-EP 数字脉宽调制 (PWM) 系统控制器，具有 4 位，6 位或 8 位

VID 支持

1 特性

•

支持国防、航天和医疗应用

–

受控基线

1

•

完全可配置四输出非隔离式直流/直流 PWM 控制

器，此控制器支持 TMS320C6670™ 和

TMS320C6678™ 数字信号处理器 (DSP) VID 接口

同一组装和测试场所

同一制造场所

•

支持高达 2MHz 的开关频率，此时占空比分辨率为

250ps

支持军用（-55°C 至 125°C）温度范围

延长的产品生命周期

延长的产品变更通知

产品可追溯性

•

高达 1mV 的闭环分辨率

用于改进瞬态性能的具有非线性增益的硬件加

速，3 级 / 3 零补偿器

•

支持多个包含预偏置启动的软启动和软停止配置

支持电压裕度和排序

2 应用范围

•

网络互连设备

多个 UCD92xx 器件间的同步输入端子使 DPWM

时钟保持一致

电信设备

现场可编程门阵列 (FPGA)，DSP 和存储器电源

•

电源参数的 12 位数字监控包括：

–

输入电流和电压

3 说明

输出电流和电压

UCD9244 是一款设计用于非隔离式直流/直流电源应用

的四轨同步降压数字 PWM 控制器。这个器件集成了

用于直流/直流环路管理的专用电路，支持多达四个

VID 接口。此外，UCD9244 具有闪存存储器和一个串

口以支持可配置性、监控和管理。

每个功率级上的温度

辅助模数转换器 (ADC) 输入

•

多级过流故障保护：

–

外部电流故障输入

模拟比较器监控电流感测电压

被持续数字监控的电流

器件信息

订货编号

封装

封装尺寸

9mm x 9mm

•

过压和欠压故障保护

四方扁平无引线

(QFN) (64)

UCD9244MRGCTEP

过热故障保护

支持纠错码 (ECC) 的增强型非易失性存储器

Fusion Power Peripheral 4

器件由具有一个内部稳压器控制器的单电源供电运

行，此内部稳压器控制器可实现宽电源电压范围内

的运行

Digital

High Res

PWM

DPWM4A

FLT4A

EAp4

EAn4

Analog Front End

(AFE)

Compensator

3P/3Z IIR

Fusion Power Peripheral 3

Digital

High Res

PWM

DPWM3A

FLT3A

EAp3

EAn3

Analog Front End

(AFE)

Compensator

3P/3Z IIR

•

由 Fusion Digital Power™ 设计工具，一个基于全

功能 PC 的设计工具提供支持，以模拟、配置和监

控电源性能。

Fusion Power Peripheral 2

Digital

High Res

PWM

DPWM2A

FLT2A

EAp2

EAn2

Analog Front End

(AFE)

Compensator

3P/3Z IIR

Fusion Power Peripheral 1

Analog Front End

Compensator

EAp1

EAn1

Diff

Amp

Digital

High Res

PWM

DPWM1A

FLT1A

Err

Amp

ADC

bit

IIR

3P/3Z

6

Ref

Coeff.

Regs

SyncIn/JTAG_TDI

PowerGood

5

6

GPIO

V33x

xGnd

3.3V reg.

controller

& 1.8V

regulator

Analog Comparators

VID1A

VID1B

BPCap

VID1C

OC

Ref

1

2

3

4

VID1S

DPWM1

ARM-7 core

VID2A

Addr0

Addr1

VID2B

OC

DPWM2

VID2C

CS1A

CS2A

VID

1 - 4

VID2S

12-bit

ADC

260 ksps

Flash

Memory with

ECC

VID3A

CS3A

OC

VID3B

CS4A

DPWM3

VID3C

Temp1/AuxADC1

Temp2/AuxADC2

Temp3/AuxADC3

Temp4/AuxADC4

VID3S

OC

DPWM4

VID4A/JTAG_TCK

VID4B/JTAG_TDO

VID4C/JTAG_TMS

VID4S

Osc

POR/BOR

Internal

Temp Sense

PMBus_Clk

PMBus_Data

PMBus_Alert

PMBus_Cntrl

PMBus

JTAG

RCK

nRESET

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLVSC86

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

说明（继续） ........................................................... 3

Terminal Configuration and Functions................ 4

Specifications......................................................... 7

7.1 Absolute Maximum Ratings ..................................... 7

7.2 Handling Ratings....................................................... 7

7.3 Recommended Operating Conditions...................... 7

7.4 Thermal Information.................................................. 7

7.5 Electrical Characteristics.......................................... 8

7.6 Electrical Characteristics (Continued)...................... 9

7.7 ADC Monitoring Intervals And Response Times ... 10

7.8 Hardware Fault Detection Latency ......................... 11

7.9 PMBus/SMBus/I²C ................................................. 11

7.10 I²C/SMBus/PMBus Timing Requirements............. 12

7.11 Typical Characteristics.......................................... 13

8

9

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

8.2 Functional Block Diagram ....................................... 15

8.3 Feature Description ................................................ 16

8.4 Device Functional Modes........................................ 28

Applications and Implementation ...................... 31

9.1 Application Information............................................ 31

9.2 Typical Applications ................................................ 31

10 Power Supply Recommendations ..................... 35

11 Layout................................................................... 35

11.1 Layout Guidelines ................................................. 35

11.2 Layout Example .................................................... 35

12 Device and Documentation Support ................. 36

12.1 Trademarks........................................................... 36

12.2 Electrostatic Discharge Caution............................ 36

12.3 Glossary................................................................ 36

13 Mechanical, Packaging, and Orderable

Information ........................................................... 36

4 修订历史记录

Changes from Original (January 2014) to Revision A

Page

•

已更改将格式更改为符合最新标准，已添加详细说明和电源部分.......................................................................................... 1

Added footnote to t_retentionparameter ..................................................................................................................................... 9

2

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

5 说明（继续）

支持几个电压识别 (VID) 模式，其中包括一个 4 位并口，一个 6 位接口和一个 8 位串口。

UCD9244 被设计用于提供针对非隔离式直流/直流转换器应用的多种所需特性，与此同时，通过减少外部电路来最

大限度地减少总体系统组件数量。此解决方案集成具有排序、裕度和跟踪的多环路管理，以针对总体系统效率进行

优化。此外，在无需添加额外组件的情况下，支持环路补偿和校准。

为了简化器件配置，提供德州仪器 (TI) Fusion Digital Power™ 设计工具。这个基于 PC 的图形用户界面为该器件

提供了一个直观的界面。这个工具使得设计人员能够为应用配置系统运行参数、将配置保存至片上非易失性存储器

并且观察每个功率级输出的频域和时域仿真。

TI 还开发了多个互补功率级解决方案 - 从 UCD7k 系列中的离散驱动器到 PTD 系列中经完全测试的电源传动模

块。这些解决方案已被开发用于为 UCD92xx 系列系统电源控制器提供补充。

3

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

6 Terminal Configuration and Functions

RGC Package

QFN-64

(Top View)

48

47 BPCap

CS4A

Agnd2

1

CS3A

CS2A

2

3

46

45 V33D

44

V33A

VinMon

Temp1/AuxADC1

Temp2/AuxADC2

V33DIO1

4

5

V33DIO2

43 Dgnd3

42 VID1B

6

7

41 VID1A

Dgnd1

8

40

39

JTAG_nTRST

UCD9244

nRESET

9

VID4C/JTAG_TMS

JTAG_RCK

FLT1A

10

11

38 SyncIn/JTAG_TDI

VID4B/JTAG_TDO

VID4A/JTAG_TCK

VID4S

37

36

35

34

33

VID1S

FLT2A

12

13

VID2S

PMBus_Clk

PMBus_Data

14

15

16

FLT4A

VID3S

4

(1) In case of conflict between and the table shall take precedence

(2) Preliminary versions of this data sheet prior to June 14, 2010 had a different definition for terminals 17, 18, and 21.

Board designs made with that earlier pinout should be updated.

4

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

Terminal Functions

TERMINAL TERMINAL LABEL

NUMBER

TERMINAL DESCRIPTION

1

CS4A

Power stage 4A current sense input and input to analog comparator 4

Power stage 3A current sense input and input to analog comparator 3

Power stage 2A current sense input and input to analog comparator 2

Input Voltage monitor

2

CS3A

3

CS2A

4

VinMon

5

Temp1/AuxADC1

Temp2/AuxADC2

V33DIO1

Dgnd1

Temperature sense input for Rail 1, or Auxiliary ADC input 1

Temperature sense input for Rail 2, or Auxiliary ADC input 2

Digital Input / Output 3.3V supply

6

7

8

Digital ground

9

nRESET

Active low device reset input. Pull up to 3.3V with a 10kΩ resistor

JTAG Return Clock

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

JTAG_RCK

FLT1A

Fault indicator for stage 1A

VID1S

VID Select terminal for Rail 1

FLT2A

Fault indicator for stage 2A

VID2S

VID Select terminal for Rail 2

PMBus_Clk

PMBus_Data

DPWM1A

VID1C

PMBus Clock. Pull up to 3.3V with a 2kΩ resistor

PMBus Data. Pull up to 3.3V with a 2kΩ resistor

Digital Pulse Width Modulator output 1A

VID input terminal for Rail 1 - most significant bit

Digital Pulse Width Modulator output 2A

VID input terminal for Rail 2 - least significant bit

Digital Pulse Width Modulator output 3A

VID input terminal for Rail 2

DPWM2A

VID2A

DPWM3A

VID2B

DPWM4A

Power_Good

FLT3A

Digital Pulse Width Modulator output 4A

Power Good Indication

Fault indicator for stage 3A

Dgnd2

Digital Ground

PMBus_Alert

PMBus_Cntrl

VID2C

PMBus Alert. Pull up to 3.3V with a 2kΩ resistor

PMBus Control. Pull up to 3.3V with a 2kΩ resistor

VID input terminal for Rail 2 - most significant bit

VID input terminal for Rail 3 - least significant bit

VID input terminal for Rail 3

VID3A

VID3B

VID3C

VID input terminal for Rail 3 - most significant bit

VID Select terminal for Rail 3

VID3S

FLT4A

Fault indicator for stage 4A

VID4S

VID Select terminal for Rail 4

VID4A/JTAG_TCK

VID4B/JTAG_TDO

SyncIn/JTAG_TDI

VID4C/JTAG_TMS

Mux'ed terminal - VID input terminal for Rail 4 (LSB), JTAG Test Clock

Mux'ed terminal - VID input terminal for Rail 4, JTAG Test Data Output

Mux'ed terminal - SyncIn, JTAG Test Data In. Tie to V33D with 10kΩ resistor

Mux'ed terminal - VID input for rail 4 (MSB); JTAG Test mode select. Tie to V33D with a 10kΩ

resistor

40

41

42

43

44

45

46

JTAG_nTRST

VID1A

JTAG Test Reset - Tie to ground with a 10kohm resistor

VID input terminal for Rail 1 - least significant bit

VID input terminal for Rail 1

VID1B

Dgnd3

Digital Ground

V33DIO2

V33D

Digital Input / Output 3.3V supply

Digital core 3.3V supply

V33A

Analog 3.3V supply

5

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

Terminal Functions (continued)

TERMINAL TERMINAL LABEL

NUMBER

TERMINAL DESCRIPTION

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

BPCap

Agnd2

1.8V Bypass Capacitor -- tie 0.1µF cap to analog ground

Analog ground

Agnd1

Analog ground

EAp1

Error analog, differential voltage, Positive channel 1 input

Error analog, differential voltage, Negative channel 1 input

Error analog, differential voltage, Positive channel 2 input

Error analog, differential voltage, Negative channel 2 input

Error analog, differential voltage, Positive channel 3 input

Error analog, differential voltage, Negative channel 3 input

Error analog, differential voltage, Positive channel 4 input

Error analog, differential voltage, Negative channel 4 input

Connection to the base of 3.3V linear regulator transistor (no connect if unused)

Power stage 1A current sense input and input to analog comparator 1

PMBus Address sense. Channel 1.

EAn1

EAp2

EAn2

EAp3

EAn3

EAp4

EAn4

V33FB

CS1A

Addr1

Addr0

PMBus Address sense. Channel 0.

Temp3/AuxADC3

Temp4/AuxADC4

Agnd3

Temperature sense input for Rail 3, or Auxiliary ADC input 3

Temperature sense input for Rail 4, or Auxiliary ADC input 4

Analog ground

PowerPad

It is recommended that this pad be connected to analog ground

6

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

–0.3 to 3.8

150

UNIT

V

Voltage applied at V_33Dto DGND

Voltage applied at V_33Ato AGND

Voltage applied to any terminal⁽²⁾

Maximum junction temperature (T_J)

V

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to GND.

7.2 Handling Ratings

MIN

MAX

UNIT

T_stg

Storage temperature range

-55

150

°C

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM

MAX UNIT

V

Supply voltage during operation, V_33D, V_33DIO, V_33A

Operating junction temperature range

3

3.3

3.6

V

T_J

–55

125

°C

7.4 Thermal Information

UCD9244-EP

THERMAL METRIC⁽¹⁾

QFN

UNIT

64 TERMINAL

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

24.6

10

θ_JCtop

θ_JB

4.2

0.2

4.1

1

°C/W

ψ_JT

ψ_JB

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

7

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

MAX UNIT

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

TEST CONDITIONS

MIN

NOM

SUPPLY CURRENT

I_V33A

V_33A= 3.3 V

8

42

54

52

15

55

80

65

mA

I_V33DIO

I_V33

V_33DIO= 3.3 V

Supply current

Total V₃₃supply current, V_33A= V_33DIO= 3.3 V

I_V33DIO

V_33D= 3.3 V storing configuration parameters

in flash memory

INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS

V₃₃

3.3-V linear regulator

Emitter of NPN transistor

3.25

3.3

4

3.6

4.6

8

V

V_33FB

I_V33FB

Beta

3.3-V linear regulator feedback

Series pass base drive

Series NPN pass device

V_IN= 12 V

0.2

40

0.4

mA

EXTERNALLY SUPPLIED 3.3 V POWER

V_33D, V_33DIO1

V_33DIO2

,

Digital 3.3-V power

T_J= 25°C

3.0

3.6

V

V33A

Analog 3.3-V power

ERROR AMPLIFIER INPUTS EAPn, EANn

V_CM

Common mode voltage each

terminal

0

1.8

V

V_ERROR

EAP-EAN

R_EA

Internal error Voltage range

Error voltage digital resolution

Input Impedance

AFE_GAIN field of CLA_GAINS = 1X⁽¹⁾

AFE_GAIN field of CLA_Gains = 8X

Ground reference, T_J= 25°C

–256

248

mV

MΩ

µA

1

1.5

I_OFFSET

Vref 10-bit DAC

V_ref

Input offset current

1-kΩ source impedance,T_J= 25°C

–5

0

5

Reference Voltage Setpoint

Reference Voltage Resolution

1.7

V

V_refres

1.56

mV

ANALOG INPUTS CS1A, CS2A, CS3A, CS4A,VinMon, Temp1, Temp2, Temp3, Temp4, Addr0, Addr1

V_{ADC_RANGE}

Measurement range for voltage

monitoring

Inputs: VinMon, Temp1, Temp2, Temp3,

Temp4, CS1A, CS2A, CS3A, CS4A

0

2.6

V

Voffset

input offset voltage

–27

27

2

mV

V

V_{OC_THRS}

Over-current comparator threshold Inputs: CS1A, CS2A, CS3A, CS4A

voltage range⁽²⁾

0.032

V_{OC_RES}

Over-current comparator threshold Inputs: CS, 1A, CS2A, CS3A, CS4A

voltage range

31.25

mV

Temp_internal

Int. temperature sense accuracy

ADC integral nonlinearity

Input leakage current

Over range from 0°C to 100°C

T_J= -40°C to 125°C

–15

15

2.5

°C

mV

nA

INL

I_lkg

–2.5

3V applied to terminal

Ground reference

100

R_IN

C_IN

Input impedance

8

MΩ

pF

Current Sense Input capacitance

10

(1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.

(2) Can be disabled by setting to '0'

8

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

7.6 Electrical Characteristics (Continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DIGITAL INPUTS/OUTPUTS

Dgnd

+0.3

V_OL

V_OH

Low-level output voltage

High-level output voltage

I_OL= 6 mA⁽¹⁾, V_33DIO= 3 V

I_OH= -6 mA⁽²⁾, V_33DIO= 3 V

V

V_33DIO

–0.6V

V_IH

V_IL

High-level input voltage

Low-level input voltage

V_33DIO= 3V

2.1

3.6

1.4

V

V_33DIO= 3.5 V

SYSTEM PERFORMANCE

V_RESETVoltage where device comes out of reset

t_RESET

V_33Dterminal

2.3

2

2.4

10

V

Pulse width needed for reset

Setpoint Reference Accuracy

nRESET terminal

µs

Vref commanded to be 1V, at 25°C AFEgain = 4,

–10

mV

1V input to EAP/N measured at output of the

EADC⁽³⁾

V_RefAcc

Setpoint Reference Accuracy over

temperature

–55°C to 125°C

–40

–4

40

4

mV

AFEgain = 4 compared to

AFEgain = 1, 2, or 8

V_DiffOffset

Differential offset between gain settings

Digital Compensator Delay

240 + 1

switching

cycle

t_Delay

F_SW

240

ns

Switching Frequency

Accuracy

15.260

–5%

0%

2000

5%

kHz

Duty

Max and Min Duty Cycle

100%

V33 slew rate between 2.3V and 2.9V,

T_J= -40°C to 125°C

V₃₃Slew

t_retention

Minimum V₃₃slew rate

0.25

V/ms

Retention of configuration parameters⁽⁴⁾

T_J= 25 °C

100

20

Years

Write_Cycles Number of nonvolatile erase/write cycles

T_J= 25 °C

K cycles

All rails configured to accept VID messages⁽⁵⁾

All rails configured to accept 6-bit VID messages⁽⁵⁾

All rails configured to accept 8-bit VID messages⁽⁶⁾

1

4

Rate_VID

Max VID message rate

msg/msec

(1) The maximum I_OL, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.

(2) The maximum I_OH, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.

(3) With default device calibration. PMBus calibration can be used to improve the regulation tolerance.

(4) The data retention specification is based on accelerated stress testing at 170°C for 420 hours and using an Arrhenius model with

activation energy of 0.6 eV.

(5) VID message rate on each interface. Measured over a 1.0 msec interval.

(6) VID message rate on PMBus interface.

9

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

7.7 ADC Monitoring Intervals And Response Times

The ADC operates in a continuous conversion sequence that measures each rail's output voltage and output

current, plus six other variables (input voltage, internal temperature, and four external temperature sensors). The

length of the sequence is determined by the number of output rails (NumRails) configured for use. The time to

complete the monitoring sampling sequence is give by the formula: t_{ADC_SEQ}= t_ADC× (2 × NumRAILS + 6)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_ADC

ADC single-sample time

3.84

µs

t_{ADC_SEQ}

ADC sequencer interval Min = 2 × 1 Rail + 6 = 8 samples

Max = 2 × 4 Rails + 6 = 14 samples

30.72

53.76

µs

The most recent ADC conversion results are periodically converted into the proper measurement units (volts,

amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The

monitoring operates asynchronously to the ADC, at intervals shown in the table below.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_Vout

Output voltage monitoring interval

Output current monitoring interval

Input voltage monitoring interval

Temperature monitoring interval

Auxiliary ADC monitoring interval

200

µs

t_Iout

200×NRails

t_Vin

1

100

ms

t_TEMP

t_AUXADC

Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response

time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC

sequence interval. Once a fault condition is detected, some additional time is required to determine the correct

action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following

table lists the worse-case fault response times.

MAX

no VID /w VID

MAX

(1)

PARAMETER

TEST CONDITIONS

TYP

UNIT

t_OVF

t_UVF

,

Over-/under-voltage fault response time

during normal operation

Normal regulation, no PMBus activity,

4 stages enabled

250

800

400

800

µs

t_OVF

t_UVF

Over-/under-voltage fault response time, During data logging to nonvolatile

during data logging

memory⁽²⁾

1000

µs

t_OVF

t_UVF

Over-/under-voltage fault response time, During tracking and soft-start ramp.

when tracking or sequencing enable

t_OCF

t_UCF

,

Over-/under-current fault response time

during normal operation

Normal regulation, no PMBus activity,

4 stages enabled 75% to 125% current

step⁽³⁾

100 +

(600 × NRails)

5000

t_OCF

t_UCF

,

Over-/under-current fault response time, During data logging to nonvolatile

during data logging

600 +

(600 × NRails)

µs

sec

µs

memory 75% to 125% current step

t_OTF

Over-temperature fault response time

Temperature rise of 10°C/sec, at OT

threshold

1.60

5.5

t_3-StateTime to tristate the PWM output after a

shutdown is initiated

DRIVER_CONFIG = 0x01

(1) Controller receiving VID commands at a rate of 4000 msg/sec.

(2) During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can

be up to 10 ms.

(3) Because the current measurement is averaged with a smoothing filter, the response time to an over-current condition depends on a

combination of the time constant (τ) from Table 6, the recent measurement history, and how much the measured value exceeds the

over-current limit.

10

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

7.8 Hardware Fault Detection Latency

The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.

PARAMETER

TEST CONDITIONS

MAX TIME

UNIT

Time to disable DPWM output base on active FAULT

terminal signal

t_FAULT

t_CLF

High level on FAULT terminal

18

µs

Time to disable the DPWM A output based on internal

analog comparator

Switch

Cycles

Step change in CS voltage from 0V to 2.5V

4

7.9 PMBus/SMBus/I²C

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and

PMBus are shown below.

t_r

t_(LOW)

t_f

V_IH

SMBDATA

V_IL

t_(HIGH)

t_(HD:STA)

t_(HD:DAT)

t_(SU:STA)

t_(SU:STO)

t_(SU:DAT)

V_IH

SMBDATA

V_IL

t_(BUF)

P

S

P

Start

Stop

t_(LOW;SEXT)

CLK_ACK

t_(LOW:MEXT)

SMB_CLK

SMB_DATA

Figure 1. I²C/SMBus/PMBus Timing In Extended Mode Diagram

11

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

MAX UNIT

7.10 I²C/SMBus/PMBus Timing Requirements

T_J= –55°C to 125°C, 3V < V₃₃< 3.6V, typical values at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN TYP

f_SMB

SMBus/PMBus operating frequency

I C operating frequency

Bus free time between start and stop

Hold time after (repeated) start

Repeated start setup time

Stop setup time

Slave mode; SMBC 50% duty cycle

Slave mode; SCL 50% duty cycle

10

5

1000

kHz

µs

f_I2C

t_(BUF)

t_(HD:STA)

t_(SU:STA)

t_(SU:STO)

t_(HD:DAT)

t_(SU:DAT)

t_(TIMEOUT)

t_(LOW)

0.3

0

µs

Data hold time

Receive mode

ns

Data setup time

55

ns

(1)

Error signal/detect

See

35

ms

µs

Clock low period

0.55

0.3

(2)

t_(HIGH)

Clock high period

See

50

25

µs

(3)

t_(LOW:SEXT)Cumulative clock low slave extend time See

ms

ns

t_FALL

Clock/data fall time

Rise time t_RISE= V_ILMAX– 0.15) to (V_IHMIN+ 0.15),

T_J= -40°C to 125°C

1000

t_RISE

Clock/data rise time

Fall time t_FALL= 0.9 V₃₃to (V_ILMAX– 0.15),

T_J= -40°C to 125°C

1000

ns

(1) The UCD9244 times out when any clock low exceeds _t(TIMEOUT)

.

(2) t_(HIGH), max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9244 that is

in progress.

(3) t_(LOW:SEXT)is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

12

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

7.11 Typical Characteristics

Figure 3. Soft-Stop Ramp

Figure 2. Soft-Start Ramp

13

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

8 Detailed Description

8.1 Overview

The UCD9244 contains four Fusion Power Peripherals (FPP). Each FPP consists of:

•

A differential input error voltage amplifier.

A 10-bit DAC used to set the output regulation reference voltage.

A fast ADC with programmable input gain to digitally measure the error voltage.

A dedicated 3-pole/3-zero digital filter to compensate the error voltage

A digital PWM (DPWM) engine that generates the PWM pulse width based on the compensator output.

Each controller is configurable through the PMBus serial interface.

14

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

8.2 Functional Block Diagram

Fusion Power Peripheral 4

Digital

High Res

PWM

DPWM4A

EAp4

EAn4

Analog Front End

(AFE)

Compensator

3P/3Z IIR

FLT4A

Fusion Power Peripheral 3

Digital

High Res

PWM

DPWM3A

EAp3

EAn3

Analog Front End

(AFE)

Compensator

3P/3Z IIR

FLT3A

Fusion Power Peripheral 2

Digital

High Res

PWM

DPWM2A

EAp2

EAn2

Analog Front End

(AFE)

Compensator

3P/3Z IIR

FLT2A

Fusion Power Peripheral 1

Analog Front End

Compensator

EAp1

EAn1

Diff

Amp

Digital

High Res

PWM

DPWM1A

Err

Amp

ADC

6 bit

IIR

3P/3Z

FLT1A

Ref

Coeff.

Regs

SyncIn/JTAG_TDI

5

6

PowerGood

GPIO

V33x

xGnd

3.3V reg.

controller

& 1.8V

regulator

Analog Comparators

VID1A

VID1B

VID1C

VID1S

VID2A

VID2B

VID2C

BPCap

OC

Ref 1

Ref 2

Ref 3

Ref 4

DPWM1

ARM-7 core

Addr0

Addr1

OC

DPWM2

CS1A

CS2A

VID

1 - 4

VID2S

12-bit

ADC

260 ksps

Flash

Memory with

ECC

VID3A

CS3A

OC

VID3B

CS4A

DPWM3

VID3C

Temp1/AuxADC1

Temp2/AuxADC2

Temp3/AuxADC3

Temp4/AuxADC4

VID3S

OC

DPWM4

VID4A/JTAG_TCK

VID4B/JTAG_TDO

VID4C/JTAG_TMS

VID4S

Osc

POR/BOR

Internal

Temp Sense

PMBus_Clk

PMBus_Data

PMBus_Alert

PMBus_Cntrl

PMBus

JTAG

RCK

nRESET

15

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

8.3 Feature Description

8.3.1 PMBus Interface

The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus

interface that is built on the I²C physical specification. The UCD9244 supports revision 1.2 of the PMBus

standard. Wherever possible, standard PMBus commands are used to support the function of the device. For

unique features of the UCD9244, MFR_SPECIFIC commands are defined to configure or activate those features.

These commands are defined in the UCD92xx PMBUS Command Reference.

The UCD9244 is PMBus compliant, in accordance with the "Compliance" section of the PMBus specification. The

firmware is also compliant with the SMBus 2.0 specification, including support for the SMBus ALERT function.

The hardware can support 100 kHz, 400 kHz, or 1 MHz PMBus operation.

8.3.2 Resistor Programmed PMBus Address Decode

The PMBus Address is selected using resistors attached to the ADDR0 and ADDR1 terminals. At power-up, the

device applies a bias current to each address detect terminal. The measured voltage on each terminal

determines the PMBus address as defined in Table 1. For example, a 133kΩ resistor on ADDR1 and a 75kΩ on

ADDR0 will select PMBus address = 100. Resistors are chosen from the standard EIA-E96 series, and should

have accuracy of 1% or better.

V33

ADDR - 0,

ADDR - 1 pins

10 mA

I_BIAS

Resistor to

set PMBus

Address

To 12 -bit ADC

Figure 4. PMBus Address Detection Method

A short or open on either address terminal causes the PMBus address to default to address 126. To avoid

potential conflicts between multiple devices, it is best to avoid using address 126.

Some addresses should be avoided; see Table 1 for details.

16

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

Feature Description (continued)

Table 1. PMBus Address Bins⁽¹⁾

ADDR0

(short)

< 36.5k

(open)

> 237k

42.2k 48.7k 56.2k 64.9k

75k

86.6k 100k 115k 133k 154k 178k 205k

< 36.5k

(short)

126

42.2k

48.7k

56.2k

64.9k

75k

126

126⁽²⁾

24

1

2

3

4

5

6

18

7

19

8

20

9

10

22

11⁽³⁾

33

126

13

14

15

16

17

21

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

86.6k

100k

115k

133k

154k

178k

205k

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

112

124

126

101

113

125

126

102

114

103

115

104

116

105

117

126

106

118

126

107

119

126

108

120

126

109

121

126

110

122

126

111

123

126

126 126⁽²⁾126

126

> 237k

(open)

126

(1) Shaded addresses are not recommended as they will cause conflict when multiple devices are used.

(2) Reserved. Do not use.

(3) Conflicts with ROM. Do not use.

8.3.3 VID Interface

The UCD9244 supports VID (Voltage Identification) inputs from up to four external VID enabled devices. The VID

codes may be 4-, 6-, or 8-bit values; the format is selected using the VID_CONFIG PMBus command. In 4- and

6-bit mode, each host uses four VID input signals (VID_A, VID_B, VID_C, and VID_S) to send VID codes to the

UCD9244. In 8-bit mode, the PMBus input is used to receive VID commands from the VID devices’ I²C

interfaces.

VID device #1

VCNTL[0]

VCNTL[1]

VCNTL[2]

VCNTL[3]

VID device #3

VCNTL[0]

VCNTL[1]

VCNTL[2]

VCNTL[3]

VID1A

VID1B

VID1C

VID1S

VID4A

VID4B

VID4C

VID4S

UCD9244

VID device #2

VCNTL[0]

VCNTL[1]

VCNTL[2]

VCNTL[3]

VID device #4

VCNTL[0]

VCNTL[1]

VCNTL[2]

VCNTL[3]

VID2A

VID2B

VID2C

VID2S

VID3A

VID3B

VID3C

VID3S

Figure 5. One UCD9244 Controlled By Four DSPS/ASICS Devices Using 4-Bit Or 6-Bit VID Format

17

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

Regardless of which VID mode is used, the commanded output voltage reference is set according to this formula:

Vref_cmd = (VID_CODE × VID_Slope) + VID_Offset

(1)

(2)

(3)

where

VID_Slope = (VID_Vout_High – VID_Vout_Low) / ((2^VID_Format) -1)

and

VID_Offset = VID_Vout_Low

The VID_Vout_High, VID_Vout_Low, and VID_Format values are set using the VID_CONFIG PMBus command.

The same command is used to set the initial VID code that will be used at power-up. In addition, the

VID_CONFIG command also sets the initial voltage that the device ramps to at the end of the soft start; and

defines a lockout interval over which the VID is ignored during the soft start.

VID Lockout Interval: Because the VID signals may be originating from a device that is being powered by the

UCD9244, the voltage levels on the VID signal may not be valid logic levels until the supply voltage at the

powered device has stabilized. For this reason a configurable lockout interval is applied each time the regulated

output voltage is turned on. The lockout interval timer starts when the output voltage reaches the top of the soft-

start ramp. Positive values range from 1 to 32767 ms, with 1 ms resolution. A value of 0 will enable the VID

inputs immediately at the top of the start ramp. Negative values disable the lockout, allowing the VID inputs to

remain active all the time regardless of the output voltage state. The default value is 0.

8.3.4 Jtag Interface

The JTAG interface can provide an alternate interface for programming the device. Four of the JTAG terminals

on the UD9244 (TMS, TDI, TDO, and TCK) are shared with other functions (VID4A, VID4B, VID4C, and Syncln).

JTAG is disabled by default. There are three conditions under which the JTAG interface is enabled:

1. When the ROM_MODE PMBus command is issued.

2. On power-up if the Data Flash is blank. This allows JTAG to be used for writing the configuration parameters

to a programmed device with no PMBus interaction.

3. When an invalid address is detected at power-up. By opening or shorting one of the address terminals to

ground, an invalid address can be generated that enables JTAG.

When the JTAG port is enabled the shared terminals are not available for use as Syncln or VID terminals.

If JTAG is to be used, an external mechanism such as jumpers or a mux must be used to prevent conflict

between JTAG and the Syncln or VID terminals.

8.3.5 Bias Supply Generator (Shunt Regulator Controller)

The I/O and analog circuits in the UCD9244 require 3.3V to operate. This can be provided using a stand-alone

external 3.3V supply, or it can be generated from the main input supply using an internal shunt regulator and an

external transistor. Regardless of which method is used to generate the 3.3V supply, bypass capacitors of 0.1 µF

and 4.7 µF should be connected from V33A and V33D to ground near the device. An additional bypass capacitor

from 0.1 to 1 µF must be connected from the BPCap terminal to ground for the internal 1.8V supply to the

device’s logic circuits.

Figure 6 shows a typical application using the external transistor. The base of the transistor is driven by a resistor

R1 to Vin and a transconductance amplifier whose output is on the V33FB terminal. The NPN emitter becomes

the 3.3V supply for the chip.

18

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

To Power Stage

Vin

FCX491A

+3.3V

+1.8V

4.7μ

0.1μ

R1

0.1μ

UCD9244

Figure 6. 3.3V Shunt Regulator Controller I/O

In order to generate the correct voltage on the base of the external pass transistor, the internal transconductance

amplifier sinks current into the V33FB terminal and a voltage is produced across R1. This resistor value should

be chosen so that ISINK is in the range from 0.2 to 0.4mA. R1 is defined as

V - 3.3 - V_be

in

R₁=

I_E

+I_SINK

b +1

( )

(4)

Where I_SINKis the current into the V33FB terminal; V_inis the power supply input voltage, typically 12V; I_Eis the

current draw of the device and any pull up resistors tied to the 3.3V supply; and β is the beta of the pass

transistor. For I_SINK= 0.3 mA, V_in=12V, β=99, V_be= 0.7V and I_E=50mA, this formula selects R1 = 10kΩ. Weaker

transistors or larger current loads will require less resistance to maintain the desired I_SINKcurrent. For example,

lowering β to 40 would require R1 = 5.23 kΩ; likewise, an input voltage of 5V requires a value of 1.24 kΩ for R1.

8.3.6 Power-On Reset

The UCD9244 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the

POR circuit detects the V33D rise. When V33D is greater than V_RESET, the device initiates an internal startup

sequence. At the end of the startup sequence, the device begins normal operation, as defined by the

downloaded device PMBus configuration.

8.3.7 External Reset

The device can be forced into the reset state by an external circuit connected to the nRESET terminal. A logic

low voltage on this terminal holds the device in reset. To avoid an erroneous trigger caused by noise, a 10kΩ pull

up resistor to 3.3V is recommended.

8.3.8 ON_OFF_CONFIG

The ON_OFF_CONFIG command is used to select the method of turning rails on and off. It can be configured so

that the rail:

•

stays off,

turns on automatically,

responds to the PMBus_Cntrl terminal,

responds to OPERATION command, or

responds to logical-AND of the PMBus_Cntrl terminal and the OPERATION command.

The ON_OFF_CONFIG command also sets the active polarity of the PMBus_Cntrl terminal.

19

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

8.3.9 Output Voltage Adjustment

The output voltage may be set to maintain a steady voltage or it may be controlled dynamically by the VID

interface, depending on the VID_CONFIG setting. When not being commanded by the VID interface, the nominal

output voltage is programmed by a combination of PMBus settings: VOUT_COMMAND, VOUT_CAL_OFFSET,

VOUT_SCALE_LOOP, and VOUT_MAX. Their relationship is shown in Figure 7. These PMBus parameters need

to be set such that the resulting Vref DAC value does not exceed the maximum value of V_ref.

Output voltage margining is configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands.

The OPERATION command selects between the nominal output voltage and either of the margin voltages. The

OPERATION command also includes an option to suppress certain voltage faults and warnings while operating

at the margin settings.

OPERATION Command

V_OUT

VOUT_CAL_OFFSET

VOUT_MARGIN_HIGH

R1

V_Sense

3:1

Mux

VOUT_COMMAND

VOUT_MARGIN_LOW

VID_CODE_RAILx

4-wire VID interface

VOUT_MAX

R2

VOUT_

SCALE_

LOOP

3:1

Mux

Limiter

Vref DAC

eADC

+

VOUT_OV_FAULT_LIMIT

VOUT_OV_WARN_LIMIT

VOUT_UV_WARN_LIMIT

VOUT_UV_FAULT_LIMIT

digital

compensator

VID_CONFIG

Figure 7. PMBus Voltage Adjustment Mechanisms

For a complete description of the commands supported by the UCD9244 see the UCD92xx PMBUS Command

Reference (SLUU337). Each of these commands can also be issued from the Texas Instruments Fusion Digital

Power™ Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands

to configure the UCD9244 device.

8.3.10 Calibration

To optimize the operation of the UCD9244, PMBus commands are supplied to enable fine calibration of output

voltage, output current, and temperature measurements. The supported commands and related calibration

formulas may be found in the UCD92xx PMBUS Command Reference (SLUU337).

8.3.11 Analog Front End (AFE)

V_EAP

G_AFE= 1, 2, 4, or 8

V_ead

6-bit

V_EA

result

V_EAN

Error

ADC

G_eADC= 8mV/LSB

Vref

DAC

CPU

Vref = 1.563 mV/LSB

PMBus

Figure 8. Analog Front End Block Diagram

The UCD9244 senses the power supply output voltage differentially through the EAP and EAN terminals. The

error amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output

voltage sense signals. The fully differential nature of the error amplifier also ensures low offset performance.

20

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus

command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then

transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by

the 10-bit Vref DAC as shown in Figure 8. The resulting error voltage is then amplified by a programmable gain

circuit before the error voltage is converted to a digital value by the error ADC (EADC). This programmable gain

is configured through the PMBus and affects the dynamic range and resolution of the sensed error voltage as

shown in Table 2. The internal reference gains and offsets are factory-trimmed at the 4x gain setting, so it is

recommended that this setting be used whenever possible.

Table 2. Analog Front End Resolution

AFE_GAIN for

PMBus Command

EFFECTIVE ADC

RESOLUTION (mV)

DIGITAL ERROR VOLTAGE

DYNAMIC RANGE (mV)

AFE Gain

0

1x

2x

4x

8x

8

4

2

1

–256 to 248

–128 to 124

–64 to 62

1

2 (Recommended)

3

–32 to 31

The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by

issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank

for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This

allows the user to trade-off resolution and dynamic range for each operational mode.

The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time.

However, its range is limited as shown in Table 2. If the output voltage is different from the reference by more

than this, the EADC reports a saturated value at –32 LSBs or 31 LSBs. The UCD9244 overcomes this limitation

by adjusting the Vref DAC up or down in order to bring the error voltage out of saturation. In this way, the

effective range of the ADC is extended. When the EADC saturates, the Vref DAC is slewed at a rate of 0.156

V/ms, referred to the EA differential inputs.

The differential feedback error voltage is defined as V_EA= V_EAP– V_EAN. An attenuator network using resistors R1

and R2 (Figure 9) should be used to ensure that V_EAdoes not exceed the maximum value of Vref when

operating at the commanded voltage level. The commanded voltage level is determined by the PMBus settings

described in the Output Voltage Adjustment section.

R1

EAP

+Vout

-Vout

C2

R2

Rin

Ioff

EAN

Figure 9. Input Offset Equivalent Circuit

8.3.12 Voltage Sense Filtering

Conditioning should be provided on the EAP and EAN signals. Figure 9 shows a divider network between the

output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output

voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the

signal conditioned by the low-pass filter formed by R1 and C2.

As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly

across an output capacitor as close to the load as possible. Route the positive and negative differential sense

signals as a balanced pair of traces or as a twisted pair cable back to the controller. Put the divider network close

to the controller. This ensures that there is low impedance driving the differential voltage sense signal from the

voltage rail output back to the controller. The resistance of the divider network is a trade-off between power loss

and minimizing interference susceptibility. A parallel resistance (R_p) of 1kΩ to 4kΩ is a good compromise. Once

RP is chosen, R1 and R2 can be determined from the following formulas.

21

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

R_P

R₁=

K

R_P

R₂=

1-K

V_EA

where K =

@ VOUT_SCALE_LOOP

V_OUT

(5)

It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an

additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter,

the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as:

1

C2 =

2p´0.35´F_SW´R_P

(6)

To obtain the best possible accuracy, the input resistance and offset current on the device should be considered

when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the

UCD9244. The input resistance and input offset current are specified in the parametric tables in this datasheet.

V_EA= V_EAP– V_EANin the equation below.

R₂

R₁R₂

V_EA

=

V_OUT

+

I_OFFSET

æ

ç

ö

÷

ø

æ

ç

ö

÷

ø

R₁R₂

R_EA

R₁R₂

R_EA

R + R +

1

2

1

2

è

(7)

The effect of the offset current can be reduced by making the resistance of the divider network low.

8.3.13 DPWM Engine

The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse

width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty

cycle as a digital number representing a percentage from 0 to 100%. The duty cycle value is multiplied by the

configured period to generate a comparator threshold value. This threshold is compared against the high speed

switching period counter to generate the desired DPWM pulse width. This is shown in Figure 10.

Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the SyncIn

and SyncOut terminals. Configuration of the synchronization function is done through a MFR_SPECIFIC PMBus

command. See the DPWM Synchronization section for more details.

DPWM Engine (1 of 4)

Clk

SysClk

High Res

Ramp

Counter

reset

SyncIn

S

R

PWM gate drive output

Switch period

Current balance adj

Compensator output

EADC trigger

(Calculated duty cycle)

SyncOut (not available

on UCD9244)

EADC trigger

threshold

Figure 10. DPWM Engine

22

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

8.3.14 Rail/Power Stage Configuration

Unlike many other products in the UCD92xx family, the UCD9244 does not support assigning power stages to

arbitrary rails, or combining multiple power stages on the same rail. The UCD9244 supports up to two single-

phase rails, and the channel number of each rail’s DPWM output must match that of its EAP/EAN feedback

inputs.

8.3.15 DPWM Phase Synchronization

DPWM synchronization provides a method to link the timing between voltage rails controlled by the UCD92xx

device--either internally or between devices. The configuration of the synchronization between rails is performed

by the issuing the SYNC_CONFIG command. For details of issuing this command, see the UCD92xx PMBUS

Command Reference (SLUU337). The synchronization behavior can also be configured using the Fusion Digital

Power Designer software. Below is a summary of the function.

Each digital pulse width modulator (PWM) engine in the UCD92xx controller can accept a sync signal that resets

the PWM ramp generator. The ramp generator can be set to free-run, accept a reset signal from another internal

PWM engine, or accept a reset signal from the external SyncIn terminal. In this way the PWM timers can be

"daisy-chained" to set up the desired phase relationship between power stages.

The PWM engine reset input can accept the following inputs

Table 3. Sync Trigger Inputs

SYNC SIGNAL

None (free run)

DPWM 1

DPWM 2

DPWM 3

DPWM 4

SyncIn terminal

Table 4. Available Source For SyncOut

SYNC SIGNAL

Disabled

DPWM 1

DPWM 2

DPWM 3

DPWM 4

When configuring a PWM engine to run synchronous to another internal PWM output, set the switching

frequency of each PWM output to the same value using the FREQUENCY_SWITCH PMBus command. Set the

time point where the controller samples the voltage to be regulated by setting the EADC_SAMPLE_TRIGGER

value to the minimum value (228-240 nsec before the end of the switching period).

When configuring a PWM engine to run synchronous to an external sync signal, the switching period must be set

to be longer than the period of the sync signal by setting the value of the FREQUENCY_SWITCH command to

be lower than the frequency of the sync signal. This way the external sync signal will reset the PWM ramp

counter before it is internally reset. In this operating condition, the error ADC sample trigger time must be set to:

1

0.95

EADC_SAMPLE_TRIGGER ³

-

+ 248ns

F

SW

sync

(8)

where F_swis the switching frequency set by FREQUENCY_SWITCH and F_syncis the minimum synchronization

frequency. The factor of 0.95 is due to the 5% tolerance on the internal clock in the controller. This will ensure

that the regulation voltage is sampled "just in time" to calculate the appropriate control effort for each switching

period. This is shown in Figure 11.

23

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

ADC sample = Period-EADC trigger

Early sync

Sync-in

EADC Threshold

Convert ADC

sample and

calculate

insufficient time

to convert ADC

sample

compensated

error

Compensated error

effort

PWM pulse

Figure 11. Relationship Of EADC Trigger To External Sync

If two rails share a common sync source other than the SyncIn terminal, they must have the same delay. When

the SyncIn terminal is used as a sync source, the delay is applied using a different register (EV1) than when

using the other sources (which use the PhaseTrig registers). Using the EV1 register introduces delay in the

control loop calculation that will introduce phase loss that must be taken into consideration when calculating the

loop compensation. Therefore, under most conditions it will be desirable to set the delay to zero for the PWM

signal synchronized by the SyncIn terminal.

8.3.16 Output Current Measurement

Terminals CS1A, CS2A, CS3A, and CS4A are used to measure either output current or inductor current in each

of the controlled power stages. PMBus commands IOUT_CAL_GAIN and IOUT_CAL_OFFSET are used to

calibrate each measurement. See the UCD92xx PMBus Command Reference (SLUU337) for specifics on

configuring this voltage to current conversion.

When the measured current is outside the range of either the over-current or under-current fault threshold, a

current limit fault is declared and the UCD9244 performs the PMBus configured fault recovery. ADC current

measurements are digitally averaged before they are compared against the over-current and under-current

warning and fault thresholds. The output current is measured at a rate of one output rail per t_Ioutmicroseconds.

The current measurements are then passed through a digital smoothing filter to reduce noise on the signal and

prevent false errors. The output of the smoothing filter asymptotically approaches the input value with a time

constant that is approximately 3.5 times the sampling interval.

Table 5. Output Current Filter Time Constants

NUMBER OF

OUTPUT CURRENT

FILTER

OUTPUT RAILS

SAMPLING INTERVALS (µs)

TIME CONSTANT τ (ms)

1

2

3

4

200

400

600

800

0.7

1.4

2.1

2.8

This smoothed current measurement is used for output current fault detection; see the Over-Current Detection

section. The smoothed current measurement is also reported in response to a PMBus request for a current

reading.

8.3.17 Current Sense Input Filtering

Each power stage current is monitored by the device at the CS terminals. The device monitors the current with a

12-bit ADC and also monitors the current with a digitally programmable analog comparator. The comparator can

be disabled by writing a zero to the FAST_OC_FAULT_LIMIT.

24

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

Because the current sense signal is both digitally sampled and compared to the programmable over-current

threshold, it should be conditioned with an RC network acting as an anti-alias filter. If the comparator is disabled,

the CS input should be filtered at 35% of the sampling rate. An RC network with this characteristic can be

calculated as

N_railsT

Iout

R = 0.45

C

(9)

where N_railsis the number of rails configured and T_Ioutis the sample period for the current sense inputs.

Therefore, when the comparator is not used, the recommended component values for the RC network are C = 10

nF and R = 35.7 kΩ.

When the fast over-current comparator is used, the filter corner frequency based on the ADC sample rate may

be too slow and a corner frequency that is a compromise between the requirements of fast over-current detection

and attenuating aliased content in the sampled current must be sought. In this case, the filter corner frequency

can be calculated based on the time to cross the over-current threshold.

V_{OC_thres}= V_{CS_nom}+ DV_Imon(1- e^{-t t}

)

(10)

where V_{OC_thres}is the programmed OC comparator threshold, V_{CS_nom}is the nominal CS voltage, ΔV_Imonis the

change in CS voltage due to an over-current fault and τ is the filter time constant. Using the equation for the

comparator voltage above, the RC network values can be calculated as

T_det

C

1

R =

´

ln DV

(

- ln DV_Imon- V_{OC_thres}+ V_{CS_nom}

(

)

Imon

(11)

where T_detis the time to cross the over-current comparator threshold. For T_det= 10 µs, ΔV_Imon= 1.5V, V_{OC_thres}

=

2.0V and V_{CS_nom}= 1.5V, the corner frequency is 6.4 kHz and the recommended RC network component values

are C = 10 nF and R = 2.49 kΩ.

8.3.18 Over-Current Detection

Several mechanisms are provided to sense output current fault conditions. This allows for the design of power

systems with multiple layers of protection.

1. Integrated gate drivers such as the UCD72xx family can be used to generate the FLT signal. The driver

monitors the voltage drop across the high side FET and if it exceeds a resistor/voltage programmed

threshold, the driver activates its fault output. A logic high signal on the FLT input causes a hardware

interrupt to the internal CPU, which then disables the DPWM output. This process takes about 14

microseconds.

2. Inputs CS1A, CS2A, CS3A, and CS4A each drive an internal analog comparator. These comparators can be

used to detect the voltage output of a current sense circuit. Each comparator has a separate threshold that

can be set by the FAST_OC_FAULT_LIMIT PMBus command. Though the command is specified in

amperes, the hardware threshold is programmed with a value between 31mV and 2V in 64 steps. The

relationship between amperes to sensed volts is configured by the IOUT_CAL_GAIN command. When the

current sense voltage exceeds the threshold, the corresponding DPWM output is driven low on the voltage

rail with the fault.

3. Each Current Sense input to the UCD9244 is also monitored by the 12-bit ADC. Each measured value is

scaled using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands and then passed through a digital

smoothing filter. The smoothed current measurements are compared to fault and warning limits set by the

IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT commands. The action taken when an OC fault is

detected is defined by the IOUT_OC_FAULT_RESPONSE command.

Because the current measurement is averaged with a smoothing filter, the response time to an over-current

condition depends on a combination of the time constant (τ) from Table 5, the recent measurement history, and

how much the measured value exceeds the over-current limit. When the current steps from a current (I₁) that is

less than the limit to a higher current (I₂) that is greater than the limit, the output of the smoothing filter is

I_smoothedt = I + I -I 1- e^{-t t}

( )

(

)

(

)

1

2

1

(12)

At the point when I_smoothedexceeds the limit, the smoothing filter lags time, t_lagis

25

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

æ

ç

è

ö

÷

ø

I₂-I₁

I₂-I

t_lag= tln

limit

(13)

The worst case response time to an over-current condition is the sum of the sampling interval (Table 5) and the

smoothing filter lag, t_lagfrom Equation 13.

8.3.19 Input Voltage Monitoring

The VinMon terminal on the UCD9244 monitors the input voltage. The VinMon terminal is monitored using the

internal 12-bit ADC which has a dynamic range of 0 to 2.5V. The fault thresholds for the input voltage are set

using the VIN_OV_FAULT_LIMIT and VIN_UV_FAULT_LIMIT commands. The scaling for Vin is set using the

VIN_SCALE_MONITOR command.

8.3.20 Input UV Lockout

The input supply lock-out voltage thresholds are configured with the VIN_ON and VIN_OFF commands. When

input supply voltage drops below the value set by VIN_OFF, the device starts a normal soft stop ramp. When the

input supply voltage drops below the voltage set by VIN_UV_FAULT_LIMIT, the device performs as configured

by the VIN_UV_FAULT_RESPONSE command. For example, when the bias supply for the controller is derived

from another source, the response code can be set to "Continue" or "Continue with delay," and the controller

attempts to finish the soft stop ramp. If the bias voltages for the controller and gate driver are uncertain below

some voltage, the user can set the UV fault limit to that voltage and specify the response code to be "shut down

immediately," disabling all DPWM outputs. VIN_OFF sets the voltage at which the output voltage soft-stop ramp

is initiated, and VIN_UV_FAULT_LIMIT sets the voltage where power conversion is stopped.

8.3.21 Temperature Monitoring

The UCD9244 monitors temperature using the 12-bit ADC. The ADC12 is read every 100us and combined into a

running sum. At the end of each 100ms monitoring interval, the ~1000 sample in the running sum are averaged

together and the running sum is restarted. These averaged values are used to calculate the temperature from

external temperature sensors. These same values may be read directly using the READ_AUX_ADCS PMBus

command.

The averaged values are passed through an additional digital smoothing filter to further reduce the chance of

reporting false over-temperature events. The smoothing filter has a time constant of 1.55 seconds.

8.3.22 Auxiliary ADC Input Monitoring

Unused external temperature sensor inputs may be used for general-purpose analog monitoring. The

READ_AUX_ADCS PMBus command returns a block of four 16-bit values, each of which is the average of

multiple raw measurements from the Temp/AuxADC inputs. A value of 0 corresponds to 0.00V and a value of

65535 corresponds to 2.50V. Unlike many other variables that can be monitored via PMBus, no mechanism is

provided for adjusting the gain or offset of the Aux ADC measurements.

When using the temperature sensor inputs as Auxiliary ADCs, the temperature warning and faults should be

disabled to prevent shut-downs due to non-existent over-temperature conditions.

8.3.23 Soft Start, Soft Stop Ramp Sequence

The UCD9244 performs soft start and soft stop ramps under closed-loop control.

Performing a start or stop ramp or tracking is considered a separate operational mode. The other operational

modes are normal regulation and light load regulation. Each operational mode can be configured to have an

independent loop gain and compensation. Each set of loop gain coefficients is called a "bank" and is configured

using the CLA_GAINS PMBus command.

Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal

reference toward the commanded reference voltage at the rate specified by the TON_RISE time and

VOUT_COMMAND. The DPWM outputs are enabled when the internal ramp reference equals the preexisting

voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width specified by

DRIVER_MIN_PULSE. This ensures that a constant ramp rate is maintained, and that the ramp is completed at

the same time it would be if there had not been a pre-bias condition.

26

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

Figure 12 and Figure 13 show the operation of soft-start and soft-stop ramps.

Figure 13. Soft-Stop Ramp

Figure 12. Soft-Start Ramp

When a voltage rail is in its idle state, the DPWM outputs are disabled, and the differential voltage on the

EAP/EAN terminals are monitored by the controller. During idle the Vref DAC is adjusted to match the feedback

voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the

start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is

required to match the measured voltage on the rail. Nominally this is calculated as Vout / Vin. If the pre-bias

voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the

DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage

has increased to the point where the required duty cycle exceeds the specified minimum duty.

Once a soft start/stop ramp has begun, the output is controlled by adjusting the Vref DAC at a fixed rate and

allowing the digital compensator control engine to generate a duty cycle based on the error. The Vref DAC

adjustments are made at a rate of 10 kHz and are based on the TON_RISE or TOFF_FALL PMBus configuration

parameters.

Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when

the DPWM signals become active, the time from when the controller starts processing the turn-on command to

the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or minimum duty

cycle.

During a normal ramp (i.e. no tracking, no current limiting events and no EADC saturation), the set point slews at

a pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the

compensator follows this ramp up to the regulation point.

Because the EADC in the controller has a limited range, it may saturate due to a large transient during a

start/stop ramp. If this occurs, the controller overrides the calculated set point ramp value, and adjusts the Vref

DAC in the direction to minimize the error. It continues to step the Vref DAC in this direction until the EADC

comes out of saturation. Once it is out of saturation, the start ramp continues, but from this new set point voltage;

and therefore, has an impact on the ramp time.

8.3.24 Non-Volatile Memory Error Correction Coding

The UCD9244 uses Error Correcting Code (ECC) to improve data integrity and provide high reliability storage of

Data Flash contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written

into the Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array.

These extra check bits, along with the hardware ECC algorithm, allow for any single bit error to be detected and

corrected when the Data Flash is read.

27

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

8.3.25 Data Logging

The UCD9244 maintains a data log in non-volatile memory. This log tracks the peak internal and external

temperature sensor measurements, peak current measurements and fault history. The PMBus commands and

data format for the Data Logging can be found in the UCD92xx PMBus Command Reference (SLUU337).

8.4 Device Functional Modes

8.4.1 4-Bit VID Mode

In 4-bit VID mode, the four VID input signals are used to provide the four bits of VID data, as shown in the table

below. The VID lines are level-sensitive, and are periodically polled every 400µs. When the VID lines are

changed to command a new voltage, there may be a delay of 500 to 600µs while the UCD9244 confirms that the

VID signal levels are stable. The output voltage will then slew to the new setpoint voltage at the rate specified by

the PMBus VOUT_TRANSITION_RATE command.

TERMINAL

VID_A

PURPOSE

RAIL 1

VID1A

VID1B

VID1C

VID1S

RAIL 2

VID2A

VID2B

VID2C

VID2S

RAIL 3

VID3A

VID3B

VID3C

VID3S

RAIL 4

VID4A

VID4B

VID4C

VID4S

Data bit 0 (least significant bit)

Data bit 1

VID_B

VID_C

Data bit 2

VID_S

Data bit 3 (most significant bit)

8.4.2 6-Bit VID Mode

In 6-bit VID mode, the four VID input signals are used to provide the six bits of VID data, as shown in the table

below. Each of the three data lines (VID_A, VID_B, and VID_C) carries two bits of data per VID code. The bits

are clocked and selected by the VID_S select line.

TERMINAL PURPOSE

RAIL 1

RAIL 2

RAIL 3

RAIL 4

VID_A

VID_B

VID_C

VID_S

Data bit 0 when VID_S is low,

Data bit 3 when VID_S is high

VID1A

VID2A

VID3A

VID4A

Data bit 1 when VID_S is low,

Data bit 4 when VID_S is high

VID1B

VID1C

VID1S

VID2B

VID2C

VID2S

VID3B

VID3C

VID3S

VID4B

VID4C

VID4S

Data bit 2 when VID_S is low,

Data bit 5 when VID_S is high

Select Line:

Low= LSB, High = MSB

The falling edge of the VID_S line triggers the UCD9244 to read bits 2:0 on the three VID data lines. The rising

edge of VID_S triggers the UCD9244 to read bits 5:3 on the three VID data lines and calculate a new VOUT

setpoint. This calculation takes from 35 to 135µs. The output voltage will then slew to the new setpoint voltage at

the rate specified by the VOUT_TRANSITION_RATE PMBus command.

VID_S

Lower Half

VID_A = bit 0

VID_B = bit 1

UpperHalf

VID_A = bit 3

VID_B = bit 4

Lower Half

VID_A = bit 0

VID_B = bit 1

Upper Half

VID_A = bit 3

VID_B = bit 4

VID_A

VID_B

VID_C

VID_C = bit 2 VID_C = bit 5

VOUT

Figure 14. 6-Bit VID Data Transfer

28

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

The set-up time on the data lines is 0 µs. All four VID lines must hold at the same level for some time after a

change in the VID_S line to allow the UCD9244 to read and validate the data signals and perform necessary

voltage calculations. The UCD9244 can tolerate single hold times as short as 70µs, but does not have sufficient

computation power to sustain continuous VID messaging that quickly. It is expected that the hold time will be at

least 125µs for sustained operations. It is recommended that the DSP only send VID messages when the

regulated voltage needs to change; sending the same VID code repeatedly and continuously provides no benefit.

Figure 15 and Table 6 illustrate the critical timing measurements as they apply to the 6-bit VID interface.

Tsu

Thd

Tchi

Tclo

VID_S

VID_A,

VID_B,

VID_C

Tr

Tf

Tvo

VOUT

Figure 15. 6-Bit VID Timing

Table 6. 6-Bit VID Timing

SYMBOL

Tr

PARAMETER

MIN

–

TYP

MAX

2.5

UNITS

µs

Data and clock rise time

Data and clock fall time

Data setup before changing clock

Data hold until next clock change

Clock high time

Tf

–

0.3

µs

Tsu

0

µs

Thd

Tchi

Tclo

Tvo

70

35

µs

125

µs

Clock low time

µs

Response time from rising edge of VID_S to start of

Vout slewing to new setpoint

135

µs

8.4.3 8-Bit VID Mode

In 8-bit VID mode, the four VID input signals are not used. Instead, an 8-bit VID code is transmitted to the

UCD9244 through the PMBus / I2C port using one of the VID_CODE_RAILn commands, where n is the rail

number from 1 to 4.

NAME

DESCRIPTION⁽¹⁾

CODE

0xBB

0xBC

0xBD

0xBE

0xBF

VID_CONFIG

Selects the VID mode, sets the upper and lower voltage limits, and the starting voltage code at power-up.

VID_CODE_RAIL1 Selects the VID code used to set the output voltage for Rail 1.

VID_CODE_RAIL2 Selects the VID code used to set the output voltage for Rail 2.

VID_CODE_RAIL3 Selects the VID code used to set the output voltage for Rail 3.

VID_CODE_RAIL4 Selects the VID code used to set the output voltage for Rail 4.

(1) For a complete description of the serial VID commands, see the UCD92xx PMBus Command Reference(SLUU337)

29

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

V_OUT

T_MSGVO

T_MSG

T_VO

Addr

Cmd

Data

PEC

Start

Stop

PMBus Clock

PMBus Data

ACK

Figure 16. PMBus Timing For VID_CODE_RAILn Command

Table 7. Typical PMBus Timing For VID_CODE_RAILn Command at 400kHz

SYMBOL

PARAMETER

CONDITIONS

TYP

UNITS

T_msgPEC

Message Transmit Time, with PEC

400 kHz clock, PEC enabled

162 – 256

126 – 221

28 – 140

169 – 314

µs

Message Transmit Time, without PEC

End of message until Vout starts changing

Start of message until Vout start changing

T_vo

µs

T_msgvo

400 kHz clock, PEC disabled

The total time to transmit the serial VID command will vary depending on the other tasks that the UCD92xx

processor is performing. Typical packet times varied from 162 to 256µs when the PMBus is configured for a 400

kb/s transfer rate running and the optional PEC byte is enabled. Disabling the PEC byte saves about 35µs and

the transfer times are from 126 to 221µs. Note that these are not specified best-case/worst-case timings, but

indicate a range given the typical acknowledge overhead in the host and controller.

After the VID packet has been received by the controller there is a delay before the set-point reference DAC is

updated. This delay time varies from ~28µs to 140µs (typical ) depending on the existing priority of updating set-

point reference DAC when the command is received.

With a 221µs packet transfer time, it would seem possible to send 4500 VID messages per second to the device.

Very short bursts at this rate might be acceptable, but doing so for sustained periods could overwhelm the

available processing resources in the UCD92xx, causing it to be delayed in performing its other monitoring and

fault response tasks. In addition, if multiple hosts are trying to talk on the PMBus at such high rates then bus

contention will occur with great regularity.

To prevent these issues, it is prudent to limit the total VID messaging rate to less than 4 messages per

millisecond. In a system with four independent hosts, each host might need to be limited to less than 1 message

per millisecond. Therefore, to minimize PMBus traffic, it is best to only issue the VID command when a voltage

change is required. There is no benefit to sending the same VID code continuously and repeatedly.

8.4.4 Current Foldback Mode

When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the

UCD9244 attempts to continue to operate by reducing the output voltage in order to maintain the output current

at the value set by IOUT_OC_FAULT_LIMIT. This continues indefinitely as long as the output voltage remains

above the minimum value specified by IOUT_OC_LV_FAULT_LIMIT. If the output voltage is pulled down to less

than that value, the device responds as programmed by the IOUT_OC_LV_FAULT_RESPONSE command.

30

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

9 Applications and Implementation

9.1 Application Information

9.1.1 Automatic System Identification (Auto-ID™)

By using digital circuits to create the control function for a switch-mode power supply, additional features can be

implemented. One of those features is the measurement of the open loop gain and stability margin of the power

supply without the use of external test equipment. This capability is called automatic system identification or

Auto-ID™. To identify the frequency response, the UCD9244 internally synthesizes a sine wave signal and

injects it into the loop at the Vref DAC. This signal excites the system, and the closed-loop response to that

excitation can be measured at another point in the loop. The UCD9244 measures the response to the excitation

at the output of the digital compensator. From the closed-loop response, the open-loop transfer function is

calculated. The open-loop transfer function may be calculated from the closed-loop response.

Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be

divided out of the measured open-loop gain. In this way the UCD9244 can accurately measure the power

stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and

send the measurement data back to a host through the PMBus interface without the need for external test

equipment. Details of the Auto-ID™ PMBus measurement commands can be found in the UCD92xx PMBus

Command Reference (SLUU337).

9.2 Typical Applications

Figure 17 shows the UCD9244 power supply controller as part of a system that provides the regulation of two

independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding

into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate

drivers for each power stage.

The ±V_senserail signals must be routed to the EAp/EAn input that matches the DPWM number that controls the

output power stage. For example, the power stage driven by DPWM1A must have its feedback routed to EAP1

and EAN1.

31

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

9.2.1 Design Requirements

APPROXIMATE

DESIGN PARAMETER

UNITS

LOWER BOUND

UPPER BOUND

K_DC

F_Z

60

3 kHz

0.1

103

Fsw/5

5.0

dB

kHz

n/a

Q_Z

9.2.2 Detailed Design Procedure

9.2.2.1 Digital Compensator

Each voltage rail controller in the UCD9244 includes a digital compensator. The compensator consists of a

nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter

section cascaded with a first order IIR filter section.

The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the

compensator coefficients. The design tool allows the compensator to be described in terms of the pole

frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power™

Designer can be used to characterize the power stage so that the compensator coefficients can be chosen based

on the total loop gain for each feedback system. The coefficients of the filter sections are generated through

modeling the power stage and load.

Additionally, the UCD9244 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or

tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is

below the configured light load threshold.

Limit 3

Limit 2

Limit 1

Limit 0

Thresold

Logic

B01

B11

B21

Gain 4

Gain 3

Gain 2

Gain 1

Gain 0

z^-1

Clamp

z^-1

Nonlinear Gain Block

2nd Order Filter Section

A11

A21

Duty out

eADC

B12

z^-1

Clamp

A21

1st Order Filter Section

Figure 18. Digital Compensator

To calculate the values of the digital compensation filter continuous-time design parameters K_DC, F_Zands Q_Zare

entered into the Fusion Digital Power Designer software (or it calculates them automatically). Where the

compensating filter transfer function is

33

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

S²

s

+

+1

2

w

w Q_Z

Z

H s = K

( )

DC

æ

ö

÷

ø

s

+1

ç

w

è

P2

(14)

There are approximate limits the design parameters K_DC, F_Zands Q_Z. Though design parameters beyond these

upper a lower bounds can be used to calculate the discrete-time filter coefficients, there will be significant round-

off error when the continuous-time floating-point design parameters are converted to the discrete-time fixed-point

integer coefficients to be downloaded to the controller.

The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from

zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and

Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to

be symmetrical. For example, the four limit registers could all be set to positive values causing the Gain 0 value

to set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.

The cascaded 1^storder filter section is used to generate the third zero and third pole.

34

UCD9244-EP

www.ti.com.cn

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

10 Power Supply Recommendations

The recommended power supply for analog and digital is from 3 V to 3.6 V.

11 Layout

11.1 Layout Guidelines

The UCD9244 device has separate analog and digital ground terminals, and separate analog, digital, and I/O

power terminals. Tying the analog and digital ground together to a ground plane under the controller has been

shown to produce good results. The V33A terminal requires very good decoupling. If desired, this terminal can be

separated from the V33D and V33IO terminals with a ferrite bead; in most cases, this bead is not necessary.

11.2 Layout Example

4.7 mf

0.1 mf

on 3.3 V

0.1 mf

on 1.8 V

0.1 mf

on 3.3 V

Figure 19. Recommended Decoupling Capacitor Layout

Refer to design guide SLUU490 for details.

35

UCD9244-EP

ZHCSC55A –JANUARY 2014–REVISED MARCH 2014

www.ti.com.cn

12 Device and Documentation Support

12.1 Trademarks

TMS320C6670, TMS320C6678, Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

12.2 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

36

重要声明

德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据

JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售

都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。

TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，

客户应提供充分的设计与操作安全措施。

TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予的直接或隐含权

限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服务的许可、授权、或认可。使用

此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它知识产权方面的许可。

对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行

复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。

在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件或服务的所有明

示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。

客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品相关的所有法

律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障

及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因在此类安全关键应用中使用任何 TI 组件而

对 TI 及其代理造成的任何损失。

在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用

的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。

TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。

只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面

向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独力负责满足与此类使用相关的所有

法律和法规要求。

TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要

求，TI不承担任何责任。

产品

应用

www.ti.com.cn/telecom

数字音频

www.ti.com.cn/audio

www.ti.com.cn/amplifiers

www.ti.com.cn/dataconverters

www.dlp.com

通信与电信

计算机及周边

消费电子

能源

放大器和线性器件

数据转换器

DLP® 产品

DSP - 数字信号处理器

时钟和计时器

接口

www.ti.com.cn/computer

www.ti.com/consumer-apps

www.ti.com/energy

www.ti.com.cn/dsp

工业应用

医疗电子

安防应用

汽车电子

视频和影像

www.ti.com.cn/industrial

www.ti.com.cn/medical

www.ti.com.cn/security

www.ti.com.cn/automotive

www.ti.com.cn/video

www.ti.com.cn/clockandtimers

www.ti.com.cn/interface

www.ti.com.cn/logic

逻辑

电源管理

www.ti.com.cn/power

www.ti.com.cn/microcontrollers

www.ti.com.cn/rfidsys

www.ti.com/omap

微控制器 (MCU)

RFID 系统

OMAP应用处理器

无线连通性

www.ti.com.cn/wirelessconnectivity

德州仪器在线技术支持社区

www.deyisupport.com

IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

UCD9244MRGCTEP

VQFN

RGC

64

250

180.0

16.4

9.3

1.1

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2015

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGC 64

SPQ

Length (mm) Width (mm) Height (mm)

210.0 185.0 35.0

UCD9244MRGCTEP

250

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGC 64

9 x 9, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224597/A

www.ti.com

PACKAGE OUTLINE

RGC0064B

VQFN - 1 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

9.15

8.85

A

B

PIN 1 INDEX AREA

9.15

8.85

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 7.5

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

17

32

16

33

65

SYMM

2X 7.5

4.25 0.1

60X

0.5

1

48

0.30

0.18

64X

49

64

PIN 1 ID

0.1

C A B

0.5

0.3

64X

0.05

4219010/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGC0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.25)

SEE SOLDER MASK

DETAIL

SYMM

64X (0.6)

49

64

64X (0.24)

1

48

60X (0.5)

(R0.05) TYP

(1.18) TYP

(8.8)

65

SYMM

(0.695) TYP

(

0.2) TYP

VIA

33

16

32

17

(0.695) TYP

(1.18) TYP

(8.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219010/A 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGC0064B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

SYMM

64X (0.6)

64

49

64X (0.24)

1

48

60X (0.5)

(R0.05) TYP

9X ( 1.19)

65

SYMM

(8.8)

(1.39)

33

16

17

32

(1.39)

(8.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 65

71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4219010/A 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	UCD9244MRGCTEP
厂家：	TEXAS INSTRUMENTS
描述：	支持 4 位、6 位或 8 位 VID 的数字 PWM 系统控制器 \| RGC \| 64 \| -55 to 125 控制器开关
文件：	总46页 (文件大小：2284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCD9244MRGCTEP [TI]

相关型号：

UCD9244RGCR

UCD9244RGCT

UCD9246

UCD9246RGCR

UCD9246RGCT

UCD9248

UCD9248PFC

UCD9248PFCR

UCD9501

UCD9501PZA

UCD9501PZS

UCE-1.2/25-D48PHL2-C