ULN2003BDR [TI]
支持 3V 输入电压且具有较低成本的 50V、7 通道达林顿阵列 | D | 16 | -40 to 105;
| 型号： | ULN2003BDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持 3V 输入电压且具有较低成本的 50V、7 通道达林顿阵列 | D | 16 | -40 to 105 开关 光电二极管 晶体管 |
| 文件： | 总25页 (文件大小：906K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ULN2003B
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
ULN2003B 高电压、高电流达灵顿晶体管阵列
1 特性
3 说明
1
•
•
•
•
•
•
输出泄漏电流 (ICEX) 超过 ULN2003A 的四倍
ULN2003B 是一款高电压、高电流达灵顿晶体管阵
列。 这个器件包含 7 个高压输出型 NPN 达灵顿晶体
管对，这些晶体管具有针对电感负载开关的共阴极钳位
二极管。 单个达灵顿对的集电极电流额定值为
500mA。 将达灵顿对并联可以提供更高的电流。
500mA 额定集电极电流（单路输出）
高压输出 50V
钳位二极管输出
可兼容各类逻辑的输入
继电器驱动器应用
ULN2003B 的每个达灵顿对具有一个 2.7kΩ 基极串联
电阻器，可直接用于晶体管逻辑 (TTL) 或互补金属氧
化物半导体 (CMOS) 器件。
2 应用
•
•
•
•
•
•
继电器驱动器
器件信息(1)
封装
锤式驱动器
部件号
封装尺寸（标称值）
19.30mm x 6.35mm
9.90mm x 3.91mm
5.00mm x 4.40mm
灯驱动器
PDIP (16)
显示屏驱动器（LED 和气体放电元件）
线路驱动器
ULN2003B
SOIC (16)
TSSOP (16)
逻辑缓冲器
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
4 简化电路原理图
9
COM
16
1C
1
2
3
4
5
6
7
1B
2B
3B
4B
5B
6B
7B
15
2C
14
3C
13
4C
12
5C
11
6C
10
7C
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLRS064
ULN2003B
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
目录
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化电路原理图........................................................ 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 Handling Ratings ...................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics, TA = 25°C ....................... 5
7.6 Electrical Characteristics, TA = –40°C to 105°C ...... 5
7.7 Switching Characteristics, TA = 25°C........................ 5
7.8 Switching Characteristics, TA = –40°C to 105°C ...... 5
7.9 Typical Characteristics.............................................. 6
7.10 Thermal Information................................................ 7
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1 Overview ................................................................... 9
9.2 Functional Block Diagram ......................................... 9
9.3 Feature Description................................................... 9
9.4 Device Functional Modes........................................ 10
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 器件和文档支持 ..................................................... 13
13.1 商标....................................................................... 13
13.2 静电放电警告......................................................... 13
13.3 术语表 ................................................................... 13
14 机械封装和可订购信息 .......................................... 13
8
5 修订历史记录
Changes from Original (June 2014) to Revision A
Page
•
完整版的最初发布版本。 ....................................................................................................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
ULN2003B
www.ti.com.cn
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
D, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
2B
3B
4B
5B
6B
7B
E
1C
2C
3C
4C
5C
6C
7C
COM
Pin Functions
PIN
I/O
DESCRIPTION
NAME
<1:7>B
<1:7>C
E
NO.
1 - 7
16 - 10
7
Input
Output
–
Channel 1 through 7 darlington base input
Channel 1 through 7 darlington collector output
Common Emmitter shared by all channels (typically tied to ground)
COM
8
Input/Output Common cathode node for flyback diodes (required for inductive loads)
Copyright © 2014, Texas Instruments Incorporated
3
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ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings(1)
at 25°C free-air temperature (unless otherwise noted)
MIN
MAX
UNIT
V
VCC
Collector-emitter voltage
Clamp diode reverse voltage(2)
Input voltage(2)
50
50
V
VI
30
V
Peak collector current(3)(4)
500
500
–2.5
105
81
mA
mA
A
IOK
Output clamp current
Total emitter-terminal current
Operating free-air temperature range
TA
–40
°C
D package
N package
PW package
θJA
Package thermal impedance(3)(4)
49.7
105
150
°C/W
°C
TJ
Operating virtual junction temperature
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
2000
500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VI
0
0
5
50
V
V
VCC
TJ
Junction Temperature
-40
125
°C
7.4 Thermal Information
ULN2003B
THERMAL METRIC(1)
PW
16 PINS
105.4
32.9
D
16 PINS
81.2
UNIT
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
40.3
51.3
38.9
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.1
10.9
ψJB
50.6
38.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
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ULN2003B
www.ti.com.cn
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
7.5 Electrical Characteristics, TA = 25°C
TEST FIGURE
ULN2003B
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
2.4
2.7
3
IC = 200 mA
IC = 250 mA
IC = 300 mA
IC = 100 mA
IC = 200 mA
IC = 350 mA
II = 0
VI(on)
On-state input voltage
图 12
图 11
VCE = 2 V
V
II = 250 μA,
II = 350 μA,
II = 500 μA,
VCE = 50 V,
IF = 350 mA
VCE = 50 V,
VI = 3.85 V
VR = 50 V
VI = 0,
0.9
1
1.1
1.3
1.6
10
Collector-emitter saturation
voltage
VCE(sat)
V
1.2
ICEX
VF
II(off)
II
Collector cutoff current
Clamp forward voltage
Off-state input current
Input current
图 8
图 14
图 9
μA
V
1.7
65
2
IC = 500 μA
50
μA
mA
μA
pF
图 10
图 13
0.93
1.35
50
IR
Clamp reverse current
Input capacitance
Ci
f = 1 MHz
15
25
7.6 Electrical Characteristics, TA = –40°C to 105°C
PARAMETER
TEST FIGURE
TEST CONDITIONS
ULN2003B
UNIT
V
MIN
TYP
MAX
IC = 200 mA
2.7
2.9
3
VI(on)
On-state input voltage
图 12
VCE = 2 V
IC = 250 mA
IC = 300 mA
IC = 100 mA
IC = 200 mA
IC = 350 mA
II = 0
II = 250 μA,
II = 350 μA,
II = 500 μA,
VCE = 50 V,
IF = 350 mA
VCE = 50 V,
VI = 3.85 V
VR = 50 V
VI = 0,
0.9
1
1.2
1.4
1.7
20
VCE(sat)
Collector-emitter saturation voltage
图 11
V
1.2
ICEX
VF
II(off)
II
Collector cutoff current
Clamp forward voltage
Off-state input current
Input current
图 8
图 14
图 9
μA
V
1.7
65
2.2
IC = 500 μA
30
μA
mA
μA
pF
图 10
图 13
0.93
1.35
100
25
IR
Clamp reverse current
Input capacitance
Ci
f = 1 MHz
15
7.7 Switching Characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH
tPHL
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
0.25
0.25
1
1
μs
μs
VS
–
20
VOH
High-level output voltage after switching
VS = 50 V,
IO ≈ 300 mA
mV
7.8 Switching Characteristics, TA = –40°C to 105°C
PARAMETER
TEST CONDITIONS
MIN
TYP
1
MAX UNIT
tPLH
tPHL
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
10
10
μs
μs
1
VS
–
50
VOH
High-level output voltage after switching
VS = 50 V,
IO ≈ 300 mA
mV
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ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
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7.9 Typical Characteristics
2.2
1.8
1.65
1.5
Iin = 250uA
Iin = 350uA
Iin = 500uA
Iin = 250uA
Iin = 350uA
Iin = 500uA
2
1.8
1.6
1.4
1.2
1
1.35
1.2
1.05
0.9
0.8
0.6
0.4
0.75
0.6
0.45
0
50 100 150 200 250 300 350 400 450 500
IC- Collector Current - mA
0
80 160 240 320 400 480 560 640 720 800
IC- Collector Current - mA
D001
D001
图 1. Collector-Emitter Saturation Voltage vs Collector
图 2. Collector-Emitter Saturation Voltage vs Total Collector
Current (One Darlington)
Current (Two Darlingtons in Parallel)
1400
1200
1000
800
600
400
200
0
700
TJ = 25°C
TJ = 40°C
TJ = 125°C
TJ = 25°C
TJ = -40°C
TJ = 125°C
650
600
550
500
450
400
350
1.8 2.1 2.4 2.7
3
3.3 3.6 3.9 4.2 4.5 4.8 5.1
Input Voltage - V
250
300
350
400
450
500
Input Current - µA
550
600
650
D001
D001
图 3. Input Current vs Input Voltage
图 4. Output Current vs Input Current
1.6
TJ = 25°C
TJ = -40°C
TJ = 125°C
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
100
150
200
250
300
350
400
450
500
IC - Collector Current - mA
D001
图 5. Collector-Emitter Saturation Voltage vs Collector Current
6
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ULN2003B
www.ti.com.cn
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
7.10 Thermal Information
0.5
0.45
0.4
0.5
0.45
0.4
N = 1
N = 2
N = 3
N = 4
N = 5
N = 6
N = 7
N = 1
N = 2
N = 3
N = 4
N = 5
N = 6
N = 7
0.35
0.3
0.35
0.3
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0.05
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Duty Cycle
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Duty Cycle
1
D001
D001
图 6. D Package Maximum collector Current vs Duty Cycle
图 7. PW Package Maximum collector Current vs Duty Cycle
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ULN2003B
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
8 Parameter Measurement Information
Open
Open
V
V
CE
CE
I
I
I(off)
I
C
CEX
Open
图 8. ICEX Test Circuit
图 9. II(off) Test Circuit
Open
Open
I
C
h
=
I
FE
I(on)
I
I
V
Open
I
V
CE
I
I
I
C
图 10. II Test Circuit
图 11. hfe , VCE(sat) Test Circuit
Open
V
R
I
R
Open
V
V
CE
I(on)
I
C
图 12. VI(on) Test Circuit
图 13. IR Test Circuit
V
F
I
F
Open
图 14. VF Test Circuit
8
版权 © 2014, Texas Instruments Incorporated
ULN2003B
www.ti.com.cn
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
9 Detailed Description
9.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This is due to it's
integration of 7 Darlington transistors that are capable of sinking up to 500 mA and wide GPIO range capability.
The ULN2003B comprises seven high voltage, high current NPN Darlington transistor pairs. All units feature a
common emitter and open collector outputs. To maximize their effectiveness, these units contain suppression
diodes for inductive loads. The ULN2003B has a series base resistor to each Darlington pair, thus allowing
operation directly with TTL or CMOS operating at supply voltages of 5.0 V or 3.3 V. The ULN2003B offers
solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and LEDs.
Applications requiring sink currents beyond the capability of a single output may be accommodated by paralleling
the outputs.
This device can operate over a wide temperature range (–40°C to 105°C).
9.2 Functional Block Diagram
COM
Output
C
2.7 kΩ
Input
B
7.2 kΩ
3 kΩ
E
All resistor values shown are nominal.
图 15. Schematic (Each Comparator)
9.3 Feature Description
Each channel of ULN2003B consists of Darlington connected NPN transistors. This connection creates the effect
of a single transistor with a very high current gain (β2). This can be as high as 10,000 A/A at certain currents.
The very high β allows for high output current drive with a very low input current, essentially equating to
operation with low GPIO voltages.
The GPIO voltage is converted to base current via the 2.7 kΩ resistor connected between the input and base of
the pre-driver Darlington NPN. The 7.2 kΩ & 3.0 kΩ resistors connected between the base and emitter of each
respective NPN act as pull-downs and suppress the amount of leakage that may occur from the input.
The diodes connected between the output and COM pin is used to suppress the kick-back voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply via the kick-back diode.
In normal operation the diodes on base and collector pins to emitter will be reversed biased. If these diode are
forward biased, internal parasitic NPN transistors will draw (a nearly equal) current from other (nearby) device
pins.
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www.ti.com.cn
9.4 Device Functional Modes
9.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, ULN2003B is able to drive inductive loads and supress the
kick-back voltage via the internal free wheeling diodes.
9.4.2 Resistive Load Drive
When driving a resistive load, a pull-up resistor is needed in order for ULN2003B to sink current and for there to
be a logic high level. The COM pin can be left floating for these applications.
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
ULN2003B will typically be used to drive a high voltage and/or current peripheral from an MCU or logic device
that cannot tolerate these conditions. The following design is a common application of ULN2003B, driving
inductive loads. This includes motors, solenoids & relays. Each load type can be modeled by what's seen in
图 16.
10.2 Typical Application
VSUP
ULN2003B
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
COM
3.3V Logic
3.3V Logic
3.3V Logic
VSUP
图 16. ULN2003B as Inductive Load Driver
10
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ULN2003B
www.ti.com.cn
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
Typical Application (接下页)
10.2.1 Design Requirements
For this design example, use the parameters listed in 表 1 as the input parameters.
表 1. Design Parameters
DESIGN PARAMETER
GPIO Voltage
EXAMPLE VALUE
3.3 V or 5.0 V
Coil Supply Voltage
Number of Channels
12 V to 48 V
7
20 mA to 300 mA per channel
100%
Output Current (RCOIL
)
Duty Cycle
10.2.2 Detailed Design Procedure
When using ULN2003B in a coil driving application, determine the following:
•
•
•
•
Input Voltage Range
Temperature Range
Output & Drive Current
Power Dissipation
10.2.2.1 Drive Current
The coil current is determined by the coil voltage (VSUP), coil resistance & output low voltage (VOL or VCE(SAT)).
ICOIL = (VSUP – VCE(SAT)) / RCOIL
(1)
10.2.2.2 Output Low Voltage
The output low voltage (VOL) is the same thing as VCE(SAT) and can be determined by, 图 1, 图 2, or 图 5.
10.2.2.3 Power Dissipation & Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. The number of coils
driven can be determined by 图 6 or 图 7.
For a more accurate determination of number of coils possible, use the below equation to calculate ULN2003B
on-chip power dissipation PD:
N
V
´ILi
P = å
D
OLi
i=1
Where:
N is the number of channels active together.
VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT)
(2)
In order to guarantee reliability of ULN2003B and the system the on-chip power dissipation must be lower that or
equal to the maximum allowable power dissipation (PD(MAX)) dictated by below equation 公式 3.
T
J(MAX) - TA
(
)
PD(MAX)
=
qJA
Where:
TJ(MAX) is the target maximum junction temperature.
TA is the operating ambient temperature.
θJA is the package junction to ambient thermal resistance.
(3)
It is recommended to limit ULN2003B IC’s die junction temperature to less than 125°C. The IC junction
temperature is directly proportional to the on-chip power dissipation.
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www.ti.com.cn
10.2.3 Application Curves
The following curves were generated with ULN2003B driving an OMRON G5NB relay – Vin = 5.0V; Vsup= 12 V &
RCOIL= 2.8 kΩ
13
12
11
10
9
14
12
10
8
8
7
6
6
5
4
4
3
2
2
1
0
0
-0.004
0
0.004
0.008
Time (s)
0.012
0.016
-0.004
0
0.004
0.008
Time (s)
0.012
0.016
D001
D001
图 17. Output Response With Activation of Coil (Turn On)
图 18. Output Response With De-activation of Coil (Turn
Off)
11 Power Supply Recommendations
This part does not need a power supply; however, the COM pin is typically tied to the system power supply.
When this is the case, it is very important to make sure that the output voltage does not heavily exceed the COM
pin voltage. This will heavily forward bias the fly-back diodes and cause a large current to flow into COM,
potentially damaging the on-chip metal or over-heating the part.
12 Layout
12.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive UNL2003B. Care
must be taken to separate the input channels as much as possible, as to eliminate cross-talk. Thick traces are
recommended for the output, in order to drive whatever high currents that may be needed. Wire thickness can be
determined by the trace material's current density and desired drive current.
Since all of the channels currents return to a common emitter, it is best to size that trace width to be very wide.
Some applications require up to 2.5 A.
12.2 Layout Example
1C
2C
1B
2B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
3C
4C
5C
6C
3B
4B
5B
6B
7B
E
10 7C
VCOM
9
GND
图 19. Package Layout
12
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ULN2003B
www.ti.com.cn
ZHCSCU6A –JUNE 2014–REVISED SEPTEMBER 2014
13 器件和文档支持
13.1 商标
All trademarks are the property of their respective owners.
13.2 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.3 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ULN2003BDR
ULN2003BN
ACTIVE
ACTIVE
SOIC
PDIP
D
N
16
16
2500 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 105
-40 to 105
ULN2003B
25
RoHS &
SN
ULN2003BN
UN2003B
Non-Green
ULN2003BPWR
ACTIVE
TSSOP
PW
16
2000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ULN2003BDR
ULN2003BDR
ULN2003BPWR
ULN2003BPWR
SOIC
SOIC
D
D
16
16
16
16
2500
2500
2000
2000
330.0
330.0
330.0
330.0
16.4
16.8
12.4
12.4
6.5
6.5
6.9
6.9
10.3
10.3
5.6
2.1
2.1
1.6
1.6
8.0
8.0
8.0
8.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
TSSOP
TSSOP
PW
PW
5.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ULN2003BDR
ULN2003BDR
ULN2003BPWR
ULN2003BPWR
SOIC
SOIC
D
D
16
16
16
16
2500
2500
2000
2000
356.0
364.0
356.0
364.0
356.0
364.0
356.0
364.0
35.0
27.0
35.0
27.0
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
PDIP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ULN2003BN
N
16
25
506.1
9
600
5.4
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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