US3855BJ [TI]

US3855BJ;


型号：	US3855BJ
厂家：	TEXAS INSTRUMENTS
描述：	US3855BJ
文件：	总9页 (文件大小：430K)
中文：	中文翻译
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UC1855A/B

UC2855A/B

UC3855A/B

High Performance Power Factor Preregulator

FEATURES

DESCRIPTION

• Controls Boost PWM to Near Unity

Power Factor

The UC1855A/B provides all the control features necessary for high

power, high frequency PFC boost converters. The average current mode

control method allows for stable, low distortion AC line current program-

ming without the need for slope compensation. In addition, the UC1855

utilizes an active snubbing or ZVT (Zero Voltage Transition technique) to

dramatically reduce diode recovery and MOSFET turn-on losses, result-

ing in lower EMI emissions and higher efficiency. Boost converter switch-

ing frequencies up to 500kHz are now realizable, requiring only an

additional small MOSFET, diode, and inductor to resonantly soft switch

the boost diode and switch. Average current sensing can be employed us-

ing a simple resistive shunt or a current sense transformer. Using the cur-

rent sense transformer method, the internal current synthesizer circuit

buffers the inductor current during the switch on-time, and reconstructs the

inductor current during the switch off-time. Improved signal to noise ratio

and negligible current sensing losses make this an attractive solution for

higher power applications.

• Fixed Frequency Average Current

Mode Control Minimizes Line Current

Distortion

• Built-in Active Snubber (ZVT) allows

Operation to 500kHz, improved EMI

and Efficiency

• Inductor Current Synthesizer allows

Single Current Transformer Current

Sense for Improved Efficiency and

Noise Margin

• Accurate Analog Multiplier with Line

Compensator allows for Universal

Input Voltage Operation

The UC1855A/B also features a single quadrant multiplier, squarer, and

divider circuit which provides the programming signal for the current loop.

The internal multiplier current limit reduces output power during low line

conditions. An overvoltage protection circuit disables both controller out-

puts in the event of a boost output OV condition.

• High Bandwidth (5MHz), Low Offset

Current Amplifier

• Overvoltage and Overcurrent

protection

• Two UVLO Threshold Options

• 150µA Startup Supply Current Typical

• Precision 1% 7.5V Reference

Low startup supply current, UVLO with hysteresis, a 1% 7.5V reference,

voltage amplifier with softstart, input supply voltage clamp, enable com-

parator, and overcurrent comparator complete the list of features. Avail-

able packages include: 20 pin N, DW, Q, J, and L.

BLOCK DIAGRAM

UDG-94001-2

License Patent from Pioneer Magnetics. Pin numbers refer to DIL-20 J or N packages.

6/98

UC1855A/B

UC2855A/B

UC3855A/B

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

Supply Voltage VCC. . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited

VCC Supply Clamp Current . . . . . . . . . . . . . . . . . . . . . . . 20mA

PFC Gate Driver Current (continuous) . . . . . . . . . . . . . . ± 0.5A

PFC Gate Driver Current (peak) . . . . . . . . . . . . . . . . . . . ± 1.5A

ZVT Drive Current (continuous) . . . . . . . . . . . . . . . . . . . ± 0.25A

ZVT Drive Current (peak) . . . . . . . . . . . . . . . . . . . . . . . ± 0.75A

Input Current (IAC, RT, RVA) . . . . . . . . . . . . . . . . . . . . . . . 5mA

Analog Inputs (except Peak Limit). . . . . . . . . . . . . . −0.3 to 10V

Peak Limit Input . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 6.5V

Softstart Sinking Current . . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA

Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . −55°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C

PLCC-20 & LCC-20 (Top View)

Q or L Package

Currents are positive into, negative out of the specified termi-

nal. Consult Packaging Section of Databook for thermal limita-

tions and considerations of packages. All voltages are

referenced to GND.

DIL–20 (Top View)

J or N Package

SOIC-20 (Top View)

DW Package

ELECTRICAL CHARACTERISTICS: Unless otherwise specified: VCC = 18V, R_T= 15k, RVS = 23k, CT = 470pF, CI =

150pF, VRMS = 1.5V, IAC = 100µA, I_SENSE= 0V, CA_OUT= 4V, VAOUT= 3.5V, VSENSE = 3V. TA = TJ. TA = –55°C to 125°C

(UC1855A/B), –40°C to 85°C (UC2855A/B), 0°C to 70°C (UC3855A/B).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

Overall

Supply Current, OFF

CAO, VAOUT = 0V, VCC = UVLO −0.3V

150

500

µA

Supply Current, OPERATING

VCC Turn-On Threshold

VCCTurn-Off Threshold

VCC Turn-On Threshold

VCC Clamp

UC1855A

15.5

17.5

UC1855A,B

UC1855B

10.5

10.8

I(VCC) = I_CC(on)+ 5mA

Voltage Amplifier

Input Voltage

2.9

−500

3.1

VSENSE Bias Current

Open Loop Gain

500

V_OUT= 2 to 5V

I_LOAD= –300µA

I_LOAD= 300µA

VOUT = 0V

V_OUTHigh

5.75

6.25

0.5

V_OUTLow

0.3

0.6

Output Short Circuit Current

UC1855A/B

UC2855A/B

UC3855A/B

ELECTRICAL CHARACTERISTICS: Unless otherwise specified: VCC = 18V, R_T= 15k, RVS = 23k, CT = 470pF, CI =

150pF, VRMS = 1.5V, IAC = 100µA, I_SENSE= 0V, CA_OUT= 4V, VAOUT= 3.5V, VSENSE = 3V. TA = TJ. TA = –55°C to 125°C

(UC1855A/B), –40°C to 85°C (UC2855A/B), 0°C to 70°C (UC3855A/B).

PARAMETER

Current Amplifier

TEST CONDITIONS

MIN

TYP

MAX UNITS

Input Offset Voltage

Input Bias Current (Sense)

Open Loop Gain

V_CM= − 2.5V

−4

−500

V_CM= 2.5V

500

V_CM= 2.5V, VOUT = 2 to 6V

I_LOAD= −500µA

I_LOAD= 500µA

110

VOUT High

VOUT Low

0.3

0.5

Output Short Circuit Current

Common Mode Range

Gain Bandwidth Product

Reference

V_OUT= 0V

−0.3

F_IN= 100kHz, 10mV, P–P, T_A= 25°C

2.5

MHz

Output Voltage

I_REF= 0mA, TA = 25°C

I_REF= 0mA

7.388

7.313

−15

7.5

7.613

7.688

Load Regulation

Line Regulation

_REF= 1 to 10 mA

VCC = 15 to 35V

REF = 0V

−10

Short Circuit Current

Oscillator

Initial Accuracy

T_A= 25°C

170

200

230

kHz

Voltage Stability

V_CC= 12 to 18V

Line, Temp.

Total Variation

160

4.9

1.1

240

5.9

1.6

kHz

Ramp Amplitude (P–P)

Ramp Valley Voltage

Enable/OVP/Current Limit

Enable Threshold

OVP Threshold

1.8

7.5

400

200

2.2

7.66

600

OVP Hysteresis

200

µA

OVP Propagation Delay

OVP Input Bias Current

PKLIMIT Threshold

PKLIMIT Input Current

PKLIMIT Prop. Delay

Multiplier

V= 7.5V

1.25

1.5

100

1.75

V_PKLIMIT= 1.5V

µA

Output Current - IAC Limited

Output Current - Zero

Output Current - Power Limited

Output Current

IAC = 100µA, VRMS = 1V

IAC = 0µA

−235 −205 −175

−2 −0.2

µA

1/V

VRMS = 1.5V, VAOUT = 5.5V

VRMS = 1.5V, VAOUT = 2V

VRMS = 1.5V VAOUT = 5V

VRMS = 5V, VAOUT = 2V

VRMS = 5V, VAOUT = 5V

Refer to Note 1

−250 −209 −160

−26

−190

−3

−17

Gain Constant

−0.95 −0.85 −0.75

Gate Driver Output

Output High Voltage

Output Low Voltage

Output Low (UVLO)

Output RISE/FALL Time

Output Peak Current

l_OUT= −200mA, VCC = 15V

l_OUT= 200mA

12.8

2.2

500

1.5

l_OUT= 10mA

300

0.9

lOUT = 50mA, VCC = 0V

CLOAD = 1nF

CLOAD = 10nF

1.5

UC1855A/B

UC2855A/B

UC3855A/B

ELECTRICAL CHARACTERISTICS: Unless otherwise specified: VCC = 18V, R_T= 15k, RVS = 23k, CT = 470pF, CI =

150pF, VRMS = 1.5V, IAC = 100µA, I_SENSE= 0V, CA_OUT= 4V, VAOUT= 3.5V, VSENSE = 3V. TA = TJ. TA = –55°C to 125°C

(UC1855A/B), –40°C to 85°C (UC2855A/B), 0°C to 70°C (UC3855A/B).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

ZVT

Reset Threshold

2.3

2.6

2.9

µA

Input Bias Current

Propagation Delay

Maximum Pulse Width

Output High Voltage

Output Low Voltage

V = 2.5V, V_CT= 0

Measured at ZVTOUT

100

400

12.8

l_OUT= −100mA, VCC = 15V

l_OUT= 100mA

2.2

900

1.5

l_OUT= 10mA

300

0.9

Output Low (UVLO)

Output RISE/FALL Time

Output Peak Current

Current Synthesizer

ION to CS Offset

l_OUT= 50mA, V_CC= 0V

C_LOAD= 1nF

C_LOAD= 10nF

0.75

VION = 0V

IAC = 50µA

IAC = 500µA

118

µA

Cl Discharge Current

105

0.3

140

IAC Offset Voltage

0.65

1.1

ION Buffer Slew Rate

ION Input Bias Current

RVS Output Voltage

V/µs

µA

V_ION= 2V

23k from RVS to GND

2.87

3.13

•

Note 1: Gain constant (K) =

at V_RMS= 1.5V, VA_OUT= 5.5V.

•

PIN DESCRIPTIONS

CS: The reconstructed inductor current waveform gener-

ated on the CI pin is level shifted down a diode drop to

this pin. Connect the current amplifier input resistor be-

tween CS and the inverting input of the current amplifier.

The waveform on this pin is compared to the multiplier

output waveform through the average current sensing

current amplifier. The input to the peak current limiting

comparator is also connected to this pin. A voltage level

greater than 1.5 volts on this pin will trip the comparator

and disable the gate driver output.

CA−: This is the inverting input to the current amplifier.

Connect the required compensation components be-

tween this pin and CAOUT. The common mode operating

range for this input is between −0.3V and 5V.

CAO: This is the output of the wide bandwidth current

amplifier and one of the inputs to the PWM duty cycle

comparator. The output signal generated by this amplifier

commands the PWM to force the correct input current.

The output can swing from 0.1V to 7.5V.

CT: A capacitor from CT to GND sets the PWM oscillator

frequency according to the following equation:

CI: The level shifted current sense signal is impressed

upon a capacitor connected between this pin and GND.

The buffered current sense transformer signal charges

the capacitor when the boost switch is on. When the

switch is off, the current synthesizer discharges the ca-

pacitor at a rate proportional to the dI/dt of the boost in-

ductor current. In this way, the discharge current is

approximately equal to

f ≈

11200 • CT

Use a high quality ceramic capacitor with low ESL and

ESR for best results. A minimum CT value of 200pF in-

sures good accuracy and less susceptibility to circuit lay-

out parasitics. The oscillator and PWM are designed to

provide practical operation to 500kHz.

IAC

–

RRVS

Discharging the CI capacitor in this fashion, a “recon-

structed” version of the inductor current is generated us-

ing only one current sense transformer.

GND: All voltages are measured with respect to this pin.

All bypass and timing capacitors connected to GND

should have leads as short and direct as possible.

UC1855A/B

UC2855A/B

UC3855A/B

PIN DESCRIPTIONS (cont.)

GTOUT: The output of the PWM is a 1.5A peak totem

pole MOSFET gate driver on GTOUT. A series resistor

between GTOUT and the MOSFET gate of at least 10

REF: REF is the output of the precision reference. The

output is capable of supplying 25mA to peripheral cir-

cuitry and is internally short circuit current limited. REF is

ohms should be used to limit the overshoot on GTOUT. disabled and low whenever VCC is below the UVLO

In addition, a low VF Schottky diode should be connected

between GTOUT and GND to limit undershoot and possi-

ble erratic operation.

threshold, and when OVP is below 1.8V. A REF “GOOD”

comparator senses REF and disables the stage until

REF has attained approximately 90% of its nominal

value. Bypass REF to GND with a 0.1µF or larger ce-

ramic capacitor for best stability.

IAC: This is a current input to the multiplier. The current

into this pin should correspond to the instantaneous

value of the rectified AC input line voltage. This is accom-

plished by connecting a resistor directly between IAC and

the rectified input line voltage. The nominal 650mV level

present on IAC negates the need for any additional com-

pensating resistors to accommodate for the zero cross-

ings of the line. A current equal to one fourth of the IAC

current forms one of the inductor current synthesizer in-

puts.

RVS: The nominal 3V signal present on the VSENSE pin

is buffered and brought out to the RVS pin. A current pro-

portional to the output voltage is generated by connect-

ing a resistor between this pin and GND. This current

forms the second input to the current synthesizer.

VAO: This is the output of the voltage amplifier. At a

given input RMS voltage, the voltage on this pin will vary

directly with the output load. The output swing is limited

from approximately 100mV to 6V. Voltage levels below

1.5V on this pin will inhibit the multiplier output.

IMO: This is the output of the multiplier, and the non-

inverting input of the current amplifier. Since this output is

a current, connect a resistor between this pin and ground

equal in value to the input resistor of the current amplifier.

The common mode operating range for this pin is −0.3V

to 5V.

VCC: Positive supply rail for the IC. Bypass this pin to

GND with a 1µF low ESL, ESR ceramic capacitor. This

pin is internally clamped to 20V. Current into this clamp

should be limited to less than 10mA. The UC1855A has a

15.5V (nominal) turn on threshold with 6 volts of hystere-

sis while the UC1855B turns on at 10.5V with 500mV of

hysteresis.

ION: This pin is the current sensing input. It should be

connected to the secondary side output of a current

sensing transformer whose primary winding is in series

with the boost switch. The resultant signal applied to this

input is buffered and level shifted up a diode to the CI ca-

pacitor on the CI pin. The ION buffer has a source only

output. Discharge of the CI cap is enabled through the

current synthesizer circuitry. The current sense trans-

former termination resistor should be designed to obtain

a 1V input signal amplitude at peak switch current.

VRMS: This pin is the feedforward line voltage compen-

sation input to the multiplier. A voltage on VRMS propor-

tional to the AC input RMS voltage commands the

multiplier to alter the current command signal by

1/VRMS to maintain a constant power balance. The in-

put to VRMS is generally derived from a two pole low

pass filter/voltage divider connected to the rectified AC

input voltage. This feature allows universal input supply

voltage operation and faster response to input line fluc-

tuations for the PFC boost preregulator. For most de-

signs, a voltage level of 1.5V on this pin should

correspond to low line, and 4.7V for high line. The input

range for this pin extends from 0 to 5.5V.

OVP: This pin senses the boost output voltage through a

voltage divider. The enable comparator input is TTL com-

patible and can be used as a remote shutdown port. A

voltage level below 1.8V, disables VREF, oscillator, and

the PWM circuitry via the enable comparator. Between

1.8V and VREF (7.5V) the UC1855 is enabled. Voltage

levels above 7.5V will set the PWM latch via the hystere-

tic OVP comparator and disable both ZVTOUT and

GTOUT until the OVP level has decayed by the nominal

hysteresis of 400mV. If the voltage divider is designed to

initiate an OVP fault at 5% of OV, the internal hysteresis

enables normal operation again when the output voltage

has reached its nominal regulation level. Both the OVP

and enable comparators have direct logical connections

to the PWM output and exhibit typical propagation delays

of 200ns.

VSENSE: This pin is the inverting input of the voltage

amplifier and serves as the output voltage feedback point

for the PFC boost converter. It senses the output voltage

through a voltage divider which produces a nominal 3V.

The voltage loop compensation is normally connected

between this pin and VAO. The VSENSE pin must be

above 1.5V at 25°C, (1.9V at –55°C) for the current syn-

thesizer to work properly.

UC1855A/B

UC2855A/B

UC3855A/B

PIN DESCRIPTIONS (cont.)

ZVS: This pin senses when the drain voltage of the main ZVTOUT: The output of the ZVT block is a 750mA peak

MOSFET switch has reached approximately zero volts, totem pole MOSFET gate driver on ZVTOUT. Since the

and resets the ZVT latch via the ZVT comparator. A mini- ZVT MOSFET switch is typically 3X smaller than the

mum and maximum ZVTOUT pulse width are program- main switch, less peak current is required from this out-

put. Like GTOUT, a series gate resistor and Schottky di-

ode to GND are recommended. This pin may also be

used as a high current synchronization output driver.

mable from this pin. To directly sense the ≈400V drain

voltage of the main switch, a blocking diode is connected

between ZVS and the high voltage drain. When the drain

reaches 0V, the level on ZVS is ≈0.7V which is below the

2.6V ZVT comparator threshold. The maximum ZVTOUT

pulse width is approximately equal to the oscillator blank-

ing period time.

For more information see Unitrode Applications Note U-153.

5.992 496 516 MHz

120

Gain

-90

100

120

Phase

Margin

degrees

100

-45 Phase

Degrees

Open-Loop

Gain

-20

0.1

100

1000

10000

-20

-40

-60

Frequency

kHz

10kHz

100kHz

1MHz

log f

10MHz

Figure 1. Current Amplifier Frequency Response

Figure 2. Voltage Amplifier Gain Phase vs Frequency

Figure 3. Voltage Amplifier Input Threshold

Figure 4. Supply Current ON

UC1855A/B

UC2855A/B

UC3855A/B

Figure 5. Multiplier Current Gain Constant

Figure 6. Oscillator Initial Accuracy

UC1855A/B

UC2855A/B

UC3855A/B

TYPICAL APPLICATION

UDG-95165-1

Figure 7. Typical Application

UNITRODE CORPORATION

7 CONTINENTAL BLVD. • MERRIMACK, NH 03054

TEL. (603) 424-2410 FAX (603) 424-3460

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