V62/03609-01XE [TI]
增强型产品 12 位、6MSPS ADC，四通道（可配置）、DSP/uP IF、集成16x Fifo | DA | 32 | -55 to 125;
| 型号： | V62/03609-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品 12 位、6MSPS ADC，四通道（可配置）、DSP/uP IF、集成16x Fifo | DA | 32 | -55 to 125 转换器 模数转换器 |
| 文件： | 总43页 (文件大小：782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ
ꢃ ꢄ ꢇꢊꢋ ꢀ ꢆ ꢌ ꢂꢉꢂ ꢍ ꢂꢋ ꢌꢎ ꢏꢀꢐꢑꢈ ꢒꢎ ꢂ ꢂ ꢐꢌ ꢉ ꢏꢋ ꢑꢓ
ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
D
Internal Voltage References . . . 50 PPM/°C
features
and 5% Accuracy
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
D
D
Glueless DSP Interface
Parallel µC/DSP Interface
Integrated FIFO
D
D
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Available in TSSOP Package
applications
D
D
D
D
D
Enhanced Product Change Notification
D
Radar Applications
†
Qualification Pedigree
D
D
D
D
Communications
High-Speed 6 MSPS ADC
Control Applications
4 Single-Ended or 2 Differential Inputs
High-Speed DSP Front-End
Selected Military Applications
Simultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
DA PACKAGE
(TOP VIEW)
D
D
D
Differential Nonlinearity Error: 1 LSB
Integral Nonlinearity Error: 1.8 LSB
Signal-to-Noise and Distortion Ratio: 68 dB
D0
D1
D2
D3
D4
D5
AINP
1
32
31
30
29
28
27
26
25
24
23
22
AINM
2
at f = 2 MHz
I
BINP
3
D
D
D
D
Auto-Scan Mode for 2, 3, or 4 Inputs
3-V or 5-V Digital Interface Compatible
Low Power: 216 mW Max
BINM
4
REFIN
REFOUT
REFP
REFM
AGND
5
6
5-V Analog Single Supply Operation
BV
7
DD
†
BGND
D6
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
8
9
D7
AV
10
11
12
13
14
15
16
DD
D8
CS0
D9
21 CS1
D10/RA0
D11/RA1
20 WR (R/W)
19 RD
18
17
CONV_CLK (CONVST)
DATA_AV
DV
DD
DGND
description
The THS1206 is a CMOS, low-power, 12-bit,
6 MSPS analog-to-digital converter (ADC). The
speed, resolution, bandwidth, and single-supply
operation are suited for applications in radar,
imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error
correction logic provides for no missing codes over the full operating temperature range. Internal control
registers are used to program the ADC into the desired mode. The THS1206 consists of four analog inputs,
which are sampled simultaneously. These inputs can be selected individually and configured to single-ended
or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off
of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002 − 2003, Texas Instruments Incorporated
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ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢃꢄ ꢇꢊꢋ ꢀ ꢆ ꢌ ꢂꢉꢂꢍ ꢂ ꢋ ꢌꢎꢏꢀꢐꢑ ꢈꢒ ꢎꢂ ꢂ ꢐꢌꢉ ꢏ ꢋꢑꢓ
ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
description (continued)
An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the
application. Two different conversion modes can be selected. In single conversion mode, a single and
simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal
(CONVST). The conversion clock in single conversion mode is generated internally using a clock oscillator
circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the
THS1206. The internal clock oscillator is switched off in continuous conversion mode.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
−55°C to 125°C
TSSOP − DA Tape and reel
THS1206MDAREP
THS1206MEP
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
functional block diagram
AV
DD
DV
DD
2.5 V
3.5 V
1.5 V
REFP
1.225 V
REF
REFOUT
REFM
REFIN
V
S/H
S/H
S/H
S/H
REFM
AINP
AINM
BINP
BINM
DATA_AV
V
REFP
BV
D0
DD
Single
Ended
and/or
Differential
MUX
+
−
12 Bit
Pipeline
ADC
12
12
FIFO
16 × 12
D1
D2
D3
D4
D5
D6
D7
D8
D9
Buffers
D10/RA0
D11/RA1
CONV_CLK (CONVST)
CS0
Logic
and
Control
CS1
RD
Control
Register
BGND
WR (R/W)
AGND
DGND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ
ꢃ ꢄ ꢇꢊꢋ ꢀ ꢆ ꢌ ꢂꢉꢂ ꢍ ꢂꢋ ꢌꢎ ꢏꢀꢐꢑꢈ ꢒꢎ ꢂ ꢂ ꢐꢌ ꢉ ꢏꢋ ꢑꢓ
ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
32
31
30
29
23
24
7
AINP
AINM
BINP
BINM
I
I
I
I
I
I
I
I
I
Analog input, single-ended or positive input of differential channel A
Analog input, single-ended or negative input of differential channel A
Analog input, single-ended or positive input of differential channel B
Analog input, single-ended or negative input of differential channel B
Analog supply voltage
AV
DD
AGND
Analog ground
BV
DD
BGND
Digital supply voltage for buffer
8
Digital ground for buffer
CONV_CLK (CONVST)
15
Digital input. This input is used to apply an external conversion clock in continuous conversion
mode. In single conversion mode, this input functions as the conversion start (CONVST) input.
A high to low transition on this input holds simultaneously the selected analog input channels
and initiates a single conversion of all selected analog inputs.
CS0
22
21
16
I
I
Chip select input (active low)
Chip select input (active high)
CS1
DATA_AV
O
Data available signal, which can be used to generate an interrupt for processors and as a level
information of the internal FIFO. This signal can be configured to be active low or high and can
be configured as a static level or pulse output. See Table 14.
DGND
17
18
I
I
Digital ground. Ground reference for digital circuitry.
Digital supply voltage
DV
DD
D0 – D9
1−6, 9−12
13
I/O/Z Digital input, output; D0 = LSB
D10/RA0
I/O/Z Digital input, output. The data line D10 is also used as an address line (RA0) for the control
register. This is required for writing to the control register 0 and control register 1. See Table 8.
D11/RA1
14
I/O/Z Digital input, output (D11 = MSB). The data line D11 is also used as an address line (RA1) for
the control register. This is required for writing to control register 0 and control register 1. See
Table 8.
REFIN
REFP
28
26
I
Common-mode reference input for the analog input channels. It is recommended that this pin
be connected to the reference output REFOUT.
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal
reference voltage. An external reference voltage at this input can be applied. This option can
be programmed through control register 0. See Table 9.
REFM
25
I
Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal
reference voltage. An external reference voltage at this input can be applied. This option can
be programmed through control register 0. See Table 9.
REFOUT
27
19
20
O
I
Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The
reference output requires a capacitor of 10 µF to AGND for filtering and stability.
†
RD
WR (R/W)
The RD input is used only if the WR input is configured as a write only input. In this case, it is a
digital input, active low as a data read select from the processor. See timing section.
†
I
This input is programmable. It functions as a read-write input R/W and can also be configured
as a write-only input WR, which is active low and used as data write select from the processor.
In this case, the RD input is used as a read input from the processor. See timing section.
†
The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢃꢄ ꢇꢊꢋ ꢀ ꢆ ꢌ ꢂꢉꢂꢍ ꢂ ꢋ ꢌꢎꢏꢀꢐꢑ ꢈꢒ ꢎꢂ ꢂ ꢐꢌꢉ ꢏ ꢋꢑꢓ
ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, DGND to DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.5 V
DD
DD
DD
BGND to BV
AGND to AV
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND − 0.3 V to AV
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 + AGND to AV
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to BV /DV
+ 1.5 V
+ 0.3 V
+ 0.3 V
DD
DD
DD
DD
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
J
Operating free-air temperature range,T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
‡
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
DA
1453 mW
11.62 mW/°C
930 mW
756 mW
291 mW
‡
This is the inverse of the traditional junction-to-ambient thermal resistance (R
informational purposes only.
). Thermal resistances are not production tested and are for
θJA
recommended operating conditions
power supply
MIN NOM
MAX
5.25
5.25
5.25
UNIT
AV
DD
4.75
3
5
3.3
3.3
DV
Supply voltage
V
DD
DD
BV
3
analog and reference inputs
MIN NOM
MAX
UNIT
Analog input voltage in single-ended configuration
V
V
V
V
V
V
V
REFM
REFP
4
Common-mode input voltage V
in differential configuration
(optional)
1
2.5
CM
External reference voltage,V
3.5 AV −1.2
DD
REFP
External reference voltage, V
REFM
(optional)
1.4
1.5
2
Input voltage difference, REFP − REFM
digital inputs
MIN NOM
MAX
UNIT
V
BV
BV
BV
BV
DV
DV
= 3.3 V
2
DD
DD
DD
DD
DD
DD
High-level input voltage, V
IH
= 5.25 V
2.6
V
= 3.3 V
0.6
0.6
V
Low-level input voltage, V
IL
= 5.25 V
V
Input CONV_CLK frequency
= 3 V to 5.25 V
= 3 V to 5.25 V
0.1
80
6
MHz
ns
CONV_CLK pulse duration, clock high, t
83
83
5000
w(CONV_CLKH)
CONV_CLK pulse duration, clock low, t
Operating free-air temperature, T
DV
= 3 V to 5.25 V
80
5000
125
ns
w(CONV_CLKL)
DD
−55
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ
ꢃ ꢄ ꢇꢊꢋ ꢀ ꢆ ꢌ ꢂꢉꢂ ꢍ ꢂꢋ ꢌꢎ ꢏꢀꢐꢑꢈ ꢒꢎ ꢂ ꢂ ꢐꢌ ꢉ ꢏꢋ ꢑꢓ
ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
electrical characteristics over recommended operating conditions, V
otherwise noted)
= internal (unless
REF
digital specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital inputs
I
I
High-level input current
DV
= digital inputs
DD
−50
−50
50
50
µA
µA
pF
IH
Low-level input current
Input capacitance
Digital input = 0 V
IL
C
5
i
Digital outputs
BV −0.5
DD
V
High-level output voltage
Low-level output voltage
V
V
OH
OL
BV −0.5
DD
BV
BV
= 3.3 V,
= 5 V
DD
DD
I
= −50 µA
OH
0.4
0.4
10
V
I
High-impedance-state output current
Output capacitance
CS1 = DGND, CS0 = DVDD
−10
µA
pF
pF
OZ
C
C
5
O
L
Load capacitance at databus D0 − D11
30
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
Bits
Accuracy
Integral nonlinearity, INL
1.8
1
LSB
LSB
LSB
LSB
LSB
Differential nonlinearity, DNL
After calibration in single-ended mode
After calibration in differential mode
20
15
Offset error
Gain error
20
20
−20
−20
Analog input
Input capacitance
Input leakage current
pF
V
AIN
= V
REFM
to V
REFP
10
µA
Internal voltage reference
Accuracy, V
Accuracy, V
3.3
1.3
3.5
1.5
50
3.7
1.7
V
REFP
V
PPM/°C
µV
REFM
Temperature coefficient
Reference noise
100
2.5
Accuracy, REFOUT
2.3
2.7
V
Power supply
I
I
I
I
Analog supply current
AV
AV
AV
AV
AV
AV
= 5 V, BV
= DV
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
= 3.3 V
36
0.5
1.5
40
1
mA
mA
mA
mA
mW
mW
DDA
DDD
DDB
DD_P
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Digital supply voltage
= 5 V, BV
= 5 V, BV
= 5 V, BV
= 5 V, DV
= 5 V, DV
= DV
= DV
= DV
= BV
= BV
Buffer supply voltage
4
Supply current in power-down mode
Power dissipation
10
216
186
30
Power dissipation in power down
†
Not production tested.
5
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
electrical characteristics over recommended operating conditions, V
I
= internal, f = 6 MHz,
s
REF
f = 2 MHz at −1dBFS (unless otherwise noted)
ac specifications, AV
= 5 V, BV
= DV
= 3.3 V, C < 30 pF
DD
DD
DD L
PARAMETER
TEST CONDITIONS
MIN
TYP
65
MAX
UNIT
dB
Differential mode
63
SINAD Signal-to-noise ratio + distortion
Single-ended mode (see Note 1)
Differential mode
64
dB
64
69
dB
SNR
THD
Signal-to-noise ratio
Single-ended mode (see Note 1)
Differential mode
68
dB
−70
−68
11
−67
Total harmonic distortion
Effective number of bits
dB
Single-ended mode
Differential mode
10.17
67
Bits
Bits
dB
ENOB
(SNR)
Single-ended mode (see Note 1)
Differential mode
10.4
71
SFDR Spurious free dynamic range
Single-ended mode
69
dB
Analog Input
Full-power bandwidth with a source impedance of
150 Ω in differential configuration.
FS sinewave, −3 dB
96
54
96
54
MHz
MHz
MHz
MHz
Full-power bandwidth with a source impedance of
150 Ω in single-ended configuration.
FS sinewave, −3 dB
Small-signal bandwidth with a source impedance
of 150 Ω in differential configuration.
100 mVpp sinewave, −3 dB
100 mVpp sinewave, −3 dB
Small-signal bandwidth with a source impedance
of 150 Ω in single-ended configuration.
NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the
sampling clock.
timing specifications, AV
= 5 V, BV
= DV
= 3.3 V, V
= internal, C < 30 pF
DD
DD
DD
REF L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
Delay time
Delay time
5
ns
d(DATA_AV)
5
5
ns
d(o)
CONV
CLK
t
Latency
pipe
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
†
timing specification of the single conversion mode
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
175
UNIT
ns
t
c
Clock cycle of the internal clock oscillator
159
167
1 analog input
2 analog inputs
3 analog inputs
4 analog inputs
1.5×t
ns
c
c
c
c
2.5×t
3.5×t
4.5×t
t
Pulse width, CONVST
Aperture time
1
t
1
ns
ns
dA
1 analog input
2×t
3×t
4×t
5×t
c
c
c
c
2 analog inputs
t
2
Time between consecutive start of single conversion
3 analog inputs
ns
ns
ns
ns
ns
ns
ns
4 analog inputs
1 analog input, TL = 1
2 analog inputs, TL = 2
3 analog inputs, TL = 3
4 analog inputs, TL = 4
1 analog input, TL = 4
2 analog inputs, TL = 4
3 analog inputs, TL = 6
4 analog inputs, TL = 8
1 analog input, TL = 8
2 analog inputs, TL = 8
3 analog inputs, TL = 9
4 analog inputs, TL = 12
1 analog input, TL = 14
2 analog inputs, TL = 12
3 analog inputs, TL = 12
6×t
7×t
8×t
9×t
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 0
3×t +6×t
2
t
2
t
2
t
2
+7×t
+8×t
+9×t
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 0
t
d(DATA_AV)
7×t +6×t
2
3×t +7×t
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 1
2
2×t +8×t
2
2×t +9×t
2
13×t +6×t
2
ns
ns
Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 1
5×t +7×t
t
d(DATA_AV)
2
3×t +8×t
2
†
Timing parameters are ensured by design but are not tested.
7
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
detailed description
reference voltage
The THS1206 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V
and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and
REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.
analog inputs
The THS1206 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.
converter
The THS1206 uses a 12-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages,
which achieves a high sample rate with low power consumption. The THS1206 distributes the conversion over
several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device
passes the results from stage to stage. This distributed conversion requires a small fraction of the number of
comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages
permits the first stage to operate on a new input sample while the second through the eighth stages operate
on the seven preceding samples.
conversion modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the
conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In
the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal.
sampling rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels.
Table 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
CHANNEL CONFIGURATION
1 single-ended channel
1
2
3
4
1
2
2
3
6 MSPS
3 MSPS
2 MSPS
1.5 MSPS
6 MSPS
3 MSPS
3 MSPS
2 MSPS
2 single-ended channels
3 single-ended channels
4 single-ended channels
1 differential channel
2 differential channels
1 single-ended and 1 differential channel
2 single-ended and 1 differential channels
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
6 MSPS
# channels
fc +
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
sampling rate (continued)
Table 2 shows the maximum conversion rate in the single conversion mode.
Table 2. Maximum Conversion Rate in Single Conversion Mode
NUMBER OF
CHANNELS
MAXIMUM CONVERSION
RATE PER CHANNEL
CHANNEL CONFIGURATION
1 single-ended channel
1
2
3
4
1
2
2
3
3 MSPS
2 MSPS
2 single-ended channels
3 single-ended channels
1.5 MSPS
1.2 MSPS
3 MSPS
4 single-ended channels
1 differential channel
2 differential channels
2 MSPS
1 single-ended and 1 differential channel
2 single-ended and 1 differential channels
1.5 MSPS
1.2 MSPS
single conversion mode
In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.
A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and
hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence
for the selected channels is started.
The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode
can be selected according to Table 13.
Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can
be selected to be sampled simultaneously (see Table 2).
t
2
CONVST
AIN
t
t
1
1
t
d(A)
Sample N
t
DATA_AV
DATA_AV,
Trigger Level = 1
Figure 1. Timing of Single Conversion Mode
The time (t ) between consecutive starts of single conversions is dependent on the number of selected analog
2
input channels. The time t
, until DATA_AV becomes active is given by: t
= t
+ n × t . This
DATA_AV
DATA_AV
pipe c
equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all
other trigger level conditions refer to the timing specifications of single conversion mode.
9
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
continuous conversion mode
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode.
In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running
external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is
written into the FIFO.
Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The
maximum throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case
of a trigger level set to 1 or 4.
Sample N
Channel 1
Sample N+1 Sample N+2 Sample N+3 Sample N+4 Sample N+5 Sample N+6 Sample N+7 Sample N+8
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
AIN
t
d(A)
t
d(pipe)
w(CONV_CLKL)
50%
t
t
w(CONV_CLKH)
50%
t
CONV_CLK
t
d(O)
c
Data Into
FIFO
Data N−5
Channel 1
Data N−4
Channel 1
Data N−3
Channel 1
Data N−2
Channel 1
Data N−1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
Data N+3
Channel 1
t
d(DATA_AV)
DATA_AV,
Trigger Level = 1
t
d(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 2. Timing of Continuous Conversion Mode (1-channel operation)
Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The
maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows
the order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger
level set to 2 or 4.
Sample N
Channel 1,2
Sample N+1
Channel 1,2
Sample N+2
Channel 1,2
Sample N+3
Channel 1,2
Sample N+4
Channel 1,2
AIN
t
d(A)
t
d(Pipe)
w(CONV_CLKL)
50%
t
t
w(CONV_CLKH)
50%
CONV_CLK
t
c
t
d(O)
Data Into
FIFO
Data N−3
Channel 2
Data N−2
Channel 1
Data N−2
Channel 2
Data N−1
Channel 1
Data N−1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N+1
Channel 2
t
d(DATA_AV)
DATA_AV,
Trigger Level = 2
t
d(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 3. Timing of Continuous Conversion Mode (2-channel operation)
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
continuous conversion mode (continued)
Figure 4 shows the timing of continuous conversion mode when three analog input channels are selected. The
maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows
in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for
a trigger level set to 3.
Sample N
Sample N+1
Sample N+2
Channel 1,2,3
Channel 1,2,3
Channel 1,2,3
AIN
t
d(A)
t
d(Pipe)
w(CONV_CLKL)
50%
t
t
w(CONV_CLKH)
50%
CONV_CLK
t
c
t
d(O)
Data Into
FIFO
Data N−2
Channel 2
Data N−2
Channel 3
Data N−1
Channel 2
Data N−1
Channel 2
Data N−1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 3
t
d(DATA_AV)
DATA_AV,
Trigger Level = 3
Figure 4. Timing of Continuous Conversion Mode (3-channel operation)
Figure 5 shows the timing of continuous conversion mode when four analog input channels are selected. The
maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows
in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for
a trigger level of 4.
Sample N
Sample N+1
Sample N+2
Channel 1,2,3,4
Channel 1,2,3,4
Channel 1,2,3,4
AIN
t
d(A)
t
d(Pipe)
w(CONV_CLKL)
50%
t
t
w(CONV_CLKH)
50%
CONV_CLK
t
c
t
d(O)
Data Into
FIFO
Data N−2
Channel 4
Data N−1
Channel 1
Data N−1
Channel 2
Data N−1
Channel 3
Data N−1
Channel 4
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
Data N
Channel 4
t
d(DATA_AV)
DATA_AV,
Trigger Level = 4
Figure 5. Timing of Continuous Conversion Mode (4-channel operation)
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
digital output data format
The digital output data format of the THS1206 can either be in binary format or in twos complement format. The
following tables list the digital outputs for the analog input voltages.
Table 3. Binary Output Format for Single-Ended Configuration
SINGLE-ENDED, BINARY OUTPUT
ANALOG INPUT VOLTAGE
AIN = V
DIGITAL OUTPUT CODE
FFFh
800h
000h
REFP
AIN = (V
+ V )/2
REFM
REFP
AIN = V
REFM
Table 4. Twos Complement Output Format for Single-Ended Configuration
SINGLE-ENDED, TWOS COMPLEMENT
ANALOG INPUT VOLTAGE
AIN = V
DIGITAL OUTPUT CODE
7FFh
000h
800h
REFP
AIN = (V
+ V )/2
REFM
REFP
AIN = V
REFM
Table 5. Binary Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
DIGITAL OUTPUT CODE
V
= AINP − AINM
in
V
= V
− V
REF
REFP REFM
V
in
V
in
V
in
= V
FFFh
800h
000h
REF
= 0
= −V
REF
Table 6. Twos Complement Output Format for Differential Configuration
DIFFERENTIAL, BINARY OUTPUT
ANALOG INPUT VOLTAGE
= AINP − AINM
DIGITAL OUTPUT CODE
V
in
V
REF
= V
− V
REFP REFM
V
in
V
in
V
in
= V
= 0
7FFh
000h
800h
REF
= −V
REF
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
FIFO description
In order to facilitate an efficient connection to today’s processors, the THS1206 is supplied with a FIFO. This
integrated FIFO enables a problem-free processing of data with today’s processors. The FIFO is provided as
a flexible circular buffer. The circular buffer integrated in the THS1206 can store up to 16 conversion values.
Therefore, the amount of interrupts to be served by a processor can be reduced significantly.
16
1
15
2
Read Pointer
14
3
13
12
4
5
Trigger Pointer
6
11
Data in FIFO
Free
7
10
8
9
Write Pointer
Figure 6. Circular Buffer
The converted data of the THS1206 is automatically written into the FIFO. To control the writing and reading
process, a write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the
location which will be read next. The write pointer indicates the location which contains the last written sample.
With a selection of multiple analog input channels, the converted values are written in a predefined sequence
to the circular buffer (autoscan mode). In this way, the channel information for the reading processor is
continually maintained.
The FIFO can be programmed through the control register of the ADC. The user has the ability to select a
specific trigger level according to Table 13 in order to choose the configuration which best fits the application.
The FIFO provides the signal DATA_AV, which signals the processor to read the amount of data equal to the
trigger level selected in Table 13. The signal DATA_AV becomes active when the trigger condition is satisfied.
The trigger condition is satisfied when as many values as selected for the trigger level where written into the
FIFO.
The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine
call, the processor must read the amount of data equal to the trigger level from the ADC. The first data represents
the first channel according to the autoscan mode, which is shown in Table 10. The channel information is
therefore always maintained.
13
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
Reading data from the FIFO
The THS1206 informs the connected processor via the digital output DATA_AV (data available) that a block of
conversion values are ready to be read. The block size to be read is always equal to the setting of the trigger
level. The selectable trigger levels depend on the number of selected analog input channels. For example, when
choosing one analog input, a trigger level of 1, 4, 8 and 14 can be selected. The following figures demonstrate
the principle of reading the data.
In Figure 7, a trigger level of 1 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 7. Trigger Level 1 Selected
In Figure 8, a trigger level of 4 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 8. Trigger Level 4 Selected
In Figure 9, a trigger level of 8 is selected. The control signal DATA_AV is set to an active low pulse. This means
that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.
CONV_CLK
DATA_AV
READ
Figure 9. Trigger Level 8 Selected
In Figure 10, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This
means that the connected processor has the task to read 14 values from the ADC after every DATA_AV low
pulse.
CONV_CLK
DATA_AV
READ
Figure 10. Trigger Level 14 Selected
READ is always the logical combination of CS0, CS1 and RD.
14
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
ADC Control Register
The THS1206 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the
desired mode. The bit definitions of both control registers are shown in Table 7.
Table 7. Bit Definitions of Control Register CR0 and CR1
BIT
CR0
CR1
BIT 9
TEST1
RBACK
BIT 8
TEST0
OFFSET
BIT 7
SCAN
BIN/2’s
BIT 6
DIFF1
R/W
BIT 5
DIFF0
BIT 4
BIT 3
CHSEL0
TRIG1
BIT 2
PD
BIT 1
MODE
BIT 0
VREF
CHSEL1
DATA_T
DATA_P
TRIG0
OVFL/FRST
RESET
Writing to control register 0 and control register 1
The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control
register and writing the register value to the ADC. The addressing is performed with the upper data bits D10
and D11, which function in this case as address lines RA0 and RA1. During this write process, the data bits D0
to D9 contain the desired control register value. Table 8 shows the addressing of each control register.
Table 8. Control Register Addressing
D0 – D9
D10/RA0
D11/RA1
Addressed Control Register
Control Register 0
Desired register value
Desired register value
Desired register value
Desired register value
0
1
0
1
0
0
1
1
Control Register 1
Reserved for future
Reserved for future
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
initialization of the THS1206
The initialization of the THS1206 should be done according to the configuration flow shown in Figure 11.
Start
No
Use Default
Values?
Yes
Write 0x401 to
Write 0x401 to
THS1206
THS1206
(Set Reset Bit in
(Set Reset Bit in CR1)
CR1)
Clear RESET By
Writing 0x400 to
CR1
Clear RESET By
Writing 0x400 to
CR1
Write The User
Configuration to
CR0
Write The User
Configuration to
CR1 (Can Include
FIFO Reset, Must
Exclude RESET)
Continue
Figure 11. THS1206 Configuration Flow
16
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SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
ADC control registers
control register 0 (see Table 8)
−
−
−
−
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
DIFF0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TEST1
TEST0
SCAN
DIFF1
CHSEL1 CHSEL0
PD
MODE
VREF
Table 9. Control Register 0 Bit Functions
RESET
VALUE
BITS
NAME
VREF
FUNCTION
0
0
Vref select:
Bit 0 = 0 → The internal reference is selected
Bit 0 = 1 → The external reference voltage is selected
1
0
MODE
Continuous conversion mode/single conversion mode
Bit 1 = 0 → Continuous conversion mode is selected
An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the
CONV_CLK signal a new converted value is written into the FIFO.
Bit 1 = 1 → Single conversion mode is selected
In this mode, the CONV_CLK input functions as a CONVST input. A single conversion is initiated on the
THS1206 by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of
the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the
selected channels is started. The signal DATA_AV (data available) becomes active when the trigger
condition is satisfied.
2
0
PD
Power down.
Bit 2 = 0 → The ADC is active
Bit 2 = 1 → Power down
The reading and writing to and from the digital outputs is possible during power down. It is also possible to
read out the FIFO.
3, 4
5,6
7
0,0
1,0
0
CHSEL0,
CHSEL1
Channel select
Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10.
DIFF0, DIFF1 Number of differential channels
Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 10.
SCAN
Autoscan enable
Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10.
8,9
0,0
TEST0,
TEST1
Test input enable
Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This
feedback allows the check of all hardware connections and the ADC operation.
Refer to Table 11 for selection of the three different test voltages. The control signal DATA_AV is disabled in
the test mode. Test voltage readings have to be done independent from DATA_AV. To get the THS1206
back to the normal operating mode, apply the the initialization routine.
17
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
analog input channel selection
The analog input channels of the THS1206 can be selected via bits 3 to 7 of control register 0. One single
channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the
selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more
than one input channel is selected. Table 10 shows the possible selections.
Table 10. Analog Input Channel Configurations
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
DESCRIPTION OF THE SELECTED INPUTS
SCAN DIFF1 DIFF0 CHSEL1 CHSEL0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Analog input AINP (single ended)
Analog input AINM (single ended)
Analog input BINP (single ended)
Analog input BINM (single ended)
Differential channel (AINP−AINM)
Differential channel (BINP−BINM)
Autoscan two single ended channels: AINP, AINM, AINP, …
Autoscan three single ended channels: AINP, AINM, BINP, AINP, …
Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …
Autoscan one differential channel and one single ended channel AINP, (BINP−BINM),
AINP, (BINP−BINM), …
1
1
0
0
1
1
0
1
1
0
Autoscan one differential channel and two single ended channel AINP, AINM, (BINP−
BINM), AINP, …
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
0
1
0
1
Autoscan two differential channels (AINP−AINM), (BINP−BINM), (AINP−AINM), …
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
test mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown
in Table 11.
Table 11. Test Mode
BIT 9
TEST1 TEST0
BIT 8
OUTPUT RESULT
0
0
1
1
0
1
0
1
Normal mode
V
REFP
)+(V
((V
))/2
REFM
REFP
REFM
V
Three different options can be selected. This feature allows support testing of hardware connections between
the ADC and the processor.
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
analog input channel selection (continued)
control register 1 (see Table 8)
−
−
−
−
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
DATA_P
BIT 4
BIT 3
TRIG1
BIT 2
BIT 1
BIT 0
RBACK
OFFSET
BIN/2s
R/W
DATA_T
TRIG0
OVFL/FRST
RESET
Table 12. Control Register 1 Bit Functions
RESET
VALUE
BITS
NAME
FUNCTION
0
0
RESET
Reset
Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset
values. In addition the FIFO pointer and offset register is reset. After reset, it takes 5 clock cycles until the first
value is converted and written into the FIFO.
1
0
OVFL
Overflow flag (read only)
(read only) Bit 1 of control register 1 indicates an overflow in the FIFO.
Bit 1 = 0 → no overflow occurred.
Bit 1 = 1 → an overflow occurred. This bit is reset to 0, after this control register is read from the processor.
FRST: FIFO reset (write only)
By writing a 1 into this bit, the FIFO is reset.
FRST
(write only)
2, 3
0,0
1
TRIG0,
TRIG1
FIFO trigger level
Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached,
the signal DATA_AV (data available) becomes active according to the settings of DATA_T and DATA_P. This
indicates to the processor that the ADC values can be read. Refer to Table 13.
4
DATA_T
DATA_AV type
Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g for edge or level
sensitive interrupt inputs). If it is set to 0, the DATA_AV signal is static. If it is set to 1, the DATA_AV signal is a
pulse. Refer to Table 14.
5
6
1
0
DATA_P
R/W
DATA_AV polarity
Bit 5 of control register 1 controls the polarity of DATA_AV. If it is set to 1, DATA_AV is active high. If it is set to 0,
DATA_AV is active low. Refer to Table 14.
R/W, RD/WR selection
Bit 6 of control register 1 controls the function of the inputs RD and WR. When bit 6 in control register 1 is set
to 1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write
with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input
WR becomes a write input.
7
8
0
0
BIN/2s
Complement select
If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of
control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 3 through Table 6.
OFFSET
Offset cancellation mode
Bit 8 = 0 → normal conversion mode
Bit 8 = 1 → offset calibration mode
If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a con-
version. The conversion result is stored in an offset register and subtracted from all conversions in order
to reduce the offset error.
9
0
RBACK
Debug mode
Bit 9 = 0 → normal conversion mode
Bit 9 = 1 → enable debug mode
When bit 9 of control register 1 is set to 1, debug mode is enabled. In this mode, the contents of control
register 0 and control register 1 can be read back. The first read after bit 9 is set to 1 contains the value of
control register 0. The second read after bit 9 is set to 1 contains the value of control register 1. To get the
THS1206 back to the normal operating mode, apply the the initialization routine.
19
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
FIFO trigger level
Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13).
If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of
the signal DATA_AV to indicate to the processor that the ADC values can be read.
Table 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which
can be selected, is dependent on the number of input channels. Both, a differential or a single-ended input is
considered as one channel. The processor therefore always reads the data from the FIFO in the same order
and is able to distinguish between the channels.
Table 13. FIFO Trigger Level
TRIGGER LEVEL
FOR 1 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 2 CHANNELS
(ADC values)
TRIGGER LEVEL
FOR 3 CHANNEL
(ADC values)
TRIGGER LEVEL
FOR 4 CHANNELS
(ADC values)
BIT 3
TRIG1
BIT 2
TRIG0
0
0
1
1
0
1
0
1
01
04
08
14
02
04
08
12
03
06
09
12
04
08
12
Reserved
Timing and Signal Description of the THS1206
The reading from the THS1206 and writing to the THS1206 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS1206 takes place by an internal RD signal, which is generated from the logical
int
combination of the external signals CS0, CS1 and RD (see Figure 12). This signal is then used to strobe the
words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to
become valid will make RD active while the write input (WR) is inactive. The first of those external signals going
int
to its inactive state will then deactivate RD again.
int
Writing to the THS1206 takes place by an internal WR signal, which is generated from the logical combination
int
of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control
registers 0 and 1. The last external signal (either CS0, CS1 or WR) to become valid will make WR active while
int
the read input (RD) is inactive. The first of those external signals going to its inactive state will then deactivate
WR again.
int
Read Enable
Write Enable
CS0
CS1
RD
WR
Control/Data
Registers
Data Bits
Figure 12. Logical Combination of CS0, CS1, RD, and WR
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
DATA_AV type
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of
control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register
determines the polarity of DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P
BIT 4
DATA_T
DATA_AV TYPE
0
0
1
1
0
1
0
1
Active low level
Active low pulse
Active high level
Active high pulse
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive independent
of the DATA_T selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling
edge of READ). The trigger condition is checked again after TL reads.
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in
continuous conversion mode and one half of a clock cycle of the internal oscillator in single conversion mode.
The next DATA_AV pulse (when the trigger condition is satisfied) is sent out the earliest, when the TL values,
written into the FIFO before, were read out by the processor.
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
timing and signal description of the THS1206
read timing (using R/W, CS0-controlled)
Figure 13 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid.
t
w(CS)
90%
CS0
CS1
10%
10%
t
t
su(R/W)
h(R/W)
90%
90%
R/W
RD
t
t
a
h
90%
90%
D(0−11)
t
d(CSDAV)
90%
DATA_AV
Figure 13. Read Timing Diagram Using R/W (CS0-controlled)
read timing parameter (CS0-controlled)
PARAMETER
Setup time, R/W high to last CS valid
MIN
0
TYP
MAX
10
UNIT
ns
t
t
t
t
t
t
su(R/W)
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, first external CS invalid to R/W change
Pulse duration, CS active
0
ns
a
12
ns
d(CSDAV)
h
0
5
5
ns
ns
h(R/W)
w(CS)
10
ns
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
timing and signal description of the THS1206 (continued)
write timing (using R/W, CS0-controlled)
Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid.
t
w(CS)
90%
CS0
CS1
10%
10%
t
t
su(R/W)
h(R/W)
WR
RD
t
su
t
h
90%
90%
D(0−11)
DATA_AV
Figure 14. Write Timing Diagram Using R/W (CS0-controlled)
write timing parameter (RD-controlled)
PARAMETER
Setup time, R/W stable to last CS valid
MIN
0
TYP
MAX
UNIT
ns
t
t
t
t
t
su(R/W)
Setup time, data valid to first CS invalid
Hold time, first CS invalid to data invalid
Hold time, first CS invalid to R/W change
Pulse duration, CS active
5
ns
su
2
ns
h
5
ns
h(R/W)
w(CS)
10
ns
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
interfacing the THS1206 to the TMS320C30/31/33 DSP
The following application circuit shows an interface of the THS1206 to the TMS320C30/31/33 DSPs. The read
and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
THS1206
TMS320C30/31/33
DV
DD
STRB
A23
CS0
CS1
R/W
R/W
RD
INTX
TOUT
DATA
DATA_AV
CONV_CLK
DATA
interfacing the THS1206 to the TMS320C54x using I/O strobe
The following application circuit shows an interface of the THS1206 to the TMS320C54x. The read and write
timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
THS1206
TMS320C54x
DV
DD
I/O STRB
A15
CS0
CS1
R/W
R/W
RD
INTX
DATA_AV
CONV_CLK
DATA
BCLK
DATA
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
timing and signal description of the THS1206 (continued)
read timing (using RD, RD-controlled)
Figure 15 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The
input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last
external signal of CS0, CS1, and RD which becomes valid.
CS0
CS1
t
t
su(CS)
h(CS)
WR
RD
t
w(RD)
10%
10%
t
t
a
h
90%
90%
D(0−11)
t
d(CSDAV)
90%
DATA_AV
Figure 15. Read Timing Diagram Using RD (RD-controlled)
read timing parameter (RD-controlled)
PARAMETER
Setup time, RD low to last CS valid
MIN
0
TYP
MAX
10
UNIT
ns
t
t
t
t
t
t
su(CS)
Access time, last CS valid to data valid
Delay time, last CS valid to DATA_AV inactive
Hold time, first CS invalid to data invalid
Hold time, RD change to first CS invalid
Pulse duration, RD active
0
ns
a
12
ns
d(CSDAV)
h
0
5
5
ns
ns
h(CS)
w(RD)
10
ns
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
timing and signal description of the THS1206 (continued)
write timing (using WR, WR-controlled)
Figure 16 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only.
The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is
the last external signal of CS0, CS1, and WR which becomes valid.
CS0
CS1
t
t
h(CS)
su(CS)
t
w(WR)
WR
RD
10%
10%
t
su
t
h
90%
90%
D(0−11)
DATA_AV
Figure 16. Write Timing Diagram Using WR (WR-controlled)
write timing parameter using WR (WR-controlled)
PARAMETER
MIN
0
TYP
MAX
UNIT
ns
t
t
t
t
t
Setup time, CS stable to last WR valid
Setup time, data valid to first WR invalid
Hold time, WR invalid to data invalid
Hold time, WR invalid to CS change
Pulse duration, WR active
su(CS)
5
ns
su
2
ns
h
5
ns
h(CS)
w(WR)
10
ns
26
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
interfacing the THS1206 to the TMS320C6201 DSP
The following application circuit shows an interface of the THS1206 to the TMS320C6201. The read (using RD,
RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface.
THS1206−1
TMS320C6201
CE1
CS0
CS1
EA20
ARE
RD
AWE
WR
EXT_INT6
DATA
DATA_AV
DATA
TOUT1
TOUT2
EA21
CONV_CLK
THS1206−2
EXT_INT7
CS0
CS1
RD
WR
DATA_AV
DATA
CONV_CLK
analog input configuration and reference voltage
The THS1206 features four analog input channels. These can be configured for either single-ended or
differential operation. Best performance is achieved in differential mode. Figure 17 shows a simplified model,
where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are
V
V
and V
(either internal or external reference voltage). The analog input voltage range goes from
REFP
REFM
REFM
to V
. This means that V
defines the minimum voltage, which can be applied to the ADC. V
REFP
REFM REFP
defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the
voltage V
of 1.5 V and the voltage V
of 3.5 V. The resulting analog input voltage swing of 2 V can be
REFM
REFP
expressed by:
V
v AINP v V
REFM
REFP
(1)
V
REFP
12-Bit
ADC
AINP
V
REFM
Figure 17. Single-Ended Input Stage
27
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
analog input configuration and reference voltage (continued)
A differential operation is desired for many applications. Figure 18 shows a simplified model for the analog inputs
AINM and AINP, which are configured for differential operation. This configuration has a few advantages, which
are discussed in the following paragraphs.
V
REFP
AINP
+
V
ADC
12-Bit
ADC
Σ
−
AINM
V
REFM
Figure 18. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, V
input of the ADC is the difference between the input AINP and AINM. This means that V
, which is applied at the
ADC
defines the
REFM
minimum voltage (V
can be applied to the ADC. The voltage V
) which can be applied to the ADC. V
defines the maximum voltage (VADC) which
ADC
REFP
can be calculated as follows:
ADC
(
)
V
+ ABS AINP–AINM
ADC
(2)
(3)
An advantage to single-ended operation is that the common-mode voltage
AINM ) AINP
V
+
CM
2
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND v AINM, AINP v AV
DD
(4)
(5)
1 V v V
v 4 V
CM
In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection which
is common to both analog inputs. See also Figure 20.
single-ended mode of operation
The THS1206 can be configured for single-ended operation using dc or ac coupling. In either case, the input
of the THS1206 must be driven from an operational amplifier that does not degrade the ADC performance.
Because the THS1206 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar
signals to comply with its input requirements. This can be achieved with dc and ac coupling. An application
example is shown for dc-coupled level shifting in the following section, dc coupling.
28
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
dc coupling
An operational amplifier can be configured to shift the signal level according to the analog input voltage range
of the THS1206. The analog input voltage range of the THS1206 goes from 1.5 V to 3.5 V. An op-amp specified
for 5-V single supply can be used as shown in Figure 19.
Figure 19 shows an application example where the analog input signal in the range from −1 V up to 1 V is shifted
by an op-amp to the analog input range of the THS1206 (1.5 V to 3.5 V). The op-amp is configured as an
inverting amplifier with a gain of −1. The required dc voltage of 1.25 V at the noninverting input is derived from
the 2.5-V output reference REFOUT of the THS1206 by using a resistor divider. Therefore, the op-amp output
voltage is centered at 2.5 V. The use of ratio matched, thin-film resistor networks minimizes gain and offset
errors.
R
3.5 V
2.5 V
1.5 V
5 V
1 V
0 V
R
THS1206
AINP
_
R
S
−1 V
+
1.25 V
REFIN
REFOUT
R
R
Figure 19. Level-Shift for DC-Coupled Input
differential mode of operation
For the differential mode of operation, a conversion from single-ended to differential is required. A conversion
to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best
performance is achieved in differential mode.
Mini Circuits
T4−1
THS1206
49.9 Ω
R
AINP
C
C
200 Ω
R
AINM
REFOUT
Figure 20. Transformer Coupled Input
29
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE AND DISTORTION
vs
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
SAMPLING FREQUENCY (SINGLE-ENDED)
80
75
70
65
60
55
50
45
40
70
65
60
55
50
45
40
AV
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
DD
DD
DD
f
IN
AV
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
DD
DD
DD
f
IN
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
f
− Sampling Frequency − MHz
f
− Sampling Frequency − MHz
s
s
Figure 21
Figure 22
SIGNAL-TO-NOISE
vs
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
SAMPLING FREQUENCY (SINGLE-ENDED)
70
65
60
55
50
45
40
90
AV
f
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
DD
IN
DD
DD
85
80
75
70
65
60
55
50
45
40
AV
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
DD
DD
DD
f
IN
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
f
− Sampling Frequency − MHz
f
− Sampling Frequency − MHz
s
s
Figure 23
Figure 24
30
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE AND DISTORTION
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
85
80
75
70
65
60
55
50
45
40
80
75
70
65
60
55
50
45
40
AV
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
DD
DD
DD
f
IN
AV
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
DD
DD
DD
f
IN
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
f
− Sampling Frequency − MHz
f
− Sampling Frequency − MHz
s
s
Figure 25
Figure 26
SIGNAL-TO-NOISE
vs
SPURIOUS FREE DYNAMIC RANGE
vs
SAMPLING FREQUENCY (DIFFERENTIAL)
SAMPLING FREQUENCY (DIFFERENTIAL)
80
75
70
65
60
55
50
45
40
100
AV
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
AV
f
IN
= 5 V, DV
= BV
= 3 V,
= 500 kHz, AIN = −0.5 dB FS
DD
DD
DD
DD
DD
DD
95
90
85
80
75
70
65
60
55
50
45
40
f
IN
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
f
− Sampling Frequency − MHz
f
− Sampling Frequency − MHz
s
s
Figure 27
Figure 28
31
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
SIGNAL-TO-NOISE AND DISTORTION
vs
INPUT FREQUENCY (SINGLE-ENDED)
85
80
75
70
65
60
55
50
45
40
80
75
70
65
60
55
50
45
40
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 29
Figure 30
SIGNAL-TO-NOISE
vs
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY (SINGLE-ENDED)
INPUT FREQUENCY (SINGLE-ENDED)
80
75
70
65
60
55
50
45
40
100
95
90
85
80
75
70
65
60
55
50
45
40
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
AV
= 5 V, DV
= BV
= 3 V,
f = 6 MHz, AIN = −0.5 dB FS
s
DD
s
DD
DD
DD
DD
DD
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 31
Figure 32
32
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ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE AND DISTORTION
vs
TOTAL HARMONIC DISTORTION
vs
INPUT FREQUENCY (DIFFERENTIAL)
INPUT FREQUENCY (DIFFERENTIAL)
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 34
Figure 33
SPURIOUS FREE DYNAMIC RANGE
vs
SIGNAL-TO-NOISE
vs
INPUT FREQUENCY (DIFFERENTIAL)
INPUT FREQUENCY (DIFFERENTIAL)
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 35
Figure 36
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS
vs
vs
SAMPLING FREQUENCY (SINGLE-ENDED)
SAMPLING FREQUENCY (DIFFERENTIAL)
12
11
10
9
12
11
10
9
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
AV
= 5 V, DV
= BV
= 3 V,
f = 6 MHz, AIN = −0.5 dB FS
s
DD
s
DD
DD
DD
DD
DD
8
8
7
7
6
6
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
f
− Sampling Frequency − MHz
f
− Sampling Frequency − MHz
s
s
Figure 38
Figure 37
EFFECTIVE NUMBER OF BITS
vs
EFFECTIVE NUMBER OF BITS
vs
INPUT FREQUENCY (SINGLE-ENDED)
INPUT FREQUENCY (DIFFERENTIAL)
12
11
10
9
12
11
10
9
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
s
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
DD
DD
DD
s
DD
DD
8
8
7
7
6
6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 40
Figure 39
34
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
GAIN
vs
INPUT FREQUENCY (SINGLE-ENDED)
5
0
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
−5
−10
−15
−20
−25
−30
0
10 20 30 40 50 60 70 80 90 100 110 120
f − Input Frequency − MHz
i
Figure 41
35
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ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM (4096 POINTS)
(SINGLE-ENDED)
vs
FREQUENCY
20
0
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
−20
−40
−60
−80
−100
−120
−140
0
500000
1000000
1500000
2000000
2500000
3000000
3500000
f − Frequency − Hz
Figure 42
FAST FOURIER TRANSFORM (4096 POINTS)
(DIFFERENTIAL)
vs
FREQUENCY
20
0
AV
f
= 5 V, DV
= BV
= 3 V,
= 6 MHz, AIN = −0.5 dB FS
DD
s
DD
DD
−20
−40
−60
−80
−100
−120
−140
0
500000
1000000
1500000
2000000
2500000
3000000
3500000
f − Frequency − Hz
Figure 43
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ꢐꢑꢐ ꢏꢒ ꢓ ꢇꢀꢒ ꢇꢔꢋꢓ ꢋ ꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈꢗ ꢀꢈ ꢗ ꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
APPLICATION INFORMATION
definitions of specifications and terminology
integral nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than 1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
signal-to-noise ratio + distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(
)
SINAD * 1.76
N +
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal
and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢃꢄ ꢇꢊꢋ ꢀ ꢆ ꢌ ꢂꢉꢂꢍ ꢂ ꢋ ꢌꢎꢏꢀꢐꢑ ꢈꢒ ꢎꢂ ꢂ ꢐꢌꢉ ꢏ ꢋꢑꢓ
ꢐ ꢑꢐꢏ ꢒꢓꢇ ꢀꢒꢇꢔ ꢋ ꢓ ꢋꢀꢐꢏ ꢕꢒ ꢑꢖ ꢈ ꢗꢀꢈ ꢗꢂ
SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
MECHANICAL DATA
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
38 PINS SHOWN
0,30
0,19
M
0,13
0,65
38
20
6,20
8,40
NOM 7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°−ā8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
30
32
38
DIM
11,10
10,90
11,10
10,90
12,60
12,40
A MAX
A MIN
4040066/D 11/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
THS1206MDAREP
V62/03609-01XE
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DA
32
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
DA
32
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS1206-EP :
Catalog: THS1206
Military: THS1206M
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Military - QML certified for Military and Defense Applications
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
THS1206MDAREP
TSSOP
DA
32
2000
330.0
24.4
8.6
11.5
1.6
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Jul-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DA 32
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
THS1206MDAREP
2000
Pack Materials-Page 2
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