V62/04602-01XE [TI]
3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的3.3V ABT 16位总线收发器
| 型号： | V62/04602-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总17页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVTH16245A-EP
3.3-V ABT 16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS693G–APRIL 2003–REVISED OCTOBER 2006
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Controlled Baseline
– One Assembly
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1OE
1A1
1A2
GND
1A3
1A4
VCC
– One Test Site
2
– One Fabrication Site
3
•
Enhanced Diminishing Manufacturing
Sources (DMS) Support
4
5
•
•
•
Enhanced Product-Change Notification
6
(1)
Qualification Pedigree
7
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
Member of the Texas Instruments Widebus™
Family
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
•
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
•
•
•
•
•
•
•
•
•
Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC
)
Supports Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
2B5
2B6
GND
2B7
2B8
2DIR
2A5
2A6
GND
2A7
2A8
2OE
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVTH16245A-EP
3.3-V ABT 16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS693G–APRIL 2003–REVISED OCTOBER 2006
DESCRIPTION/ORDERING INFORMATION
The SN74LVTH16245A is a 16-bit (dual-octal) noninverting 3-state transceiver designed for low-voltage (3.3-V)
VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the devices so that the buses effectively are isolated.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 V and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(TOP VIEW)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
1A5
1A7
12A2
2A4
2A6
2A8
NC
G
H
J
GND
VCC
GND
NC
GND
VCC
GND
NC
G
H
J
K
K
(1) NC – no internal connection
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
CLVTH16245AQDLREP
TOP-SIDE MARKING
LH16245AEP
SSOP – DL
Tape and reel
–40°C to 125°C
TSSOP – DGG
TVSOP – DGV
VFBGA – GQL
Tape and reel
Tape and reel
CLVTH16245AQDGGREP
CLVTH16245AIDGVREP
CLVTH16245AIGQLREP
LH16245AEP
LL245AEP
–40°C to 85°C
–55°C to 125°C
Tape and reel
Tape and reel
LL245AEP
VFBGA – ZQL
(Pb-free)
CLVTH16245AIZQLREP
CLVTH16245AMDLREP
SSOP – DL
LH16245AEP
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
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SN74LVTH16245A-EP
3.3-V ABT 16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS693G–APRIL 2003–REVISED OCTOBER 2006
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE DIR
OPERATION
L
L
L
H
X
B data to A bus
A data to B bus
Isolation
H
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
1OE
2OE
36
47
1A1
2A1
13
2
2B1
1B1
To Seven Other Channels
To Seven Other Channels
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high state(2)
4.6
7
V
V
V
V
VO
VO
7
–0.5 VCC + 0.5
SN74LVTH16245A(Q/M)
96
128
48
IO
Current into any output in the low state
Current into any output in the high state(3)
mA
mA
SN74LVTH16245AI
SN74LVTH16245A(Q/M)
SN74LVTH16245AI
VI < 0
IO
64
IIK
Input clamp current
Output clamp current
–50
–50
70
mA
mA
IOK
VO < 0
DGG package
DGV package
DL package
58
θJA
Package thermal impedance(4)
°C/W
°C
63
GQL/ZQL package
42
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SN74LVTH16245A-EP
3.3-V ABT 16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS693G–APRIL 2003–REVISED OCTOBER 2006
Recommended Operating Conditions(1)
SN74LVTH16245AQ SN74LVTH16245AI SN74LVTH16245AM
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
MIN
2.7
2
MAX
VCC
VIH
VIL
Supply voltage
3.6
3.6
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
–24
24
0.8
5.5
–32
64
0.8
5.5
–24
24
V
VI
V
IOH
IOL
High-level output current
Low-level output current
Input transition rise or fall rate
mA
mA
∆t/∆v
Outputs enabled
10
10
10 ns/V
∆t/∆VCC Power-up ramp rate
TA Operating free-air temperature
200
–40
200
–40
200
–55
µs/V
125
85
125
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
4
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SN74LVTH16245A-EP
3.3-V ABT 16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS693G–APRIL 2003–REVISED OCTOBER 2006
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
SN74LVTH16245AQ
MIN TYP(1) MAX
–1.2
SN74LVTH16245AI
MIN TYP(1) MAX
–1.2
SN74LVTH16245AM
MIN TYP(1) MAX
–1.2
PARAMETER
TEST CONDITIONS
UNIT
VIK
VCC = 2.7 V,
II = –18 mA
V
VCC = 2.7 V to 3.6 V,
VCC
VCC
VCC
IOH = –100 µA
– 0.2
– 0.2
– 0.2
VCC = 2.7 V,
IOH = –8 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 24 mA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
2.4
2
2.4
2.4
2
VOH
V
V
VCC = 3.3 V
VCC = 2.7 V
2
0.2
0.5
0.4
0.2
0.5
0.4
0.5
0.55
0.2
0.5
0.4
VOL
VCC = 3 V
VCC = 3.6 V,
VI = VCC or GND
±1
±1
±1
Control inputs
VCC = 0 or 3.6 V,
VI = 5.5 V
10
10
10
II
µA
VI = 5.5 V
VI = VCC
VI = 0
20
5
20
1
20
5
A or B port(2) VCC = 3.6 V
–5
–5
–5
VCC = 0,
VI or VO = 0 to 4.5 V
Ioff
±100
µA
µA
VI = 0.8 V
VI = 2 V
75
75
75
VCC = 3 V
–75
–75
–75
(3)
II(hold)
A or B port
VCC = 3.6 V,
VI = 0 to 3.6 V
500
–750
VCC = 0 to 1.5 V,
VO = 0.5 V to 3 V,
OE = don't care
IOZPU
±100
±100
±100
±100
±100 µA
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
OE = don't care
IOZPD
±100 µA
Outputs high
0.19
5
0.19
5
0.19
VCC = 3.6 V,
IO = 0,
Outputs low
5
ICC
mA
VI = VCC or
GND
Outputs
disabled
0.19
0.19
0.19
VCC = 3 V to 3.6 V,
One input at VCC – 0.6 V,
Other inputs at VCC or GND
(4)
∆ICC
0.2
0.2
0.2 mA
Ci
VI = 3 V or 0
VO = 3 V or 0
4
4
4
pF
pF
Cio
10
10
10
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) Unused pins at VCC or GND
(3) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
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SN74LVTH16245A-EP
3.3-V ABT 16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS693G–APRIL 2003–REVISED OCTOBER 2006
Switching Characteristics
over operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74LVTH16245AQ
SN74LVTH16245AM
SN74LVTH16245AI
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC = 3.3 V
±0.3 V
VCC = 3.3 V
±0.3 V
UNIT
VCC = 2.7 V
VCC = 2.7 V
MIN MAX
MIN MAX
MIN TYP(1) MAX
MIN MAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
0.5
0.5
0.5
0.5
1
4.5
4.4
6.5
5.4
6.8
6.2
4.6
3.9
6.6
6.2
7
1.5
1.3
1.5
1.6
2.3
2.2
2.3
2.1
2.8
2.9
3.7
3.5
3.3
3.3
4.5
4.6
5.1
5.1
0.5
3.7
3.5
5.3
5.2
5.5
5.4
0.5
ns
ns
ns
ns
A or B
OE
B or A
A or B
A or B
OE
1
6.3
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6
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SN74LVTH16245A-EP
3.3-V ABT 16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS693G–APRIL 2003–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
6 V
Open
GND
TEST
S1
S1
500 W
From Output
Under Test
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
CL = 50 pF
(see Note A)
GND
500 W
2.7 V
0 V
LOAD CIRCUIT
tw
1.5 V
Timing Input
tsu
th
2.7 V
2.7 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
Input
1.5 V
1.5 V
tPZL
tPLZ
tPLH
tPHL
Output
Waveform 1
S1 at 6 V
V
V
3 V
V
1.5 V
Output
Output
1.5 V
1.5 V
1.5 V
tPLH
VOL + 0.3 V
tPHZ
(see Note B)
tPZH
tPHL
Output
Waveform 2
S1 at GND
V
V
V
V
OH - 0.3 V
1.5 V
1.5 V
»0 V
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 59 W, tr £ 2.5 ns, tf £ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2008
PACKAGING INFORMATION
Orderable Device
8V16245AMDLREPG4
CLVTH16245AIDGVREP
CLVTH16245AIZQLREP
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DL
48
48
56
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
DGV
ZQL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
CLVTH16245AMDLREP
CLVTH16245AQDGGREP
CLVTH16245AQDLREP
V62/04602-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
TSSOP
SSOP
DL
DGG
DL
48
48
48
48
48
56
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04602-01YE
TSSOP
DGG
GQL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04602-02UA
BGA MI
CROSTA
R JUNI
OR
TBD
Call TI
Call TI
V62/04602-02ZE
V62/04602-03XE
ACTIVE
ACTIVE
TVSOP
DGV
DL
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2008
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH16245A-EP :
Catalog: SN74LVTH16245A
Automotive: SN74LVTH16245A-Q1
Military: SN54LVTH16245A
•
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
•
•
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CLVTH16245AIDGVREP TVSOP
DGV
ZQL
48
56
2000
1000
330.0
330.0
16.4
16.4
7.1
4.8
10.2
7.3
1.6
12.0
8.0
16.0
16.0
Q1
Q1
CLVTH16245AIZQLREP BGA MI
1.45
CROSTA
R JUNI
OR
CLVTH16245AMDLREP SSOP
CLVTH16245AQDGGREP TSSOP
DL
DGG
DL
48
48
48
1000
2000
1000
330.0
330.0
330.0
32.4
24.4
32.4
11.35 16.2
8.6 15.8
11.35 16.2
3.1
1.8
3.1
16.0
12.0
16.0
32.0
24.0
32.0
Q1
Q1
Q1
CLVTH16245AQDLREP
SSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CLVTH16245AIDGVREP
TVSOP
DGV
ZQL
48
56
2000
1000
367.0
333.2
367.0
345.9
38.0
28.6
CLVTH16245AIZQLREP BGA MICROSTAR
JUNIOR
CLVTH16245AMDLREP
CLVTH16245AQDGGREP
CLVTH16245AQDLREP
SSOP
TSSOP
SSOP
DL
DGG
DL
48
48
48
1000
2000
1000
367.0
367.0
367.0
367.0
367.0
367.0
55.0
45.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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