V62/04657-01XE [TI]
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER; 3线至8线译码器/多路解复用器
| 型号： | V62/04657-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER |
| 文件： | 总13页 (文件大小：612K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC138A-EP
www.ti.com....................................................................................................................................... SCAS734D–NOVEMBER 2003–REVISED NOVEMBER 2008
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
xxx
1
FEATURES
•
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D OR PW PACKAGE
(TOP VIEW)
•
•
•
•
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.8 ns at 3.3 V
1
2
3
4
5
6
7
8
16
15 Y0
14
V
A
B
CC
Y1
C
13 Y2
12 Y3
11 Y4
10 Y5
G2A
G2B
G1
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
•
Typical VOHV (Output VOH Undershoot) > 2 V at
VCC = 3.3 V, TA = 25°C
Y7
9
Y6
GND
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range(1)
•
•
•
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
(1) Custom temperature ranges available
DESCRIPTION/ORDERING INFORMATION
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short
propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system
decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder
and the enable time of the memory usually are less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC138A-EP
SCAS734D–NOVEMBER 2003–REVISED NOVEMBER 2008....................................................................................................................................... www.ti.com
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
SN74LVC138AQDREP
TOP-SIDE MARKING
C138AEP
SOIC - D
Reel of 2500
-40°C to 125°C
–55°C to 125°C
TSSOP - PW
TSSOP – PW
Reel of 2000
Reel of 250
SN74LVC138AQPWREP
SN74LVC138AMPWTEP
C138AEP
C138AME
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
X
G2A G2B
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
H
X
X
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
X
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
2
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Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC138A-EP
SN74LVC138A-EP
www.ti.com....................................................................................................................................... SCAS734D–NOVEMBER 2003–REVISED NOVEMBER 2008
LOGIC DIAGRAM (POSITIVE LOGIC)
15
Y0
1
A
14
Y1
2
3
Select
Inputs
B
C
13
12
11
10
9
Y2
Y3
Y4
Y5
Y6
Data
Outputs
6
G1
4
5
Enable
Inputs
7
G2A
G2B
Y7
Copyright © 2003–2008, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN74LVC138A-EP
SN74LVC138A-EP
SCAS734D–NOVEMBER 2003–REVISED NOVEMBER 2008....................................................................................................................................... www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)(3)
6.5
V
VO
IIK
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
±50
±100
73
D package
θJA
Package thermal impedance(4)
Storage temperature range(5)
°C/W
°C
PW package
108
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Recommended Operating Conditions(1)
MIN
2
MAX UNIT
Operating
3.6
V
VCC
Supply voltage
Data retention only
VCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
1.5
2
VIH
VIL
VI
High-level input voltage
Low-level input voltage
Input voltage
V
0.8
5.5
VCC
–12
–24
12
V
V
V
0
0
VO
Output voltage
VCC = 2.7 V
VCC = 3 V
VCC = 2.7 V
VCC = 3 V
IOH
High-level output current
Low-level output current
mA
mA
IOL
24
Δt/Δv Input transition rise or fall rate
TA Operating free-air temperature
10
ns/V
°C
–55
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC138A-EP
SN74LVC138A-EP
www.ti.com....................................................................................................................................... SCAS734D–NOVEMBER 2003–REVISED NOVEMBER 2008
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.7 V to 3.6 V VCC – 0.2
MIN TYP(1)
MAX UNIT
IOH = –100 µA
2.7 V
3 V
2.2
2.4
2.2
VOH
IOH = –12 mA
V
IOH = –24 mA
IOL = 100 µA
3 V
2.7 V to 3.6 V
2.7 V
0.2
VOL
IOL = 12 mA
0.4
0.55
±5
V
IOL = 24 mA
3 V
II
VI = 5.5 V or GND
VI = VCC or GND,
3.6 V
µA
µA
µA
pF
ICC
ΔICC
Ci
IO = 0
3.6 V
10
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
2.7 V to 3.6 V
3.3 V
500
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
＝ 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN
MAX
6.7
A or B or C
G2A or G2B
G1
7.9
7.4
6.4
1
1
1
tpd
Y
6.5
ns
5.8
Operating Characteristics
TA = 25°C
VCC = 2.5 V
VCC = 3.3 V
TYP
TEST
CONDITIONS
PARAMETER
Power dissipation capacitance
UNIT
TYP
Cpd
f = 10 MHz
26
27
pF
Copyright © 2003–2008, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): SN74LVC138A-EP
SN74LVC138A-EP
SCAS734D–NOVEMBER 2003–REVISED NOVEMBER 2008....................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
2.7 V
2.7 V
2.7 V
≤2.5 ns
≤2.5 ns
1.5 V
1.5 V
6 V
6 V
50 pF
50 pF
500 Ω
500 Ω
0.3 V
0.3 V
3.3 V ± 0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
- V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright © 2003–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC138A-EP
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2008
PACKAGING INFORMATION
Orderable Device
SN74LVC138AMPWTEP
SN74LVC138AQDREP
SN74LVC138AQPWREP
V62/04657-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
16
16
16
16
16
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
TSSOP
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04657-01YE
TSSOP
TSSOP
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/04657-02YE
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC138A-EP :
Catalog: SN74LVC138A
Automotive: SN74LVC138A-Q1
Military: SN54LVC138A
•
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Military - QML certified for Military and Defense Applications
•
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC138AMPWTEP TSSOP
SN74LVC138AQDREP SOIC
SN74LVC138AQPWREP TSSOP
PW
D
16
16
16
250
2500
2000
330.0
330.0
330.0
12.4
16.4
12.4
6.9
6.5
6.9
5.6
10.3
5.6
1.6
2.1
1.6
8.0
8.0
8.0
12.0
16.0
12.0
Q1
Q1
Q1
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC138AMPWTEP
SN74LVC138AQDREP
SN74LVC138AQPWREP
TSSOP
SOIC
PW
D
16
16
16
250
2500
2000
367.0
333.2
367.0
367.0
345.9
367.0
35.0
28.6
35.0
TSSOP
PW
Pack Materials-Page 2
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