V62/04729-01XE_技术文档

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

D

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D

UBT  (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Enhanced Diminishing Manufacturing

Sources (DMS) Support

D

Bus Hold on Data Inputs Eliminates the

Need for External Pullup Resistors

Enhanced Product-Change Notification

B-Port Outputs of SN74LVTH182502A

Device Have Equivalent 25-Ω Series

Resistors, So No External Resistors Are

Required

†

Qualification Pedigree

Members of the Texas Instruments

SCOPE  Family of Testability Products

Members of the Texas Instruments

Widebus Family

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V V

D

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

SCOPE  Instruction Set

)

CC

− IEEE Standard 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

D

Support Unregulated Battery Operation

Down to 2.7 V

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

− Parallel-Signature Analysis at Inputs

− Pseudorandom Pattern Generation From

Outputs

− Sample Inputs/Toggle Outputs

− Binary Count From Outputs

− Device Identification

− Even-Parity Opcodes

description/ordering information

The SN74LVTH18502A and SN74LVTH182502A scan test devices, with 18-bit universal bus transceivers, are

members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports

IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan

access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) V

capability to provide a TTL interface to a 5-V system environment.

operation, but with the

CC

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit

transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples

of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP

in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

‡

T

A

PACKAGE

LQFP − PM

Tape and reel

8V18502AIPMREP

LH18502AEP

−40°C to 85°C

§

8V182502AIPMREP

‡

§

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

Product Preview

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE, Widebus, and UBT are trademarks of Texas Instruments.

Copyright  2004, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

description/ordering information (continued)

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when

LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.

Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the

B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is

similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry

performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),

test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs

other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudorandom pattern

generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of SN74LVTH182502A, which are designed to source or sink up to 12 mA, include 25-Ω

series resistors to reduce overshoot and undershoot.

PM PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

1

1B4

1B5

1B6

GND

48

47

46

45

2

3

4

5

44 1B7

43 1B8

6

7

42

41

40

39

38

37

36

35

34

33

1B9

8

V

CC

9

V

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

CC

10

11

12

13

14

15

16

2A1

2A2

2A3

GND

2A4

2A5

2A6

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

†

FUNCTION TABLE

(normal mode, each register)

INPUTS

OUTPUT

B

OEAB

LEAB

CLKAB

A

X

L

‡

B

0

L

H

L

↑

X

L

H

L

H

L

H

X

H

X

H

Z

†

‡

A-to-B data flow is shown. B-to-A data flow is similar,

but uses OEBA, LEBA, and CLKBA.

Output level before the indicated steady-state input

conditions are established

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

functional block diagram

Boundary-Scan Register

60

1LEAB

59

1CLKAB

V

CC

62

1OEAB

1LEBA

54

55

1CLKBA

1OEBA

V

CC

53

C1

1D

C1

1D

63

51

1B1

1A1

C1

1D

C1

1D

One of Nine Channels

22

23

2LEAB

2CLKAB

V

CC

21

2OEAB

2LEBA

28

27

2CLKBA

2OEBA

V

CC

30

C1

1D

C1

1D

40

10

2B1

2A1

C1

1D

C1

1D

One of Nine Channels

Bypass Register

Boundary-Control

Register

Identification

Register

V

58

CC

24

TDO

Instruction

Register

TDI

V

CC

56

TMS

TCK

TAP

Controller

26

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

Terminal Functions

TERMINAL NAME

DESCRIPTION

1A1−1A9,

2A1−2A9

Normal-function A-bus I/O ports. See function table for normal-mode logic.

Normal-function B-bus I/O ports. See function table for normal-mode logic.

1B1−1B9,

2B1−2B9

1CLKAB, 1CLKBA,

2CLKAB, 2CLKBA

Normal-function clock inputs. See function table for normal-mode logic.

Ground

GND

1LEAB, 1LEBA,

2LEAB, 2LEBA

Normal-function latch enables. See function table for normal-mode logic.

1OEAB, 1OEBA,

2OEAB, 2OEBA

Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal forces the

terminal to a high level if left unconnected.

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous

to TCK. Data is captured on the rising edge of TCK, and outputs change on the falling edge of TCK.

TCK

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data

through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data

through the instruction register or selected data register.

TDO

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP

controller states. An internal pullup forces TMS to a high level if left unconnected.

V

CC

Supply voltage

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

test architecture

Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard

1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The

TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the

synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip

control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.

The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and

output data changes on the falling edge of TCK. This scheme ensures that the data to be captured is valid for

fully one-half of the TCK cycle.

The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan

architecture and the relationship among the test bus, the TAP controller, and the test registers. As shown, the

device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit

boundary-control register, a 1-bit bypass register, and a 32-bit device identification register.

Test-Logic-Reset

TMS = H

TMS = L

TMS = H

Run-Test/Idle

Select-DR-Scan

TMS = L

Select-IR-Scan

TMS = L

TMS = H

Capture-DR

TMS = L

Capture-IR

TMS = L

Shift-DR

Shift-IR

TMS = L

TMS = H

Exit1-IR

TMS = H

Exit1-DR

TMS = L

Pause-DR

TMS = H

Pause-IR

TMS = H

Exit2-IR

TMS = L

Exit2-DR

TMS = H

Update-IR

Update-DR

TMS = H

TMS = L

TMS = H

TMS = L

Figure 1. TAP-Controller State Diagram

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

state diagram description

The TAP controller is a synchronous finite-state machine that provides test control signals throughout the

device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP

controller proceeds through its states, based on the level of TMS at the rising edge of TCK.

As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in

the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive

TCK cycles. Any state that does not meet this criterion is an unstable state.

There are two main paths through the state diagram: one to access and control the selected data register and

one to access and control the instruction register. Only one register can be accessed at a time.

Test-Logic-Reset

The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset

and is disabled so that the normal logic function of the device is performed. The instruction register is reset to

an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data

registers also can be reset to their power-up values.

The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more

than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left

unconnected or if a board defect causes it to be open circuited.

For the SN74LVTH18502A and SN74LVTH182502A, the instruction register is reset to the binary value

10000001, which selects the IDCODE instruction. Bits 47−44 in the boundary-scan register are reset to logic

1, ensuring that these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode

were invoked, the outputs would be at the high-impedance state). Reset values of other bits in the

boundary-scan register should be considered indeterminate. The boundary-control register is reset to the binary

value 010, which selects the PSA test operation.

Run-Test/Idle

The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test

operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.

Run-Test/Idle is a stable state in which the test logic actively can be running a test or can be idle. The test

operations selected by the boundary-control register are performed while the TAP controller is in the

Run-Test/Idle state.

Select-DR-Scan, Select-lR-Scan

No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits

either of these states on the next TCK cycle. These states allow the selection of either data-register scan or

instruction-register scan.

Capture-DR

When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the

Capture-DR state, the selected data register can capture a data value as specified by the current instruction.

Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the

Capture-DR state.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

Shift-DR

Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the

first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic

level present in the least-significant bit of the selected data register.

While in the stable Shift-DR state, data is shifted serially through the selected data register on each TCK cycle.

The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during

the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).

The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.

Exit1-DR, Exit2-DR

The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return

to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling

edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.

Pause-DR

No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain

indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.

Update-DR

If the current instruction calls for the selected data register to be updated with current data, such update occurs

on the falling edge of TCK, following entry to the Update-DR state.

Capture-IR

When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In

the Capture-IR state, the instruction register captures its current status value. This capture operation occurs

on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the SN74LVTH18502A

and SN74LVTH182502A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.

Shift-IR

Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On

the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to the

logic level present in the least-significant bit of the instruction register.

While in the stable Shift-IR state, instruction data is shifted serially through the instruction register on each TCK

cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs

during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to

Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state.

Exit1-IR, Exit2-IR

The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to

return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the

first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.

Pause-IR

No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain

indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss

of data.

Update-IR

The current instruction is updated and takes effect on the falling edge of TCK, following entry to the

Update-IR state.

8

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

register overview

With the exception of the bypass and device-identification registers, any test register can be thought of as a

serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that

they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,

Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current

instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted

out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or

Update-DR), the shadow latches are updated from the shift register.

instruction register description

The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information

contained in the instruction includes the mode of operation (either normal mode, in which the device performs

its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation

to be performed, which of the four data registers is to be selected for inclusion in the scan path during

data-register scans, and the source of data to be captured into the selected data register during Capture-DR.

Table 3 lists the instructions supported by the SN74LVTH18502A and SN74LVTH182502A. The even-parity

feature specified for SCOPE devices is supported in this device. Bit 7 of the instruction opcode is the parity bit.

Any instructions that are defined for SCOPE devices, but are not supported by this device, default to BYPASS.

During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted

out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value

that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated,

and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the

binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.

Bit 7

Parity

(MSB)

Bit 0

(LSB)

TDI

TDO

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Figure 2. Instruction Register Order of Scan

9

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ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

data register description

boundary-scan register

The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each

normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and

output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins,

and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at

the device input pins.

The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The

contents of the BSR can change during Run-Test/Idle, as determined by the current instruction. At power up

or in Test-Logic-Reset, BSCs 47−44 are reset to logic 1, ensuring that these cells, which control A-port and

B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at the

high-impedance state). Reset values of other BSCs should be considered indeterminate.

The BSR order of scan is from TDI through bits 47−0 to TDO. Table 1 shows the BSR bits and their associated

device pin signals.

Table 1. Boundary-Scan Register Configuration

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

BSR BIT

NUMBER

DEVICE

SIGNAL

47

46

45

44

43

42

41

40

39

38

37

36

−−

2OEAB

1OEAB

2OEBA

1OEBA

2CLKAB

1CLKAB

2CLKBA

1CLKBA

2LEAB

1LEAB

2LEBA

1LEBA

−−

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

2A9-I/O

2A8-I/O

2A7-I/O

2A6-I/O

2A5-I/O

2A4-I/O

2A3-I/O

2A2-I/O

2A1-I/O

1A9-I/O

1A8-I/O

1A7-I/O

1A6-I/O

1A5-I/O

1A4-I/O

1A3-I/O

1A2-I/O

1A1-I/O

17

16

15

14

13

12

11

10

9

2B9-I/O

2B8-I/O

2B7-I/O

2B6-I/O

2B5-I/O

2B4-I/O

2B3-I/O

2B2-I/O

2B1-I/O

1B9-I/O

1B8-I/O

1B7-I/O

1B6-I/O

1B5-I/O

1B4-I/O

1B3-I/O

1B2-I/O

1B1-I/O

8

7

6

5

−−

4

−−

3

−−

2

−−

1

−−

0

10

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

boundary-control register

The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test

(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set.

Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that

are decoded by the BCR.

During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is

reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.

Bit 2

(MSB)

Bit 0

(LSB)

TDI

TDO

Bit 1

Figure 3. Boundary-Control Register Order of Scan

bypass register

The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,

reducing the number of bits per test pattern that must be applied to complete a test operation. During

Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.

TDI

TDO

Bit 0

Figure 4. Bypass Register Order of Scan

11

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ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

device-identification register

The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,

part number, and version of this device.

For the SN74LVTH18502A, the binary value 00110000000000011100000000101111 (3001C02F, hex) is

captured (during Capture-DR state) in the IDR to identify this device as Texas Instruments SN74LVTH18502A.

For the SN74LVTH182502A, the binary value 00110000000000100001000000101111 (3002102F, hex) is

captured (during Capture-DR state) in the device-identification register to identify this device as Texas

Instruments SN74LVTH182502A.

The IDR order of scan is from TDI through bits 31−0 to TDO. Table 2 shows the IDR bits and their significance.

Table 2. Device-Identification Register Configuration

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

IDR BIT

NUMBER

IDENTIFICATION

SIGNIFICANCE

†

31

30

29

28

−−

VERSION3

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

PARTNUMBER15

PARTNUMBER14

PARTNUMBER13

PARTNUMBER12

PARTNUMBER11

PARTNUMBER10

PARTNUMBER09

PARTNUMBER08

PARTNUMBER07

PARTNUMBER06

PARTNUMBER05

PARTNUMBER04

PARTNUMBER03

PARTNUMBER02

PARTNUMBER01

PARTNUMBER00

11

10

9

MANUFACTURER10

MANUFACTURER09

MANUFACTURER08

MANUFACTURER07

MANUFACTURER06

MANUFACTURER05

MANUFACTURER04

MANUFACTURER03

MANUFACTURER02

MANUFACTURER01

MANUFACTURER00

VERSION2

VERSION1

VERSION0

8

−−

7

6

5

4

3

2

1

†

0

LOGIC1

−−

†

Note that, for TI products, bits 11−0 of the device-identification register always contain the binary value 000000101111

(02F, hex).

12

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

instruction-register opcode description

The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of

each instruction.

Table 3. Instruction-Register Opcodes

†

BINARY CODE

BIT 7 → BIT 0

MSB → LSB

SELECTED DATA

REGISTER

SCOPE OPCODE

DESCRIPTION

MODE

00000000

10000001

10000010

00000011

10000100

00000101

00000110

10000111

10001000

00001001

00001010

10001011

00001100

10001101

10001110

00001111

All others

EXTEST

IDCODE

Boundary scan

Identification read

Boundary scan

Device identification

Boundary scan

Bypass

Test

Normal

Modified test

Test

SAMPLE/PRELOAD

Sample boundary

‡

BYPASS

HIGHZ

Bypass scan

Bypass

Bypass scan

Bypass

Control boundary to high impedance

Control boundary to 1/0

Bypass scan

Bypass

CLAMP

Bypass

‡

BYPASS

Bypass

Normal

Test

RUNT

Boundary-run test

Bypass

READBN

READBT

CELLTST

TOPHIP

SCANCN

SCANCT

BYPASS

Boundary read

Boundary scan

Bypass

Normal

Test

Boundary read

Boundary self test

Boundary toggle outputs

Boundary-control register scan

Bypass scan

Normal

Test

Boundary control

Bypass

Normal

Test

Normal

†

‡

Bit 7 is used to maintain even parity in the 8-bit instruction.

The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the SN74LVTH18502A or SN74LVTH182502A.

boundary scan

This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST instruction. The BSR is selected in the

scan path. Data appearing at the device input and I/O pins is captured in the associated BSCs. Data that has

been scanned into the I/O BSCs for pins in the output mode is applied to the device I/O pins. Data present at

the device pins, except for output enables, is passed through the BSCs to the normal on-chip logic. For I/O pins,

the operation of a pin as input or output is determined by the contents of the output-enable BSCs (bits 47−44

of the BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode.

Otherwise, the I/O pins operate in the input mode. The device operates in the test mode.

identification read

This instruction conforms to the IEEE Standard 1149.1-1990 IDCODE instruction. The IDR is selected in the

scan path. The device operates in the normal mode.

sample boundary

This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is

selected in the scan path. Data appearing at the device input pins and I/O pins in the input mode is captured

in the associated BSCs, while data appearing at the outputs of the normal on-chip logic is captured in the BSCs

associated with I/O pins in the output mode. The device operates in the normal mode.

13

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

bypass scan

This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in the normal mode.

control boundary to high impedance

This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device

operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device

input pins remain operational, and the normal on-chip logic function is performed.

control boundary to 1/0

This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is

selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O

BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode.

boundary-run test

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during

Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),

PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up

(PSA/COUNT).

boundary read

The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This

instruction is useful for inspecting data after a PSA operation.

boundary self test

The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.

In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and

shadow-latch elements of the BSR. The device operates in the normal mode.

boundary toggle outputs

The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during

Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising

edge of TCK in Run-Test/Idle and then is updated in the shadow latches and applied to the associated device

I/O pins on each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data

appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the

test mode.

boundary-control-register scan

The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This

operation must be performed before a boundary-run test operation to specify which test operation is to

be executed.

14

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

boundary-control-register opcode description

The BCR opcodes are decoded from BCR bits 2−0, as shown in Table 4. The selected test operation is

performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail

the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.

Table 4. Boundary-Control Register Opcodes

BINARY CODE

BIT 2 → BIT 0

MSB → LSB

DESCRIPTION

X00

X01

X10

011

111

Sample inputs/toggle outputs (TOPSIP)

Pseudorandom pattern generation/36-bit mode (PRPG)

Parallel-signature analysis/36-bit mode (PSA)

Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)

Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)

While the control input BSCs (bits 47−36) are not included in the toggle, PSA, PRPG, or COUNT algorithms,

the output-enable BSCs (bits 47−44 of the BSR) control the drive state (active or high impedance) of the selected

device output pins. These BCR instructions are valid only when both bytes of the device are operating in one

direction of data flow (i.e., 1OEAB ≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction of data flow (i.e.,

1OEAB = 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.

sample inputs/toggle outputs (TOPSIP)

Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the

associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode

BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated

device I/O pins on each falling edge of TCK.

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

pseudorandom pattern generation (PRPG)

A pseudorandom pattern is generated in the shift-register elements of the selected BSCs on each rising edge

of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each

falling edge of TCK. Figures 5 and 6 show the 36-bit linear-feedback shift-register algorithms through which the

patterns are generated. An initial seed value should be scanned into the BSR before performing this operation.

A seed value of all zeroes does not produce additional patterns.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 5. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

parallel-signature analysis (PSA)

Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the

shift-register elements of the selected BSCs on each rising edge of TCK. Data in the shadow latches of the

selected output-mode BSCs remains constant and is applied to the associated device I/O pins. Figures 7 and 8

show the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial

seed value should be scanned into the BSR before performing this operation.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 7. 36-Bit PSA Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 8. 36-Bit PSA Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

simultaneous PSA and PRPG (PSA/PRPG)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in

the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an

18-bit pseudorandom pattern is generated in the shift-register elements of the selected output-mode BSCs on

each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each

falling edge of TCK. Figures 9 and 10 show the 18-bit linear-feedback shift-register algorithms through which

the signature and patterns are generated. An initial seed value should be scanned into the BSR before

performing this operation. A seed value of all zeroes does not produce additional patterns.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 9. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 10. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

simultaneous PSA and binary count up (PSA/COUNT)

Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in

the shift-register elements of the selected input-mode BSCs on each rising edge of TCK. At the same time, an

18-bit binary count-up pattern is generated in the shift-register elements of the selected output-mode BSCs on

each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each

falling edge of TCK. Figures 11 and 12 show the 18-bit linear-feedback shift-register algorithms through which

the signature is generated. An initial seed value should be scanned into the BSR before performing

this operation.

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

MSB

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

LSB

=

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

Figure 11. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O

1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O

MSB

2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O

LSB

=

1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O

Figure 12. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

timing description

All test operations of the SN74LVTH18502A and SN74LVTH182502A are synchronous to the TCK signal. Data

on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO

and normal-function output pins on the falling edge of TCK. The TAP controller is advanced through its states

(as shown in Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge

to TCK.

A simple timing example is shown in Figure 13. In this example, the TAP controller begins in the

Test-Logic-Reset state and is advanced through its states, as necessary, to perform one instruction-register

scan and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and

TDO is used to output serial data. The TAP controller then is returned to the Test-Logic-Reset state. Table 5

details the operation of the test circuitry during each TCK cycle.

Table 5. Explanation of Timing Example

TCK

CYCLE(S)

TAP STATE

AFTER TCK

DESCRIPTION

TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward

the desired state.

1

Test-Logic-Reset

2

3

4

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the

Capture-IR state.

5

6

Capture-IR

Shift-IR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on

the rising edge of TCK as the TAP controller advances to the next state.

One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value

11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned

out of the IR via TDO. In TCK cycle 13, TMS is changed to a logic 1 value to end the IR scan on the next TCK

cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.

7−13

Shift-IR

14

15

16

Exit1-IR

Update-IR

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.

Select-DR-Scan

The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the

Capture-DR state.

17

18

Capture-DR

Shift-DR

TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on

the rising edge of TCK as the TAP controller advances to the next state.

19−20

21

Shift-DR

Exit1-DR

The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.

TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.

The selected data register is updated with the new data on the falling edge of TCK.

22

Update-DR

23

Select-DR-Scan

Select-IR-Scan

24

25

Test-Logic-Reset Test operation completed

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

1

2

3

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5

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8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TCK

TMS

TDI

TDO

TAP

Controller

State

3-State (TDO) or Don’t Care (TDI)

Figure 13. Timing Example

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . −0.5 V to 7 V

O

Current into any output in the low state, I : SN74LVTH18502A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

O

SN74LVTH182502A (A port or TDO) . . . . . . . . . . . . . . . . 128 mA

SN74LVTH182502A (B port) . . . . . . . . . . . . . . . . . . . . . . . . 30 mA

Current into any output in the high state, I (see Note 2): SN74LVTH18502A . . . . . . . . . . . . . . . . . . . . 64 mA

O

SN74LVTH182502A (A port or TDO) . . . . 64 mA

SN74LVTH182502A (B port) . . . . . . . . . . . 30 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

JA

stg

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

.

CC

O

3. The package thermal impedance is calculated in accordance with JESD 51.

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

recommended operating conditions (see Note 4)

SN74LVTH18502A-EP

UNIT

MIN

2.7

2

MAX

V

Supply voltage

3.6

V

CC

High-level input voltage

Low-level input voltage

Input voltage

IH

0.8

5.5

−32

32

V

IL

V

I

High-level output current

Low-level output current

Input transition rise or fall rate

Operating free-air temperature

mA

ns/V

°C

OH

OL

†

64

OL

∆t/∆v

Outputs enabled

10

T

A

−40

85

†

Current duty cycle ≤50%, f ≥ 1 kHz

NOTE 4: All unused CLK, LE, or TCK inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI

CC

application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀ

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ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢌ

ꢊ

ꢋ

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ꢒ ꢓꢒ ꢎꢅ ꢍꢔꢆ ꢀꢕ ꢍꢁ ꢆ ꢏꢀꢆ ꢖ ꢏꢅ ꢗ ꢕꢏ

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN74LVTH18502A-EP

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

V

= 2.7 V,

I = −18 mA

−1.2

V

IK

CC

I

= 2.7 V to 3.6 V,

= 2.7 V,

I

= −100 µA

= −3 mA

= −8 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 64 mA

V

CC

−0.2

2.4

2

OH

OL

V

OH

V

= 3 V

CC

0.2

0.5

0.4

0.5

0.55

1

V

= 2.7 V

V

OL

V

CC

= 3 V

V

= 3.6 V,

V = V or GND

I CC

CC

CLK,

LE, TCK

= 0 or 3.6 V,

V = 5.5 V

I

10

CC

V = 5.5 V

I

5

OE, TDI,

TMS

V = V

1

V

= 3.6 V

I

CC

I

µA

V = 0

I

−25

−100

20

V = 5.5 V

I

A or B

V = V

1

V

I

CC

‡

ports

V = 0

I

−5

I

V

= 0,

V or V = 0 to 4.5 V

100

500

µA

off

CC

I

O

V = 0.8 V

I

75

150

A or B

ports

§

= 3 V

CC

I(hold)

V = 2 V

I

−75

−150 −500

I

TDO

V

CC

V

CC

V

CC

V

CC

= 3.6 V,

V

O

V

O

V

O

V

O

= 3 V

1

−1

50

µA

OZH

= 3.6 V,

= 0.5 V

OZL

= 0 to 1.5 V,

= 1.5 V to 0,

= 0.5 V or 3 V

OZPU

OZPD

Outputs high

Outputs low

0.6

18

2

24

2

I

V

= 3.6 V, I = 0, V = V

CC

or GND

mA

CC

O

I

Outputs disabled

0.6

¶

V

= 3 V to 3.6 V, One input at V

CC

− 0.6 V, Other inputs at V

or GND

0.5

mA

pF

∆I

CC

C

V = 3 V or 0

I

4

10

8

i

V

= 3 V or 0

io

o

O

V

†

‡

§

¶

All typical values are at V

= 3.3 V, T = 25°C.

A

CC

Unused pins at V

or GND

CC

The parameter I

includes the off-state output leakage current.

I(hold)

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

CC

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (normal mode) (see Figure 14)

SN74LVTH18502A-EP

V = 3.3 V

CC

0.3 V

V

CC

= 2.7 V

UNIT

MIN

MAX

MIN

0

MAX

f

t

Clock frequency CLKAB or CLKBA

CLKAB or CLKBA high or low

0

4.4

3

100

80

MHz

ns

clock

5.6

3

Pulse duration

Setup time

Hold time

w

LEAB or LEBA high

A before CLKAB↑ or B before CLKBA↑

2.8

1.5

1.6

1.4

3.1

3

CLK high

CLK low

0.7

1.6

1.1

3.5

t

ns

su

A before LEAB↓ or B before LEBA↓

A after CLKAB↑ or B after CLKBA↑

A after LEAB↓ or B after LEBA↓

h

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (test mode) (see Figure 14)

SN74LVTH18502A-EP

V = 3.3 V

CC

0.3 V

V

CC

= 2.7 V

UNIT

MIN

MAX

MIN

0

MAX

f

t

Clock frequency

Pulse duration

TCK

0

9.5

6.5

2.5

1.5

50

40

MHz

ns

clock

TCK high or low

10.5

7

w

A, B, CLK, LE, or OE before TCK↑

TDI before TCK↑

3.5

1

t

Setup time

Hold time

ns

su

h

TMS before TCK↑

A, B, CLK, LE, or OE after TCK↑

TDI after TCK↑

1

t

TMS after TCK↑

1

t

Delay time

Rise time

Power up to TCK↑

50

1

ns

d

V

CC

power up

1

µs

r

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢒ ꢓꢒ ꢎꢅ ꢍꢔꢆ ꢀꢕ ꢍꢁ ꢆ ꢏꢀꢆ ꢖ ꢏꢅ ꢗ ꢕꢏ

ꢘ

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SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (normal mode) (see Figure 14)

SN74LVTH18502A-EP

V

= 3.3 V

FROM

(INPUT)

TO

(OUTPUT)

CC

0.3 V

V

= 2.7 V

MAX

PARAMETER

UNIT

CC

MIN

MAX

MIN

f

t

CLKAB or CLKBA

A or B

100

1.5

2.5

80

MHz

ns

max

4.9

5.8

7.4

5.7

7.1

7.8

5.6

6.8

8.4

6.4

8.3

8.4

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

B or A

CLKAB or CLKBA

LEAB or LEBA

OEAB or OEBA

ns

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (test mode) (see Figure 14)

SN74LVTH18502A-EP

V

= 3.3 V

FROM

(INPUT)

TO

(OUTPUT)

CC

0.3 V

V

= 2.7 V

MAX

PARAMETER

UNIT

CC

MIN

MAX

MIN

f

t

TCK

50

2.5

1

40

MHz

ns

max

14

5.5

6.5

17

5.5

18

17

7

17

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

TCK↓

A or B

TDO

6.5

7.5

20

TCK↓

ns

1.5

4

A or B

TDO

4

20

1

6.5

20

1.5

4

A or B

TDO

4

18.5

8.5

8

1.5

7

29

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

recommended operating conditions (see Note 4)

SN74LVTH182502A-EP

UNIT

MIN

2.7

2

MAX

V

CC

V

IH

V

IL

V

I

Supply voltage

3.6

V

High-level input voltage

Low-level input voltage

Input voltage

0.8

5.5

−32

−12

32

A port, TDO

B port

I

High-level output current

Low-level output current

mA

OH

OL

A port, TDO

B port

I

12

†

Low-level output current

A port, TDO

Outputs enabled

64

mA

ns/V

°C

OL

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

10

T

−40

85

A

†

Current duty cycle ≤50%, f ≥ 1 kHz

NOTE 1: All unused CLK, LE, or TCK inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI

CC

application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

ꢐ

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ꢦ

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ꢥ

ꢩ

ꢦ

ꢟ

ꢪ

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ꢠ ꢥ ꢟ ꢞ ꢰ ꢦ ꢪꢝ ꢧ ꢟ ꢥ ꢡꢨ ꢠꢥ ꢱ ꢥ ꢬ ꢡꢪ ꢤꢥ ꢦ ꢜꢓ ꢕ ꢝꢧ ꢩꢧ ꢢꢜ ꢥꢩ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢩ

ꢜ

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ꢡ

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ꢧ

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ꢦ

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ꢡ

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ꢧ

ꢟ

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ꢢ ꢝ ꢧ ꢦ ꢰꢥ ꢡꢩ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣ ꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢪꢩ ꢡ ꢠꢣꢢ ꢜꢟ ꢮ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢓ

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30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢈ

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ꢒ ꢓꢒ ꢎꢅ ꢍꢔꢆ ꢀꢕ ꢍꢁ ꢆ ꢏꢀꢆ ꢖ ꢏꢅ ꢗ ꢕꢏ

ꢘ

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ꢍ

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ꢚ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN74LVTH182502A-EP

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

V

= 2.7 V,

I = −18 mA

−1.2

V

IK

CC

I

A, B, TDO

= 2.7 V to 3.6 V,

= 2.7 V,

I

= −100 µA

= −3 mA

= −8 mA

= −32 mA

= −12 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 64 mA

= 12 mA

V

CC

−0.2

2.4

2

OH

OL

A port,

TDO

V

OH

V

CC

= 3 V

B port

V

CC

V

CC

V

CC

= 3 V,

2

A, B, TDO

= 2.7 V,

0.2

0.5

0.4

0.5

0.55

0.8

1

A port,

TDO

V

OL

V

CC

= 3 V

B port

V

CC

V

CC

V

CC

= 3 V,

= 3.6 V,

V = V or GND

I CC

CLK,

LE, TCK

= 0 or 3.6 V,

V = 5.5 V

I

10

V = 5.5 V

I

5

OE,

TDI, TMS

V = V

1

V

= 3.6 V

I

CC

I

µA

V = 0

I

−25

−100

20

V = 5.5 V

I

A or B

ports

V = V

1

V

I

CC

‡

V = 0

I

−5

I

V

= 0,

V or V = 0 to 4.5 V

100

500

µA

off

CC

I

O

V = 0.8 V

I

75

150

A or B

ports

§

= 3 V

CC

I(hold)

V = 2 V

I

−75

−150 −500

I

TDO

V

CC

V

CC

V

CC

V

CC

= 3.6 V,

V

O

V

O

V

O

V

O

= 3 V

1

−1

50

µA

OZH

= 3.6 V,

= 0.5 V

OZL

= 0 to 1.5 V,

= 1.5 V to 0,

= 0.5 V or 3 V

OZPU

OZPD

Outputs high

Outputs low

0.6

18

2

24

2

I

V

= 3.6 V, I = 0, V = V

CC

or GND

mA

CC

O

I

Outputs disabled

0.6

¶

V

= 3 V to 3.6 V, One input at V

CC

− 0.6 V, Other inputs at V

or GND

0.5

mA

pF

∆I

CC

C

V = 3 V or 0

I

4

10

8

i

V

= 3 V or 0

io

o

O

V

†

‡

§

¶

All typical values are at V

= 3.3 V, T = 25°C.

A

CC

Unused pins at V

or GND

CC

The parameter I

includes the off-state output leakage current.

I(hold)

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

CC

ꢐ

ꢚ

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ꢙ

ꢕ

ꢆ

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ꢏ

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ꢦ

ꢢ

ꢥ

ꢩ

ꢦ

ꢟ

ꢪ

ꢩ

ꢡ

ꢠ

ꢣ

ꢠꢥ ꢟ ꢞ ꢰꢦ ꢪꢝ ꢧ ꢟ ꢥ ꢡꢨ ꢠꢥ ꢱ ꢥ ꢬꢡ ꢪꢤꢥ ꢦꢜꢓ ꢕ ꢝꢧ ꢩꢧ ꢢꢜ ꢥꢩ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢩ

ꢢ

ꢜ

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ꢡ

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ꢱ

ꢥ

ꢡ

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ꢟ

ꢪ

ꢥ

ꢢ

ꢞ

ꢨ

ꢞ

ꢢ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢟ

ꢧ

ꢩ

ꢥ

ꢠ

ꢥ

ꢟ

ꢞ

ꢰ

ꢦ

ꢰ

ꢡ

ꢧ

ꢬ

ꢟ

ꢓ

ꢆ

ꢥ

ꢭ

ꢧ

ꢟ

ꢗ

ꢦ

ꢟ

ꢜ

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ꢣ

ꢤ

ꢥ

ꢦ

ꢢ ꢝꢧ ꢦ ꢰꢥ ꢡꢩ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢪꢩ ꢡꢠ ꢣꢢꢜ ꢟ ꢮ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢓ

ꢜ

ꢟ

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ꢥ

ꢟ

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31

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (normal mode) (see Figure 14)

SN74LVTH182502A-EP

V = 3.3 V

CC

0.3 V

V

CC

= 2.7 V

UNIT

MIN

MAX

MIN

0

MAX

f

t

Clock frequency CLKAB or CLKBA

CLKAB or CLKBA high or low

0

4.4

3

100

80

MHz

ns

clock

5.6

3

Pulse duration

Setup time

Hold time

w

LEAB or LEBA high

A before CLKAB↑ or B before CLKBA↑

2.8

1.5

1.6

1.4

3.1

3

CLK high

CLK low

0.7

1.6

1.1

3.5

t

ns

su

A before LEAB↓ or B before LEBA↓

A after CLKAB↑ or B after CLKBA↑

A after LEAB↓ or B after LEBA↓

h

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (test mode) (see Figure 14)

SN74LVTH182502A-EP

V = 3.3 V

CC

0.3 V

V

CC

= 2.7 V

UNIT

MIN

MAX

MIN

0

MAX

f

t

Clock frequency

Pulse duration

TCK

0

9.5

6.5

2.5

1.5

50

40

MHz

ns

clock

TCK high or low

10.5

7

w

A, B, CLK, LE, or OE before TCK↑

TDI before TCK↑

3.5

1

t

Setup time

Hold time

ns

su

h

TMS before TCK↑

A, B, CLK, LE, or OE after TCK↑

TDI after TCK↑

1

t

TMS after TCK↑

1

t

Delay time

Rise time

Power up to TCK↑

50

1

ns

d

V

CC

power up

1

µs

r

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ꢡ

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ꢡ

ꢦ

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ꢥ

ꢩ

ꢦ

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ꢪ

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ꢠ ꢥ ꢟ ꢞ ꢰ ꢦ ꢪꢝ ꢧ ꢟ ꢥ ꢡꢨ ꢠꢥ ꢱ ꢥ ꢬ ꢡꢪ ꢤꢥ ꢦ ꢜꢓ ꢕ ꢝꢧ ꢩꢧ ꢢꢜ ꢥꢩ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢩ

ꢜ

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ꢱ

ꢥ

ꢡ

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ꢟ

ꢪ

ꢥ

ꢢ

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ꢨ

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ꢢ

ꢧ

ꢜ

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ꢡ

ꢦ

ꢟ

ꢧ

ꢩ

ꢥ

ꢠ

ꢥ

ꢟ

ꢞ

ꢰ

ꢦ

ꢰ

ꢡ

ꢧ

ꢬ

ꢟ

ꢓ

ꢆ

ꢥ

ꢭ

ꢧ

ꢟ

ꢗ

ꢦ

ꢟ

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ꢦ

ꢢ ꢝ ꢧ ꢦ ꢰꢥ ꢡꢩ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣ ꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢪꢩ ꢡ ꢠꢣꢢ ꢜꢟ ꢮ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢓ

ꢜ

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32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢌ

ꢍ

ꢎ

ꢏ

ꢐ

ꢑ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢌ

ꢊ

ꢋ

ꢌ

ꢍ

ꢎ

ꢏ

ꢐ

ꢀ

ꢒ ꢓꢒ ꢎꢅ ꢍꢔꢆ ꢀꢕ ꢍꢁ ꢆ ꢏꢀꢆ ꢖ ꢏꢅ ꢗ ꢕꢏ

ꢘ

ꢗ

ꢆ

ꢇ

ꢈ

ꢉ

ꢎ

ꢔ

ꢗ

ꢆ

ꢙ

ꢁ

ꢗ

ꢅ

ꢏ

ꢚ

ꢀ

ꢍ

ꢄ

ꢔ

ꢙ

ꢀ

ꢆ

ꢚ

ꢍ

ꢁ

ꢀ

ꢕ

ꢏ

ꢗ

ꢅ

ꢏ

ꢚ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (normal mode) (see Figure 14)

SN74LVTH182502A-EP

V

= 3.3 V

FROM

(INPUT)

TO

(OUTPUT)

CC

0.3 V

V

= 2.7 V

MAX

PARAMETER

UNIT

CC

MIN

MAX

MIN

f

t

CLKAB or CLKBA

A

100

1.5

2.5

80

MHz

ns

max

5.7

4.9

6.7

5.8

8.2

6.2

7.4

5.7

7.9

8.4

6.4

5.6

7.7

6.8

9.2

6.7

8.4

6.4

8.7

8.9

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

B

CLKAB

A

ns

B

A

CLKBA

LEAB

B

LEBA

A

OEAB or OEBA

B or A

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (test mode) (see Figure 14)

SN74LVTH182502A-EP

V

= 3.3 V

FROM

(INPUT)

TO

(OUTPUT)

CC

0.3 V

V

= 2.7 V

MAX

PARAMETER

UNIT

CC

MIN

MAX

MIN

f

t

TCK

50

2.5

1

40

MHz

ns

max

14

5.5

6.5

17

5.5

18

17

7

17

PLH

PHL

PLH

PHL

PZH

PZL

PZH

PZL

PHZ

PLZ

PHZ

PLZ

TCK↓

A or B

TDO

6.5

7.5

20

TCK↓

ns

1.5

4

A or B

TDO

4

20

1

6.5

20

1.5

4

A or B

TDO

4

18.5

8.5

8

1.5

7

ꢐ

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ꢆ

ꢐ

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ꢏ

ꢘ

ꢞ

ꢦ

ꢨ

ꢡ

ꢩ

ꢤ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢢ

ꢡ

ꢦ

ꢢ

ꢥ

ꢩ

ꢦ

ꢟ

ꢪ

ꢩ

ꢡ

ꢠ

ꢣ

ꢠꢥ ꢟ ꢞ ꢰꢦ ꢪꢝ ꢧ ꢟ ꢥ ꢡꢨ ꢠꢥ ꢱ ꢥ ꢬꢡ ꢪꢤꢥ ꢦꢜꢓ ꢕ ꢝꢧ ꢩꢧ ꢢꢜ ꢥꢩ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢩ

ꢢ

ꢜ

ꢟ

ꢞ

ꢦ

ꢜ

ꢝ

ꢥ

ꢨ

ꢡ

ꢩ

ꢤ

ꢧ

ꢜ

ꢞ

ꢱ

ꢥ

ꢡ

ꢩ

ꢟ

ꢪ

ꢥ

ꢢ

ꢞ

ꢨ

ꢞ

ꢢ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢟ

ꢧ

ꢩ

ꢥ

ꢠ

ꢥ

ꢟ

ꢞ

ꢰ

ꢦ

ꢰ

ꢡ

ꢧ

ꢬ

ꢟ

ꢓ

ꢆ

ꢥ

ꢭ

ꢧ

ꢟ

ꢗ

ꢦ

ꢟ

ꢜ

ꢩ

ꢣ

ꢤ

ꢥ

ꢦ

ꢢ ꢝꢧ ꢦ ꢰꢥ ꢡꢩ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢪꢩ ꢡꢠ ꢣꢢꢜ ꢟ ꢮ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢓ

ꢜ

ꢟ

ꢩ

ꢥ

ꢟ

ꢥ

ꢩ

ꢱ

ꢥ

ꢟ

ꢜ

ꢝ

ꢥ

ꢩ

ꢞ

ꢰ

ꢝ

ꢜ

ꢡ

33

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋ ꢌꢍ ꢎꢏꢐꢑ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢌ ꢊ ꢋꢌ ꢍ ꢎꢏꢐ

ꢒꢓ ꢒꢎꢅ ꢍ ꢔꢆ ꢀꢕ ꢍ ꢁ ꢆꢏ ꢀ ꢆ ꢖꢏ ꢅ ꢗ ꢕꢏ ꢀ

ꢘꢗ ꢆ ꢇ ꢈ ꢉꢎ ꢔꢗ ꢆ ꢙ ꢁ ꢗ ꢅꢏ ꢚꢀ ꢍꢄ ꢔꢙ ꢀ ꢆꢚ ꢍꢁ ꢀꢕ ꢏꢗ ꢅꢏꢚꢀ

SCAS744A − DECEMBER 2003 − REVISED JUNE 2004

PARAMETER MEASUREMENT INFORMATION

6 V

S1

500 Ω

Open

GND

From Output

Under Test

TEST

S1

t

/t

Open

6 V

PLH PHL

/t

C

= 50 pF

L

t

500 Ω

PLZ PZL

/t

(see Note A)

GND

PHZ PZH

LOAD CIRCUIT

2.7 V

0 V

1.5 V

Timing Input

Data Input

t

w

t

h

su

2.7 V

0 V

2.7 V

0 V

1.5 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

0 V

Output

Control

1.5 V

Input

1.5 V

t

PLH

PHL

PZL

PLZ

+ 0.3 V

Output

Waveform 1

S1 at 6 V

V

3 V

OH

1.5 V

Output

1.5 V

V

OL

V

OL

(see Note B)

t

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

V

OH

V

OH

− 0.3 V

OH

1.5 V

Output

≈0 V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time, with one transition per measurement.

Figure 14. Load Circuit and Voltage Waveforms

34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LQFP

Drawing

8V18502AIPMREP

V62/04729-01XE

ACTIVE

PM

64

1000

TBD

CU NIPDAU Level-3-220C-168 HR

PM

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVTH18502A-EP :

Catalog: SN74LVTH18502A

Military: SN54LVTH18502A

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

Military - QML certified for Military and Defense Applications

•

Addendum-Page 1

MECHANICAL DATA

MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

M

0,08

33

48

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

0°–7°

11,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040152/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. May also be thermally enhanced plastic with leads connected to the die pads.