V62/06651-01XE [TI]
DUAL 12-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER; 双通道12位200 MSPS数位类比转换器
| 型号： | V62/06651-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 12-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总29页 (文件大小：670K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC5662-EP
www.ti.com
SGLS340A–JUNE 2006–REVISED OCTOBER 2006
DUAL 12-BIT 200-MSPS DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
High Spurious-Free Dynamic Range (SFDR):
85 dBc at 5 MHz
•
Controlled Baseline
High Third-Order Two-Tone Intermodulation
(IMD3): 78 dBc at 15.1 and 16.1 MHz
– One Assembly
– One Test Site
WCDMA Adjacent Channel Leakage Ratio
(ACLR): 70 dB at 30.72 MHz
– One Fabrication Site
•
•
Extended Temperature Performance of
–55°C to 125°C
•
•
•
•
•
•
Independent or Single Resistor Gain Control
Dual or Interleaved Data
Enhanced Diminishing Manufacturing
Sources (DMS) Support
On-Chip 1.2-V Reference
Low Power: 330 mW
•
•
•
Enhanced Product-Change Notification
(1)
Power-Down Mode: 15 mW
Qualification Pedigree
Package: 48-Pin Thin Quad Flat Pack (TQFP)
12-Bit Dual Transmit Digital-to-Analog
Converter (DAC)
APPLICATIONS
•
•
•
200-MSPS Update Rate
Cellular Base Transceiver Station Transmit
Channel
Single Supply: 3 V to 3.6 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
– CDMA: W-CDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE/UWC-136
Medical/Test Instrumentation
Arbitrary Waveform Generators (ARB)
Direct Digital Synthesis (DDS)
•
•
•
•
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Cable Modem Termination System (CMTS)
DESCRIPTION
The DAC5662 is a monolithic, dual-channel 12-bit, high-speed digital-to-analog converter (DAC) with on-chip
voltage reference.
Operating with update rates of up to 200 MSPS, the DAC5662 offers exceptional dynamic performance, tight
gain, and offset matching characteristics that make it suitable in either I/Q baseband or direct IF communication
applications.
Each DAC has a high-impedance differential-current output, suitable for single-ended or differential
analog-output configurations. External resistors allow scaling the full-scale output current for each DAC
separately or together, typically between 2 mA and 20 mA. An accurate on-chip voltage reference is temperature
compensated and delivers a stable 1.2-V reference voltage. Optionally, an external reference may be used.
The DAC5662 has two 12-bit parallel input ports with separate clocks and data latches. For flexibility, the
DAC5662 also supports multiplexed data for each DAC on one port when operating in the interleaved mode.
The DAC5662 has been specifically designed for a differential transformer coupled output with a 50-Ω doubly
terminated load. For a 20-mA full-scale output current a 4:1 impedance ratio (resulting in an output power of
4 dBm) and 1:1 impedance ratio transformer (–2-dBm output power) are supported.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC5662-EP
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SGLS340A–JUNE 2006–REVISED OCTOBER 2006
DESCRIPTION (CONTINUED)
The DAC5662 is available in a 48-pin thin quad flat pack (TQFP). Pin compatibility between family members
provides 12-bit (DAC5662) and 14-bit (DAC5672) resolution. Furthermore, the DAC5662 is pin compatible to the
DAC2902 and AD9765 dual DACs. The device is characterized for operation over the military temperature range
of –55°C to 125°C.
FUNCTIONAL BLOCK DIAGRAM
WRTB
WRTA
CLKB CLKA
DE
MUX
IOUTA1
IOUTA2
Latch A
12−b DAC
DA[11:0]
DB[11:0]
BIASJ_A
IOUTB1
IOUTB2
Latch B
12−b DAC
MODE
GSET
BIASJ_B
EXTIO
1.2 V Reference
SLEEP
DVDD
DGND
AVDD
AGND
AVAILABLE OPTIONS
PACKAGED DEVICES
48-PIN TQFP
TA
DAC5662MPFBREP
DAC5662MPFBEP
–55°C to 125°C
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DEVICE INFORMATION
48 47 46 45 44 43 42 41 40 39 38 37
DA11 (MSB)
DA10
DA9
NC
36
35
34
33
32
31
30
1
2
3
4
5
6
7
8
9
NC
DB0 (LSB)
DB1
DA8
DA7
DB2
Top View
48-Pin TQFP
PFB Package
DA6
DB3
DA5
DB4
DA4
29 DB5
28 DB6
DA3
27
26
25
DA2 10
DA1 11
DB7
DB8
DB9
12
DA0 (LSB)
13 14 15 16 17 18 19 20 21 22 23 24
3
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SGLS340A–JUNE 2006–REVISED OCTOBER 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
38
AGND
I
I
Analog ground
AVDD
47
Analog supply voltage
BIASJ_A
BIASJ_B
CLKA/CLKIQ
CLKB/RESETIQ
DA[11:0]
DB[11:0]
DGND
44
O
O
I
Full-scale output current bias for DACA
Full-scale output current bias for DACB
Clock input for DACA, CLKIQ in interleaved mode
Clock input for DACB, RESETIQ in interleaved mode
Data port A. DA11 is MSB and DA0 is LSB.
Data port B. DB11 is MSB and DB0 is LSB.
Digital ground
41
18
19
I
1–12
23–34
15, 21
16, 22
43
I
I
I
DVDD
I
Digital supply voltage
EXTIO
I/O Internal reference output (bypass with 0.1 µF to AGND) or external reference input
GSET
42
I
Gain-setting mode: H = 1 resistor, L = 2 resistors. Internal pullup
DACA current output. Full scale with all bits of DA high.
IOUTA1
IOUTA2
IOUTB1
IOUTB2
MODE
46
O
O
O
O
I
45
DACA complementary current output. Full scale with all bits of DA low.
DACB current output. Full scale with all bits of DB high.
39
40
DACB complementary current output. Full scale with all bits of DB low.
Mode select: H = dual bus, L = interleaved. Internal pullup.
48
13, 14, 35,
36
NC
–
I
No connection
Sleep function control input: H = DAC in power-down mode, L = DAC in operating mode.
Internal pulldown.
SLEEP
37
WRTA/WRTIQ
17
20
I
I
Input write signal for PORT A (WRTIQ in interleaving mode)
Input write signal for PORT B (SELECTIQ in interleaving mode)
WRTB/SELECTIQ
4
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PFB PACKAGE THERMAL CHARACTERISTICS
PARAMETER
Thermal resistance, junction to ambient
Thermal resistance, junction to case
POWERPAD CONNECTED TO PCB THERMAL PLANE
63.7°C/W
19.6°C/W
1000
Wirebond Voiding Fail Mode
100
10
Electromigration Fail Mode
1
0.1
100
110
120
130
Continuous T − 5C
140
150
160
J
Figure 1. DAC5662MPFB Operating Life Derating Chart
5
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SGLS340A–JUNE 2006–REVISED OCTOBER 2006
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
–0.5 V to 4 V
AVDD(2)
Supply voltage range
DVDD(3)
–0.5 V to 4 V
Voltage between AGND and DGND
Voltage between AVDD and DVDD
–0.5 V to 0.5 V
–0.5 V to 0.5 V
–0.5 V to DVDD + 0.5 V
–0.5 V to DVDD + 0.5 V
–1 V to AVDD + 0.5 V
–0.5 V to AVDD + 0.5 V
20 mA
DA[11:0] and DB[11:0](3)
MODE, CLKA, CLKB, WRTA, WRTB(3)
IOUTA1, IOUTA2, IOUTB1, IOUTB2(2)
EXTIO, BIASJ_A, BIASJ_B, SLEEP(2)
Supply voltage range
Peak input current (any input)
Peak total input current (all inputs)
Operating free-air temperature range
Storage temperature range
Lead temperature
–30 mA
–55°C to 125°C
–65°C to 150°C
260°C
1,6 mm (1/16 in) from the case for 10 s
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND
(3) Measured with respect to DGND
6
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode
(unless otherwise noted)
PARAMETER
DC Specifications
Resolution
DC Accuracy(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
12
Bits
INL
Integral nonlinearity
Differential nonlinearity
1 LSB = IOUTFS/212, TA = 25°C
1 LSB = IOUTFS/212, TA = 25°C
–2
–2
0.3
0.2
2
2
LSB
LSB
DNL
Analog Output
Offset error
0.03
0.25
0.5
2
%FSR
%FSR
%FSR
mA
With external reference
With internal reference
Gain error
Minimum full-scale output current(2)
Maximum full-scale output current(2)
Gain mismatch
20
mA
With internal reference
–2
0.07
2
%FSR
V
Output voltage compliance range(3)
–0.8
1.25
RO
CO
Output resistance
300
5
kΩ
Output capacitance
pF
Reference Output
Reference voltage
Reference output current(4)
Reference Input
1.14
0.1
1.2
1.26
1.25
V
100
nA
VEXTIO
RI
Input voltage
V
Input resistance
Small signal bandwidth
Input capacitance
1
300
100
MΩ
kHz
pF
CI
Temperature Coefficients
ppm of
FSR/°C
Offset drift
0
With external reference
With internal reference
±50
±50
±20
ppm of
FSR/°C
Gain drift
Reference voltage drift
(1) Measured differentially through 50 Ω to AGND.
ppm/°C
(2) Nominal full-scale current, IOUTFS, equals 32× the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5662 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and intergral nonlinearity.
(4) Use an external buffer amplifier with high impedance input to drive any external load.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz,
independent gain set mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Power Supply
AVDD
DVDD
Analog supply voltage
Digital supply voltage
3
3
3.3
3.3
75
3.6
3.6
90
6
V
V
Including output current through load resistor
Sleep mode with clock
IAVDD
Supply current, analog
Supply current, digital
Power dissipation
2.5
2.5
25
mA
mA
mW
Sleep mode without clock
38
18
IDVDD
Sleep mode with clock
12.5
<10
330
15
Sleep mode without clock
390
Sleep mode without clock
fDATA = 200 MSPS, fOUT = 20 MHz
350
APSSR
DPSRR
TA
Analog power-supply rejection ratio
Digital power-supply rejection ratio
Operating free-air temperature
–0.2
–0.2
–55
0.2 %FSR/V
0.2 %FSR/V
125
°C
8
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ELECTRICAL CHARACTERISTICS
AC specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set
mode, differential 1:1 impedance ratio transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
Analog Output
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fclk
Maximum output update rate
200 275(1)
20
MSPS
ns
Output settling time to 0.1%
(DAC)
ts
Mid-scale transition
Output rise time 10% to 90%
(OUT)
tr
tf
1.4
1.5
ns
ns
Output fall time 90% to 10%
(OUT)
IOUTFS = 20 mA
IOUTFS = 2 mA
55
30
Output noise
pA/√Hz
AC Linearity
1st Nyquist zone, TA = 25°C, fDATA = 50 MSPS,
fOUT = 1 MHz, IOUTFS = 0 dB
81
83
81
85
78
1st Nyquist zone, TA = 25 C, fDATA = 50 MSPS,
fOUT = 1 MHz, IOUTFS = –6 dB
1st Nyquist zone, TA = 25°C, fDATA = 50 MSPS,
fOUT = 1 MHz, IOUTFS = –12 dB
1st Nyquist zone, TA = 25°C, fDATA = 100 MSPS,
fOUT = 5 MHz
SFDR
Spurious-free dynamic range
dBc
1st Nyquist zone, TA = 25°C, fDATA = 100 MSPS,
fOUT = 20 MHz
1st Nyquist zone, TA = 25°C, fDATA = 200 MSPS,
fOUT = 20 MHz
66
63
71
71
68
73
67
70
70
62
78
77
56
74
97
1st Nyquist zone, Tmin = –55°C to 125°C,
fDATA = 200 MSPS, fOUT = 20 MHz
1st Nyquist zone, TA = 25°C, fDATA = 200 MSPS,
fOUT = 41 MHz
1st Nyquist zone, TA = 25°C, fDATA = 100 MSPS,
fOUT = 5 MHz
SNR
Signal-to-noise ratio
dB
dB
1st Nyquist zone, TA = 25°C, fDATA = 200 MSPS,
fOUT = 20 MHz
W-CDMA signal with 3.84-MHz bandwidth,
fDATA = 61.44 MSPS, IF = 15.36 MHz
ACLR
IMD3
Adjacent channel leakage ratio
W-CDMA signal with 3.84-MHz bandwidth,
fDATA = 122.88 MSPS, IF = 30.72 MHz
Each tone at –6 dBFS, TA = 25°C, fDATA = 200 MSPS,
fOUT = 45.4 MHz and 46.4 MHz
Third-order two-tone
intermodulation
dBc
Each tone at –6 dBFS, TA = 25°C, fDATA = 100 MSPS,
fOUT = 15.1 MHz and 16.1 MHz
Each tone at –12 dBFS, TA = 25°C, fDATA = 100 MSPS,
fOUT = 15.6, 15.8, 16.2, and 16.4 MHz
Each tone at –12 dBFS, TA = 25°C, fDATA = 165 MSPS,
fOUT = 68.8, 69.6, 71.2, and 72 MHz
IMD
Four-tone intermodulation
Channel isolation
dBc
dBc
Each tone at –12 dBFS, TA = 25°C, fDATA = 165 MSPS,
fOUT = 19.0, 19.1, 19.3, and 19.4 MHz
TA = 25°C, fDATA = 165 MSPS, fOUT (CH1) = 20 MHz,
fOUT (CH2) = 21 MHz
(1) Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA
(unless otherwise noted)
PARAMETER
MIN
TYP MAX UNIT
Digital Input
VIH
VIL
IIH
High-level input voltage
2
0
3.3
0.8
V
Low-level input voltage
High-level input current
Low-level input current
V
50
10
µA
µA
µA
µA
µA
µA
pF
IIL
IIH(GSET) High-level input current, GSET pin
IIL(GSET) Low-level input current, GSET pin
7
–30
–30
–80
5
IIH(MODE) High-level input current, MODE pin
IIL(MODE) Low-level input current, MODE pin
CI
Input capacitance
SWITCHING CHARACTERISTICS
Digital specifications over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA
(unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
Timing – Dual Bus Mode
tsu
Input setup time
1
1
ns
ns
ns
th
Input hold time
tLPH
tLAT
tPD
Input clock pulse high time
Clock latency (WRTA/B to outputs)(1)
2
4
4
4
clk
ns
Propagation delay time
1.5
Timing – Single Bus Interleaved Mode
tsu
Input setup time
0.5
0.5
ns
ns
clk
ns
th
Input hold time
Clock latency (WRTA/B to outputs)(1)
tLAT
tPD
4
Propagation delay time
1.5
(1) Specified by design
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TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
INPUT CODE
0.4
0.3
0.2
0.1
0.0
−0.1
−0.2
−0.3
−0.4
0
512
1024
1536
2048
2560
3072
3584
4096
Input Code
G001
Figure 2.
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
0.20
0.15
0.10
0.05
0.00
−0.05
−0.10
−0.15
−0.20
0
512
1024
1536
2048
2560
3072
3584
4096
Input Code
G002
Figure 3.
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TYPICAL CHARACTERISTICS (continued)
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
0 dBf
S
−6 dBf
S
0 dBf
S
−6 dBf
S
−12 dBf
S
−12 dBf
S
f
= 52 MSPS
f
= 78 MSPS
Dual Bus Mode
data
data
Dual Bus Mode
0
4
8
12
16
20
24
0
5
10
15
20
25
30
35
f
O
− Output Frequency − MHz
f
O
− Output Frequency − MHz
G003
G004
Figure 4.
Figure 5.
SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs
vs
OUTPUT FREQUENCY
OUTPUT FREQUENCY
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
0 dBf
S
0 dBf
S
−6 dBf
S
−6 dBf
S
−12 dBf
S
−12 dBf
S
f
= 100 MSPS
Dual Bus Mode
f
= 165 MSPS
data
data
Dual Bus Mode
0
5
10
15
20
25
30
35
40
0
5
10 15 20 25 30 35 40 45 50 55 60 65
f
O
− Output Frequency − MHz
f
O
− Output Frequency − MHz
G005
G006
Figure 6.
Figure 7.
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TYPICAL CHARACTERISTICS (continued)
SINGLE-TONE SPECTRUM
SINGLE-TONE SPECTRUM
0
-20
-40
-60
-80
0
−20
f
f
= 78 MSPS
= 15 MHz
f
f
= 165 MSPS
= 30.1 MHz
data
data
OUT
OUT
Dual Bus Mode
Dual Bus Mode
−40
−60
−80
-100
0.0
−100
7.8
15.6
23.4
31.2
39.0
0.0
16.5
33.0
49.5
66.0
82.5
f - Frequency - MHz
f − Frequency − MHz
G007
G008
Figure 8.
Figure 9.
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
95
f
100
95
90
85
80
75
70
65
60
55
50
= 78 MSPS
f
= 165 MSPS
data
data
Dual Bus Mode
Dual Bus Mode
90
85
80
75
70
65
60
0
5
10
15
20
25
30
35
0
10
20
30
40
50
f
O
− Output Frequency − MHz
f
O
− Output Frequency − MHz
G009
G010
Figure 10.
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
TWO-TONE SPECTRUM
TWO-TONE SPECTRUM
0
−20
0
−20
f
f
= 165 MSPS
= 30.1 MHz
f
f
= 78 MSPS
= 20.1 MHz
data
data
OUT
OUT
and 31.1 Mhz
Dual Bus Mode
and 21.1 MHz
Dual Bus Mode
−40
−40
−60
−60
−80
−80
−100
−100
19.0
19.5
20.0
20.5
21.0
21.5
22.0
29.0
29.5
30.0
30.5
31.0
31.5
32.0
f − Frequency − MHz
f − Frequency − MHz
G011
G012
Figure 12.
Figure 13.
POWER
vs
FREQUENCY
POWER
vs
FREQUENCY
−20
−40
−20
−40
f
= 122.88 MSPS
f
= 122.88 MSPS
data
data
Baseband Signal
ACPR = 72 dB
Dual Bus Mode
IF = 30.72 MHz
ACPR = 72 dB
Dual Bus Mode
−60
−60
−80
−80
−100
−120
−100
−120
0
1
2
3
4
5
6
7
8
9
10
18 20 22 24 26 28 30 32 34 36 38 40 42 44
f − Frequency − MHz
f − Frequency − MHz
G013
G014
Figure 14.
Figure 15.
14
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DIGITAL INPUTS AND TIMING
Digital Inputs
The data input ports of the DAC5662 accept a standard positive coding with data bit D11 being the most
significant bit (MSB). The converter outputs are specified to support a clock rate up to 200 MSPS. The best
performance is typically be achieved with a symmetric duty cycle for write and clock; however, the duty cycle
may vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within
their specified limits.
All digital inputs of the DAC5662 are CMOS compatible. Figure 16 and Figure 17 show schematics of the
equivalent CMOS digital inputs of the DAC5662. The 12-bit digital data input follows the offset positive binary
coding scheme. The DAC5662 is designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.
DVDD
DA[11:0]
DB[11:0]
Internal
SLEEP
Digital In
CLKA/B
WRTA/B
DGND
Figure 16. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
DVDD
Internal
GSET
Digital In
MODE
DGND
Figure 17. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
Input Interfaces
The DAC5662 features two operating modes selected by the MODE pin (see Table 1).
•
For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own
separate data input bus, clock input, and data write signal (data latch-in).
•
In single-bus interleaved mode, the data should be presented interleaved at the I-channel input bus. The
Q-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.
Table 1. Operating Modes
MODE PIN
BUS INPUT
Mode pin connected to DGND
Mode pin connected to DVDD
Single-bus interleaved mode, clock and write input equal for both DACs Dual-bus mode, DACs operate independently
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DIGITAL INPUTS AND TIMING (continued)
Dual-Bus Data Interface and Timing
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5662
consist of two independent, 12-bit, parallel data ports. Each DAC channel is controlled by its own set of write
(WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRT lines control the channel input latches and the CLK
lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the WRT line
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock
domains having equal periods (but possibly different phases) are input to the DAC5662. This is defined by a
minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.
This essentially implies that the rising edge of CLK must occur at the same time or before the rising edge of the
WRT signal. A minimum delay of 2 ns should be maintained if the rising edge of the clock occurs after the rising
edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected
externally. Note that all specifications were measured with the WRT and CLK lines connected together.
D[11:0]
Valid Data
t
su
t
h
t
1PH
WRT1/WRT2
CLK1/CLK2
t
settle
t
t
pd
LAT
IOUT
or
IOUT
Figure 18. Dual-Bus-Mode Operation
Single-Bus Interleaved Data Interface and Timing
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 19 shows the timing diagram. In
interleaved mode, the I and Q channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the I-channel input bus to either the I-channel input latch
(SELECTIQ is high) or to the Q-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data value
in the Q-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is low,
the data value in the I-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the I-channel input data rate is twice the update rate of the DAC core. As in dual-bus mode,
it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch the I-
and Q-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the I- and
Q-DAC latches on the following falling edge of the write inputs. The DAC5662 clock input is divided by a factor
of two before it is presented to the DAC latches.
Correct pairing of the I- and Q-channel data is done by RESETIQ. In interleaved mode, the clock input CLKIQ is
divided by two, which would translate to a nondeterministic relation between the rising edges of the CLKIQ and
CLKDACIQ. RESETIQ ensures, however, that the correct position of the rising edge of CLKDACIQ, with respect
to the data at the input of the DAC latch, is determined. CLKDACIQ is disabled (low) when RESETIQ is high.
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DIGITAL INPUTS AND TIMING (continued)
D[11:0]
Valid Data
t
su
t
h
SELECTIQ
WRTIQ
CLKIQ
RESETIQ
t
settle
t
t
pd
LAT
IOUT
or
IOUT
Figure 19. Single-Bus Interleaved-Mode Operation
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APPLICATION INFORMATION
Theory of Operation
The architecture of the DAC5662 uses a current steering technique to enable fast switching and high update
rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to
deliver a full-scale output current of up to 20 mA. An internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output current is formed by steering all currents to either
output summing node, IOUT1 and IOUT2. The complementary outputs deliver a differential output signal, which
improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise),
and double the peak-to-peak output signal swing by a factor of two, compared to single-ended operation.
The segmented architecture results in a significant reduction of the glitch energy and improves the dynamic
performance (SFDR) and DNL. The current outputs maintain a high output impedance of greater than 300 kΩ.
When pin 42 (GSET) is high (one resistor mode), the full-scale output current for both DACs is determined by
the ratio of the internal reference voltage (1.2 V) and an external resistor (RSET) connected to BIASJ_A. When
GSET is low (two resistor mode), the full-scale output current for each DACs is determined by the ratio of the
internal reference voltage (1.2 V) and separate external resistors (RSET) connected to BIASJ_A and BIASJ_B.
The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can
range from 2 mA to 20 mA, depending on the value of RSET
.
The DAC5662 is split into a digital and an analog portion, each of which is powered through its own supply pin.
The digital section includes edge-triggered input latches and the decoder logic, while the analog section
comprises the current source array with its associated switches, and the reference circuitry.
DAC Transfer Function
Each of the DACs in the DAC5662 has a set of complementary current outputs, IOUT1 and IOUT2. The full-scale
output current, IOUTFS, is the summation of the two complementary output currents:
I
+ I
) I
OUTFS
OUT1
OUT2
(1)
The individual output currents depend on the DAC code and can be expressed as:
Code
4096
ǒ Ǔ
I
+ I
OUT1
OUTFS
(2)
(3)
Code
4096
ǒ4095 *
Ǔ
I
+ I
OUT2
OUTFS
where Code is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the
reference current IREF, which is determined by the reference voltage and the external setting resistor (RSET).
V
REF
I
+ 32 I
+ 32
OUTFS
REF
R
SET
(4)
In most cases, the complementary outputs drive resistive loads or a terminated transformer. A signal voltage
develops at each output according to:
V
+ I
R
OUT1
OUT1
LOAD
(5)
(6)
V
+ I
R
OUT2
OUT2
LOAD
The value of the load resistance is limited by the output compliance specification of the DAC5662. To maintain
specified linearity performance, the voltage for IOUT1 and IOUT2 should not exceed the maximum allowable
compliance range.
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APPLICATION INFORMATION (continued)
The total differential output voltage is:
V
+ V
* V
OUTDIFF
OUT1
OUT2
(7)
(8)
(
)
2 Code * 4095
V
+
I
R
OUTDIFF
OUTFS
LOAD
4096
Analog Outputs
The DAC5662 provides two complementary current outputs, IOUT1 and IOUT2. The simplified circuit of the analog
output stage representing the differential topology is shown in Figure 20. The output impedance of IOUT1 and
IOUT2 results from the parallel combination of the differential switches, along with the current sources and
associated parasitic capacitances.
AVDD
S(1)
S(1)C
S(2)
S(2)C
S(N)
S(N)C
Current Source Array
I
I
OUT2
OUT1
R
LOAD
R
LOAD
Figure 20. Analog Outputs
The signal voltage swing that may develop at the two outputs, IOUT1 and IOUT2, is limited by a negative and
positive compliance. The negative limit of –1 V is given by the breakdown voltage of the CMOS process and
exceeding it compromises the reliability of the DAC5662 or even causes permanent damage. With the full-scale
output set to 20 mA, the positive compliance equals 1.2 V. Note that the compliance range decreases to about
1 V for a selected output current of IOUTFS = 2 mA. Care should be taken that the configuration of DAC5662 does
not exceed the compliance range to avoid degradation of the distortion performance and integral linearity.
Best distortion performance is typically achieved with the maximum full-scale output signal limited to
approximately 0.5 VPP. This is the case for a 50-Ω doubly terminated load and a 20-mA full-scale output current.
A variety of loads can be adapted to the output of the DAC5662 by selecting a suitable transformer while
maintaining optimum voltage levels at IOUT1 and IOUT2. Furthermore, using the differential output configuration in
combination with a transformer is instrumental for achieving excellent distortion performance. Common-mode
errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly the case with
high output frequencies.
For those applications requiring the optimum distortion and noise performance, it is recommended to select a
full-scale output of 20 mA. A lower full-scale range of 2 mA may be considered for applications that require low
power consumption, but can tolerate a slight reduction in performance level.
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APPLICATION INFORMATION (continued)
Output Configurations
The current outputs of the DAC5662 allow for a variety of configurations. As mentioned previously, utilizing the
converter’s differential outputs yield the best dynamic performance. Such a differential output circuit may consist
of an RF transformer or a differential amplifier configuration. The transformer configuration is ideal for most
applications with ac coupling, while operational amplifiers are suitable for a dc-coupled configuration.
The single-ended configuration may be considered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to ground converts the output current into a
ground-referenced voltage signal. To improve on the dc linearity by maintaining a virtual ground, an I-to-V or
operational amplifier configuration may be considered.
Differential With Transformer
Using an RF transformer provides a convenient way of converting the differential output signal into a
single-ended signal while achieving excellent dynamic performance. The appropriate transformer should be
carefully selected based on the output frequency spectrum and impedance requirements.
The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus
improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable
impedance ratio (winding ratio), the transformer can be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
Figure 21 and Figure 22 show 50-Ω doubly terminated transformer configurations with 1:1 and 4:1 impedance
ratios, respectively. Note that the center tap of the primary input of the transformer has to be grounded to enable
a dc-current flow. Applying a 20-mA full-scale output current leads to a 0.5-VPP output for a 1:1 transformer and
a 1-VPP output for a 4:1 transformer. In general, the 1:1 transformer configuration has slightly better output
distortion, but the 4:1 transformer has 6-dB higher output power.
50 Ω
1:1
I
I
OUT1
R
LOAD
AGND
100 Ω
50 Ω
OUT2
50 Ω
Figure 21. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
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APPLICATION INFORMATION (continued)
100 Ω
4:1
I
I
OUT1
R
LOAD
AGND
50 Ω
OUT2
100 Ω
Figure 22. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
Single-Ended Configuration
Figure 23 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 should be connected to AGND or terminated with a resistor of 25 Ω to
AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA
full-scale output current.
I
I
OUT1
R
LOAD
50 Ω
OUT2
50 Ω
25 Ω
AGND
Figure 23. Driving a Doubly-Terminated 50-Ω Cable Using a Single-Ended Output
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APPLICATION INFORMATION (continued)
Reference Operation
Internal Reference
The DAC5662 has an on-chip reference circuit which comprises a 1.2-V bandgap reference and two control
amplifiers, one for each DAC. The full-scale output current, IOUTFS, of the DAC5662 is determined by the
reference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by:
V
REF
I
+ 32 I
+ 32
OUTFS
REF
R
SET
(9)
The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is
determined by the ratio of VREF and RSET (see Equation 9). The full-scale output current, IOUTFS, results from
multiplying IREF by a fixed factor of 32.
Using the internal reference, a 2-kΩ resistor value results in a full-scale output of approximately 20 mA.
Resistors with a tolerance of 1% or better should be considered. Selecting higher values, the output current can
be adjusted from 20 mA down to 2 mA. Operating the DAC5662 at lower than 20-mA output currents may be
desirable for reasons of reducing the total power consumption, improving the distortion performance, or
observing the output compliance voltage limitations for a given load condition.
It is recommended to bypass the EXTIO pin with a ceramic chip capacitor of 0.1 µF or more. The control
amplifier is internally compensated and its small signal bandwidth is approximately 300 kHz.
External Reference
The internal reference can be disabled by simply applying an external reference voltage into the EXTIO pin that,
in this case, functions as an input. The use of an external reference may be considered for applications that
require higher accuracy and drift performance or to add the ability of dynamic gain control.
While a 0.1-µF capacitor is recommended to be used with the internal reference, it is optional for the external
reference operation. The reference input, EXTIO, has a high input impedance (1 MΩ) and can easily be driven
by various sources. Note that the voltage range of the external reference should stay within the compliance
range of the reference input.
Gain Setting Option
The full-scale output current on the DAC5662 can be set two ways — either for each of the two DAC channels
independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42)
must be low (that is, connected to AGND). In this mode, two external resistors are required — one RSET
connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user
has the flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the
compensation of possible gain mismatches elsewhere within the transmit signal path.
Alternatively, bringing the GSET pin high (that is, connected to AVDD), the DAC5662 switches into the
simultaneous gain set mode. Now the full-scale output current of both DAC channels is determined by only one
external RSET resistor connected to the BIASJ_A pin. The resistor at the BIASJ_2 pin may be removed;
however, this is not required since this pin is not functional in this mode and the resistor has no effect on the
gain equation.
Sleep Mode
The DAC5662 features a power-down function that can be used to reduce the total supply current to less than
3.5 mA over the specified supply range if no clock is present. Applying a logic high to the SLEEP pin initiates the
power-down mode, while a logic low enables normal operation. When left unconnected, an internal active
pulldown circuit enables the normal operation of the converter.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
DAC5662MPFBEP
DAC5662MPFBREP
V62/06651-01XE
V62/06651-02XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
TQFP
TQFP
TQFP
PFB
PFB
PFB
PFB
48
48
48
48
250
1000
1000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5662-EP :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jun-2012
Catalog: DAC5662
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC5662MPFBREP
TQFP
PFB
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PFB 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
DAC5662MPFBREP
1000
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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