V62/08631-01YE_技术文档

MSP430F2274-EP

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

MIXED SIGNAL MICROCONTROLLER

Check for Samples: MSP430F2274-EP

1

FEATURES

•

Low Supply Voltage Range 1.8 V to 3.6 V

•

10-Bit, 200-ksps A/D Converter With Internal

Reference, Sample-and-Hold, and Autoscan

and Data Transfer Controller

•

Ultralow-Power Consumption

–

Active Mode: 270 mA at 1 MHz, 2.2 V

Standby Mode: 0.7 mA

•

Two Configurable Operational Amplifiers

Brownout Detector

Off Mode (RAM Retention): 0.1 mA

Serial Onboard Programming, No External

Programming Voltage Needed Programmable

Code Protection by Security Fuse

•

Ultrafast Wake-Up From Standby Mode in Less

than 1 ms

16-Bit RISC Architecture, 62.5 ns Instruction

Cycle Time

•

Bootstrap Loader

On-Chip Emulation Logic

Basic Clock Module Configurations

Family Members Include the MSP430F2274

With 32KB + 256B Flash Memory, 1KB RAM

–

Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1%

•

Available in 40-Pin QFN Package and 38-Pin

Thin Shrink Small-Outline DA Package

–

Internal Very Low Power LF Oscillator

32-kHz Crystal

For Complete Module Descriptions, Refer to

the MSP430x2xx Family User'sGuide

(Available Only from –40°C to 105°C)

–

High-Frequency Crystal up to 16 MHz

(Available Only from –40°C to 105°C)

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

–

Resonator

External Digital Clock Source

External Resistor

•

Controlled Baseline

One Assembly/Test Site

One Fabrication Site

Available in Military (–55°C/125°C)

Temperature Range⁽¹⁾

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

•

16-Bit Timer_A With Three Capture/Compare

Registers

16-Bit Timer_B With Three Capture/Compare

Registers

•

Universal Serial Communication Interface

–

Enhanced UART Supporting

Auto-Baud-Rate Detection (LIN)

–

IrDA Encoder and Decoder

Synchronous SPI

I²C™

(1) Custom temperature ranges available

DESCRIPTION

The Texas Instruments MSP430 family of ultralow power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 ms.

The MSP430F2274M series is an ultralow-power mixed signal microcontroller with two built-in 16-bit timers, a

universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer

controller (DTC), two general-purpose operational amplifiers in the MSP430F2274M devices, and 32 I/O pins.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430F2274-EP

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

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Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data for display or for transmission to a host system. Stand-alone RF sensor front end is another

area of application.

Table 1. ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

QFN (RHA)

DA (TSSOP)

ORDERABLE PART NUMBER

MSP430F2274MRHATEP

MSP430F2274MDATEP

–55°C to 125°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

DEVICE PINOUTS

RHA PACKAGE

(TOP VIEW)

39 38 37 36 35 34 33 32

DVSS

XOUT /P2.7

1

2

3

4

5

6

7

8

9

30 P1.1/TA0

29 P1.0/TACLK /ADC10CLK

28 P2.4/TA2/A4/VREF +/VeREF +/OA1I0

27 P2.3/TA1/A3/VREF -/VeREF -/OA1I1/OA1O

26 P3.7/A7/OA1I2

XIN /P2.6

DVSS

RST /NMI /SBWTDIO

P2.0/ACLK/A0/OA0I0

P2.1/TAINCLK /SMCLK /A1/OA0O

P2.2/TA0/A2/OA0I1

P3.0/UCB0STE /UCA0CLK/A5

25 P3.6/A6/OA0I2

24 P3.5/UCA0RXD /UCA0SOMI

23 P3.4/UCA0TXD /UCA0SIMO

22 P4.7/TBCLK

P3.1/UCB0SIMO /UCB0SDA 10

21 P4.6/TBOUTH /A15/OA1I3

12 13 14 15 16 17 18 19

TI = TI

YM = YEAR/MONTH

M4F2274

LLLL = LOT TRACE CODE

S = ASSEMBLY SITE CODE

G4 = RoHS with underscore

O = PIN 1 indicator

MRHATEP

TI YMS

LLLLG4

2

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DA PACKAGE

(TOP VIEW)

1

2

3

4

5

38

37

36

35

34

33

32

TEST/SBWTCK

P1.7/TA2/TDO/TDI

P1.6/TA1/TDI

DVCC

P2.5/Rosc

P1.5/TA0/TMS

P1.4/SMCLK/TCK

P1.3/TA2

DVSS

XOUT/P2.7

XIN/P2.6

P1.2/TA1

6

7

RST/NMI/SBWTDIO

P1.1/TA0

P2.0/ACLK/A0/OA0I0

8

31

30

29

28

27

26

P1.0/TACLK/ADC 10CLK

P2.4/TA2/A4/VREF+/VeREF+/OA1I0

P2.3/TA1/A3/VREF-/VeREF-/OA1I1/OA10

P3.7/A7/OA1I2

9

P2.1/TAINCLK/SMCLK/A1/OA00

P2.2/TA0/A2/OA0I1

10

11

12

13

14

15

16

17

18

19

P3.0/UCB 0STE/UCA 0CLK/A5

P3.1/UCB 0SIMO/UCB 0SDA

P3.2/UCB 0SOMI/UCB 0SCL

P3.3/UCB 0CLK/UCA 0STE

P3.6/A6/OA0I2

P3.5/UCA0RXD/UCA0SOMI

25

24

P3.4/UCA0TXD/UCA0SIMO

P4.7/TBCLK

AVSS

AVCC

23

22

21

20

P4.6/TBOUTH/A15/OA1I3

P4.5/TB2/A14/OA1I3

P4.4/TB1/A13/OA1O

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12/OA0O

FUNCTIONAL BLOCK DIAGRAM

VCC

VSS

P1.x/P2.x

2x8

P3.x/P4.x

2x8

XIN

XOUT

ADC10

10−Bit

Ports P1/P2

ACLK

Flash

RAM

1kB

512B

Ports P3/P4

Basic Clock

System+

OA0, OA1

2x8 I/O

Interrupt

capability,

pull−up/down

resistors

SMCLK

32kB

16kB

8kB

12

2x8 I/O

pull−up/down

resistors

Channels,

Autoscan,

DTC

2 Op Amps

MCLK

MAB

16MHz

CPU

incl. 16

Registers

MDB

Emulation

(2BP)

Timer_B3

USCI_A0:

UART/LIN,

IrDA, SPI

Watchdog

WDT+

Timer_A3

JTAG

Interface

Brownout

Protection

3 CC

Registers,

Shadow

Reg

3 CC

Registers

USCI_B0:

SPI, I2C

15/16−Bit

Spy−Bi Wire

RST/NMI

NOTE: See port schematics section for detailed I/O information.

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TERMINAL FUNCTIONS⁽¹⁾

TERMINAL

I/O

DESCRIPTION

DA

RHA

NO.

NAME

NO.

General-purpose digital I/O pin

P1.0/TACLK/ADC10CLK

P1.1/TA0

31

32

29

30

I/O Timer_A, clock signal TACLK input

ADC10, conversion clock

General-purpose digital I/O pin

I/O Timer_A, capture: CCI0A input, compare: OUT0 output/BSL

transmit

General-purpose digital I/O pin

Timer_A, capture: CCI1A input, compare: OUT1 output

P1.2/TA1

33

34

35

36

37

38

8

31

32

33

34

35

36

6

I/O

General-purpose digital I/O pin

Timer_A, capture: CCI2A input, compare: OUT2 output

P1.3/TA2

I/O

General-purpose digital I/O pin/SMCLK signal output

Test Clock input for device programming and test

P1.4/SMCLK/TCK

P1.5/TA0/TMS

I/O

General-purpose digital I/O pin/Timer_A, compare: OUT0 output

Test Mode Select input for device programming and test

I/O

General-purpose digital I/O pin/Timer_A, compare: OUT1 output

Test Data Input or Test Clock Input for programming and test

P1.6/TA1/TDI/TCLK

P1.7/TA2/TDO/TDI⁽²⁾

P2.0/ACLK/A0/OA0I0

I/O

General-purpose digital I/O pin/Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test

I/O

General-purpose digital I/O pin/ACLK output

I/O

ADC10, analog input A0 / OA0, analog input I0

General-purpose digital I/O pin/Timer_A, clock signal at INCLK

I/O SMCLK signal output

P2.1/TAINCLK/SMCLK/A1/

OA0O

9

7

8

ADC10, analog input A1/OA0, analog output

General-purpose digital I/O pin

Timer_A, capture: CCI0B input/BSL receive, compare: OUT0

output

P2.2/TA0/A2/OA0I1

10

I/O

ADC10, analog input A2/OA0, analog input I1

General-purpose digital I/O pin

P2.3/TA1/A3/V_REF–/V_eREF–

OA1I1/OA1O

/

Timer_A, capture CCI1B input, compare: OUT1 output

ADC10, analog input A3 / negative reference voltage output/input

OA1, analog input I1/OA1, analog output

29

30

27

28

I/O

General-purpose digital I/O pin/Timer_A, compare: OUT2 output

I/O ADC10, analog input A4/positive reference voltage output/input

OA1, analog input I0

P2.4/TA2/A4/V_REF+/V_eREF+/OA1I0

General-purpose digital I/O pin

Input for external DCO resistor to define DCO frequency

P2.5/R_OSC

XIN/P2.6

3

6

5

40

3

I/O

Input terminal of crystal oscillator

I/O

General-purpose digital I/O pin

Output terminal of crystal oscillator

I/O

XOUT/P2.7

2

General-purpose digital I/O pin

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

11

12

9

I/O USCI_B0 slave transmit enable/USCI_A0 clock input/output

ADC10, analog input A5

General-purpose digital I/O pin

10

I/O USCI_B0 slave in/master out in SPI mode, SDA I²C data in I²C

mode

General-purpose digital I/O pin

P3.2/UCB01SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P3.4/UCA0TXD/UCA0SIMO

13

14

25

11

12

23

I/O USCI_B0 slave out/master in SPI mode, SCL I²C clock in I²C

mode

General-purpose digital I/O pin

USCI_B0 clock input/output/USCI_A0 slave transmit enable

I/O

General-purpose digital I/O pin

I/O USCI_A0 transmit data output in UART mode, slave in/master out

in SPI mode

(1) If XOUT/P2.7ca7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

(2) TDO or TDI is selected via JTAG instruction.

4

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TERMINAL FUNCTIONS ⁽¹⁾(continued)

TERMINAL

I/O

DESCRIPTION

DA

NO.

RHA

NO.

NAME

General-purpose digital I/O pin

P3.5/UCA0RXD/UCA0SOMI

26

24

I/O USCI_A0 receive data input in UART mode, slave out/master in in

SPI mode

General-purpose digital I/O pin

I/O

P3.6/A6/OA0I2

P3.7/A7/OA1I2

P4.0/TB0

27

28

17

18

19

25

26

15

16

17

ADC10 analog input A6/OA0 analog input I2

General-purpose digital I/O pin

I/O

ADC10 analog input A7/OA1 analog input I2

General-purpose digital I/O pin

Timer_B, capture: CCI0A input, compare: OUT0 output

I/O

General-purpose digital I/O pin

Timer_B, capture: CCI1A input, compare: OUT1 output

P4.1/TB1

I/O

General-purpose digital I/O pin

Timer_B, capture: CCI2A input, compare: OUT2 output

P4.2/TB2

I/O

General-purpose digital I/O pin

P4.3/TB0/A12/OA0O

P4.4/TB1A13/OA1O

P4.5/TB2A14/OA0I3

P4.6/TBOUTHA15/OA1I3

20

21

22

23

18

19

20

21

I/O Timer_B, capture: CCI0B input, compare: OUT0 output

ADC10 analog input A12/OA0 analog output

General-purpose digital I/O pin

I/O Timer_B, capture: CCI1B input, compare: OUT1 output

ADC10 analog input A13/OA1 analog output

General-purpose digital I/O pin

I/O Timer_B, compare: OUT2 output

ADC10 analog input A14/OA0 analog input I3

General-purpose digital I/O pin

I/O Timer_B, switch all TB0 to TB3 outputs to high impedance

ADC10 analog input A15/OA1 analog input I3

General-purpose digital I/O pin

I/O

P4.7/TBCLK

24

7

22

5

Timer_B, clock signal TBCLK input

Reset or nonmaskable interrupt input

RST/NMI/SBWTDIO

I

Spy-Bi-Wire test data input/output during programming and test

Selects test mode for JTAG pins on Port1. The device protection

TEST/SBWTCK

1

37

I

fuse is connected to TEST.

Spy-Bi-Wire test clock input during programming and test

DV_CC

AV_CC

DV_SS

AV_SS

2

16

4

38, 39

14

Digital supply voltage

Analog supply voltage

Digital ground reference

Analog ground reference

1, 4

13

15

Package

Pad

QFN Pad

NA

NA QFN package pad connection to DV_SSrecommended.

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SHORT-FORM DESCRIPTION

Program Counter

Stack Pointer

PC/R0

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions, are

performed as register operations in conjunction with

seven addressing modes for source operand and four

addressing modes for destination operand.

SP/R1

SR/CG1/R2

CG2/R3

R4

Status Register

Constant Generator

General-Purpose Register

The CPU is integrated with 16 registers that provide

reduced

register-to-register operation execution time is one

cycle of the CPU clock.

instruction

execution

time.

The

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and

constant generator respectively. The remaining

registers are general-purpose registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled with

all instructions.

R10

R11

Instruction Set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 2 shows examples of the three types of

instruction formats; the address modes are listed in

Table 3.

R12

R13

R14

R15

Table 2. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

e.g., ADD R4,R5

e.g., CALL R8

e.g., JNE

R4 + R5 → R5

PC → (TOS), R8 → PC

Jump-on-equal bit = 0

Table 3. Address Mode Descriptions

ADDRESS MODE

Register

S⁽¹⁾

D⁽²⁾

SYNTAX

MOV Rs,Rd

EXAMPLE

MOV R10,R11

OPERATION

•

R10 → R11

Indexed

MOV X(Rn),Y(Rm)

MOV EDE,TONI

MOV &MEM,&TCDAT

MOV @Rn,Y(Rm)

MOV 2(R5),6(R6)

M(2+R5) → M(6+R6)

M(EDE) → M(TONI)

M(MEM) → M(TCDAT)

M(R10) → M(Tab+R6)

Symbolic (PC relative)

Absolute

Indirect

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

M(R10) → R11

R10 + 2 → R10

Indirect autoincrement

Immediate

•

MOV @Rn+,Rm

MOV #X,TONI

#45 → M(TONI)

(1) S = source

(2) D = destination

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Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request and restore back to the

low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

•

Active mode ( AM)

All clocks are active.

Low-power mode 0 (LPM0)

–

•

–

CPU is disabled.

ACLK and SMCLK remain active. MCLK is disabled.

•

Low-power mode 1 (LPM1)

–

CPU is disabled ACLK and SMCLK remain active. MCLK is disabled.

DCO's dc-generator is disabled if DCO not used in active mode.

Low-power mode 2 (LPM2)

–

CPU is disabled.

MCLK and SMCLK are disabled.

DCO's dc-generator remains enabled.

ACLK remains active.

•

Low-power mode 3 (LPM3)

–

CPU is disabled.

MCLK and SMCLK are disabled.

DCO's dc-generator is disabled.

ACLK remains active.

Low-power mode 4 (LPM4)

–

CPU is disabled.

ACLK is disabled.

MCLK and SMCLK are disabled.

DCO's dc-generator is disabled.

Crystal oscillator is stopped.

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh–0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed), the CPU goes

into LPM4 immediately after power up.

SYSTEM

INTERRUPT

INTERRUPT SOURCE

INTERRUPT FLAG

WORD ADDRESS

PRIORITY

Power up

External reset

Watchdog

PORIFG

RSTIFG

WDTIFG

Reset

0FFFEh

31, highest

Flash key violation

KEYV

(2)

PC out-of-range⁽¹⁾

NMI

Oscillator fault

Flash memory access violation

NMIIFG

OFIFG

ACCVIFG

(non)-maskable,

(non)-maskable

0FFFCh

30

(2) (3)

Timer_B3

TBCCR0 CCIFG⁽⁴⁾

maskable

0FFFAh

0FFF8h

29

28

TBCCR1 and TBCCR2

CCIFGs, TBIFG^{(2) (4)}

Timer_B3

maskable

0FFF6h

0FFF4h

0FFF2h

27

26

25

Watchdog Timer

Timer_A3

WDTIFG

TACCR0 CCIFG⁽⁴⁾

maskable

TACCR1 CCIFG,

TACCR2 CCIFG,

TAIFG

Timer_A3

maskable

0FFF0h

24

(2) (4)

USCI_A0/USCI_B0 Receive

USCI_A0/USCI_B0 Transmit

ADC10

UCA0RXIFG, UCB0RXIFG⁽²⁾

UCA0TXIFG, UCB0TXIFG⁽²⁾

ADC10IFG⁽⁴⁾

maskable

0FFEEh

0FFECh

23

22

0FFEAh

21

0FFE8h

20

I/O Port P2 (eight flags)

I/O Port P1 (eight flags)

P2IFG.6 to P2IFG.7^{(2) (4)}

P1IFG.0 to P1IFG.7^{(2) (4)}

maskable

0FFE6h

19

0FFE4h

18

0FFE2h

17

0FFE0h

16

15

(5)

(6)

0FFDEh

0FFDCh ... 0FFC0h

14 ... 0, lowest

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h–01FFh) or from

within unused address range.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit disables an interrupt event.

(4) Interrupt flags are located in the module.

(5) This location is used as bootstrap loader security key (BSLSKEY). A 0AA55h at this location disables the BSL completely. A zero (0h)

disables the erasure of the flash if an invalid password is supplied.

(6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

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Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Interrupt Enable 1 and 2

Address

00h

7

6

5

4

3

2

1

0

ACCVIE

rw-0

NMIIE

rw-0

OFIE

rw-0

WDTIE

rw-0

WDTIE:

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer

is configured in interval timer mode.

OFIE:

Oscillator fault enable

NMIIE:

ACCVIE:

(Non)maskable interrupt enable

Flash access violation interrupt enable

Address

01h

7

6

5

4

3

2

1

0

UCB0TXIE

rw-0

UCB0RXIE

rw-0

UCA0TXIE

rw-0

UCA0RXIE

rw-0

UCA0RXIE USCI_A0 receive-interrupt enable

UCA0TXIE USCI_A0 transmit-interrupt enable

UCB0RXIE USCI_B0 receive-interrupt enable

UCB0TXIE USCI_B0 transmit-interrupt enable

Interrupt Flag Register 1 and 2

Address

02h

7

6

5

4

3

2

1

0

NMIIFG

rw-0

RSTIFG

rw-(0)

PORIFG

rw-(1)

OFIFG

rw-1

WDTIFG

rw-(0)

WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation.

Reset on V_CCpower-up or a reset condition at RST/NMI pin in reset mode.

OFIFG:

Flag set on oscillator fault

RSTIFG: External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V_CC

power up.

PORIFG: Power-On Reset interrupt flag. Set on V_CCpower up.

NMIIFG: Set via RST/NMI-pin

Address

03h

7

6

5

4

3

2

1

0

UCB0

TXIFG

UCB0

RXIFG

UCA0

TXIFG

UCA0

RXIFG

rw-1

rw-0

rw-1

rw-0

UCA0RXIFG USCI_A0 receive-interrupt flag

UCA0TXIFG USCI_A0 transmit-interrupt flag

UCB0RXIFG USCI_B0 receive-interrupt flag

UCB0TXIFG USCI_B0 transmit-interrupt flag

xxx

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Legend:

rw:

Bit can be read and written.

rw-0, 1:

rw-(0), (1):

Bit can be read and written. It is Reset or Set by PUC.

Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device.

Memory Organization

MSP430F223x

MSP430F225x

MSP430F227x

Size

Flash

Memory

Main: interrupt vector

Main: code memory

8KB Flash

0FFFFh–0FFC0h

0FFFFh–0E000h

16KB Flash

0FFFFh–0FFC0h

0FFFFh–0C000h

32KB Flash

0FFFFh–0FFC0h

0FFFFh–08000h

Size

Flash

256 Byte

010FFh–01000h

256 Byte

010FFh–01000h

256 Byte

010FFh–01000h

Information memory

Boot memory

RAM

Size

ROM

1KB

0FFFh–0C00h

1KB

0FFFh–0C00h

1KB

0FFFh–0C00h

512 Byte

03FFh–0200h

512 Byte

03FFh–0200h

1KB

05FFh–0200h

Size

16-bit

8-bit

8-bit SFR

01FFh–0100h

0FFh–010h

0Fh–00h

01FFh–0100h

0FFh–010h

0Fh–00h

01FFh–0100h

0FFh–010h

0Fh–00h

Peripherals

Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial

interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete

description of the features of the BSL and its implementation, see the application report, Features of the MSP430

Bootstrap Loader, TI literature number SLAA089.

BSL Function

Data Transmit

Data Receive

DA Package Pins

32 - P1.1

RHA Package Pins

30 – P1.1

10 - P2.2

8 – P2.2

Flash Memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

•

Flash memory has n segments of main memory and four segments of information memory (A to D) of 64

bytes each. Each segment in main memory is 512 bytes in size.

•

Segments 0 to n may be erased in one step, or each segment may be individually erased.

Segments A to D can be erased individually, or as a group with segments 0–n.

Segments A to D are also called information memory.

•

Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is

required.

10

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Peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using all

instructions. For complete module descriptions, refer to the MSP430x2xx Family User's Guide.

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very low power, low frequency oscillator and an internal digitally-controlled oscillator (DCO).

The basic clock module is designed to meet the requirements of both low system cost and low-power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 ms. The basic

clock module provides the following clock signals:

•

Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator for –40°C to

105°C operation. For > 105°C, use external clock source.

•

Main clock (MCLK), the system clock used by the CPU

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules

DCO Calibration Data (provided from factory in flash info memory segment A)

DCO Frequency

Calibration Register

CALBC1_1MHZ

CALDCO_1MHZ

CALBC1_8MHZ

CALDCO_8MHZ

CALBC1_12MHZ

CALDCO_12MHZ

CALBC1_16MHZ

CALDCO_16MHZ

Size

byte

Address

010FFh

010FEh

010FDh

010FCh

010FBh

010FAh

010F9h

010F8h

1 MHz

8 MHz

12 MHz

16 MHz

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off.

Digital I/O

There are four 8-bit I/O ports implemented – ports P1, P2, P3, and P4:

•

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt condition is possible.

Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.

Read/write access to port-control registers is supported by all instructions.

Each I/O has an individually programmable pullup/pulldown resistor.

WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

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Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A3 Signal Connections

Input Pin Number

DA RHA

31 - P1.0 29 - P1.0

Device

Input

Signal

Module

Input

Name

Module

Output

Signal

Output Pin Number

DA RHA

Module

Block

TACLK

ACLK

SMCLK

TAINCLK

TA0

TACLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

CCR1

NA

TA0

TA1

9 - P2.1

7 - P2.1

32 - P1.1 30 - P1.1

10 - P2.2 8 - P2.2

32 - P1.1 30 - P1.1

10 - P2.2 8 - P2.2

TA0

V_SS

36 - P1.5 34 - P1.5

V_CC

33 - P1.2 31 - P1.2

29 - P2.3 27 - P2.3

TA1

CCI1A

CCI1B

GND

33 - P1.2 31 - P1.2

29 - P2.3 27 - P2.3

37 - P1.6 35 - P1.6

TA1

V_SS

V_CC

34 - P1.3 32 - P1.3

TA2

CCI2A

34 - P1.3 32 - P1.3

30 - P2.4 28 - P2.4

38 - P1.7 36 - P1.7

ACLK

(internal)

CCI2B

CCR2

TA2

V_SS

V_CC

GND

V_CC

12

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Timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_B3 Signal Connections

Input Pin Number

DA RHA

Device

Input

Signal

Module

Input

Name

Module

Output

Signal

Output Pin Number

DA RHA

Module

Block

24 - P4.7 22 - P4.7

TBCLK

ACLK

SMCLK

TBCLK

TB0

TBCLK

ACLK

SMCLK

INCLK

CCI0A

CCI0B

GND

Timer

CCR0

CCR1

NA

TB0

TB1

24 - P4.7 22 - P4.7

17 - P4.0 15 - P4.0

20 - P4.3 18 - P4.3

17 - P4.0 15 - P4.0

20 - P4.3 18 - P4.3

TB0

V_SS

V_CC

18 - P4.1 16 - P4.1

21 - P4.4 19 - P4.4

TB1

CCI1A

CCI1B

GND

18 - P4.1 16 - P4.1

21 - P4.4 19 - P4.4

TB1

V_SS

V_CC

19 - P4.2 17 - P4.2

TB2

CCI2A

19 - P4.2 17 - P4.2

22 - P4.5 20 - P4.5

ACLK

(internal)

CCI2B

CCR2

TB2

V_SS

V_CC

GND

V_CC

USCI

The universal serial communication interface (USCI) module is used for serial data communication. The USCI

module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous

communication protocols like UART, enhanced UART with automatic baud-rate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

ADC10

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion

result handling allowing ADC samples to be converted and stored without any CPU intervention.

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Operational Amplifier (OA)

The MSP430F2274M has two configurable low-current general-purpose operational amplifiers. Each OA input

and output terminal is software-selectable and offer a flexible choice of connections for various applications. The

OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

OA0 Signal Connections

Analog Input

Pin Number

Device Input Signal

Module Input Name

DA

RHA

8 - A0

10 - A2

27 - A6

6 - A0

8 - A2

25 - A6

OA0I0

OA0I1

OA0I2

OA0I3

OAxI0

OA0I1

OAxI1

OAxIA

OAxIB

22 - A14 20 - A14

xxxx

OA1 Signal Connections

Device Input Signal

Analog Input

Pin Number

Module Input Name

DA

RHA

30 - A4

10 - A2

29 - A3

28 - A7

28 - A4

8 - A2

OA0I0

OA0I1

OA0I2

OA0I3

OAxI0

OA0I1

OAxI1

OAxIA

OAxIB

27 - A3

26 - A7

23 - A15 21 - A15

14

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Peripheral File Map

PERIPHERALS WITH WORD ACCESS

ADC10

ADC data transfer start address

ADC memory

ADC control register 1

ADC control register 0

ADC analog enable 0

ADC analog enable 1

ADC data transfer control register 1

ADC data transfer control register 0

ADC10SA

1BCh

1B4h

1B2h

1B0h

04Ah

04Bh

049h

048h

ADC10MEM

ADC10CTL1

ADC10CTL0

ADC10AE0

ADC10AE1

ADC10DTC1

ADC10DTC0

Timer_B

Capture/compare register

Timer_B register

Capture/compare control

Timer_B control

TBCCR2

TBCCR1

TBCCR0

TBR

TBCCTL2

TBCCTL1

TBCCTL0

TBCTL

0196h

0194h

0192h

0190h

0186h

0184h

0182h

0180h

011Eh

Timer_B interrupt vector

TBIV

Timer_A

Capture/compare register

Timer_A register

Capture/compare control

Timer_A control

TACCR2

TACCR1

TACCR0

TAR

TACCTL2

TACCTL1

TACCTL0

TACTL

0176h

0174h

0172h

0170h

0166h

0164h

0162h

0160h

012Eh

Timer_A interrupt vector

TAIV

Flash Memory

Flash control 3

Flash control 2

Flash control 1

FCTL3

FCTL2

FCTL1

012Ch

012Ah

0128h

Watchdog Timer+

Watchdog/timer control

WDTCTL

0120h

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PERIPHERALS WITH BYTE ACCESS

OA1

Operational Amplifier 1 control register 1

OA1CTL1

OA1CTL0

0C3h

0C2h

OA0

Operational Amplifier 0 control register 1

OA0CTL1

OA0CTL0

0C1h

0C0h

USI_B0

USCI_B0 transmit buffer

USCI_B0 receive buffer

USCI_B0 status

USCI_B0 bit rate control 1

USCI_B0 bit rate control 0

USCI_B0 control 1

USCI_B0 control 0

USCI_B0 I2C slave address

USCI_B0 I2C own address

UCB0TXBUF

UCB0RXBUF 06Eh

06Fh

UCB0STAT

UCB0BR1

UCB0BR0

UCB0CTL1

UCB0CTL0

UCB0SA

06Dh

06Bh

06Ah

069h

068h

011Ah

0118h

UCB0OA

USI_A0

USCI_A0 transmit buffer

USCI_A0 receive buffer

USCI_A0 status

USCI_A0 modulation control

USCI_A0 baud rate control 1

USCI_A0 baud rate control 0

USCI_A0 control 1

UCA0TXBUF

UCA0RXBUF 066h

067h

UCA0STAT

UCA0MCTL

UCA0BR1

UCA0BR0

UCA0CTL1

UCA0CTL0

065h

064h

063h

062h

061h

060h

USCI_A0 control 0

USCI_A0 IrDA receive control

USCI_A0 IrDA transmit control

USCI_A0 auto baud rate control

UCA0IRRCTL 05Fh

UCA0IRTCTL 05Eh

UCA0ABCTL

05Dh

Basic Clock System+

Port P4

Basic clock system control 3

Basic clock system control 2

Basic clock system control 1

DCO clock frequency control

BCSCTL3

BCSCTL2

BCSCTL1

DCOCTL

053h

058h

057h

056h

Port P4 resistor enable

Port P4 selection

Port P4 direction

Port P4 output

P4REN

P4SEL

P4DIR

P4OUT

P4IN

011h

01Fh

01Eh

01Dh

01Ch

Port P4 input

Port P3

Port P2

Port P3 resistor enable

Port P3 selection

Port P3 direction

Port P3 output

P3REN

P3SEL

P3DIR

P3OUT

P3IN

010h

01Bh

01Ah

019h

018h

Port P3 input

Port P2 resistor enable

Port P2 selection

Port P2 interrupt enable

Port P2 interrupt edge select

Port P2 interrupt flag

Port P2 direction

P2REN

P2SEL

P2IE

P2IES

P2IFG

P2DIR

P2OUT

P2IN

02Fh

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

Port P2 output

Port P2 input

Port P1

Port P1 resistor enable

Port P1 selection

Port P1 interrupt enable

Port P1 interrupt edge select

Port P1 interrupt flag

Port P1 direction

P1REN

P1SEL

P1IE

P1IES

P1IFG

P1DIR

P1OUT

P1IN

027h

026h

025h

024h

023h

022h

021h

020h

Port P1 output

Port P1 input

Special Function

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

IFG2

IFG1

IE2

003h

002h

001h

000h

IE1

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Absolute Maximum Ratings⁽¹⁾

VALUE

–0.3 to 4.1

–0.3 to V_CC+ 0.3

±2

UNIT

V

Voltage applied at V_CCto V_SS

Voltage applied to any pin⁽²⁾

V

Diode current at any device terminal

Storage temperature, T_stg(unprogrammed device⁽³⁾

mA

°C

)

–55 to 150

–55 to 125

(3)

Storage temperature, T_stg(programmed device

)

°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak

reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

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Recommended Operating Conditions^{(1) (2)}

MIN

1.8

NOM

MAX

3.6

UNIT

V

Supply voltage during program execution

V_CC

Supply voltage during program/erase flash memory

2.2

3.6

V

V_SSSupply voltage

0

V

T_A

Operating free-air temperature range

–55

dc

125

4.15

12

°C

V_CC= 1.8 V, Duty Cycle = 50% ±10%

V_CC= 2.7 V, Duty Cycle = 50% ±10%

Processor frequency f_SYSTEM

(Maximum MCLK frequency)^{(1) (2)}

(see Figure 1)

dc

MHz

V_CC≥ 3.3 V, Duty Cycle = 50% ±10%

dc

16

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet.

Legend:

16 MHz

Supply voltage range,

during flash memory

programming

12 MHz

Supply voltage range,

during program execution

7.5 MHz

4.15 MHz

1.8 V

2.2 V

2.7 V

3.3 V 3.6 V

Supply Voltage −V

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V_CC

of 2.2 V.

Figure 1. Operating Area

18

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Active-Mode Supply Current (Into DV_CC+ AV_CC) Excluding External Current – Electrical

Characteristics^{(1) (2)}

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP MAX UNIT

f_DCO= f_MCLK= f_SMCLK= 1 MHz,

f_ACLK= 32,768 Hz,

2.2 V

270 390

Program executes in flash,

BCSCTL1 = CALBC1_1 MHZ,

DCOCTL = CALDCO_1 MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Active-mode (AM)

current (1 MHz)

I_{AM, 1MHz}

–55°C to 125°C

mA

3 V

2.2 V

3 V

390 550

f_DCO= f_MCLK= f_SMCLK= 1 MHz,

f_ACLK= 32,768 Hz,

240

Program executes in RAM,

BCSCTL1 = CALBC1_1 MHZ,

DCOCTL = CALDCO_1 MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Active-mode (AM)

current (1 MHz)

I_{AM, 1MHz}

mA

340

f_MCLK= f_SMCLK= f_ACLK= 32,768 Hz/8 = 4,096

Hz,

f_DCO= 0 Hz,

–55°C to 85°C

125°C

5

6

9

18

10

2.2 V

3 V

–55°C to 85°C

Active-mode (AM) Program executes in flash,

I_{AM, 4kHz}

mA

current (4 kHz)

SELMx = 11, SELS = 1,

DIVMx = DIVSx = DIVAx = 11,

CPUOFF = 0, SCG0 = 1, SCG1 = 0,

OSCOFF = 0

125°C

20

f_MCLK= f_SMCLK= f_{DCO(0, 0)}Ⅹ 100 kHz,

f_ACLK= 0 Hz,

Active-mode (AM) Program executes in flash,

current (100 kHz) RSELx = 0, DCOx = 0,

–55°C to 85°C

125°C

60

72

85

95

2.2 V

3 V

I_AM,100kHz

–55°C to 85°C

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 1

125°C

125

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) For T_A< 105°C, the currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.

The internal and external load capacitance is chosen to closely match the required 9 pF. For T_A> 105°C, the currents are characterized

using a 32-kHz external clock source for ACLK..

Typical Characteristics – Active-Mode Supply Current (Into DV_CC+ AV_CC)

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

5.0

4.0

3.0

2.0

1.0

0.0

f

= 16 MHz

= 12 MHz

DCO

T

= 85 °C

= 25 °C

A

T

A

f

DCO

V

CC

= 3 V

f

= 8 MHz

DCO

T

= 85 °C

= 25 °C

A

T

A

V

CC

= 2.2 V

= 1 MHz

DCO

1.5

2.0

2.5

3.0

3.5

4.0

0.0

4.0

8.0

12.0

16.0

V

CC

− Supply Voltage − V

f

DCO

− DCO Frequency − MHz

Figure 2. Active-Mode Current vs V_CC, T_A= 25°C

Figure 3. Active-Mode Current vs DCO Frequency

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Low-Power-Mode Supply Currents (Into DV_CC+ AV_CC) Excluding External Current – Electrical

Characteristics^{(1) (2)}

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP MAX UNIT

75 90

f_MCLK= 0 MHz,

2.2 V

f_SMCLK= f_DCO= 1 MHz,

f_ACLK= 32,768 Hz,

BCSCTL1 = CALBC1_1 MHZ,

DCOCTL = CALDCO_1 MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

Low-power mode 0

I_{LPM0, 1MHz}

–55°C to 125°C

mA

(LPM0) current⁽³⁾

3 V

90 120

f_MCLK= 0 MHz,

f_SMCLK= f_{DCO(0, 0)}Ⅹ 100 kHz,

f_ACLK= 0 Hz,

RSELx = 0, DCOx = 0,

CPUOFF = 1, SCG0 = 0, SCG1 = 0,

OSCOFF = 1

2.2 V

3 V

37

41

48

65

Low-power mode 0

(LPM0) current⁽³⁾

I_{LPM0, 100kHz}

–55°C to 125°C

mA

f_MCLK= f_SMCLK= 0 MHz, f_DCO= 1 MHz,

f_ACLK= 32,768 Hz,

BCSCTL1 = CALBC1_1 MHZ,

DCOCTL = CALDCO_1 MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 1,

OSCOFF = 0

–55°C to 85°C

125°C

22

25

29

40

32

2.2 V

3 V

Low-power mode 2

(LPM2) current⁽⁴⁾

I_LPM2

–55°C to 85°C

125°C

45

–55°C

25°C

0.7

2.8

6

1.4

4.5

18

2.2 V

3 V

85°C

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLK= 32,768 Hz,

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

125°C

–55°C

25°C

Low-power mode 3

(LPM3) current⁽⁴⁾

I_LPM3,LFXT1

mA

0.9

3.0

6.5

0.4

0.5

2.2

1.5

5.0

19

85°C

125°C

–55°C

25°C

1.0

4.2

2.2 V

3 V

85°C

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLKfrom internal LF oscillator (VLO),

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

125°C

–55°C

25°C

5.7 16.5

Low-power mode 3

current, (LPM3)

I_LPM3,VLO

mA

(4)

0.5

0.6

2.5

6.0

0.1

1.9

5.5

1.2

4.5

17

85°C

125°C

–55°C

25°C

0.5

4.0

16

f_DCO= f_MCLK= f_SMCLK= 0 MHz,

f_ACLK= 0 Hz,

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 1

Low-power mode 4

(LPM4) current⁽⁵⁾

2.2 V/

3 V

I_LPM4

mA

85°C

125°C

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current.

(2) For T_A< 105°C, the currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.

The internal and external load capacitance is chosen to closely match the required 9 pF. For T_A> 105°C, ACLK was sourced from an

external clock source.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

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Schmitt-Trigger Inputs (Ports P1, P2, P3, P4, and RST/NMI⁽¹⁾) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

2.2 V

3 V

MIN TYP MAX UNIT

1.00

1.35

.55

1.65

2.25

1.20

1.65

1.0

V_IT+Positive-going input threshold voltage

–55°C to 125°C

V

2.2 V

3 V

V_IT–Negative-going input threshold voltage

–55°C to 125°C

.75

2.2 V

3 V

0.2

V_hysInput voltage hysteresis (V_IT+– V_IT–

R_PullPullup/pulldown resistor

)

0.3

1.0

For pullup: V_IN= V_SS

For pulldown:

V_IN= V_CC

;

–55°C to 125°C

20

35

5

50

kΩ

C_I

Input capacitance

V_IN= V_SSor V_CC

pF

(1) RST/NMI limit values specified for -55°C to 125°C.

Inputs (Ports P1 and P2) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN MAX UNIT

20 ns

Port P1, P2: P1.x to P2.x, External

t_(int)

External interrupt timing

–55°C to 125°C

2.2 V/3 V

trigger pulse width to set interrupt flag⁽¹⁾

(1) An external signal sets the interrupt flag every time the minimum interrupt pulse width t_(int)is met. It may be set even with trigger signals

shorter than t_(int)

.

Leakage Current (Ports P1, P2, P3 and P4) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN MAX UNIT

±50 nA

High-impedance leakage

current

(1)(2)

I_lkg(Px.x)

–55°C to 125°C

2.2 V/3 V

(1) The leakage current is measured with V_SSor V_CCapplied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

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Outputs (Ports P1, P2, P3, and P4) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

V_CC– 0.25

V_CC– 0.6

V_CC– 0.25

V_CC– 0.6

MAX UNIT

(1)

I_OH(max)= –1.5 mA

–55°C to 125°C

V_CC

2.2 V

(2)

I_OH(max)= –6 mA

V_CC

High-level output

voltage

V_OH

V

I_OH(max)= –1.5 mA⁽¹⁾

I_OH(max)= –6 mA⁽²⁾

I_OL(max)= 1.5 mA⁽¹⁾

I_OL(max)= 6 mA⁽²⁾

I_OL(max)= 1.5 mA⁽¹⁾

I_OL(max)= 6 mA⁽²⁾

V_CC

3 V

2.2 V

3 V

V_CC

V_SSV_SS+0.25

V_SS

V_SS+0.6

Low-level output

voltage

V_OL

V

V_SSV_SS+0.25

V_SS

V_SS+0.6

(1) The maximum total current, I_OH(max)and I_OL(max), for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop

specified.

(2) The maximum total current, I_OH(max)and I_OL(max), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop

specified.

Output Frequency (Ports P1, P2, P3, and P4) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

2.2 V

3 V

MIN

MAX UNIT

10

Port output frequency P1.4/SMCLK, C_L= 20 pF, R_L= 1 kΩ against

(with load)

f_Px.y

–55°C to 125°C

MHz

12

V_CC/2^{(1) (2)}

2.2 V

3 V

12

Clock output

frequency

f_{Port_CLK}

P2.0/ACLK, P1.4/SMCLK, C_L= 20 pF⁽²⁾

–55°C to 125°C

MHz

16

(1) A resistive divider with 2 times 0.5 kΩ between V_CCand V_SSis used as load. The output is connected to the center tap of the divider.

(2) The output voltage reaches at least 10% and 90% V_CCat the specified toggle frequency.

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Typical Characteristics – Outputs

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

25.0

20.0

15.0

10.0

5.0

50.0

40.0

30.0

20.0

10.0

0.0

V

P4.5

= 2.2 V

T

= 25°C

V

P4.5

= 3 V

CC

A

CC

T

= 25°C

= 85°C

A

T

= 85°C

A

T

A

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output Voltage − V

Figure 4.

Figure 5.

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0.0

−5.0

0.0

−10.0

−20.0

−30.0

−40.0

−50.0

V

P4.5

= 2.2 V

V

P4.5

= 3 V

CC

−10.0

−15.0

−20.0

−25.0

T

A

= 85°C

T

A

= 85°C

T = 25°C

A

T

A

= 25°C

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

V

OH

− High-Level Output Voltage − V

V

OH

− High-Level Output Voltage − V

Figure 6.

Figure 7.

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POR/Brownout Reset (BOR) – Electrical Characteristics^{(1) (2)}

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

See Figure 8

T_A

V_CC

MIN

TYP MAX UNIT

0.7 ×

V

V_CC(start)

dV_CC/dt ≤ 3 V/s

V_{(B_IT–)}

See Figure 8 through Figure 10

dV_CC/dt ≤ 3 V/s

–55°C to 125°C

1.71

V

V_{hys(B_IT–)}See Figure 8

70

2

130 210

2000

mV

ms

t_d(BOR)

t_(reset)

See Figure 8

Pulse length needed at RST/NMI

pin to accepted reset internally

–55°C to 125°C

2.2 V/3 V

ms

(1) The current consumption of the brownout module is already included in the I_CCcurrent consumption data. The voltage level V_{(B_IT–)}

+

V_{hys(B_IT– )}is ≤ 1.8 V.

(2) During power up, the CPU begins code execution following a period of t_d(BOR)after V_CC= V_{(B_IT–)}+ V_{hys(B_IT–)}. The default DCO settings

must not be changed until V_CC≥ V_CC(min), where V_CC(min)is the minimum supply voltage for the desired operating frequency.

V

CC

V

hys(B_IT−)

V

(B_IT−)

V

CC(start)

1

0

t

d(BOR)

Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage

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Typical Characteristics - POR/Brownout Reset (BOR)

V

CC

3 V

t

pw

2

V

CC

= 3 V

Typical Conditions

1.5

1

V

CC(drop)

0.5

0

0.001

1

1000

1 ns

− Pulse Width − µs

t

pw

− Pulse Width − µs

t

pw

Figure 9. V_CC(drop)Level With a Square Voltage Drop to Generate a POR/Brownout Signal

V

t

CC

pw

2

1.5

1

3 V

V

= 3 V

CC

Typical Conditions

V

CC(drop)

0.5

t = t

f

r

0

0.001

1

1000

t

f

t

r

t

pw

− Pulse Width − µs

t

pw

− Pulse Width − µs

Figure 10. V_CC(drop)Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

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Main DCO Characteristics

•

All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

•

DCO control bits DCOx have a step size as defined by parameter S_DCO.

Modulation control bits MODx select how often f_{DCO(RSEL,DCO+1)}is used within the period of 32 DCOCLK

cycles. The frequency f_{DCO(RSEL,DCO)}is used for the remaining cycles. The frequency is an average equal to:

32 f_{DCO(RSEL,DCO)} f_DCO(RSEL,DCO) 1)

f_average

+

MOD f_{DCO(RSEL,DCO)}) (32 * MOD) f_DCO(RSEL,DCO) 1)

DCO Frequency – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

RSELx < 14

T_A

V_CC

MIN TYP MAX UNIT

–55°C to 125°C

1.8

2.2

3.0

3.6

V_CC

Supply voltage range

RSELx = 14

RSELx = 15

V

RSELx = 0, DCOx = 0,

MODx = 0

f_DCO(0,0)

f_DCO(0,3)

f_DCO(1,3)

f_DCO(2,3)

f_DCO(3,3)

f_DCO(4,3)

f_DCO(5,3)

f_DCO(6,3)

f_DCO(7,3)

f_DCO(8,3)

f_DCO(9,3)

f_DCO(10,3)

f_DCO(11,3)

f_DCO(12,3)

f_DCO(13,3)

f_DCO(14,3)

f_DCO(15,3)

f_DCO(15,7)

DCO frequency (0, 0)

DCO frequency (0, 3)

DCO frequency (1, 3)

DCO frequency (2, 3)

DCO frequency (3, 3)

DCO frequency (4, 3)

DCO frequency (5, 3)

DCO frequency (6, 3)

DCO frequency (7, 3)

DCO frequency (8, 3)

DCO frequency (9, 3)

DCO frequency (10, 3)

DCO frequency (11, 3)

DCO frequency (12, 3)

DCO frequency (13, 3)

DCO frequency (14, 3)

DCO frequency (15, 3)

DCO frequency (15, 7)

–55°C to 125°C

2.2 V/3 V

3 V

0.06

0.07

0.10

0.14

0.20

0.28

0.39

0.54

0.80

1.10

1.60

2.50

3.00

4.30

6.00

8.60

12.0

16.0

0.14

0.17

0.20

0.28

0.40

0.54

0.77

1.06

1.50

2.10

3.00

4.30

5.50

MHz

RSELx = 0, DCOx = 3,

MODx = 0

RSELx = 1, DCOx = 3,

MODx = 0

RSELx = 2, DCOx = 3,

MODx = 0

RSELx = 3, DCOx = 3,

MODx = 0

RSELx = 4, DCOx = 3,

MODx = 0

RSELx = 5, DCOx = 3,

MODx = 0

RSELx = 6, DCOx = 3,

MODx = 0

RSELx = 7, DCOx = 3,

MODx = 0

RSELx = 8, DCOx = 3,

MODx = 0

RSELx = 9, DCOx = 3,

MODx = 0

RSELx = 10, DCOx = 3,

MODx = 0

RSELx = 11, DCOx = 3,

MODx = 0

RSELx = 12, DCOx = 3,

MODx = 0

7.30 M Hz

RSELx = 13, DCOx = 3,

MODx = 0

9.60

13.9

18.5

26.0

MHz

RSELx = 14, DCOx = 3,

MODx = 0

RSELx = 15, DCOx = 3,

MODx = 0

RSELx = 15, DCOx = 7,

MODx = 0

3 V

Frequency step

between range RSEL

and RSEL+1

S_RSEL

=

S_RSEL

–55°C to 125°C

2.2 V/3 V

1.55

ratio

f_{DCO(RSEL+1,DCO)}/f_{DCO(RSEL,DCO)}

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DCO Frequency – Electrical Characteristics (continued)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP MAX UNIT

Frequency step

between tap DCO and

DCO+1

S_DCO

=

S_DCO

–55°C to 125°C

2.2 V/3 V

1.05 1.08 1.12

40 50 60

ratio

%

f_{DCO(RSEL,DCO+1)}/f_{DCO(RSEL,DCO)}

Duty cycle

Measured at P1.4/SMCLK

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Calibrated DCO Frequencies (Tolerance at Calibration) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

Frequency tolerance at calibration

25°C

3 V

–1

±0.2

1

%

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

f_{CAL(1 MHz)}

f_{CAL(8 MHz)}

f_{CAL(12 MHz)}

f_{CAL(16 MHz)}

1-MHz calibration value

8-MHz calibration value

12-MHz calibration value

16-MHz calibration value

25°C

3 V

0.990

7.920

11.88

15.84

1

8

1.010

MHz

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

8.080

12.12

16.16

MHz

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

12

16

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

Calibrated DCO Frequencies (Tolerance Over Temperature) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

3 V

MIN

–2.5

TYP

±0.5

±1.0

±2.0

1

MAX

2.5

UNIT

%

1-MHz tolerance over temperature

8-MHz tolerance over temperature

12-MHz tolerance over temperature

16-MHz tolerance over temperature

–55°C to 125°C

3 V

–2.5

2.5

%

3 V

–2.5

2.5

%

3 V

–3.0

3.0

%

2.2 V

3 V

0.970

0.975

0.970

7.760

7.800

7.600

11.70

15.52

1.030

1.025

1.030

8.400

8.200

8.240

12.30

16.48

BCSCTL1 = CALBC1_1MHz,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

f_CAL(1MHz)1-MHz calibration value

f_CAL(8MHz)8-MHz calibration value

–55°C to 125°C

1

MHz

3.6 V

2.2 V

3 V

1

8

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

8

3.6 V

2.2 V

3 V

8

12

16

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

f_CAL(12MHz)12-MHz calibration value

f_CAL(16MHz)16-MHz calibration value

–55°C to 125°C

MHz

3.6 V

3 V

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

3.6 V

15.00

16

16.48

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Calibrated DCO Frequencies (Tolerance Over Supply Voltage V_CC) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

1-MHz tolerance over V_CC

8-MHz tolerance overV_CC

12-MHz tolerance over V_CC

16-MHz tolerance over V_CC

TEST CONDITIONS

T_A

V_CC

MIN

–3

TYP

±2

MAX

UNIT

%

25°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

3

–3

±2

%

–3

±2

%

–6

±2

%

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

1-MHz

f_CAL(1MHz)

25°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

0.970

7.760

11.64

15.00

1

8

1.030

8.240

12.36

16.48

MHz

calibration value

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

8-MHz

f_CAL(8MHz)

calibration value

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

12-MHz

f_CAL(12MHz)

12

16

calibration value

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

16-MHz

f_CAL(16MHz)

calibration value

Calibrated DCO Frequencies (Overall Tolerance) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

1-MHz tolerance

over temperature

–55°C to 125°C

1.8 V to 3.6 V

-5

±2

+5

+6

%

8-MHz tolerance

over temperature

–55°C to 125°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

-5

-6

±2

±3

12-MHz tolerance

over temperature

16-MHz tolerance

over temperature

BCSCTL1 = CALBC1_1MHZ,

DCOCTL = CALDCO_1MHZ,

Gating time: 5 ms

1-MHz

calibration value

f_CAL(1MHz)

–55°C to 125°C

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

.950

7.6

1

8

1.050

8.4

MHz

BCSCTL1 = CALBC1_8MHZ,

DCOCTL = CALDCO_8MHZ,

Gating time: 5 ms

8-MHz

calibration value

f_CAL(8MHz)

f_CAL(12MHz)

f_CAL(16MHz)

BCSCTL1 = CALBC1_12MHZ,

DCOCTL = CALDCO_12MHZ,

Gating time: 5 ms

12-MHz

calibration value

11.4

15.00

12

12.6

BCSCTL1 = CALBC1_16MHZ,

DCOCTL = CALDCO_16MHZ,

Gating time: 2 ms

16-MHz

calibration value

16 17.00

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Typical Characteristics – Calibrated 1-MHz DCO Frequency

1.03

1.02

1.01

1.00

0.99

0.98

0.97

1.03

1.02

1.01

1.00

0.99

0.98

0.97

V

= 1.8 V

= 2.2 V

CC

T

= 125 °C

A

T

= 85 °C

= 25 °C

A

CC

V

= 3.0 V

CC

T

A

T

A

= -40 °C

V

CC

= 3.6 V

1.5

2.0

2.5

3.0

3.5

4.0

−50.0 −25.0

0.0

25.0

50.0

75.0 100.0

V

CC

- Suppl y Voltage - V

T

A

− Temperature − °C

Figure 11. Calibrated 1-MHz Frequency vs

Temperature

Figure 12. Calibrated 1-MHz Frequency vs V_CC

Wake-Up From Lower-Power Modes (LPM3/4) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

BCSCTL1 =

CALBC1_1MHZ,

DCOCTL =

–55°C to 125°C

2.2 V/3 V

2

CALDCO_1MHZ,

BCSCTL1 =

CALBC1_8MHZ,

DCOCTL =

CALDCO_8MHZ,

–55°C to 125°C

2.2 V/3 V

3 V

1.5

ms

1

DCO clock wake-up time

from LPM3/4⁽¹⁾

t_DCO,LPM3/4

BCSCTL1 =

CALBC1_12MHZ,

DCOCTL =

CALDCO_12MHZ,

BCSCTL1 =

CALBC1_16MHZ,

DCOCTL =

3 V

1

CALDCO_16MHZ,

1/f_MCL

CPU wake-up time from

LPM3/4⁽²⁾

+

K

t_CPU,LPM3/4

t_Clock,L

PM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge

observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

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Typical Characteristics – DCO Clock Wake-Up Time From LPM3/4

10.00

RSELx = 0...11

RSELx = 12...15

1.00

0.10

1.00

DCO Frequency − MHz

10.00

Figure 13. Clock Wake-Up Time From LPM3 vs DCO Frequency

DCO With External Resistor R_OSC– Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

2.2 V

TYP UNIT

1.8

MHz

1.95

DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0,

T_A= 25°C

f_DCO,ROSC

DCO output frequency with R_OSC

3 V

D_t

Temperature drift

Drift with V_CC

DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0

2.2 V/3 V

±0.1 %/°C

D_V

10

%/V

(1) R_OSC= 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T_K= ±50ppm/°C

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Typical Characteristics - DCO With External Resistor R_OSC

10.00

1.00

0.10

0.01

10.00

1.00

0.10

0.01

RSELx = 4

10.00

100.00

1000.00

10000.00

10.00

100.00

R − External Resistor − kW

OSC

1000.00

10000.00

R

− External Resistor − kW

OSC

Figure 14. DCO Frequency vs R_OSC

,

Figure 15. DCO Frequency vs R_OSC

,

V_CC= 2.2 V, T_A= 25°C

V_CC= 3.0 V, T_A= 25°C

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0.00

R

= 100k

OSC

R

= 100k

OSC

R

= 270k

= 1M

R

= 270k

= 1M

OSC

−50.0 −25.0

0.0

25.0

50.0

75.0 100.0

2.0

2.5

3.0

3.5

4.0

T

A

− Temperature − 5C

V

CC

− Supply Voltage − V

Figure 16. DCO Frequency vs Temperature, V_CC

3.0 V

=

Figure 17. DCO Frequency vs V_CC, T_A= 25°C

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Crystal Oscillator (LFXT1) Low-Frequency Modes – Electrical Characteristics^{(1) (2)}

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

LFXT1 oscillator crystal

frequency, LF mode 0, 1

–40°C to

105°C

f_LFXT1,LF

XTS = 0, LFXT1Sx = 0 or 1

1.8 V to 3.6 V

32,768

Hz

LFXT1 oscillator

f_LFXT1,LFlogic-level square-wave

–55°C to

125°C

XTS = 0, LFXT1Sx = 3

1.8 V to 3.6 V

10,000 32,768 50,000

Hz

input frequency, LF

,logic

mode

XTS = 0, LFXT1Sx = 0;

f_LFXT1,LF= 32,768 kHz,

C_L,eff= 6 pF

–40°C to

105°C

500

200

Oscillation allowance for

LF crystals

OA_LF

kΩ

XTS = 0, LFXT1Sx = 0;

f_LFXT1,LF= 32,768 kHz,

C_L,eff= 12 pF

–40°C to

105°C

XCAPx = 0

1

5.5

8.5

11

Integrated effective load

XCAPx = 1

XTS = 0

–40°C to

105°C

C_L,eff

capacitance,

pF

LF mode⁽³⁾

XCAPx = 2

XCAPx = 3

XTS = 0, Measured at

P1.4/ACLK,

f_LFXT1,LF= 32,768 Hz

Duty

Cycle

–55°C to

125°C

LF mode

2.2 V/3 V

30

10

50

70

%

Oscillator fault frequency

threshold, LF mode

–55°C to

125°C

f_Fault,LF

XTS = 0, LFXT1Sx = 3⁽⁵⁾

10,000

Hz

(4)

(1) To improve EMI on the LFXT1 oscillator the following guidelines should be observed:

(a) Keep as short of a trace as possible between the device and the crystal.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Use of the LFXT1 Crystal Oscillator with T_A> 105°C is not guaranteed. It is recommended that an external digital clock source or the

internal DCO is used to provide clocking.

(3) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is

recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should

always match the specification of the used crystal.

(4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(5) Measured with logic-level input frequency, but also applies to operation with crystals with T_A< 105°C.

Internal Very-Low-Power, Low-Frequency Oscillator (VLO) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

CONDITIONS

PARAMETER

VLO frequency

VLO frequency temperature drift

T_A

V_CC

MIN TYP MAX UNIT

–55°C to 85°C

125°C

2.2 V/3 V

4

12

20

22

f_VLO

kHz

(1)

(2)

df_VLO/dT

–55°C to 125°C

0.5

4

%/°C

%/V

1.8 V –

3.6V

df_VLO/dV_CCVLO frequency supply voltage drift

25°C

(1) Calculated using the box method:

I Version: [MAX(–55...85°C) – MIN(–55...85°C)]/MIN(55–...85°C)/[85°C – (–55°C)]

T Version: [MAX(–55...125°C) – MIN(–55...125°C)]/MIN(–55...125°C)/[125°C – (–55°C)]

(2) Calculated using the box method: [MAX(1.8...3.6 V) – MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V – 1.8 V)

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Crystal Oscillator (LFXT1) High Frequency Modes – Electrical Characteristics^{(1) (2)}

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP MAX UNIT

f_LFXT1,HLFXT1 oscillator crystal frequency,

XTS = 1, LFXT1Sx = 0

–40°C to 105°C

1.8 V to 3.6 V

0.4

1

MHz

HF mode 0

F0

f_LFXT1,HLFXT1 oscillator lcrystal frequency,

XTS = 1, LFXT1Sx = 1

XTS = 1, LFXT1Sx = 2

–40°C to 105°C

1.8 V to 3.6 V

4

HF mode 1

F1

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

2

10

f_LFXT1,HLFXT1 oscillator crystal frequency,

12 MHz

16

HF mode 2

F2

2

1.8 V to 3.6 V

2.2 V to 3.6 V

3 V to 3.6 V

0.4

10

LFXT1 oscillator logic-level

f_LFXT1,H

square-wave input frequency,

XTS = 1, LFXT1Sx = 3

–40°C to 105°C

12 MHz

16

F,logic

HF mode

XTS = 0, LFXT1Sx = 0;

f_LFXT1,HF= 1 MHz,

C_L,eff= 15 pF

2700

800

300

1

Oscillation allowance for HF

XTS = 0, LFXT1Sx = 1

f_LFXT1,HF= 4 MHz,

C_L,eff= 15 pF

OA_HF

crystals

Ω

(see Figure 18 and Figure 19)

XTS = 0, LFXT1Sx = 2

f_LFXT1,HF= 16 MHz,

C_L,eff= 15 pF

Integrated effective load

capacitance,

C_L,eff

XTS = 1⁽⁴⁾

–40°C to 105°C

–55°C to 125°C

pF

HF mode⁽³⁾

XTS = 1, Measured at

P1.4/ACLK,

f_LFXT1,HF= 10 MHz

40

50

60

%

Duty

Cycle

HF mode

2.2 V/3 V

XTS = 1, Measured at

P1.4/ACLK,

f_LFXT1,HF= 16 MHz

–55°C to 125°C

40

30

50

60

Oscillator fault frequency, HF mode

f_Fault,HF

XTS = 1, LFXT1Sx = 3⁽⁶⁾

300 kHz

(5)

(1) To improve EMI on the LFXT1 oscillator the following guidelines should be observed:

(a) Keep as short of a trace as possible between the device and the crystal.

(b) Design a good ground plane around the oscillator pins.

(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Use of the LFXT1 Crystal Oscillator with T_A> 105°C is not guaranteed. It is recommended that an external digital clock source or the

internal DCO is used to provide clocking.

(3) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance it is

recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should

always match the specification of the used crystal.

(4) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(5) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(6) Measured with logic-level input frequency, but also applies to operation with crystals

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Typical Characteristics – LFXT1 Oscillator in HF Mode (XTS = 1)

800.0

700.0

600.0

500.0

400.0

300.0

200.0

100.0

0.0

100000.00

10000.00

1000.00

100.00

LFXT1Sx = 3

LFXT1Sx = 2

LFXT1Sx = 1

1.00

LFXT1Sx = 1

10.00

0.10

10.00

100.00

0.0

4.0

8.0

12.0

16.0

20.0

Crystal Frequency − MHz

Figure 18. Oscillation Allowance vs Crystal

Frequency, C_L,eff= 15 pF, T_A= 25°C

Figure 19. XT Oscillator Supply Current vs Crystal

Frequency, C_L,eff= 15 pF, T_A= 25°C

Timer_A – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

MAX UNIT

Internal: SMCLK, ACLK,

External: TACLK, INCLK,

Duty cycle = 50% ± 10%

2.2 V

10

f_TA

Timer_A clock frequency

–55°C to 125°C

MHz

3 V

16

t_TA,capTimer_A, capture timing

TA0, TA1, TA2

2.2 V/3 V

20

ns

Timer_B – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

MAX UNIT

Internal: SMCLK, ACLK,

External: TBCLK,

Duty Cycle = 50% ± 10%

2.2 V

10

f_TB

Timer_B clock frequency

–55°C to 125°C

MHz

3 V

16

t_TB,capTimer_B, capture timing

TB0, TB1, TB2

2.2 V/3 V

20

ns

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MAX UNIT

USCI (UART Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP

Internal: SMCLK, ACLK,

External: UCLK;

Duty cycle = 50% ± 10%

f_SYSTE

MHz

f_USCI

USCI input clock frequency

–55°C to 125°C

M

BITCLK clock frequency

(equals baud rate in MBaud)

f_BITCLK

–55°C to 125°C

2.2 V/3 V

1

MHz

ns

2.2 V

3 V

50

150

600

t_t

UART receive deglitch time⁽¹⁾

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their width should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20 and

Figure 21)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

MAX UNIT

SMCLK, ACLK,

Duty cycle = 50% ± 10%

f_USCI

USCI input clock frequency

–55°C to 125°C

f_SYSTEMMHz

2.2 V

3 V

110

75

0

t_SU,MI

SOMI input data setup time

SOMI input data hold time

–55°C to 125°C

ns

2.2 V

3 V

t_HD,MI

0

2.2 V

3 V

30

ns

20

UCLK edge to SIMO valid,

C_L= 20 pF

t_VALID,MOSIMO output data valid time

USCI (SPI Slave Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 22 and

Figure 23)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP MAX UNIT

STE lead time,

STE low to clock

t_STE,LEAD

t_STE,LAG

t_STE,ACC

2.2 V/3 V

50

ns

STE lag time,

Last clock to STE high

–55°C to 125°C

2.2 V/3 V

10

STE access time,

STE low to SOMI data out

50

STE disable time,

STE high to SOMI high

impedance

t_STE,DIS

2.2 V/3 V

ns

2.2 V

3 V

20

15

10

t_SU,SI

SIMO input data setup time

SIMO input data hold time

–55°C to 125°C

ns

2.2 V

3 V

t_HD,SI

2.2 V

3 V

75

50

110

75

UCLK edge to SOMI valid,

C_L= 20 pF

t_VALID,SOSOMI output data valid time

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1/f

UCxCLK

CKPL = 0

CKPL = 1

UCLK

t

SU,MI

LOW/HIGH LOW/HIGH

t

HD,MI

SCMI

SIMO

t

VALID, MO

Figure 20. SPI Master Mode, CKPH = 0

1/f

UCxCLK

CKPL = 0

CKPL = 1

UCLK

t

LOW/HIGH LOW/HIGH

t

HD,MI

t

SU,MI

SCMI

SIMO

t

VALID, MO

Figure 21. SPI Master Mode, CKPH = 1

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t

STE,LAG

STE,LEAD

STE

1/f

UCxCLK

CKPL = 0

CKPL = 1

UCLK

t

SU,SIMO

LOW,HIGH LOW,HIGH

t

HD,SIMO

SIMO

SOMI

t

ACC

VALID,SOMI

DIS

Figure 22. SPI Slave Mode, CKPH = 0

t

STE,LAG

STE,LEAD

STE

1/f

UCxCLK

CKPL = 0

CKPL = 1

UCLK

t

LOW,HIGH LOW,HIGH

t

,

HD,SI

t

SU,SI

SIMO

SOMI

t

DIS

VALID,SO

ACC

Figure 23. SPI Slave Mode, CKPH = 1

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USCI (I2C Mode) – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP

MAX UNIT

Internal: SMCLK, ACLK,

External: UCLK,

Duty cycle = 50% ± 10%

f_SYST

EM

f_USCI

f_SCL

USCI input clock frequency

SCL clock frequency

MHz

–55°C to 125°C

2.2 V/3 V

0

400 kHz

f

_SCL≤ 100 kHz

f_SCL> 100 kHz

_SCL≤ 100 kHz

4.0

t_HD,STAHold time (repeated) START

ms

0.6

f

4.7

Set-up time for a repeated

t_SU,STA

START

2.2 V/3 V

ms

f_SCL> 100 kHz

0.6

t_HD,DATData hold time

2.2 V/3 V

2.2 V

0

ns

ms

t_SU,DATData set-up time

t_SU,STOSet-up time for STOP

250

4.0

50 150

50 100

600

ns

Pulse width of spikes

t_SP

–55°C to 125°C

suppressed by input filter

3 V

600

t_HD

t_SU

t_HD

t_BUF

,STA

SDA

t_LOW

t_HIGH

t_SP

SCL

t_SU

,DAT

, STO

t_HD

,DAT

Figure 24. I2C Mode Timing

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10-Bit ADC, Power-Supply and Input Range Conditions – Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_SS= 0 V

T_A

V_CC

MIN TYP MAX UNIT

V_CC

V_Ax

Analog supply voltage range

–55°C to125 °C

2.2

3.6

V

All Ax terminals,

Analog inputs selected in

ADC10AE register

(2)

Analog input voltage range

ADC10 supply current⁽³⁾

–55°C to 125°C

0

V_CC

V

f_ADC10CLK= 5.0 MHz,

ADC10ON = 1, REFON = 0,

ADC10SHT0 = 1,

2.2 V

3 V

0.52 1.05

I_ADC10

mA

0.6

1.2

ADC10SHT1 = 0,

ADC10DIV = 0

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REF2_5V = 0,

REFON = 1, REFOUT = 0

–55°C to 125°C 2.2 V/3 V

Reference supply current,

reference buffer disabled⁽⁴⁾

I_REF+

0.25

1.1

.4

mA

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REF2_5V = 1,

REFON = 1, REFOUT = 0

–55°C to 125°C

–55°C to 85°C 2.2 V/3 V

125°C 2.2 V/3 V

–55°C to 85°C 2.2 V/3 V

3 V

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REFON = 1,

REF2_5V = 0,

1.4

1.8

.7

Reference buffer supply current

with ADC10SR = 0⁽⁴⁾

I_REFB,0

REFOUT = 1, ADC10SR = 0

f_ADC10CLK= 5.0 MHz,

ADC10ON = 0, REFON = 1,

REF2_5V = 0, REFOUT = 1,

ADC10SR=1

0.5

mA

Reference buffer supply current

with ADC10SR = 1⁽⁴⁾

I_REFB,1

125°C

2.2 V/3 V

.8

Only one terminal Ax selected at

a time

C_I

R_I

Input capacitance

27

pF

Input MUX ON resistance

0 V ≤ V_Ax≤ V_CC

2.2 V/3 V

2000

Ω

(1) The leakage current is defined in the leakage current table with Px.x/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range V_R+to V_R–for valid conversion results.

(3) The internal reference supply current is not included in current consumption parameter I_ADC10

.

(4) The internal reference current is supplied via terminal V_CC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

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10-Bit ADC, Built-In Voltage Reference – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

_VREF+≤ 1 mA, REF2_5V = 0

_VREF+≤ 0.5 mA, REF2_5V = 1

_VREF+≤ 1 mA, REF2_5V = 1

_VREF+≤ I_VREF+max, REF2_5V = 0

_VREF+≤ I_VREF+max, REF2_5V = 1

T_A

V_CC

MIN TYP MAX UNIT

I

–55°C to 125°C

2.2

Positive built-in

reference analog

supply voltage range

V_CC,REF+

2.8

2.9

V

2.2 V/3 V

3 V

1.41

2.35

1.5 1.59

2.5 2.65

±0.5

Positive built-in

reference voltage

V_REF+

V

2.2 V

3 V

Maximum V_REF+load

current

I_LD,VREF+

–55°C to 125°C

mA

±1

I_VREF+= 500 mA ± 100 mA,

Analog input voltage V_AxⅩ 0.75 V,

REF2_5V = 0

2.2 V/3 V

3 V

±2

V_REF+load regulation

LSB

I_VREF+= 500 mA ± 100 mA,

Analog input voltage V_AxⅩ 1.25 V,

REF2_5V = 1

–55°C to 125°C

±2

I_VREF+= 100 mA→900 ADC10SR = 0

mA,

400

V_REF+load regulation

response time

V_AxⅩ 0.5 × V_REF+

Error of conversion

,

3 V

ns

ADC10SR = 1

–55°C to 125°C

2000

result ≤ 1 LSB

Maximum capacitance

at pin V_REF+

I_VREF+≤ = 1 mA,

REFON = 1, REFOUT = 1

C_VREF+

TC_REF+

t_REFON

–55°C to 125°C

2.2 V/3 V

3.6 V

100

pF

(1)

Temperature

coefficient

I_VREF+= const. with

0 mA ≤ I_VREF+≤ 1 mA

ppm/°

C

±100

Settling time of internal I_VREF+= 0.5 mA, REF2_5V = 0

–55°C to 125°C

30

1

ms

(2)

reference voltage

REFON = 0 → 1

I_VREF+= 0.5 mA,

REF2_5V = 0,

REFON = 1,

ADC10SR = 0

ADC10SR = 1

ADC10SR = 0

ADC10SR = 1

2.2 V

3 V

–55°C to 125°C

2.5

2

REFBURST = 1

Settling time of

t_REFBURST

reference buffer⁽²⁾

I_VREF+= 0.5 mA,

REF2_5V = 1,

REFON = 1,

4.5

REFBURST = 1

(1) The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/V_REF+/V_eREF+(REFOUT = 1),

must be limited; the reference buffer may become unstable otherwise.

(2) The condition is that the error in a conversion started after t_REFONor t_RefBufis less than ±0.5 LSB.

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10-Bit ADC, External Reference – Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN MAX UNIT

V_eREF+> V_eREF–

SREF1 = 1, SREF0 = 0

,

–55°C to 125°C

1.4 V_CC

Positive external reference input

voltage range

V_eREF+

V

(2)

V

_eREF–≤ V_eREF+≤ V_CC– 0.15

–55°C to 125°C

1.4

0

3.0

1.2

(3)

V,SREF1 = 1, SREF0 = 1

Negative external reference input

V_eREF–

V_eREF+> V_eREF–

V

(4)

voltage range

Differential external reference

input voltage range,

ΔV_eREF= V_eREF+– V_eREF–

(5)

ΔV_eREF

V_eREF+> V_eREF–

–55°C to 125°C

1.4 V_CC

0 V ≤ V_eREF+≤ V_CC

SREF1 = 1, SREF0 = 0

,

2.2 V/3 V

±1

I_VeREF+

Static input current into V_eREF+

mA

0 V ≤ V_eREF+≤ V_CC– 0.15 V ≤ 3

V,

–55°C to 125°C

2.2 V/3 V

0

SREF1 = 1, SREF0 = 1⁽³⁾

I_VeREF–

Static input current into V_eREF–

0 V ≤ V_eREF–≤ V_CC

±1

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, C_I, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current I_REFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

10-Bit ADC, Timing Parameters – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP

MAX UNIT

For specified

performance of ADC10

linearity parameters

ADC10SR=0

ADC10SR=1

–55°C to 125°C 2.2 V/3 V 0.45

6.5

ADC10 input clock

frequency

f_ADC10CLK

MHz

1.5

ADC10 built-in

oscillator frequency f_ADC10CLK= f_ADC10OSC

ADC10DIVx = 0, ADC10SSELx = 0,

f_ADC10OSC

–55°C to 125°C 2.2 V/3 V 3.25

–55°C to 125°C 2.2 V/3 V 2.06

6.45

3.51

MHz

ms

ADC10 built-in oscillator,

ADC10SSELx = 0,

f_ADC10CLK= f_ADC10OSC

t_CONVERT

Conversion time

13 =

f_ADC10CLKfrom ACLK, MCLK, or

SMCLK: ADC10SSELx ≠ 0

–55°C to 125°C

ADC10DIVx

1/f_ADC10CLK

Turn-on settling time

of the ADC

t_ADC10ON

⁽¹⁾–55°C to 125°C

100

ns

(1) The condition is that the error in a conversion started after t_ADC10ONis less than ±0.5 LSB. The reference and input signal are already

settled.

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10-Bit ADC, Linearity Parameters – Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP MAX UNIT

±1 LSB

E_I

Integral linearity error

Differential linearity error

Offset error

–55°C to 125°C

2.2 V/3 V

E_D

E_O

±1 LSB

Source impedance R_S< 100 Ω

±1 LSB

SREFx = 010, un-buffered external

reference,

V_eREF+= 1.5 V

–55°C to 125°C

2.2 V

3 V

±1.1

±2

±4

±3

±5

±7

±6

SREFx = 010; un-buffered external

reference,

V_eREF+= 2.5 V

E_G

Gain error

LSB

SREFx = 011, buffered external

reference⁽²⁾

,

2.2 V

3 V

V_eREF+= 1.5 V

SREFx = 011, buffered external

(2)

reference

,

V_eREF+= 2.5 V

SREFx = 010, unbuffered external

reference,

V_eREF+= 1.5 V

2.2 V

3 V

SREFx = 010, unbuffered external

reference,

V_eREF+= 2.5 V

±2

E_T

Total unadjusted error

LSB

SREFx = 011, buffered external

reference⁽²⁾

,

2.2 V

3 V

±2

V_eREF+= 1.5 V

SREFx = 011, buffered external

reference⁽²⁾

,

±2

V_eREF+= 2.5 V

(1) 2.2V Not Production Tested.

(2) The reference buffer's offset adds to the gain and total unadjusted error.

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10-Bit ADC, Temperature Sensor and Built-In V_MID– Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

2.2 V

3 V

MIN TYP MAX UNIT

40 120

mA

Temperature sensor

supply current⁽¹⁾

REFON = 0, INCHx = 0Ah,

T_A= 25°C

I_SENSOR

–55°C to 125°C

60 160

ADC10ON = 1, INCHx = 0Ah

TC_SENSOR

–55°C to 125°C

2.2 V/3 V 3.44 3.55 3.66 mV/°C

(2)

ADC10ON = 1, INCHx =

0Ah⁽²⁾

V_{Offset,Sensor}Sensor offset voltage

-100

100

mV

Temperature sensor voltage at

T_A= 125°C(T version only)

1265 1365 1465

1195 1295 1395

985 1085 1185

895 995 1095

Temperature sensor voltage at

T_A= 85°C

V_Sensor

Sensor output voltage⁽³⁾

2.2 V/3 V

Temperature sensor voltage at

T_A= 25°C

Temperature sensor voltage at

T_A= 0°C

ADC10ON = 1, INCHx = 0Ah,

Error of conversion result ≤ 1

LSB

t_{Sensor(sample}Sample time required

)

–55°C to 125°C

30

ms

(4)

if channel 10 is selected

2.2 V

3 V

NA

Current into divider

I_VMID

ADC10ON = 1, INCHx = 0Bh

–55°C to 125°C

mA

at channel 11⁽⁵⁾

2.2 V

3 V

1.06

1.46

1400

1.1 1.14

1.5 1.54

ADC10ON = 1, INCHx = 0Bh,

V_MIDis Ⅹ 0.5 × V_CC

V_MID

V_CCdivider at channel 11

V

ADC10ON = 1, INCHx = 0Bh,

Error of conversion result ≤ 1

LSB

2.2 V

Sample time required

if channel 11 is selected

t_VMID(sample)

–55°C to 125°C

ns

(6)

3 V

1220

(1) The sensor current I_SENSORis consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is

high). When REFON = 1, I_SENSORis included in I_REF+. When REFON = 0, I_SENSORapplies during conversion of the temperature sensor

input (INCH = 0Ah).

(2) The following formula can be used to calculate the temperature sensor output voltage:

V_Sensor,typ= TC_Sensor(273 + T [°C] ) + V_{Offset,sensor}[mV] or

V_Sensor,typ= TC_SensorT [°C] + V_Sensor(T_A= 0°C) [mV]

(3) Results based on characterization and/or production test, not TC_Sensoror V_{Offset,sensor}

.

(4) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time t_SENSOR(on)

(5) No additional current is needed. The V_MIDis used during sampling.

.

(6) The on-time t_VMID(on)is included in the sampling time t_VMID(sample); no additional on time is needed.

Operational Amplifier (OA) Supply Specifications – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX UNIT

V_CC

Supply voltage range

–55°C to 125°C

2.2

3.6

290

190

80

V

Fast Mode

180

110

50

I_CC

Supply current⁽¹⁾

Medium Mode

Slow Mode

2.2 V/3 V

mA

dB

PSSR Power-supply rejection ratio

Noninverting

70

(1) Corresponding pins configured as OA inputs and outputs, respectively.

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Operational Amplifier (OA) Input/Output Specifications – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN

TYP

MAX

V_CC

1.2

15

20

50

UNIT

-

V_I/P

Input voltage range

–55°C to 125°C

–0.1

V

–55°C to 55°C

55°C to 85°C

85°C to 125°C

–15

–20

–50

±0.5

±5

Input leakage

current^{(1) (2)}

I_lkg

2.2 V/3 V

nA

Fast Mode

50

80

Medium Mode f_V(I/P)= 1 kHz

Slow Mode

140

30

Voltage noise density,

I/P

V_n

nV/√Hz

Fast Mode

Medium Mode f_V(I/P)= 10 kHz

Slow Mode

50

65

V_IO

Offset voltage, I/P

–55°C to 125°C 2.2 V/3 V

2.2 V/3 V

±10

mV

Offset temperature

drift, I/P

(3)

±10

mV/°C

Offset voltage drift

with supply, I/P

0.3 V ≤ V_IN≤ V_CC– 1.0 V

ΔV_CC≤ ±10%, T_A= 25°C

–55°C to 125°C 2.2 V/3 V

±1.5

V_CC

mV/V

V

V_CC

0.2

–

Fast Mode, I_SOURCE≤ –500 mA

Slow Mode, I_SOURCE≤ –150 mA

–55°C to 125°C

2.2 V/3 V

High-level output

voltage,

O/P

V_OH

V_CC

0.1

–

–55°C to 125°C

Low-level output

voltage,

O/P

Fast Mode, I_SOURCE≤ 500 mA

Slow Mode, I_SOURCE≤ 150 mA

–55°C to 125°C

V_SS

0.2

0.1

V_OL

2.2 V/3 V

V

–55°C to 125°C

R_Load= 3 kΩ, C_Load= 50 pF,

V_O/P(OAx)< 0.2 V

150

0.1

70

Output resistance⁽⁴⁾

(see Figure 25)

R_Load= 3 kΩ, C_Load= 50 pF,

V_O/P(OAx)> V_CC– 1.2 V

R_O/P(OAx)

2.2 V/3 V

Ω

R_Load= 3 kΩ, C_Load= 50 pF,

0.2 V ≤ V_O/P(OAx)≤ V_CC– 0.2 V

Common-mode

rejection ratio

CMRR

Noninverting

dB

(1) ESD damage can degrade input current leakage.

(2) The input bias current is overridden by the input leakage current.

(3) Calculated using the box method

(4) Specification valid for voltage-follower OAx configuration

R

O/P(OAx)

Max

R

Load

I

Load

AV

CC

OAx

2

C

O/P(OAx)

Min

0.2V

AV

−0.2V

CC

V

AV

OUT

CC

Figure 25. OAx Output Resistance Tests

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Operational Amplifier (OA) Dynamic Specifications – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Fast Mode

T_A

V_CC

MIN TYP

MAX UNIT

1.2

0.8

0.3

100

60

SR

Slew rate

Medium Mode

Slow Mode

V/ms

Open-loop voltage gain

Phase margin

dB

deg

dB

fm

C_L= 50 pF

Gain margin

20

Noninverting, Fast Mode,

R_L= 47 kΩ, C_L= 50 pF

2.2

1.4

Gain-bandwidth product

Noninverting, Medium Mode,

(see Figure 26 and Figure 27) R_L= 300 kΩ, C_L= 50 pF

GBW

2.2 V/3 V

MHz

Noninverting, Slow Mode,

R_L= 300 kΩ, C_L= 50 pF

0.5

10

t_en(on)

t_en(off)

Enable time on

Enable time off

t_on, noninverting, Gain = 1

–55°C to 125°C

2.2 V/3 V

20

1

ms

TYPICAL OPEN-LOOP GAIN vs FREQUENCY

TYPICAL PHASE vs FREQUENCY

140

120

100

80

0

−50

Fast Mode

60

−100

−150

−200

−250

40

Medium Mode

20

Medium Mode

Slow Mode

0

Slow Mode

−20

−40

−60

−80

1

10

100

1000

10000

100000

1

10

100

1000

10000

100000

Input Frequency − kHz

Figure 26.

Figure 27.

Operational Amplifier OA Feedback Network, Resistor Network – Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

TYP

96

6

MAX UNIT

Total resistance of resistor

string

Unit resistor of resistor string⁽²⁾

R_total

R_unit

kΩ

(1) A single resistor string is composed of 4 R_unit+ 4 R_unit+ 2 R_unit+ 2 R_unit+ 1 R_unit+ 1 R_unit+ 1 R_unit+ 1 R_unit= 16 R_unit= R_total

.

(2) For the matching (i.e., the relative accuracy) of the unit resistors on a device, refer to the gain and level specifications of the respective

configurations.

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Operational Amplifier (OA) Feedback Network, Comparator Mode (OAFCx = 3) – Electrical

Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

OAFBRx = 1, OARRIP = 0

OAFBRx = 2, OARRIP = 0

OAFBRx = 3, OARRIP = 0

OAFBRx = 4, OARRIP = 0

OAFBRx = 5, OARRIP = 0

OAFBRx = 6, OARRIP = 0

OAFBRx = 7, OARRIP = 0

OAFBRx = 1, OARRIP = 1

OAFBRx = 2, OARRIP = 1

OAFBRx = 3, OARRIP = 1

OAFBRx = 4, OARRIP = 1

OAFBRx = 5, OARRIP = 1

OAFBRx = 6, OARRIP = 1

OAFBRx = 7, OARRIP = 1

Fast Mode, Overdrive 10 mV

Fast Mode, Overdrive 100 mV

Fast Mode, Overdrive 500 mV

Medium Mode, Overdrive 10 mV

Medium Mode, Overdrive 100 mV

Medium Mode, Overdrive 500 mV

Slow Mode, Overdrive 10 mV

Slow Mode, Overdrive 100 mV

Slow Mode, Overdrive 500 mV

T_A

V_CC

MIN TYP

0.242

MAX UNIT

–55°C to 125°C

1/4 0.262

0.492

0.619

½

0.512

5/8 0.639

N/A⁽¹⁾

V_Level

Comparator level

2.2 V/3 V

V_CC

–55°C to 125°C

0.057 1/16 0.071

0.122 1/8 0.128

0.182 3/16 0.197

0.242

0.367

0.492

1/4 0.262

3/8 0.383

½

N/A⁽¹⁾

40

0.512

4

3

60

Propagation delay

(low-high and high-low)

t_PLH, t_PHL

2.2 V/3 V

6

ms

5

160

20

15

(1) The level is not available due to the analog input voltage range of the operational amplifier.

Operational Amplifier (OA) Feedback Network, Noninverting Amplifier Mode (OAFCx = 4) –

Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

OAFBRx = 0

OAFBRx = 1

OAFBRx = 2

OAFBRx = 3

OAFBRx = 4

OAFBRx = 5

OAFBRx = 6

OAFBRx = 7

T_A

V_CC

MIN

0.970

1.325

1.985

2.638

3.94

TYP

1.00

1.334

2.001

2.667

4.00

5.33

7.97

15.8

–60

MAX UNIT

1.035

1.345

2.017

2.696

4.06

–55°C to 125°C

G

Gain

2.2 V/3 V

5.22

5.44

7.76

8.18

15.0

16.7

2.2 V

3 V

Total harmonic

distortion/nonlinearity

THD

t_Settle

All gains

dB

–70

Settling time⁽¹⁾

All power modes

–55°C to 125°C 2.2 V/3 V

7

12 ms

(1) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The

settling time of the amplifier itself might be faster.

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Operational Amplifier (OA) Feedback Network, Inverting Amplifier Mode (OAFCx = 6) –

Electrical Characteristics⁽¹⁾

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

OAFBRx = 1

T_A

V_CC

MIN

-0.385

-1.023

-1.712

-3.10

TYP

–0.335

–1.002

–1.668

–3.00

–4.33

–6.97

–14.8

–60

MAX UNIT

-0.305

-0.979

-1.624

-2.90

–55°C to 125°C

OAFBRx = 2

OAFBRx = 3

OAFBRx = 4

OAFBRx = 5

OAFBRx = 6

OAFBRx = 7

G

Gain

–55°C to 125°C 2.2 V/3 V

–55°C to 125°C

2.2 V

-4.51

-4.15

-7.37

-6.57

-16.6

-13.1

Total harmonic

distortion/nonlinearity

THD

t_Settle

All gains

dB

3 V

–70

Settling time⁽²⁾

All power modes

–55°C to 125°C 2.2 V/3 V

7

12 ms

(1) This includes the 2 OA configuration "inverting amplifier with input buffer". Both OA needs to be set to the same power mode OAPMx.

(2) The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The

settling time of the amplifier itself might be faster.

Flash Memory – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST

CONDITIO

NS

T_A

V_CC

MIN TYP MAX UNIT

V_{CC(PGM/ERASE)}Program and erase supply voltage

–55°C to 125°C

2.2

3.6

476

5

V

kHz

mA

f_FTG

Flash timing generator frequency

Supply current from V_CCduring program

Supply current from V_CCduring erase

Cumulative program time⁽¹⁾

257

I_PGM

2.2 V/3.6 V

1

I_ERASE

t_CPT

10.5

10

mA

ms

t_CMErase

Cumulative mass erase time

20

10⁴

100

ms

Program/Erase endurance

10⁵

cycles

years

t_FTG

t_Retention

t_Word

Data retention duration⁽²⁾

T_J= 25°C

(3)

Word or byte program time

30

25

Block program time for 1^stbyte or word

(3)

t_{Block, 0}

Block program time for each additional

byte or word

t_{Block, 1-63}

t_{Block, End}

t_{Mass Erase}

t_{Seg Erase}

18

6

t_FTG

Block program end-sequence wait time

1059

3

Mass erase time

Segment erase time

4819

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) To test the flash data retention at various temperatures we make use of accelerated tests on the flash with 500-Hours Baking Time at

250°C. These tests are wholly based on Arrhenius law and equation. For more information refer to Figure 28.

(3) These values are hardwired into the Flash Controller's state machine (t_FTG= 1/f_FTG).

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30

25

20

15

10

5

0

85

90

95

100

105

110

115

120

125

130

135

140

145

150

Junction Temperature - T_J(C)

Figure 28. Flash Data Retention vs Junction Temperature

RAM – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

CPU halted

T_A

MIN MAX UNIT

1.6

(1)

V_(RAMh)

RAM retention supply voltage

–55°C to 125°C

V

(1) This parameter defines the minimum supply voltage V_CCwhen the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

JTAG and Spy-Bi-Wire Interface – Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

V_CC

MIN TYP MAX UNIT

f_SBW

Spy-Bi-Wire input frequency

–55°C to 125°C

2.2 V/3 V

0

20 MHz

0.02

5

t_SBW,LowSpy-Bi-Wire low clock pulse length

–55°C to 125°C

2.2 V/3 V

15

ms

Spy-Bi-Wire enable time

t_SBW,En(TEST high to acceptance of first clock

1

ms

edge⁽¹⁾

)

Spy-Bi-Wire return to normal operation

time

t_SBW,Ret

f_TCK

15

100

5

ms

2.2 V

3 V

0

MHz

TCK input frequency⁽²⁾

–55°C to 125°C

10 MHz

90 kΩ

R_InternalInternal pulldown resistance on TEST

2.2 V/3 V

25

60

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t_SBW,Entime after pulling the TEST/SBWCLK pin high before

applying the first SBWCLK clock edge.

(2) f_TCKmay be restricted to meet the timing requirements of the module selected.

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JTAG Fuse⁽¹⁾– Electrical Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A

MIN

2.5

6

MAX UNIT

V_CC(FB)

V_FB

Supply voltage during fuse-blow condition

Voltage level on TEST for fuse blow

Supply current into TEST during fuse blow

Time to blow fuse

T_A= 25°C

V

–40°C to 125°C

7

100

1

V

I_FB

mA

ms

t_FB

(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to

bypass mode.

50

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

APPLICATION INFORMATION

Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger

Pad Logic

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1SEL.x

P1IN.x

P1.2/TA1

P1.3/TA2

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

Port P1 (P1.0 to P1.3) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P1.X)

X

FUNCTION⁽¹⁾

P1DIR.x

P1SEL.x

P1.0⁽³⁾

I: 0; O: 1

0

1

0

1

0

1

0

1

P1.0/TACLK/ADC10CLK

0

Timer_A3.TACLK

ADC10CLK

P1.1 ⁽⁴⁾(I/O)

Timer_A3.CCI0A

Timer_A3.TA0

P1.2⁽⁴⁾(I/O)

0

1

I: 0; O: 1

P1.1/TA0

P1.2/TA1

P1.3/TA2

1

2

3

0

1

I: 0; O: 1

Timer_A3.CCI0A

Timer_A3.TA0

P1.3⁽⁴⁾I/O

0

1

I: 0; O: 1

Timer_A3.CCI0A

Timer_A3.TA0

0

1

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Default after reset (PUC/POR)

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Port P1 Pin Schematic: P1.4 to P1.6, Input/Output With Schmitt Trigger and In-System Access

Features

Pad Logic

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P1.4/SMCLK/TCK

P1.5/TA0/TMS

P1.6/TA1/TDI

Bus

Keeper

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

To JTAG

From JTAG

Port P1 (P1.4 to P1.6) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P1.X)

X

FUNCTION⁽¹⁾

P1DIR.x

P1SEL.x

4-Wire JTAG

P1.4⁽³⁾(I/O)

SMCLK

I: 0; O: 1

0

1

X

0

1

X

0

1

X

0

1

0

1

0

1

P1.4/SMCLK/TCK

4

1

TCK

X

P1.5⁽³⁾(I/O)

Timer_A3.TA0

TMS

P1.6⁽³⁾(I/O)

Timer_A3.TA1

TDI/TCLK⁽⁴⁾

I: 0; O: 1

P1.5/TA0/TMS

5

6

1

X

I: 0; O: 1

P1.6/TA1/TDI/TCLK

1

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Function controlled by JTAG

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P1 Pin Schematic: P1.7, Input/Output With Schmitt Trigger and In-System Access Features

Pad Logic

P1REN.7

DVSS

DVCC

0

1

P1DIR.7

0

1

Direction

0: Input

1: Output

0

1

P1OUT.7

Module X OUT

P1.7/TA2/TDO/TDI

Bus

Keeper

P1SEL.7

P1IN.7

EN

D

Module X IN

P1IRQ.7

P1IE.7

EN

Q

Set

P1IFG.7

Interrupt

Edge

Select

P1SEL.7

P1IES.7

To JTAG

From JTAG

From JTAG (TDO)

Port P1 (P1.7) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P1.X)

X

FUNCTION⁽¹⁾

P1DIR.x

P1SEL.x

4-Wire JTAG

P1.7⁽³⁾(I/O)

I: 0; O: 1

0

1

X

0

1

P1.7/TA2/TDO/TDI

7

Timer_A3.TA2

TDO/TDI⁽⁴⁾

1

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Function controlled by JTAG

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MSP430F2274-EP

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

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Port P2 Pin Schematic: P2.0, P2.2, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = y

ADC10AE0.y

P2REN.x

DVSS

DVCC

0

1

P2DIR.x

0

1

Direction

0: Input

1: Output

0

1

P2OUT.x

Module X OUT

P2.0/ACLK/A0/OA0I0

P2.2/TA0/A2/OA0I1

Bus

Keeper

P2SEL.x

P2IN.x

EN

D

Module X IN

P2IRQ.x

P2IE.x

EN

Q

Set

P2IFG.x

Interrupt

Edge

Select

P2SEL.x

P2IES.x

+

OA0

−

Port P2 (P2.0, P2.2) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

Pin Name (P2.X)

X

Y

FUNCTION⁽¹⁾

P2DIR.x

P2SEL.x

ADC10AE0.y

P2.0⁽³⁾(I/O)

ACLK

A0/OA0I0⁽⁴⁾

P2.2⁽³⁾(I/O)

I: 0; O: 1

0

1

X

0

1

X

0

1

0

1

P2.0/ACLK/A0/OA0I0

0

1

X

I: 0; O: 1

Timer_A3.CCI0B

Timer_A3.TA0

A2/OA0I1⁽⁴⁾

0

1

P2.2/TA0/A2/OA0I1

2

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

54

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P2 Pin Schematic: P2.1, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = 1

ADC10AE0.1

P2REN.1

DVSS

DVCC

0

1

P2DIR.1

0

1

Direction

0: Input

1: Output

P2OUT.1

0

1

Module X OUT

P2.1/TAINCLK/SMCLK/

A1/OA0O

Bus

Keeper

P2SEL.1

P2IN.1

EN

D

Module X IN

P2IRQ.1

P2IE.1

EN

Q

Set

P2IFG.1

+

1

OA0

Interrupt

Edge

Select

P2SEL.1

P2IES.1

−

OAADCx

OAFCx

OAPMx

(OAADCx = 10 or OAFCx = 000) and OAPMx > 00

To OA0 Feedback Network

1

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

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Port P2 Pin Schematic: P2.3, Input/Output With Schmitt Trigger

SREF2

VSS

Pad Logic

0

1

To ADC10 V

R−

To ADC10

INCHx = 3

ADC10AE0.3

P2REN.3

P2DIR.3

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

0

1

P2OUT.3

Module X OUT

P2.3/TA1/

A3/VREF−/VeREF−/

OA1I1/OA1O

Bus

Keeper

P2SEL.3

P2IN.3

EN

D

Module X IN

P2IRQ.3

P2IE.3

EN

Q

Set

P2IFG.3

Interrupt

Edge

Select

P2SEL.3

P2IES.3

+

1

OA1

−

OAADCx

OAFCx

OAPMx

(OAADCx = 10 or OAFCx = 000) and OAPMx > 00

To OA1 Feedback Network

1

56

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P2 (P2.1) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P2.X)

X

Y

FUNCTION⁽¹⁾

P2.1⁽³⁾(I/O)

P2DIR.x

P2SEL.x

ADC10AE0.y

I: 0; O: 1

0

1

X

0

1

Timer_A3.INCLK

SMCLK

A1/OA0O⁽⁴⁾

0

1

X

P2.1/TAINCLK/SMCLK/A1/OA0O

1

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Port P2 (P2.3) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P2.X)

X

Y

FUNCTION⁽¹⁾

P2.3⁽³⁾(I/O)

P2DIR.x

P2SEL.x

ADC10AE0.y

I: 0; O: 1

0

1

X

0

1

Timer_A3.CCI1B

0

1

P2.3/TA1/A3/V_REF–/V_eREF–/OA1I1/OA1O

3

Timer_A3.TA1

A3/V_REF–/V_eREF–/OA1I1/OA1O⁽⁴⁾

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

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Port P2 Pin Schematic: P2.4, Input/Output With Schmitt Trigger

Pad Logic

To/from ADC10

positive reference

To ADC10

INCHx = 4

ADC10AE0.4

P2REN.4

DVSS

DVCC

0

1

P2DIR.4

0

1

Direction

0: Input

1: Output

0

1

P2OUT.4

Module X OUT

P2.4/TA2/

A4/VREF+/VeREF+/

OA1I0

Bus

Keeper

P2SEL.4

P2IN.4

EN

D

Module X IN

P2IRQ.4

P2IE.4

EN

Q

Set

P2IFG.4

Interrupt

Edge

Select

P2SEL.4

P2IES.4

+

OA1

−

Port P2 (P2.4) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P2.X)

X

Y

FUNCTION⁽¹⁾

P2.4⁽³⁾(I/O)

Timer_A3.TA2

A4/V_REF+/V_eREF+/OA1I0⁽⁴⁾

P2DIR.x

P2SEL.x

ADC10AE0.y

I: 0; O: 1

0

1

0

1

P2.4/TA2/A4/V_REF+/V_eREF+/OA1I0

4

1

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

58

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P2 Pin Schematic: P2.5, Input/Output With Schmitt Trigger and External R_OSCfor DCO

Pad Logic

To DCO

DCOR

P1REN.x

DVSS

DVCC

0

1

P1DIR.x

0

1

Direction

0: Input

1: Output

0

1

P1OUT.x

Module X OUT

P2.5/ROSC

Bus

Keeper

P1SEL.x

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

EN

Q

Set

P1IFG.x

Interrupt

Edge

Select

P1SEL.x

P1IES.x

Port P2 (P2.5) Pin Functions

CONTROL BITS/SIGNALS⁽¹⁾

PIN NAME (P2.X)

X

FUNCTION

P2DIR.x

P2SEL.x

DCOR

P2.5⁽²⁾(I/O)

0/1

0

1

X

0

1

N/A⁽³⁾

DV_SS

R_OSC

P2.5/R_OSC

5

1

X

(1) X: Don't care

(2) Default after reset (PUC/POR)

(3) N/A: Not available or not applicable

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

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Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger and Crystal Oscillator Input

BCSCTL3.LFXT1Sx = 11

LFXT1 Oscillator

P2.7/XOUT

LFXT1 off

0

1

LFXT1CLK

Pad Logic

P2SEL.7

P2REN.6

DVSS

0

1

DVCC

P2DIR.6

0

1

Direction

0: Input

1: Output

0

1

P2OUT.6

Module X OUT

P2.6/XIN

Bus

Keeper

P2SEL.6

P2IN.6

EN

D

Module X IN

P2IRQ.6

P2IE.6

EN

Set

Q

P2IFG.6

Interrupt

Edge

Select

P2SEL.6

P2IES.6

Port P2 (P2.6) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P2.X)

X

FUNCTION⁽¹⁾

P2DIR.x

I: 0; O: 1

X

P2SEL.x

P2.6 (I/O)

XIN⁽³⁾

0

1

P2.6/XIN

6

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

60

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger and Crystal Oscillator Output

BCSCTL3.LFXT1Sx = 11

LFXT1 Oscillator

LFXT1 off

0

1

LFXT1CLK

From P2.6/XIN

P2.6/XIN

Pad Logic

P2SEL.6

P2REN.7

DVSS

0

1

DVCC

P2DIR.7

0

1

Direction

0: Input

1: Output

0

1

P2OUT.7

Module X OUT

P2.7/XOUT

Bus

Keeper

P2SEL.7

P2IN.7

EN

D

Module X IN

P2IRQ.7

P2IE.7

EN

Set

Q

P2IFG.7

Interrupt

Edge

Select

P2SEL.7

P2IES.7

Port P2 (P2.7) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P2.X)

X

FUNCTION⁽¹⁾

P2DIR.x

I: 0; O: 1

X

P2SEL.x

P2.7 (I/O)

XOUT^{(3) (4)}

0

1

XOUT/P2.7

6

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this

pin after reset.

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

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Port P3 Pin Schematic: P3.0, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = 5

ADC10AE0.5

P3REN.0

DVSS

DVCC

0

1

P3DIR.0

0

1

Direction

0: Input

1: Output

USCI Direction

Control

0

1

P3OUT.0

Module X OUT

P3.0/UC1STE/UC0CLK/A5

Bus

Keeper

P3SEL.0

P3IN.0

EN

D

Module X IN

Port P3 (P3.0) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P1.X)

X

Y

FUNCTION⁽¹⁾

P3DIR.x

P3SEL.x

ADC10AE0.y

P3.0⁽³⁾(I/O)

UC1STE/UC0CLK^{(4) (5)}

A5⁽⁶⁾

I: 0; O: 1

0

1

0

1

P3.0/UC1STE/UC0CLK/A5

0

5

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) The pin direction is controlled by the USCI module.

(5) UC0CLK function takes precedence over UC1STE function. If the pin is required as UC0CLK input or output USCI1 is forced to 3-wire

SPI mode if 4-wire SPI mode is selected.

(6) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

62

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P3 Pin Schematic: P3.1 to P3.5, Input/Output With Schmitt Trigger

Pad Logic

DVSS

P3REN.x

DVSS

DVCC

0

1

P3DIR.x

0

1

Direction

0: Input

1: Output

USCI Direction

Control

0

1

P3OUT.x

Module X OUT

P3.1/UC1SIMO/UC1SCL

P3.2/UC1SOMI/UC1SDA

P3.3/UC1CLK/UC0STE

P3.4/UC0TXD/UC0SIMO

P3.5/UC0RXD/UC0SOMI

Bus

Keeper

P3SEL.x

P3IN.x

EN

D

Module X IN

Port P3 (P3.1 to P3.5) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P3.X)

P3.1/UC1SIMO/UC1SDA

P3.2/UC1SOMI/UC1SCL

P3.3/UC1CLK/UC0STE

P3.4/UC0TXD/UC0SIMO

P3.5/UC0RXD/UC0SOMI

X

1

FUNCTION⁽¹⁾

P3DIR.x

P3SEL.x

P3.1⁽³⁾(I/O)

I: 0; O: 1

0

1

0

1

0

1

0

1

0

1

UC1SIMO/UC1SDA⁽⁴⁾

P3.2⁽⁵⁾(I/O)

UC1SOMI/UC1SCL⁽⁶⁾

P3.3⁽⁵⁾(I/O)

UC1CLK/UC0STE^{(6) (7)}

P3.4⁽⁵⁾(I/O)

UC0TXD/UC0SIMO⁽⁶⁾

P3.5⁽⁵⁾(I/O)

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

I: 0; O: 1

X

UC0RXD/UC0SOMI⁽⁶⁾

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) The pin direction is controlled by the USCI module.

(5) Default after reset (PUC/POR)

(6) The pin direction is controlled by the USCI module.

(7) UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output, USCI0 is orced to 3-wire

SPI mode even if 4-wire SPI mode is selected.

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

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Port P3 Pin Schematic: P3.6 to P3.7, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = y

ADC10AE0.y

P3REN.x

P3DIR.x

DVSS

DVCC

0

1

0

1

Direction

0: Input

1: Output

0

1

P3OUT.x

Module X OUT

P3.6/A6/OA0I2

P3.7/A7/OA1I2

Bus

Keeper

P3SEL.x

P3IN.x

EN

D

Module X IN

+

OA0/1

−

Port P3 (P3.6, P3.7) Pin Functions

CONTROL BITS/SIGNALS⁽³⁾

PIN NAME (P3.X)

X

6

7

Y

6

7

FUNCTION^{(1) (2)}

P3DIR.x

P3SEL.x

ADC10AE0.y

P3.6⁽⁴⁾(I/O)

A6/OA0I2⁽⁵⁾

P3.7⁽⁴⁾(I/O)

A7/OA1I2⁽⁵⁾

I: 0; O: 1

0

X

0

1

0

1

P3.6/A6/OA0I2

X

I: 0; O: 1

X

P3.7/A7/OA1I2

X

(1) N/A: Not available or not applicable

(2) UC0CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output, USCI0 is forced to 3-wire

SPI mode if 4-wire SPI mode is selected.

(3) X: Don't care

(4) Default after reset (PUC/POR)

(5) Setting the ADC10AE0.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

64

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SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P4 Pin Schematic: P4.0 to P4.2, Input/Output With Schmitt Trigger

Timer_B Output Tristate Logic

P4.6/TBOUTH/A15/OA1I3

P4SEL.6

P4DIR.6

Pad Logic

ADC10AE1.7

P4REN.x

DVSS

DVCC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

0

1

P4OUT.x

Module X OUT

P4.0/TB0

P4.1/TB1

P4.2/TB2

Bus

Keeper

P4SEL.x

P4IN.x

EN

D

Module X IN

Port P4 (P4.0 to P4.2) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.X)

X

FUNCTION⁽¹⁾

P4DIR.x

P4SEL.x

P4.0⁽²⁾(I/O)

I: 0; O: 1

0

1

0

1

0

1

P4.0/TB0

0

Timer_B3.CCI0A

Timer_B3.TB0

P4.1⁽²⁾(I/O)

0

1

I: 0; O: 1

P4.1/TB1

P4.2/TB2

1

2

Timer_B3.CCI1A

Timer_B3.TB1

P4.2⁽²⁾(I/O)

0

1

I: 0; O: 1

Timer_B3.CCI2A

Timer_B3.TB2

0

1

(1) N/A: Not available or not applicable.

(2) Default after reset (PUC/POR)

Submit Documentation Feedback

65

Product Folder Link(s): MSP430F2274-EP

MSP430F2274-EP

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

www.ti.com

Port P4 Pin Schematic: P4.3 to P4.4, Input/Output With Schmitt Trigger

Timer_B Output Tristate Logic

P4.6/TBOUTH/A15/OA1I3

P4SEL.6

P4DIR.6

ADC10AE1.7

Pad Logic

To ADC10

†

INCHx = 8+y

ADC10AE1.y

P4REN.x

DVSS

DVCC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

P4OUT.x

0

1

Module X OUT

P4.3/TB0/A12/OA0O

P4.4/TB1/A13/OA1O

Bus

Keeper

P4SEL.x

P4IN.x

EN

D

Module X IN

+

1

OA0/1

−

OAADCx

OAPMx

OAADCx = 01 and OAPMx > 00

To OA0/1 Feedback Network

1

^†If OAADCx = 11 and not OAFCx = 000, the ADC input A12 or A13 is internally connected to the OA0 or OA1 output,

respectively, and the connections from the ADC and the operational amplifiers to the pad are disabled.

66

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Product Folder Link(s): MSP430F2274-EP

MSP430F2274-EP

www.ti.com

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P4 (P4.3 to P4.4) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P4.X)

X

Y

FUNCTION⁽¹⁾

P4.3⁽³⁾(I/O)

P4DIR.x

P4SEL.x

ADC10AE1.y

I: 0; O: 1

0

1

X

0

1

X

0

1

0

1

Timer_B3.CCI0B

Timer_B3.TB0

A12/OA0O⁽⁴⁾

0

P4.3/TB0/A12/OA0O

3

4

1

X

P4.4⁽³⁾(I/O)

I: 0; O: 1

Timer_B3.CCI1B

Timer_B3.TB1

A13/OA1O⁽⁴⁾

0

1

X

P4.4/TB1/A13/OA1O

4

5

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Submit Documentation Feedback

67

Product Folder Link(s): MSP430F2274-EP

MSP430F2274-EP

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P4 Pin Schematic: P4.5, Input/Output With Schmitt Trigger

Timer_B Output Tristate Logic

www.ti.com

P4.6/TBOUTH/A15/OA1I3

P4SEL.6

P4DIR.6

ADC10AE1.7

Pad Logic

To ADC10

INCHx = 14

ADC10AE1.6

P4REN.5

DVSS

DVCC

0

1

P4DIR.5

0

1

Direction

0: Input

1: Output

P4OUT.5

0

1

Module X OUT

P4.5/TB3/A14/OA0I3

Bus

Keeper

P4SEL.5

P4IN.5

EN

D

Module X IN

+

OA0

−

Port P4 (P4.5) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P4.X)

X

Y

FUNCTION⁽¹⁾

P4DIR.x

P4SEL.x

ADC10AE1.y

P4.5⁽³⁾(I/O)

I: 0; O: 1

0

1

0

1

P4.5/TB3/A14/OA0I3

5

6

Timer_B3.TB2

A14/OA0I3⁽⁴⁾

1

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

68

Submit Documentation Feedback

Product Folder Link(s): MSP430F2274-EP

MSP430F2274-EP

www.ti.com

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

Port P4 Pin Schematic: P4.6, Input/Output With Schmitt Trigger

Pad Logic

To ADC10

INCHx = 15

ADC10AE1.7

P4REN.6

DVSS

DVCC

0

1

P4DIR.6

0

1

Direction

0: Input

1: Output

0

1

P4OUT.6

Module X OUT

P4.6/TBOUTH/

A15/OA1I3

Bus

Keeper

P4SEL.6

P4IN.6

EN

D

Module X IN

+

OA1

−

Port P4 (P4.6) Pin Functions

CONTROL BITS/SIGNALS⁽²⁾

PIN NAME (P4.X)

X

Y

FUNCTION⁽¹⁾

P4DIR.x

P4SEL.x

ADC10AE1.y

P4.6⁽³⁾(I/O)

TBOUTH

DV_SS

I: 0; O: 1

0

1

X

0

1

0

1

P4.6/TBOUTH/A15/OA1I3

6

7

A15/OA1I3⁽⁴⁾

X

(1) N/A: Not available or not applicable

(2) X: Don't care

(3) Default after reset (PUC/POR)

(4) Setting the ADC10AE1.y bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when

applying analog signals.

Submit Documentation Feedback

69

Product Folder Link(s): MSP430F2274-EP

MSP430F2274-EP

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

www.ti.com

Port P4 Pin Schematic: P4.7, Input/Output With Schmitt Trigger

Pad Logic

DVSS

P4REN.x

DVSS

DVCC

0

1

P4DIR.x

0

1

Direction

0: Input

1: Output

0

1

P4OUT.x

Module X OUT

P4.7/TBCLK

Bus

Keeper

P4SEL.x

P4IN.x

EN

D

Module X IN

Port P4 (Pr.7) Pin Functions

CONTROL BITS/SIGNALS

PIN NAME (P4.X)

X

FUNCTION⁽¹⁾

P4DIR.x

P4SEL.x

P4.7⁽²⁾(I/O)

I: 0; O: 1

0

1

P4.7/TBCLK

7

Timer_B3.TBCLK

DV_SS

0

1

(1) N/A: Not available or not applicable

(2) Default after reset (PUC/POR)

70

Submit Documentation Feedback

Product Folder Link(s): MSP430F2274-EP

MSP430F2274-EP

www.ti.com

SLAS614B –SEPTEMBER 2008–REVISED JANUARY 2010

JTAG Fuse Check Mode

MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the

fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check

current, I_TF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care

must be taken to avoid accidentally activating the fuse check mode and increasing overall system power

consumption.

When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense

currents are terminated.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is

being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.

After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse

check mode has the potential to be activated.

The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see

Figure 29). Therefore, the additional current flow can be prevented by holding the TMS pin high (default

condition).

Time TMS Goes Low After POR

TMS

I

TF

I

TEST

Figure 29. Fuse Check Mode Current, MSP430F22xx

NOTE

The CODE and RAM data protection is ensured if the JTAG fuse is blown and the

256-bit bootloader access key is used. Also, see the Bootstrap Loader section for

more information.

Submit Documentation Feedback

71

Product Folder Link(s): MSP430F2274-EP

PACKAGE OPTION ADDENDUM

www.ti.com

17-Feb-2010

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

TSSOP

VQFN

Drawing

MSP430F2274MDATEP

MSP430F2274MRHAEP

MSP430F2274MRHATEP

ACTIVE

PREVIEW

ACTIVE

DA

38

40

2000

TBD

Call TI

RHA

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

V62/08631-01XE

ACTIVE

VQFN

RHA

40

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF MSP430F2274-EP :

Catalog: MSP430F2274

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Jan-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

MSP430F2274MRHATEP VQFN

RHA

40

250

180.0

16.4

6.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Jan-2010

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RHA 40

SPQ

Length (mm) Width (mm) Height (mm)

190.5 212.7 31.8

MSP430F2274MRHATEP

250

Pack Materials-Page 2

IMPORTANT NOTICE

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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

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型号：	V62/08631-01YE
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER
文件：	总79页 (文件大小：1362K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

V62/08631-01YE [TI]

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