V62/10610-01XE_技术文档

TLC5940-EP

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SLVSA51D –MARCH 2010–REVISED MAY 2010

16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

Check for Samples: TLC5940-EP

1

FEATURES

APPLICATIONS

•

Monocolor, Multicolor, Full-Color LED Displays

LED Signboards

Display Backlighting

General, High-Current LED Drive

2

•

16 Channels

•

12-Bit (4096 Steps) Grayscale PWM Control

Dot Correction

–

6 Bit (64 Steps)

Storable in Integrated EEPROM

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

•

Drive Capability (Constant-Current Sink) of

0 mA to 72 mA (–40°C to 125°C)

•

Controlled Baseline

One Assembly/Test Site

One Fabrication Site

Available in Q-Temp (–40°C/125°C)

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

–

0 mA to 60 mA (V_CC< 3.6 V, –40°C to 85°C)

0 mA to 120 mA (V_CC> 3.6 V, –40°C to 85°C)

•

LED Power Supply Voltage up to 17 V

V_CC= 3 V to 5.5 V

Serial Data Interface

Controlled In-Rush Current

30-MHz Data Transfer Rate

CMOS Level I/O

Error Information

–

LOD: LED Open Detection

TEF: Thermal Error Flag

DESCRIPTION

The TLC5940 is a 16-channel, constant-current sink LED driver. Each channel has an individually adjustable

4096-step grayscale PWM brightness control and a 64-step, constant-current sink (dot correction). The dot

correction adjusts the brightness variations between LED channels and other LED drivers. The dot correction

data is stored in an integrated EEPROM. Both grayscale control and dot correction are accessible via a serial

interface. A single external resistor sets the maximum current value of all 16 channels.

The TLC5940 features two error information circuits. The LED open detection (LOD) indicates a broken or

disconnected LED at an output terminal. The thermal error flag (TEF) indicates an overtemperature condition.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLC5940-EP

SLVSA51D –MARCH 2010–REVISED MAY 2010

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VCC

GND

SCLK

SIN

XLAT

DCPRG

CNT

12−Bit Grayscale

PWM Control

VPRG

Constant Current

Driver

1

0

OUT0

GS Register

DC Register

V

=1.24 V

REF

IREF

VPRG

0

11

5

Max. OUTn

Current

Delay

x0

0

DCPRG

1

6−Bit Dot

Correction

0

GSCLK

BLANK

GS Counter

CNT

DC EEPROM

VPRG

0

5

LED Open Detection

Input

Shift

Register

CNT

0

96

Status

Information:

LOD,

TED,

DC DATA

Constant Current

Driver

192

12−Bit Grayscale

PWM Control

GS Register

OUT1

12

6

23

DCPRG

1

Delay

x1

96

191

95

96

6−Bit Dot

Correction

DC Register

1

0

11

0

VPRG

DC EEPROM

6

11

LED Open Detection

96

LED Open

Detection

(LOD)

VPRG

CNT

Temperature

Error Flag

(TEF)

Blank

1

0

Input

Shift

Register

Constant Current

Driver

12−Bit Grayscale

PWM Control

GS Register

OUT15

180

191

Delay

x15

DCPRG

1

XERR

6−Bit Dot

Correction

DC Register

90

95

0

191

DC EEPROM

LED Open Detection

90

95

SOUT

VPRG

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

PART NUMBER

TLC5940QPWPREP

TLC5940QRHBREP

28-pin HTSSOP PowerPAD™

32-pin 5mm x 5mm QFN

–40°C to 125°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com.

2

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SLVSA51D –MARCH 2010–REVISED MAY 2010

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

RHB

32 PINS

33.9

30

PWP

28 PINS

35.4

THERMAL METRIC⁽¹⁾

UNIT

q_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-case (bottom) thermal resistance⁽⁴⁾

Junction-to-board thermal resistance⁽⁵⁾

Junction-to-top characterization parameter⁽⁶⁾

Junction-to-board characterization parameter⁽⁷⁾

°C/W

q_JC(TOP)

q_JC(BOTTOM)

q_JB

24.94

5.37

3.9

9.3

15.02

1.297

10.96

Ψ_JT

0.619

9.3

Ψ_JB

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction to case (bottom) thermal resistance is obtained by simulations of this device as configured per MilStd 883 method 1012.1.

(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(6) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-board characterization parameter, Ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining q_JA, using a procedure described in JESD51-2a (sections 6 and 7).

ABSOLUTE MAXIMUM RATINGS.

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

(2)

UNIT

V_I

I_O

V_I

Input voltage range⁽³⁾

Output current (dc)

Input voltage range

VCC

–0.3V to 6V

130mA

V_(BLANK), V_(DCPRG), V_(SCLK), V_(XLAT), V_(SIN), V_(GSCLK), V_(IREF)

–0.3V to V_CC+0.3V

–0.3V to 18V

–0.3V to 24V

25

V_(SOUT), V_(XERR)

V_(OUT0)to V_(OUT15)

V_(VPRG)

V_O

Output voltage range

EEPROM program range

EEPROM write cycles

HBM (JEDEC JESD22-A114, Human Body Model)

CBM (JEDEC JESD22-C101, Charged Device Model)

2kV

ESD rating

500V

T_stg

T_A

Storage temperature range

–55°C to 150°C

–40°C to 125°C

See Thermal Characteristics table

Operating ambient temperature range

Package thermal impedance

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of

overall device life. See www.ti.com/ep_quality for additional information on enhanced plastic packaging.

(3) All voltage values are with respect to network ground terminal.

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1.00E+04

Notes:

1. See datasheet for absolute maximum and minimum recommended operating conditions.

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include

package interconnect life).

3. Enhanced plastic product disclaimer applies.

1.00E+03

1.00E+02

1.00E+01

1.00E+00

Wirebond Voiding

Fail Mode (PWP)

Wirebond Voiding

Fail Mode (RHB)

100

110

120

130

140

150

160

Continuous T_J(°C)

Figure 1. TLC5940-EP Mold Compound Operating Life

4

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SLVSA51D –MARCH 2010–REVISED MAY 2010

RECOMMENDED OPERATING CONDITIONS

MIN NOM

MAX UNIT

DC CHARACTERISTICS

V_CC

V _O

V_IH

Supply Voltage

3

5.5

17

V

Voltage applied to output (OUT0–OUT15)

High-level input voltage

0.8 V_CC

V_CC

GND

0.2

V_CC

V_IL

Low-level input voltage

V

I_OH

I_OL

High-level output current

Low-level output current

V_CC= 5V at SOUT

–1

1

mA

V_CC= 5V at SOUT

–40°C to 125°C

72

I_OLC

Constant output current

OUT0 to OUT15

–40°C to 85°C, V_CC< 3.6 V

–40°C to 85°C, V_CC> 3.6 V

60

mA

120

23

V_(VPRG)

T_A

EEPROM program voltage

20

22

V

Operating free-air temperature range

-40

125

°C

AC CHARACTERISTICS

V_CC= 3 V to 5.5 V, T_A= –40°C to 125°C (unless otherwise noted)

f_(SCLK)

f_(GSCLK)

t_wh0/t_wl0

t_wh1/t_wl1

t_wh2

t_wh3

t_su0

Data shift clock frequency

SCLK

30 MHz

Grayscale clock frequency GSCLK

30 MHz

ns

SCLK pulse duration

GSCLK pulse duration

XLAT pulse duration

BLANK pulse duration

SCLK = H/L (see Figure 12)

16

20

5

GSCLK = H/L (see Figure 12)

XLAT = H (see Figure 12)

BLANK = H (see Figure 12)

ns

SIN to SCLK ↑⁽¹⁾(see Figure 12)

ns

t_su1

SCLK ↓ to XLAT ↑ (see Figure 12)

VPRG ↑ ↓ to SCLK ↑ (see Figure 12)

VPRG ↑ ↓XLAT ↑ (see Figure 12)

BLANK ↓ to GSCLK ↑ (see Figure 12)

XLAT ↑ to GSCLK ↑ (see Figure 12)

VPRG ↑ to DCPRG ↑ (see Figure 17)

SCLK ↑ to SIN (see Figure 12)

10

30

1

ns

t_su2

ns

t_su3

Setup time

ns

t_su4

ns

t_su5

ns

t_su6

ms

ns

t_h0

3

t_h1

XLAT ↓ to SCLK ↑ (see Figure 12)

SCLK ↑ to VPRG ↑ ↓ (see Figure 12)

XLAT ↓ to VPRG ↑ ↓ (see Figure 12)

GSCLK ↑ to BLANK ↑ (see Figure 12)

DCPRG ↓ to VPRG ↓ (see Figure 12)

Programming time for EEPROM (see Figure 17)

10

1

ns

t_h2

ns

Hold Time

t_h3

ns

t_h4

ns

t_h5

ms

t_prog

20

(1) ↑ and ↓ indicates a rising edge, and a falling edge respectively.

DISSIPATION RATINGS

POWER RATING DERATING FACTOR POWER RATING POWER RATING

POWER RATING

T_A= 125°C

PACKAGE

T_A< 25°C

3958mW

2026mW

ABOVE T_A= 25°C

T_A= 70°C

2533mW

1296mW

T_A= 85°C

2058mW

1053mW

28-pin HTSSOP with

31.67mW/°C

791mW

405mW

PowerPAD™ soldered⁽¹⁾

28-pin HTSSOP with

16.21mW/°C

PowerPAD™ unsoldered

32-pin QFN(1)

3482mW

27.86mW/°C

2228mW

1811mW

696mW

(1) The PowerPAD is soldered to the PCB with a 2 oz. (56,7 grams) copper trace. See SLMA002 for further information.

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ELECTRICAL CHARACTERISTICS

V_CC= 3 V to 5.5 V, T_A= –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OH

V_OL

High-level output voltage

Low-level output voltage

I_OH= -1mA, SOUT

I_OL= 1mA, SOUT

V_CC–0.5

V

0.5

1

V

V_I= V_CCor GND; BLANK, DCPRG, GSCLK, SCLK, SIN,

XLAT

–1

–2

mA

V_I= GND; VPRG

2

50

10

I_I

Input current

V_I= V_CC; VPRG

V_I= 21V; VPRG; DCPRG = V_CC

4

No data transfer, all output OFF,

V_O= 1V, R_(IREF)= 10kΩ

0.9

6

No data transfer, all output OFF,

V_O= 1V, R_(IREF)= 1.3kΩ

5.2

16

30

12

I_CC

Supply current

mA

Data transfer 30MHz, all output ON,

V_O= 1V, R_(IREF)= 1.3kΩ

Data transfer 30MHz, all output ON,

V_O= 1V, R_(IREF)= 640Ω

All output ON, V_O= 1V, R_(IREF)= 640Ω, 25°C

54

42

61

69

72

Constant sink current (see

Figure 3)

I_O(LC)

I_lkg

mA

All output ON, V_O= 1V, R_(IREF)= 640Ω, Full temperature

All output OFF, V_O= 15V, R_(IREF)= 640Ω,

OUT0 to OUT15

Leakage output current

±1

±4

mA

All output ON, V_O= 1V, R_(IREF)= 640Ω,

OUT0 to OUT15, 25°C

All output ON, V_O= 1V, R_(IREF)= 640Ω,

±12

±4

OUT0 to OUT15⁽¹⁾, Full temperature

Constant sink current error

(see Figure 3)

ΔI_O(LC0)

%

All output ON, V_O= 1V, R_(IREF)= 1300Ω,

OUT0 to OUT15, 25°C

All output ON, V_O= 1V, R_(IREF)= 1300Ω,

OUT0 to OUT15⁽¹⁾, Full temperature

±8

–2

+0.4

Constant sink current error

(see Figure 3)

Device to device, Averaged current from OUT0 to

ΔI_O(LC1)

ΔI_O(LC2)

%

OUT15, R_(IREF)= 1920Ω (20mA)⁽²⁾

–2.7

+2

Constant sink current error

(see Figure 3)

Device to device, Averaged current from OUT0 to

OUT15, R_(IREF)= 480Ω (80mA)⁽²⁾

All output ON, V_O= 1V, R_(IREF)= 640Ω

OUT0 to OUT15⁽³⁾, 25°C

±4

All output ON, V_O= 1V, R_(IREF)= 640Ω

±11

±4

OUT0 to OUT15⁽³⁾, Full temperature

ΔI_O(LC3)Line regulation (see Figure 3)

%/V

All output ON, V_O= 1V, R_(IREF)= 1300Ω ,

OUT0 to OUT15⁽³⁾, 25°C

All output ON, V_O= 1V, R_(IREF)= 1300Ω ,

±4

OUT0 to OUT15⁽³⁾, Full temperature

All output ON, V_O= 1V to 3V, R_(IREF)= 640Ω,

OUT0 to OUT15⁽⁴⁾, 25°C

±6

All output ON, V_O= 1V to 3V, R_(IREF)= 640Ω,

±20

±6

OUT0 to OUT15⁽⁴⁾, Full temperature

ΔI_O(LC4)Load regulation (see Figure 3)

%/V

All output ON, V_O= 1V to 3V, R_(IREF)= 1300Ω,

OUT0 to OUT15⁽⁴⁾, 25°C

All output ON, V_O= 1V to 3V, R_(IREF)= 1300Ω,

±6

OUT0 to OUT15⁽⁴⁾, Full temperature

(1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1.

(2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1.

The ideal current is calculated by Equation 3 in Table 1.

(3) The line regulation is calculated by Equation 4 in Table 1.

(4) The load regulation is calculated by Equation 5 in Table 1.

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SLVSA51D –MARCH 2010–REVISED MAY 2010

ELECTRICAL CHARACTERISTICS (continued)

V_CC= 3 V to 5.5 V, T_A= –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Junction temperature⁽⁵⁾

MIN

TYP

MAX UNIT

T_(TEF)

V_(LED)

Thermal error flag threshold

LED open detection threshold

150

170

0.4

°C

V

0.3

Reference voltage

output

V_(IREF)

R_(IREF)= 640Ω

1.20

1.24

1.28

V

(5) Not tested. Specified by design

Table 1. Test Parameter Equations

I_OUTn- I_{OUTavg _ 0-15}

´100

D(%) =

I_{OUTavg _ 0-15}

(1)

I_OUTavg- I_OUT(IDEAL)

D(%) =

´100

I_OUT(IDEAL)

(2)

æ

ç

ö

÷

1.24V

R_IREF

I_OUT(IDEAL)= 31.5 ´

è

ø

(3)

(4)

(5)

(I_OUTnat V_CC= 5.5V) - (I_OUTnat V_CC= 3.0V)

(I_OUTnat V_CC= 3.0V)

100

2.5

D(% / V) =

D(%/ V) =

´

(I_OUTnat V_OUTn= 3.0V) - (I_OUTnat V_OUTn= 1.0V)

(I_OUTnat V_OUTn= 1.0V)

100

´

2.0

SWITCHING CHARACTERISTICS

V_CC= 3V to 5.5V, T_A= -40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_r0

SOUT

16

ns

30

Rise time

t_r1

OUTn, V_CC= 5V, T_A= 60°C, DCn = 3Fh

SOUT

10

t_f0

16

ns

30

Fall time

t_f1

OUTn, V_CC= 5V, T_A= 60°C, DCn = 3Fh

SCLK to SOUT (see Figure 12)

BLANK to OUT0

t_pd0

t_pd1

t_pd2

t_pd3

t_pd4

t_pd5

t_d

30

60

ns

OUTn to XERR (see Figure 12 )

GSCLK to OUT0 (see Figure 12 )

XLAT to I_OUT(dot correction) (see Figure 12 )

DCPRG to OUT0 (see Figure 12)

OUTn to OUT(n+1) (see Figure 12 )

1000

60

Propagation delay time

60

30

Output delay time

20

30

t_on-err

Output on-time error

t_outon– T_gsclk(see Figure 12), GSn = 01h, GSCLK = 11 MHz

10

–50

–90

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DEVICE INFORMATION

PWP PACKAGE

(TOP VIEW)

RHB PACKAGE

(TOP VIEW)

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GND

VCC

BLANK

XLAT

SCLK

SIN

2

IREF

3

DCPRG

GSCLK

SOUT

4

5

25

16 OUT10

DCPRG

VPRG

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

XERR

OUT15

OUT14

OUT13

OUT12

OUT11

OUT10

OUT9

6

Thermal

PAD

IREF 26

VCC 27

NC 28

15 OUT9

14 OUT8

13 NC

7

8

THERMAL

PAD

9

10

11

12

13

14

NC 29

12 NC

GND 30

11 OUT7

10 OUT6

31

BLANK

XLAT 32

9

OUT5

OUT8

8

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SLVSA51D –MARCH 2010–REVISED MAY 2010

TERMINAL FUNCTION

TERMINAL

NO.

RHB

I/O

DESCRIPTION

NAME

PWP

Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also reset.

When BLANK = L, OUTn are controlled by grayscale PWM control.

BLANK

2

31

I

Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H, DC is

connected to the DC register.

DCPRG

26

25

DCPRG also controls EEPROM writing, when VPRG = V_(PRG). EEPROM data = 3Fh (default)

GND

1

30

24

26

G

I

Ground

GSCLK

IREF

25

27

Reference clock for grayscale PWM control

Reference current terminal

I

12, 13,

28, 29

NC

–

No connection

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

SCLK

SIN

7

4

5

O

I

Constant current output

Serial data shift clock

Serial data input

8

9

6

10

11

12

13

14

15

16

17

18

19

20

21

22

4

7

8

9

10

11

14

15

16

17

18

19

20

21

1

5

2

I

SOUT

VCC

24

28

23

27

O

I

Serial data output

Power supply voltage

Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = V_CC, the

device is in DC mode. When VPRG = V_(VPRG), DC register data can programmed into DC EEPROM

with DCPRG=HIGH. EEPROM data = 3Fh (default)

VPRG

XERR

XLAT

6

23

3

I

O

I

22

32

Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.

Level triggered latch signal. When XLAT = high, the TLC5940 writes data from the input shift register

to either GS register (VPRG = low) or DC register (VPRG = high). When XLAT = low, the data in GS

or DC register is held constant.

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PARAMETER MEASUREMENT INFORMATION

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

Resistor values are equivalent resistances, and they are not tested.

INPUT EQUIVALENT CIRCUIT

OUTPUT EQUIVALENT CIRCUIT (SOUT)

VCC

(BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG)

VCC

23 W

400 W

INPUT

SOUT

GND

INPUT EQUIVALENT CIRCUIT (IREF)

V_(IREF)

OUTPUT EQUIVALENT CIRCUIT (XERR)

VCC

23 W

Amp

_

XERR

400 W

+

INPUT

100 W

GND

INPUT EQUIVALENT CIRCUIT (VCC)

INPUT

OUTPUT EQUIVALENT CIRCUIT (OUT)

OUT

GND

INPUT EQUIVALENT CIRCUIT (VPRG)

INPUT

GND

Figure 2. Input and Output Equivalent Circuits

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PARAMETER MEASUREMENT INFORMATION (continued)

t

, t , t

t

, t , t

, t

d

r0 f0 pd0

r1 f1 pd1 pd2 pd3 pd4 pd5

V_O= 4V

Testpoint

SOUT

R

= 51W

L

C

= 15pF

L

Testpoint

= 15pF

OUTn

C

L

I

, DI

O(LC3)

DI

O(LC)

O(LC0)

O(LC1)

O(LC2)

O(LC4)

OUTn

V

= 1V

O

V

= 1V to 3V

O

V

t

(IREF)

pd3

V

Testpoint

= 640W

IREF

CC

R

(IREG)

470kΩ

XERR

Figure 3. Parameter Measurement Circuits

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TYPICAL CHARACTERISTICS

REFERENCE RESISTOR

POWER DISSIPATION RATE

vs

OUTPUT CURRENT

FREE-AIR TEMPERATURE

4 k

10 k

TLC5940PWP

PowerPAD Soldered

7.68 kΩ

TLC5940RHB

3 k

2 k

1.92 kΩ

0.96 kΩ

1 k

0.64 kΩ

TLC5940PWP

PowerPAD Unsoldered

0.48 kΩ

0.38 kΩ

1 k

0.32 kΩ

100

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

− Free-Air Temperature − ^oC

I

− Output Current − mA

O

T

A

Figure 4.

Figure 5.

OUTPUT CURRENT

vs

OUTPUT CURRENT

vs

OUTPUT VOLTAGE

65

64

140

T

= 25°C,

I

= 60 mA,

V = 5 V

CC

I

= 120 mA

= 100 mA

= 80 mA

A

O

V

= 5 V

CC

120

100

T

= 85°C

A

63

62

61

60

I

O

I

O

80

60

T

= 25°C

I

= 60 mA

= 40 mA

A

O

T

= -40°C

A

59

58

I

O

40

20

0

I

= 20 mA

= 5 mA

57

56

55

O

0

0.5

1

1.5

2

2.5

3

0

0.5

1

1.5

2

- Output Voltage - V

2.5

3

V

- Output Voltage - V

O

Figure 6.

Figure 7.

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TYPICAL CHARACTERISTICS (continued)

CONSTANT OUTPUT CURRENT, ΔI_OLC

vs

AMBIENT TEMPERATURE

OUTPUT CURRENT

8

6

8

6

T

= 25°C,

I

= 60 mA

A

O

V

= 5 V

CC

4

2

0

4

2

V

= 3.3 V

CC

0

-2

-4

-6

-8

-2

-4

V

= 5 V

CC

-6

-8

0

20

40

- Output Current - mA

60

80

-40

-20

0

20

40

60

80

100

I

T

- Ambient Temperature - °C

O

A

Figure 8.

Figure 9.

OUTPUT CURRENT

vs

OUTPUT CURRENT

vs

DOT CORRECTION LINEARITY (ABS VALUE)

140

120

70

60

T

= 25°C,

I

= 60 mA,

= 5 V

A

I = 120 mA

O

T

= 25°C

A

V

= 5 V

V

CC

T

= 85°C

A

100

80

50

I

= 80 mA

O

T

= -40°C

40

30

A

I

= 60 mA

O

60

40

20

I

= 30 mA

= 5 mA

O

20

0

10

0

I

O

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

Dot Correction Data - dec

Figure 10.

Figure 11.

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PRINCIPLES OF OPERATION

SERIAL INTERFACE

The TLC5940 has a flexible serial interface, which can be connected to microcontrollers or digital signal

processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal

shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT

signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT

signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the

programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although

new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale

data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing

grayscale data. Figure 12 shows the timing chart. More than two TLC5940s can be connected in series by

connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two

TLC5940s is shown in Figure 13 and the timing chart is shown in Figure 14. The SOUT pin can also be

connected to the controller to receive status information from TLC5940 as shown in Figure 23.

VPRG

DC Data Input Mode

GS Data Input Mode

t

h3

su3

t

wh2

XLAT

1st GS Data Input Cycle

2nd GS Data Input Cycle

DC

MSB

DC

LSB

GS1

MSB

GS1

GS2

MSB

GS2

LSB

GS3

MSB

SIN

LSB

su1

192

t

su2

su0

h1

t

h2

t

wh0

h0

193

1

192

96

1

193

1

t

SCLK

SOUT

BLANK

GSCLK

t

pd0

wl0

SID2

MSB-1

GS1

MSB

SID1

MSB MSB-1

SID2

MSB

DC

-

MSB

GS2

MSB

SID1

LSB

-

t

wh3

1st GS Data Output Cycle

2nd GS Data Output Cycle

t

wh1

su4

h4

t

su5

1

4096

1

t

pd3

wl1

T

t

gsclk

pd4

pd1

t

pd3

OUT0

(current)

t

+ t

t

outon

d

pd3

d

t

pd1

+ t

d

OUT1

(current)

15 x t

d

t

+ 15 x t

pd1

d

OUT15

(current)

t

pd2

XERR

Figure 12. Serial Data Input Timing Chart

SIN(a)

SIN

SOUT(b)

SOUT

TLC5940 (a)

TLC5940 (b)

SCLK, XLAT,

BLANK,

GSCLK,

DCPRG,

VPRG

Figure 13. Cascading Two TLC5940 Devices

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VPRG

XLAT

SIN(a)

SCLK

DCb

MSB

DCa

LSB

GSb1

MSB

GSa1

LSB

GSb2

MSB

GSa2

LSB

GSb3

MSB

385

1

384

192

1

385

1

96X2

192X2

SIDb2

MSB-1

GSb1

MSB

SIDb1

MSB-1

SIDb2

MSB

DCb

MSB

GSb2

MSB

SIDa1

LSB

SIDb1

MSB

-

SOUT(b)

BLANK

1

4096

1

GSCLK

OUT0

(current)

OUT1

(current)

OUT15

(current)

XERR

Figure 14. Timing Chart for Two Cascaded TLC5940 Devices

ERROR INFORMATION OUTPUT

The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal

operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is

pulled up to V_CCthrough an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned

on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and

pulled up to V_CCwith a single pullup resistor. This reduces the number of signals needed to report a system error

(see Figure 23).

To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.

Table 2. XERR Truth Table

ERROR CONDITION

TEMPERATURE

ERROR INFORMATION

SIGNALS

OUTn VOLTAGE

Don't Care

TEF

L

LOD

X

BLANK

XERR

T_J< T_(TEF)

T_J> T_(TEF)

H

L

H

L

H

Don't Care

H

X

OUTn > V_(LED)

OUTn < V_(LED)

OUTn > V_(LED)

OUTn < V_(LED)

L

T_J< T_(TEF)

L

H

L

H

L

T_J> T_(TEF)

H

TEF: THERMAL ERROR FLAG

The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If

the junction temperature exceeds the threshold temperature (160°C typical), TEF becomes H and XERR pin

goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes

L and XERR pin becomes high impedance. TEF status can also be read out from the TLC5940 status register.

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LOD: LED OPEN DETECTION

The TLC5940 has an LED-open detector that detects broken or disconnected LEDs. The LED open detector

pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the Status

Information Data is only active under the following open-LED conditions.

1. OUTn is on and the time tpd2 (1 ms typical) has passed.

2. The voltage of OUTn is < 0.3V (typical)

The LOD status of each output can be also read out from the SOUT pin. See STATUS INFORMATION OUTPUT

section for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low

after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch the

LOD error into the Status Information Data for subsequent reading via the serial shift register.

DELAY BETWEEN OUTPUTS

The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current

driver block of the device (see the functional block diagram). The fixed-delay time is 20ns (typical), OUT0 has no

delay, OUT1 has 20ns delay, and OUT2 has 40ns delay, etc. The maximum delay is 300ns from OUT0 to

OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large

inrush currents which reduces the bypass capacitors when the outputs turn on.

OUTPUT ENABLE

All OUTn channels of the TLC5940 can be switched off with one signal. When BLANK is set high, all OUTn

channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When

BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high

again in less than 300ns, all outputs programmed to turn on still turn on for either the programmed number of

grayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if all

outputs are programmed to turn on for 1ms, but the BLANK signal is only low for 200ns, all outputs still turn on

for 200ns, even though some outputs are turning on after the BLANK signal has already gone high.

Table 3. BLANK Signal Truth Table

BLANK

LOW

OUT0 - OUT15

Normal condition

Disabled

HIGH

SETTING MAXIMUM CHANNEL CURRENT

The maximum output current per channel is programmed by a single resistor, R_(IREF), which is placed between

IREF pin and GND pin. The voltage on IREF is set by an internal band gap V_(IREF)with a typical value of

1.24V. The maximum channel current is equivalent to the current flowing through R_(IREF)multiplied by a factor of

31.5. The maximum output current per channel can be calculated by Equation 6:

V

(IREF)

I

+

31.5

max

R

(IREF)

(6)

where:

V_(IREF)= 1.24 V

R_(IREF)= User-selected external resistor.

I_maxmust be set between 5 mA and 120 mA. The output current may be unstable if I_maxis set lower than 5 mA.

Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dot

correction.

Figure 4 shows the maximum output current I_Oversus R_(IREF). R_(IREF)is the value of the resistor between IREF

terminal to GND, and I_Ois the constant output current of OUT0 to OUT15. A variable power supply may be

connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum

output current per channel is 31.5 times the current flowing out of the IREF pin.

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POWER DISSIPATION CALCULATION

The device power dissipation must be below the power dissipation rating of the device package to ensure correct

operation. Equation 7 calculates the power dissipation of device:

DC

n

x d

PWM

x N

P

= V

(

x I

CC

+

V

OUT

x I x

MAX

(

)

D

CC

63

(7)

where:

V_CC: device supply voltage

I_CC: device supply current

V_OUT: TLC5940 OUTn voltage when driving LED current

I_MAX: LED current adjusted by R_(IREF)Resistor

DC_n: maximum dot correction value for OUTn

N: number of OUTn driving LED at the same time

d_PWM: duty cycle defined by BLANK pin or GS PWM value

OPERATING MODES

The TLC5940 has operating modes depending on the signals DCPRG and VPRG. Table 4 shows the available

operating modes. The TPS5940 GS operating mode (see Figure 12) and shift register values are not defined

after power up. One solution to solve this is to set dot correction data after TLS5940 power-up and switch back

to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch

it while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register are

unknown just after power on. The DC and GS register values should be properly stored through the serial

interface before starting the operation.

Table 4. TLC5940 Operating Modes Truth Table

SIGNAL

INPUT SHIFT REGISTER

MODE

DC VALUE

DCPRG

VPRG

L

H

L

EEPROM

DC Register

EEPROM

GND

192 bit

96 bit

Grayscale PWM Mode

Dot Correction Data Input Mode

V_CC

H

L

DC Register

EEPROM

V_(VPRG)

X

EEPROM Programming Mode

H

Write dc register value to EEPROM. (Default

data: 3Fh)

SETTING DOT CORRECTION

The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently.

This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to

the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The

channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current I_max. Dot correction

for all channels must be entered at the same time. Equation 8 determines the output current for each output n:

DCn

63

I

+ I

max

OUTn

(8)

where:

I_max= the maximum programmable output current for each output.

DCn = the programmed dot correction value for output n (DCn = 0 to 63).

n = 0 to 15

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Figure 15 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The

format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC

15.5 in Figure 15 stands for the 5^thmost significant bit for output 15.

MSB

95

LSB

0

90

89

6

5

DC 15.5

DC 15.0 DC 14.5

DC 1.0

DC 0.5

DC 0.0

DC OUT15

DC OUT0

DC OUT14 − DC OUT2

Figure 15. Dot Correction Data Packet Format

When VPRG is set to VCC, the TLC5940 enters the dot correction data input mode. The length of input shift

register becomes 96 bits. After all serial data are shifted in, the TLC5940 writes the data in the input shift register

to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a

level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed

while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal

does not need to be high to latch in new data. XLAT has setup time (tsu1) and hold time (th1) to SCLK as shown

in Figure 16.

DC Mode Data

Input Cycle n

Input Cycle n+1

V

CC

VPRG

SIN

DC n

MSB

DC n

MSB−1

DC n

MSB−2

DC n

LSB+1

DC n

LSB

DC n+1

MSB

DC n+1

MSB−1

DC n−1

LSB

t

wh0

SCLK

1

2

3

95

96

1

2

t

wl0

DC n−1

MSB

DC n−1

MSB−1

DC n−1

MSB−2

DC n−1

LSB+1

DC n−1

LSB

DC n

MSB

DC n

MSB−1

DC n

MSB−2

SOUT

XLAT

t

wh2

t

su1

t

h1

Figure 16. Dot Correction Data Input Timing Chart

The TLC5940 also has an EEPROM to store dot correction data. To store data from the dot correction register to

EEPROM, DCPRG is set to high after applying V_PRGto the VPRG pin. Figure 17 shows the EEPROM

programming timings. The EEPROM has a default value of all 1s.

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V(PRG)

VPRG

DCPRG

XLAT

VCC

t

h5

su6

prog

DC

MSB

DC

LSB

SIN

96

1

SCLK

SOUT

DC

MSB

-

Figure 17. EEPROM Programming Timing Chart

DCPRG

t

pd5

OUT0

(Current)

OUT15

(Current)

Figure 18. DCPRG and OUTn Timing Diagram

SETTING GRAYSCALE

The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits

per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 9 determines

the brightness level for each output n:

GSn

4095

Brightness in % +

100

(9)

where:

GSn = the programmed grayscale value for output n (GSn = 0 to 4095)

n = 0 to 15

Grayscale data for all OUTn

Figure 19 shows the grayscale data packet format which consists of 12 bits x 16 channels, totaling 192 bits. The

format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc.

MSB

191

LSB

0

180

GS 15.0 GS 14.11

179

12

11

GS 0.11

GS 15.11

GS 1.0

GS 0.0

GS OUT15

GS OUT14 − GS OUT2

GS OUT0

Figure 19. Grayscale Data Packet Format

When VPRG is set to GND, the TLC5940 enters the grayscale data input mode. The device switches the input

shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into

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the grayscale register (see Figure 12). New grayscale data immediately becomes valid at the rising edge of the

XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is

high.The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to

complete the grayscale update cycle. All GS data in the input shift register is replaced with status information

data (SID) after updated the grayscale register.

STATUS INFORMATION OUTPUT

The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG=GND).

After the XLAT signal latches the data into the GS register the input shift register data will be replaced with status

information data (SID) of the device (see Figure 19). LOD, TEF, and dot correction EEPROM data

(DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at SOUT pin. The status

information data packet is 192 bits wide. Bits 0-15 contain the LOD status of each channel. Bit 16 contains the

TEF status. If DCPRG is low, bits 24-119 contain the data of the dot-correction EEPROM. If DCPRG is high, bits

24-119 contain the data of the dot-correction register.The remaining bits are reserved. The complete status

information data packet is shown in Figure 20.

SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown Figure 21.

The next SCLK pulse, which will be the clock for receiving the SMB of the next grayscale data, transmits MSB-1

of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status flage becomes

active. The LOD status flag is an internal signal that pulls XERR pin down to low when the LOD status flag

becomes active. The delay time, tpd2 (1 ms maximum), is from the time of turning on the output sink current to

the time LOD status flage becomes valid. The timing for each channel's LOD status to become valid is shifted by

the 30-ns (maximum) channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD status is

valid; tpd3 + tpd2 = 60 ns + 1 ms. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 ms = 1.09 ms.

OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 ms, and so on. It takes 1.51 ms maximum (tpd3 + 15*td +

tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be > 1.51 ms (see Figure 21) to

ensure that all LOD data are valid.

LSB

191

MSB

0

23

X

15

24

119

120

X

16

X

LOD 15

LOD 0

TEF

DC 15.5

DC 0.0

DC Values

Reserved

LOD Data

TEF

Figure 20. Status Information Data Packet Format

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VPRG

XLAT

GS Data Input Mode

1st GS Data Input Cycle

2nd GS Data Input Cycle

GS1

MSB

GS1

LSB

GS2

MSB

GS2

LSB

SIN

> tpd4 + 15 x td + tpd3

t

suLOD

1

192

193

1

SCLK

SOUT

BLANK

GSCLK

GS1

MSB

SID1

MSB-1

GS2

MSB

SID1

LSB

SID1

MSB

-

(1st GS Data Output Cycle)

4096

1

t

pd3

OUT0

(current)

t

d

OUT1

(current)

15 x t

d

OUT15

(current)

t

pd2

XERR

t

pd3

+ 15 x t + t

d

pd2

Figure 21. Readout Status Information Data (SID) Timing Chart

GRAYSCALE PWM OPERATION

The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low

increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following

rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of

each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values

are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and

completes the grayscale PWM cycle (see Figure 22). When the counter reaches a count of FFFh, the counter

stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets

the counter to zero.

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GS PWM

Cycle n

GS PWM

Cycle n+1

BLANK

GSCLK

t

wl1

t

su4

t

wh1

t

h4

wh3

4096

1

2

3

1

t

wl1

t

pd3

pd1

pd3

OUT0

(Current)

n x t

d

t

+ n x t

pd3 d

t

+ t

d

pd1

OUT1

(Current)

t

OUT15

(Current)

+ 15 x t

d

pd1

t

pd2

XERR

Figure 22. Grayscale PWM Cycle Timing Chart

SERIAL DATA TRANSFER RATE

Figure 23 shows a cascading connection of n TLC5940 devices connected to a controller, building a basic

module of an LED display system. The maximum number of cascading TLC5940 devices depends on the

application system and is in the range of 40 devices. Equation 10 calculates the minimum frequency needed:

f

+ 4096 f

(GSCLK)

+ 193 f

(update)

n

f

(SCLK)

(update)

(10)

where:

f_(GSCLK): minimum frequency needed for GSCLK

f_(SCLK): minimum frequency needed for SCLK and SIN

f_(update): update rate of whole cascading system

n: number cascaded of TLC5940 device

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APPLICATION EXAMPLE

V

(LED)

CC

(LED)

100 k

OUT0

OUT15

SOUT

OUT0

OUT15

SOUT

SIN

XERR

SCLK

SIN

XERR

SCLK

XERR

SCLK

XLAT

V

CC

100 nF

XLAT

TLC5940

IC 0

TLC5940

IC n

GSCLK

DCPRG

BLANK

SOUT

GSCLK

DCPRG

BLANK

VPRG

GSCLK

DCPRG

BLANK

VPRG

IREF

Controller

W_EEPROM

VPRG_D

7

VPRG_OE

V

(22V)

50 k

VPRG

Figure 23. Cascading Devices

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Product Folder Link(s): TLC5940-EP

PACKAGE OPTION ADDENDUM

www.ti.com

10-May-2010

PACKAGING INFORMATION

Orderable Device

TLC5940QPWPREP

TLC5940QRHBREP

V62/10610-01XE

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

28

32

28

32

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

HTSSOP

QFN

RHB

PWP

RHB

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

V62/10610-01YE

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC5940-EP :

Catalog: TLC5940

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLC5940QRHBREP

QFN

RHB

32

3000

330.0

12.4

5.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFN RHB 32

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 35.0

TLC5940QRHBREP

3000

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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components to meet such requirements.

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Applications

www.ti.com/audio

amplifier.ti.com

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www.dlp.com

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Data Converters

DLP® Products

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Computers and Peripherals

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www.ti.com/computers

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www.ti.com/energy

dsp.ti.com

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Interface

www.ti.com/clocks

interface.ti.com

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www.ti.com/industrial

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www.ti.com/security

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RFID

power.ti.com

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microcontroller.ti.com

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Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	V62/10610-01XE
厂家：	TEXAS INSTRUMENTS
描述：	16-CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL 16通道LED驱动器，具有点校正和灰度PWM控制显示驱动器驱动程序和接口接口集成电路光电二极管
文件：	总33页 (文件大小：1164K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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