V62/12667-01XE [TI]
增强型产品 16 位双电源总线收发器 | DGG | 48 | -55 to 125;
| 型号： | V62/12667-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品 16 位双电源总线收发器 | DGG | 48 | -55 to 125 光电二极管 逻辑集成电路 总线收发器 |
| 文件： | 总21页 (文件大小：1256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC16T245-EP
www.ti.com.cn
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
16 位双电源总线收发器
此收发器具有可配置电压转换和三态输出
查询样品: SN74LVC16T245-EP
1
特性
DGG 封装
(顶视图)
•
•
控制输入 VIH和 VIL电平以 VCCA电压为基准
CC隔离特性-如果任何一个 VCC输入接地 (GND)，
那么两个端口都处于高阻抗状态
V
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
VCCA
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCCA
2A5
2A6
GND
2A7
2A8
2OE
2
•
•
过压耐受输入和输出可实现混合电压模式数据通信
3
完全可配置双电源轨设计可使每个端口在整个
1.65V-5.5V 电源电压范围内运行
4
5
•
•
I关闭 支持部分断电模式工作
6
锁断性能超过 100mA（符合 JESD 78，II 类规范
的要求）
7
V
CCB
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCCB
2B5
2B6
GND
2B7
2B8
2DIR
•
静电放电 (ESD) 保护性能超过 JESD 22 规范要求
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
–
–
–
2000V 人体模型 (A114-A)
200V 机器模型 (A115-A)
1000V 充电器件模型 (C101)
支持国防、航空航天、和医疗应用
•
•
•
•
•
•
•
受控基线
一个组装和测试场所
一个制造场所
(1)
军用（-55°C 至 125°C）温度范围内可用
延长的产品生命周期
延长的产品变更通知
产品可追溯性
(1) 可定制工作温度范围
说明
这个 16 位非反相总线收发器使用两个独立的可配置电源轨。 A 端口被设计用于跟踪 VCCA。 VCCA可接受从 1.65V
到 5.5V 范围内的任意电源电压。B 端口被设计用于跟踪 VCCB。 VCCB可接受从 1.65 至 5.5V 间的任一电源电压
值。这可实现 1.8V，2.5V，3.3V和 5V 电压节点间的通用低压双向转换。
说明（继续）
SN74LVC16T245 针对两条数据总线间的异步通信而设计。 方向控制 (DIR) 输入和输出使能 (OE) 输入的逻辑电平
激活 B 端口输出或者 A 端口输出，或者将两个输出端口都置于高阻抗模式。 当 B 端口输出被激活时，此器件将数
据从 A 总线发送到 B 总线，而当 A 端口输出被激活时，此器件将数据从 B 总线发送到 A 总线。 A 端口和 B 端口
上的输入电路一直处于激活状态并且必须施加一个逻辑高或低电平以防止过多的 ICC和 ICCZ
。
SN74LVC16T245 的设计方式决定了控制引脚（1DIR，2DIR，1OE和2OE）由 VCCA供电。
该器件完全符合使用 I关闭的部分断电应用的规范要求。 I关闭电路禁用输出，从而可防止其断电时破坏性电流从该器
件回流。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
English Data Sheet: SCES843
SN74LVC16T245-EP
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
VCC隔离特性可确保 VCC中的任何一个是否接地，然后两个端口都处于高阻抗状态。
为了确保加电或断电期间的高阻抗状态，OE应通过一个上拉电阻器被连接至 VCC；该电阻器的最小值由驱动器的
电流吸收能力来决定。
Table 1. ORDERING INFORMATION(1)
ORDERABLE PART
TA
PACKAGE
TOP-SIDE MARKING
VID NUMBER
NUMBER
Reel of 2000
Tube of 40
CLVC16T245MDGGREP
CLVC16T245MDGGEP
V62/12667-01XE
–55°C to 125°C
TSSOP-DGG
LVC16T245M
V62/12667-01XE-T
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
FUNCTION TABLE(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS
OUTPUT CIRCUITS
OPERATION
OE
L
DIR
L
A PORT
Enabled
Hi-Z
B PORT
Hi-Z
B data to A bus
A data to B bus
Isolation
L
H
Enabled
Hi-Z
H
X
Hi-Z
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
1A1
48
25
13
1OE
2OE
2B1
36
47
2A1
2
1B1
To Seven Other Channels
To Seven Other Channels
2
Copyright © 2013, Texas Instruments Incorporated
SN74LVC16T245-EP
www.ti.com.cn
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
VCCB
–0.5
6.5
V
I/O ports (A port)
I/O ports (B port)
Control inputs
A port
–0.5
–0.5
–0.5
–0.5
–0.5
6.5
6.5
6.5
6.5
6.5
VI
Input voltage range(2)
V
Voltage range applied to any output
VO
VO
V
V
in the high-impedance or power-off state(2)
B port
A port
–0.5 VCCA + 0.5
Voltage range applied to any output in the high or low state(2) (3)
B port
–0.5 VCCB + 0.5
IIK
IOK
IO
Input clamp current
VI < 0
–50
–50
mA
mA
mA
mA
°C
Output clamp current
VO < 0
Continuous output current
±50
Continuous current through each VCCA, VCCB, and GND
Maximum junction temperature
Storage temperature range
±100
150
TJ
Tstg
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
THERMAL INFORMATION
SN74LVC16T245
THERMAL METRIC(1)
DGG
48 PINS
59.9
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
13.9
27.1
°C/W
ψJT
0.5
ψJB
26.8
θJCbot
N/A
(1) 有关传统和新的热 度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然 对流条件下的结至环
境热阻。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但 可在 ANSI SEMI 标准 G30-
88 中能找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过 在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。
(5) 结至顶部特征参数， ψJT，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该参
数以便获得 θJA
(6) 结至电路板特征参数， ψJB，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中 描述的程序从仿真数据中 提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得 结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准 测试，但可在 ANSI SEMI
标准 G30-88 中能找到内容接近的说明。
空白
Copyright © 2013, Texas Instruments Incorporated
3
SN74LVC16T245-EP
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
MAX UNIT
Recommended Operating Conditions(1)(2)(3)(4)
VCCI
VCCO
MIN
1.65
VCCA
5.5
V
Supply voltage
VCCB
1.65
5.5
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCI × 0.65
1.7
High-level
input voltage
VIH
VIL
VIH
VIL
Data inputs(5)
Data inputs(5)
V
2
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCI × 0.7
VCCI × 0.35
0.7
0.8
Low-level
input voltage
V
V
V
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCI × 0.3
VCCA × 0.65
1.7
2
High-level
input voltage
Control inputs
(referenced to VCCA
(6)
(6)
)
)
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VCCA × 0.7
VCCA × 0.35
0.7
Low-level
input voltage
Control inputs
(referenced to VCCA
0.8
4.5 V to 5.5 V
VCCA × 0.3
VI
Input voltage
Control inputs
Active state
3-State
0
0
0
5.5
VCCO
5.5
–4
V
V
VI/O
Input/output voltage
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
–8
IOH
High-level output current
mA
mA
–24
–32
4
4.5 V to 5.5 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
8
IOL
Low-level output current
Input transition
24
4.5 V to 5.5 V
32
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
20
20
Δt/Δv
Data inputs
ns/V
°C
rise or fall rate
10
4.5 V to 5.5 V
5
TA
Operating free-air temperature
–55
125
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused or driven (floating) data inputs (I/Os) of the device must be held at logic HIGH or LOW (preferably VCCI or GND) to ensure
proper device operation and minimize power. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature
number SCBA004.
(4) All unused data inputs of the device must be held at VCCA or GND to ensure proper device operation.
(5) For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
(6) For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
4
Copyright © 2013, Texas Instruments Incorporated
SN74LVC16T245-EP
www.ti.com.cn
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
Electrical Characteristics(1)(2)
TA = −55°C to 125°C, over recommended input voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
1.65 V to 4.5 V
1.65 V
VCCB
1.65 V to 4.5 V
1.65 V
MIN
VCCO – 0.1
1.2
TYP
MAX UNIT
IOH = –100 μA,
VI = VIH
VI = VIH
VI = VIH
VI = VIH
VI = VIH
VI = VIL
VI = VIL
VI = VIL
VI = VIL
VI = VIL
IOH = –4 mA,
IOH = –8 mA,
IOH = –24 mA,
IOH = –32 mA,
IOL = 100 μA,
IOL = 4 mA,
VOH
2.3 V
2.3 V
1.9
V
3 V
3 V
2.35
4.5 V
4.5 V
3.75
1.65 V to 4.5 V
1.65 V
1.65 V to 4.5 V
1.65 V
0.1
0.45
VOL
IOL = 8 mA,
2.3 V
2.3 V
0.3
0.65
0.65
V
IOL = 24 mA,
IOL = 32 mA,
3 V
3 V
4.5 V
4.5 V
Control
inputs
II
VI = VCCA or GND
1.65 V to 5.5 V
1.65 V to 5.5 V
±2
μA
μA
μA
0 V
0 to 5.5 V
0 V
±10
±10
A or B
port
Ioff
IOZ
VI or VO = 0 to 5.5 V
0 to 5.5 V
A or B
port
VO = VCCO or GND,
OE = VIH
1.65 V to 5.5 V
1.65 V to 5.5 V
±10
1.65 V to 5.5 V
1.65 V to 5.5 V
20
20
VI = VCCI or GND,
IO = 0
ICCA
5 V
0 V
μA
0 V
1.65 V to 5.5 V
5 V
5 V
1.65 V to 5.5 V
0 V
–2.5
20
VI = VCCI or GND,
IO = 0
ICCB
–2.5
20
μA
μA
0 V
5 V
VI = VCCI or GND,
IO = 0
ICCA + ICCB
A port
1.65 V to 5.5 V
3 V to 5.5 V
1.65 V to 5.5 V
3 V to 5.5 V
30
50
One A port at VCCA – 0.6 V,
DIR at VCCA, B port = open
ΔICCA
μA
DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND
DIR
50
50
One B port at VCCB – 0.6 V,
DIR at GND, A port = open
ΔICCB
Ci
B port
3 V to 5.5 V
3.3 V
3 V to 5.5 V
3.3 V
μA
pF
pF
Control
inputs
VI = VCCA or GND
4
A or B
port
Cio
VO = VCCA/B or GND
3.3 V
3.3 V
8.5
(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
Copyright © 2013, Texas Instruments Incorporated
5
SN74LVC16T245-EP
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
1000000
100000
10000
1000
WB Voiding Fail Mode
100
80
90
100
110
120
Junction Temperature, TJ (°C)
130
140
150
160
(1) See datasheet for absolute maximum and minimum recommended operating conditions.
Figure 1. SN74LVC16T245-EP Operating Life Derating Chart
6
Copyright © 2013, Texas Instruments Incorporated
SN74LVC16T245-EP
www.ti.com.cn
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
Switching Characteristics
TA = −40°C to 85°C, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 2)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
1.7
21.9
1.3
9.2
23.6
29.4
13.1
23.8
16
1
7.4
0.8
7.1
23.4
29.2
10.3
23.7
10.8
ns
ns
ns
ns
ns
ns
B
0.9
1.6
2.4
0.4
1.8
23.8
29.6
32.2
24
0.8
1.5
1.9
0.4
1.6
0.7
1.5
1.7
0.4
1.2
23.4
29.3
12
0.7
1.4
1.3
0.4
0.9
OE
OE
OE
OE
23.7
12.6
32
Switching Characteristics
TA = −55°C to 125°C, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 2)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
25.9
13.2
27.8
33.4
17.1
27.8
22
11.4
11.1
27.4
33.2
14.3
27.7
14.8
ns
ns
ns
ns
ns
ns
B
27.8
33.6
36.2
28
27.4
33.3
16
OE
OE
OE
OE
27.7
16.6
36
Copyright © 2013, Texas Instruments Incorporated
7
SN74LVC16T245-EP
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
Switching Characteristics
TA = −40°C to 85°C, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 2)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN
MAX MIN
MAX MIN
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
1.6 21.4
1.2
1
9
9.1
9
0.8
1
6.2
8.9
9
0.6
0.9
1.4
0.9
1
4.8
ns
ns
ns
ns
ns
ns
B
1.2
1.4
9.3
9
8.8
9
OE
OE
OE
OE
1.4
1.8
1
1.4
1.7
1
2.3 29.6
11
9.3
10.9
9.4
6.9
10.9
6.9
1
10.9
10.9
12.9
1.7 28.2
1.6
1.2
1
Switching Characteristics
TA = −55°C to 125°C, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 2)
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN
MAX MIN
MAX MIN
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
25.4
13
10.2
12.9
13
8.8
ns
ns
ns
ns
ns
ns
B
13.3
13
13.1
13
12.8
13
OE
OE
OE
OE
33.6
14.9
32.2
14
14.3
14.9
13.4
10.9
14.9
10.9
14.9
16.9
8
Copyright © 2013, Texas Instruments Incorporated
SN74LVC16T245-EP
www.ti.com.cn
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
Switching Characteristics
TA = −40°C to 85°C, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
VCCB = 1.8 V VCCB = 2.5 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
± 0.15 V
± 0.2 V
PARAMETER
UNIT
MIN MAX MIN
MAX
MIN
MAX MIN MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
1.5
0.9
1.6
2.1
0.8
1.6
21.2
7.2
8.2
29
1.1
0.8
1.6
1.7
0.8
1.4
8.8
6.2
0.8
6.1
6.1
6.2
8.6
7.8
8.5
0.5
0.6
1.6
0.8
0.8
0.9
4.4
6
ns
ns
ns
ns
ns
ns
B
0.7
1.6
1.5
0.8
1.1
OE
OE
OE
OE
8.2
8.2
6.3
7.8
8.4
10.3
7.8
7.8
27.7
12.4
Switching Characteristics
TA = −55°C to 125°C, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
VCCB = 1.8 V VCCB = 2.5 V
± 0.15 V ± 0.2 V
VCCB = 3.3 V
± 0.3 V
VCCB = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN
MAX
MIN
MAX MIN MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
25.2
11.2
12.2
33
12.8
10.2
10.1
12.2
12.8
12.1
12.9
8.4
10
ns
ns
ns
ns
ns
ns
B
10.2
12.2
14.3
12.1
16.4
OE
OE
OE
OE
12.2
10.3
12.1
10.4
11.8
31.7
Copyright © 2013, Texas Instruments Incorporated
9
SN74LVC16T245-EP
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
www.ti.com.cn
Switching Characteristics
TA = −40°C to 85°C, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN
MAX MIN
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
1.6 21.4
1
0.4
0.3
1.6
0.7
1.3
8.8
4.8
0.7
6
4.5
5.4
8
0.4
0.3
0.3
0.7
0.7
0.9
4.2
4.3
6.4
5.7
5.5
6
ns
ns
ns
ns
ns
ns
B
0.7
0.3
2
6.8
5.4
0.3
0.3
1.4
0.7
1
OE
OE
OE
OE
5.4
28.7
5.5
9.7
0.7
5.5
5.5
8.1
1.6 27.6
11.4
Switching Characteristics
TA = −55°C to 125°C, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN
MAX
MIN
MAX MIN
MAX
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
A
B
A
A
B
A
B
25.4
14.3
10
8.5
8.2
8.3
ns
ns
ns
ns
ns
ns
B
11
9.4
8.8
9.4
OE
OE
OE
OE
9.4
9.4
32.7
10.4
31.6
13.7
10.4
19.3
12
9.7
10.4
12.6
10.4
10
Operating Characteristics
TA = 25°C
VCCA
VCCB = 1.8 V
=
VCCA
VCCB = 2.5 V
=
VCCA
VCCB = 3.3 V
=
VCCA =
VCCB = 5 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
2
TYP
2
TYP
2
TYP
3
A-port input, B-port output
(1)
CpdA
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
B-port input, A-port output
18
18
2
19
19
2
19
20
2
22
22
2
pF
A-port input, B-port output
(1)
CpdB
B-port input, A-port output
(1) Power dissipation capacitance per transceiver
10
Copyright © 2013, Texas Instruments Incorporated
SN74LVC16T245-EP
www.ti.com.cn
ZHCSAQ3A –JANUARY 2013–REVISED FEBRUARY 2013
PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
L
Open
GND
t
Open
pd
From Output
Under Test
t
t
/t
/t
2 × V
CCO
GND
PLZ PZL
PHZ PZH
C
L
R
L
(see Note A)
t
w
LOAD CIRCUIT
V
CCI
V
CCI
/2
V
CCI
/2
Input
C
L
V
TP
R
L
V
CCO
0 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
15 pF
15 pF
15 pF
15 pF
VOLTAGE WAVEFORMS
PULSE DURATION
0.3 V
V
CCA
Output
Control
(low-level
enabling)
V /2
CCA
V
CCA
/2
t
0 V
t
PZL
PLZ
V
V
CCO
Output
Waveform 1
V
CCI
V
/2
/2
CCO
Input
V
CCI
/2
V
CCI
/2
V
+ V
OL
TP
S1 at 2 × V
CCO
OL
0 V
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− V
TP
V
CCO
Output
V /2
CCO
V
CCO
/2
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
pd
PHL
is the V associated with the input port.
CC
CCI
is the V associated with the output port.
CCO
CC
J. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 2013, Texas Instruments Incorporated
11
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CLVC16T245MDGGEP
CLVC16T245MDGGREP
V62/12667-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
DGG
48
48
48
48
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
LVC16T245M
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
LVC16T245M
LVC16T245M
LVC16T245M
V62/12667-01XE-T
40
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CLVC16T245MDGGREP TSSOP
DGG
48
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
CLVC16T245MDGGREP
2000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
CLVC16T245MDGGEP
V62/12667-01XE-T
DGG
DGG
TSSOP
TSSOP
48
48
40
40
530
530
11.89
11.89
3600
3600
4.9
4.9
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0048A
TSSOP - 1.2 mm max height
SCALE 1.350
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
46X 0.5
48
1
12.6
12.4
NOTE 3
2X
11.5
24
B
25
0.27
0.17
48X
6.2
6.0
1.2
1.0
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.75
0.05
0.50
DETAIL A
TYPICAL
4214859/B 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
(R0.05)
TYP
SYMM
24
25
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214859/B 11/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGG0048A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
48X (1.5)
SYMM
1
48
48X (0.3)
46X (0.5)
SYMM
(R0.05) TYP
24
25
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4214859/B 11/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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