V62/13622-01XE [TI]
支持 4 位、6 位或 8 位 VID 的数字 PWM 系统控制器，UCD9222-EP | RGZ | 48 | -55 to 115;
| 型号： | V62/13622-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 支持 4 位、6 位或 8 位 VID 的数字 PWM 系统控制器，UCD9222-EP | RGZ | 48 | -55 to 115 控制器 CD 开关 |
| 文件： | 总35页 (文件大小：2457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCD9222-EP
www.ti.com.cn
ZHCSBS2 –OCTOBER 2013
具有 4 位，6 位 或 8 位电压识别 (VID) 支持的数字脉宽调制 (PWM) 系统控
制器
查询样片: UCD9222-EP
1
特性
2
•
完全可配置双输出非隔离直流/直流 PWM 控制器，
此控制器支持 TMS320C6670™ 和
TMS320C6678™ 数字信号处理器 (DSP) VID 接口
•
•
支持纠错码 (ECC) 的增强型非易失性存储器
由具有一个内部稳压器控制器的单电源供电运行的
器件可实现宽电源电压范围内的运行
•
支持高达 2MHz 的开关频率，此时占空比分辨率为
250ps
•
由 Fusion Digital Power™ 设计工具，一个基于
全功能 PC 的设计工具提供支持，以模拟、配置和
监控电源性能
•
•
高达 1mV 的闭环分辨率
用于改进瞬态性能的具有非线性增益的硬件加
速，3 级 / 3 零补偿器
应用范围
•
•
•
网络设备
•
•
•
支持多个包含预偏置启动的软启动和软停止配置
支持电压裕度和定序
电信设备
现场可编程门阵列 (FPGA)，DSP 和存储器电源
同步输入/输出引脚使多个 UCD92xx 器件之间的
DPWM 时钟保持一致
支持国防、航空航天、和医疗应用
•
电源参数的 12 位数字监控包括:
•
•
•
•
•
•
•
受控基线
–
–
–
–
输入电流和电压
同一组装和测试场所
同一制造场所
输出电流和电压
每个功率级上的温度
辅助模数转换器 (ADC) 输入
在扩展（-55°C 至 115°C）温度范围内可用
延长的产品生命周期
延长的产品变更通知
产品可追溯性
•
多电平过流故障保护：
–
–
–
外部电流故障输入
模拟比较器监控电流感测电压
被持续数字监控的电流
•
•
过压和欠压故障保护
过热故障保护
说明
UCD9222 是一款设计用于非隔离式直流/直流电源应用的双轨同步降压数字 PWM 控制器。 这个器件集成了用于直
流/直流环路管理的专用电路，支持多达两个 VID 接口。 此外，UCS9222 具有闪存存储器和一个串口以支持可配
置性、监控和管理。
支持几个电压识别 (VID) 模式，其中包括一个 4 位并口，一个 6 位接口和一个 8 位串口。
UCD9222 被设计用于提供针对非隔离式直流/直流转换器应用的多种所需特性，与此同时，通过减少外部电路来最
大限度地减少总体系统组件数量。 此解决方案集成具有定序、裕度和跟踪的多环路管理，以针对总体系统效率进行
优化。 此外，在无需添加额外组件的情况下，支持环路补偿和校准。
为了简化器件配置，提供德州仪器 (TI) Fusion Digital Power™ 设计工具。 这个基于 PC 的图形用户界面为该器件
提供了一个直观的界面。 这个工具使得设计人员能够为应用配置系统运行参数、将配置存储至片上非易失性存储器
并且观察每个功率级输出的频域和时域仿真。
TI 还开发了多个互补功率级解决方案 - 从 UCD7k 系列中的离散驱动器到 PTD 系列中经完全测试的电源传动模
块。 这些解决方案已被开发用于为 UCD92xx 系列系统电源控制器提供补充。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
TMS320C6670, TMS320C6678, Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
English Data Sheet: SLVSBY1
UCD9222-EP
ZHCSBS2 –OCTOBER 2013
www.ti.com.cn
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
OPERATING TEMPERATURE
RANGE, TJ
ORDERABLE PART
NUMBER
PIN
COUNT
TOP SIDE
MARKING
SUPPLY
PACKAGE
VID NUMBER
–55°C to 115°C
UCD9222WRGZREP
48-pin
Reel of 2500
QFN
UCD9222EP
V62/13622-01XE
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
–0.3 to 3.8
UNIT
V
Voltage applied at V33D to DGND
Voltage applied at V33A to AGND
Voltage applied to any pin(2)
–0.3 to 3.8
–0.3 to 3.8
–55 to 150
V
V
Storage temperature (TSTG
)
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to GND.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM
MAX UNIT
V
Supply voltage during operation, V33D, V33DIO, V33A
Operating junction temperature range
Maximum junction temperature
3
3.3
3.6
115
125
V
TJ
–55
°C
°C
THERMAL INFORMATION
UCD9222-EP
RGZ
THERMAL METRIC(1)
UNITS
48 PINS
27.1
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
θJCtop
θJB
12.9
4.3
°C/W
ψJT
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
0.2
ψJB
4.3
θJCbot
0.6
(1) 有关传统和全新热度量的更多信息，请参阅 IC 封装热度量 应用报告 （文献号：ZHCA543）。
(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的规定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环
境热阻抗。
(3) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI 标准 G30-
88 中找到内容接近的说明。
(4) 按照 JESD51-8 中的说明，通过在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结至电路板的热阻。
(5) 结至顶部的特征参数，( ψJT)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
(6) 结至电路板的特征参数，(ψJB)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
。
。
(7) 通过在外露（电源）焊盘上进行冷板测试仿真来获得结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI
标准 G30-88 中找到了内容接近的说明。
间距
2
Copyright © 2013, Texas Instruments Incorporated
UCD9222-EP
www.ti.com.cn
ZHCSBS2 –OCTOBER 2013
ELECTRICAL CHARACTERISTICS
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
SUPPLY CURRENT
IV33
Total V33 supply current,
V33A = V33DIO = 3.3 V
54
80
mA
IV33DIO
IV33A
V33DIO = 3.3 V
V33A = 3.3 V
42
8
55
15
65
mA
mA
mA
Supply current
IV33DIO
V33DIO = 3.3 V storing configuration
parameters in flash memory
52
INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS
V33
3.3-V linear regulator
Emitter of NPN transistor
3.25
3.3
4
3.6
4.6
8
V
V
V33FB
IV33FB
Beta
3.3-V linear regulator feedback
Series pass base drive
Series NPN pass device
VIN = 12 V
0.2
40
0.4
100
mA
EXTERNALLY SUPPLIED 3.3 V POWER
V33D, V33DIO1
V33DIO2
,
Digital 3.3-V power
TJ = 25°C
TJ = 25°C
3.0
3.0
3.6
3.6
V
V
V33A
Analog 3.3-V power
ERROR AMPLIFIER INPUTS EAPn, EANn
VCM
Common mode voltage each pin
0
1.8
V
VERROR
EAP-EAN
REA
Internal error voltage range
Error voltage digital resolution
Input impedance
AFE_GAIN field of CLA_GAINS = 1X(1)
AFE_GAIN field of CLA_Gains = 8X
Ground reference, TJ = 25°C
–256
248
mV
mV
MΩ
µA
1
1.5
IOFFSET
Vref 10-bit DAC
Vref
Input offset current
1 kΩ source impedance, TJ = 25°C
–5
0
5
Reference voltage setpoint
Reference voltage resolution
1.7
V
Vrefres
1.56
mV
ANALOG INPUTS CS1A, CS2A, VinMon, IinMon, Vtrack, Temp1, Temp2, Addr0, Addr1
VADC_RANGE
Measurement range for voltage
monitoring
Inputs: VinMon, IinMon, Vtrack, Temp1,
Temp2, CS1A, CS2A
0
2.6
V
Voffset
input offset voltage
–27
27
2
mV
V
VOC_THRS
Over-current comparator threshold Inputs: CS1A, CS2A
voltage range(2)
0.032
VOC_RES
Over-current comparator threshold Inputs: CS1A, CS2A
voltage range
31.25
mV
°C
Tempinternal
Internal temperature sense
accuracy
Over range from 0°C to 100°C
–15
15
INL
Ilkg
ADC integral nonlinearity
Input leakage current
TJ = -40°C to 115°C
3 V applied to pin
Ground reference
–2.5
2.5
mV
nA
100
RIN
CIN
Input impedance
8
MΩ
pF
Current sense input capacitance
10
(1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.
(2) Can be disabled by setting to '0'
Copyright © 2013, Texas Instruments Incorporated
3
UCD9222-EP
ZHCSBS2 –OCTOBER 2013
www.ti.com.cn
ELECTRICAL CHARACTERISTICS (Continued)
over operating junction temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
Dgnd
+0.3
VOL
VOH
Low-level output voltage
High-level output voltage
IOL = 6 mA(1), V33DIO = 3 V
IOH = -6 mA(2), V33DIO = 3 V
V
V
V33DIO
–0.6V
VIH
VIL
High-level input voltage
Low-level input voltage
V33DIO = 3V
2.1
3.6
1.4
V
V
V33DIO = 3.5 V
SYSTEM PERFORMANCE
VRESET Voltage where device comes out of reset
tRESET
V33D Pin
2.3
2
2.4
10
V
Pulse width needed for reset
Setpoint reference accuracy
nRESET pin
µs
Vref commanded to be 1V, at 25°C AFEgain = 4,
1V input to EAP/N measured at output of the
EADC(3)
–10
mV
VRefAcc
Setpoint reference accuracy over
temperature
–55°C to 115°C
–40
–4
40
4
mV
mV
AFEgain = 4 compared to
AFEgain = 1, 2, or 8
VDiffOffset
Differential offset between gain settings
Digital compensator delay
240 + 1
switching
cycle
tDelay
FSW
240
ns
Switching frequency
Accuracy
15.260
–5%
0%
2000
5%
kHz
Duty
Maximum and minimum duty cycle
100%
V33 slew rate between 2.3V and 2.9V,TJ = -40°C
to 115°C
V33Slew
tretention
Minimum V33 slew rate
0.25
V/ms
Retention of configuration parameters(4)
TJ = 25 °C
100
20
Years
Write_Cycles Number of nonvolatile erase/write cycles
TJ = 25 °C
K cycles
All rails configured to accept 4-bit VID messages(5)
All rails configured to accept 6-bit VID messages(5)
All rails configured to accept 8-bit VID messages(6)
1
4
4
RateVID
Max VID message rate
msg/msec
(1) The maximum IOL, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
(2) The maximum IOH, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
(3) With default device calibration. PMBus calibration can be used to improve the regulation tolerance.
(4) The data retention specification is based on accelerated stress testing at 170°C for 420 hours and using an Arrhenius model with
activation energy of 0.6 eV.
(5) VID message rate on each interface. Measured over a 1.0 msec interval
(6) VID message rate on PMBus interface.
4
Copyright © 2013, Texas Instruments Incorporated
UCD9222-EP
www.ti.com.cn
ZHCSBS2 –OCTOBER 2013
ADC MONITORING INTERVALS AND RESPONSE TIMES
The ADC operates in a continuous conversion sequence that measures each rail's output voltage and output
current, plus six other variables (input voltage, input current, internal temperature, tracking source, and two
external temperature sensors). The length of the sequence is determined by the number of output rails
(NumRails) configured for use. The time to complete the monitoring sampling sequence is give by the formula:
tADC_SEQ = tADC × (2 × NumRAILS + 6)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tADC
ADC single-sample time
3.84
µs
tADC_SEQ
ADC sequencer interval Min = 2 × 1 Rail + 6 = 8 samples
Max = 2 × 2 Rails + 6 = 10 samples
30.72
38.40
µs
The most recent ADC conversion results are periodically converted into the proper measurement units (volts,
amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The
monitoring operates asynchronously to the ADC, at intervals shown in the table below.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tVout
tIout
Output voltage monitoring interval
Output current monitoring interval
Input voltage monitoring interval
Input current monitoring interval
Temperature monitoring interval
Auxiliary ADC monitoring interval
200
µs
µs
200×NRails
tVin
1
1
ms
ms
ms
ms
tIin
tTEMP
tAUXADC
100
100
Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response
time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC
sequence interval. Once a fault condition is detected, some additional time is required to determine the correct
action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following
table lists the worse-case fault response times.
MAX
no VID /w VID
MAX
(1)
PARAMETER
TEST CONDITIONS
TYP
UNIT
tOVF
tUVF
,
,
,
Over-/under-voltage fault response time
during normal operation
Normal regulation, no PMBus activity,
4 stages enabled
250
800
400
800
µs
tOVF
tUVF
Over-/under-voltage fault response time, During data logging to nonvolatile
during data logging
memory(2)
1000
µs
µs
µs
tOVF
tUVF
Over-/under-voltage fault response time, During tracking and soft-start ramp.
when tracking or sequencing enable
tOCF
tUCF
,
Over-/under-current fault response time
during normal operation
Normal regulation, no PMBus activity,
100 +
(600 × NRails)
5000
5000
4 stages enabled 75% to 125% current
step(3)
tOCF
tUCF
,
Over-/under-current fault response time, During data logging to nonvolatile
during data logging
600 +
(600 × NRails)
µs
sec
µs
memory 75% to 125% current step
tOTF
Over-temperature fault response time
Temperature rise of 10°C/sec, at OT
threshold
1.60
5.5
t3-State Time to tristate the PWM output after a
shutdown is initiated
DRIVER_CONFIG = 0x01
(1) Controller receiving VID commands at a rate of 4000 msg/sec.
(2) During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can
be up to 10 ms.
(3) Because the current measurement is averaged with a smoothing filter, the response time to an over-current condition depends on a
combination of the time constant (τ) from Table 3, the recent measurement history, and how much the measured value exceeds the
over-current limit.
Copyright © 2013, Texas Instruments Incorporated
5
UCD9222-EP
ZHCSBS2 –OCTOBER 2013
www.ti.com.cn
HARDWARE FAULT DETECTION LATENCY
The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.
PARAMETER
TEST CONDITIONS
High level on FAULT pin
Step change in CS voltage from 0V to 2.5V
MAX TIME
UNIT
Time to disable DPWM output base on active FAULT pin
signal
tFAULT
tCLF
18
µs
Time to disable the DPWM A output based on internal
analog comparator
Switch
Cycles
4
PMBUS/SMBUS/I2C
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and
PMBus are shown below.
Figure 1. I2C/SMBus/PMBus Timing in Extended Mode Diagram
I2C/SMBus/PMBus TIMING REQUIREMENTS
TJ = –55°C to 115°C, 3 V < V33 < 3.6 V, typical values at TJ = 25°C
PARAMETER
TEST CONDITIONS
Slave mode; SMBC 50% duty cycle
Slave mode; SCL 50% duty cycle
MIN TYP
MAX UNIT
fSMB
SMBus/PMBus operating frequency
I C operating frequency
Bus free time between start and stop
Hold time after (repeated) start
Repeated start setup time
Stop setup time
10
10
5
1000
1000
kHz
kHz
µs
fI2C
t(BUF)
t(HD:STA)
t(SU:STA)
t(SU:STO)
t(HD:DAT)
t(SU:DAT)
t(TIMEOUT)
t(LOW)
0.3
0.3
0.3
0
µs
µs
µs
Data hold time
Receive mode
ns
Data setup time
55
ns
(1)
Error signal/detect
See
35
ms
µs
Clock low period
0.55
0.3
(2)
t(HIGH)
Clock high period
See
50
25
µs
(3)
t(LOW:SEXT) Cumulative clock low slave extend time See
tFALL Clock/data fall time
ms
ns
Rise time tRISE = VILMAX – 0.15) to (VIHMIN + 0.15) ,
TJ = -40°C to 115°C
1000
(1) The UCD9222 times out when any clock low exceeds t(TIMEOUT)
.
(2) t(HIGH) , max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9222 that is
in progress.
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
6
Copyright © 2013, Texas Instruments Incorporated
UCD9222-EP
www.ti.com.cn
ZHCSBS2 –OCTOBER 2013
I2C/SMBus/PMBus TIMING REQUIREMENTS (continued)
TJ = –55°C to 115°C, 3 V < V33 < 3.6 V, typical values at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
tRISE
CIN
Clock/data rise time
Fall time tFALL = 0.9 V33 to (VILMAX – 0.15) , TJ = -
40°C to 115°C
1000
ns
FUNCTIONAL BLOCK DIAGRAM
Fusion Power Peripheral 2
Digital
High Res
PWM
DPWM2A
FLT2A
EAp2
Analog Front End
(AFE)
Compensator
3P/3Z IIR
EAn2
Fusion Power Peripheral 1
Analog Front End
Compensator
EAp1
EAn1
Diff
Amp
Digital
High Res
PWM
DPWM1A
FLT1A
Err
Amp
ADC
6 bit
IIR
3P/3Z
Ref
Coeff.
Regs
SyncIn/JTAG_TDI
SyncOut/JTAG_TDO
5
6
VID1A
VID1B
VID1C
VID1S
VID2A
VID2B
VID2C
VID2S
V33x
xGnd
3.3V reg.
controller
& 1.8V
regulator
Analog Comparators
BPCap
VID
1 - 2
OC
Ref 1
Ref 2
DPWM1
ARM-7 core
Addr0
Addr1
OC
DPWM2
CS1A
TCK
TDI
Flash
Memory with
ECC
12-bit
ADC
260 ksps
CS2A
TDO
TMS
RCK
nTRST
JTAG
Osc
VinMon
IinMon/AuxADC4
Vtrack/AuxADC3
Temp2/AuxADC2
Temp1/AuxADC1
POR/BOR
PowerGood
PG1
GPIO
PG2
EN1
EN2
Internal
Temp Sense
PMBus_Clk
PMBus_Data
PMBus_Alert
PMBus_Cntrl
nRESET
PMBus
Copyright © 2013, Texas Instruments Incorporated
7
UCD9222-EP
ZHCSBS2 –OCTOBER 2013
www.ti.com.cn
36
AGND2
1
IinMon/AuxADC4
35
34
BPCap
V33A
2
3
Temp2/AuxADC2
CS2A
33
32
31
30
29
28
27
26
25
V33DIO
DGND3
4
5
VinMon
nRESET
FLT1A
6
JTAG_nTRST
JTAG_TMS
7
VID1S
SyncIn/JTAG_TDI
SyncOut/JTAG_TDO
JTAG_TCK
EN2
8
FLT2A
9
VID2S
10
11
12
PMBus_CLK
PMBus_Data
DPWM1A
EN1
(1) In case of conflict between Figure 2 and Table 1 the table shall take precedence
(2) Preliminary versions of this data sheet prior to June 14, 2010 had a different definition for pins 17, 18, and 21. Board
designs made with that earlier pinout should be updated.
Figure 2. Pin Assignment Diagram
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Table 1. PIN FUNCTIONS
PIN NO.
1
PIN LABEL
IinMon/AuxADC4
Temp2/AuxADC2
CS2A
DESCRIPTION
Input current monitor, or Auxiliary ADC input 4
Temperature sense input for Rail 2, or Auxiliary ADC input 2
Power stage 2A current sense input and input to analog comparator 2
Input voltage monitor
2
3
4
VinMon
5
nRESET
FLT1A
Active low device reset input. Pull up to 3.3V with a 10k ohm resistor
Fault indicator for stage 1A
6
7
VID1S
VID Select pin for Rail 1
8
FLT2A
Fault indicator for stage 2A
9
VID2S
VID Select pin for Rail 2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
PMBus_Clk
PMBus_Data
DPWM1A
PG1
PMBus Clock. Pull up to 3.3V with a 2k ohm resistor
PMBus Data. Pull up to 3.3V with a 2k ohm resistor
Digital Pulse Width Modulator output 1A
Rail 1 Power Good Indicator
DPWM2A
PG2
Digital Pulse Width Modulator output 2A
Rail 2 Power Good Indicator
VID1A
VID input pin for Rail 1 – least significant bit
Power Good Indication
PowerGood
VID1B
VID input pin for Rail 1
PMBus_Alert
PMBus_Cntrl
VID1C
PMBus Alert. Pull up to 3.3V with a 10k ohm resistor
PMBus Control. Pull up to 3.3V with a 10k ohm resistor
VID input pin for Rail 1 – most significant bit
VID input pin for Rail 2 – least significant bit
VID input pin for Rail 2
VID2A
VID2B
VID2C
VID input pin for Rail 2 – most significant bit
Rail 1 Enable
EN1
EN2
Rail 2 Enable
JTAG_TCK
SyncOut/JTAG_TDO
SyncIn/JTAG_TDI
JTAG_TMS
(JTAG) nTRST
Dgnd3
JTAG Test Clock
Mux'ed pin JTAG Test Data Output, DPWM Sync Output
Mux'ed pin – JTAG Test Data In, DPWM Sync Input
JTAG Test mode select. Pull up to 3.3V with a 10k ohm resistor
JTAG Test Reset – Tie to ground with a 10k ohm resistor
Digital Ground
V33DIO
3.3V supply for Digital I/O and Core
V33A
Analog 3.3V supply
BPCap
1.8V Bypass Capacitor – tie 0.1 µF cap to analog ground
Analog ground
Agnd2
EAp1
Error analog, differential voltage, Positive channel 1 input
Error analog, differential voltage, Negative channel 1 input
Error analog, differential voltage, Positive channel 2 input
Error analog, differential voltage, Negative channel 2 input
EAn1
EAp2
EAn2
V33FB
Connection to the base of 3.3V linear regulator transistor (no connect if unused)
Power stage 1A current sense input and input to analog comparator 1
PMBus Address sense. Channel 1.
CS1A
Addr1
Addr0
PMBus Address sense. Channel 0.
Vtrack/AuxADC3
Temp1/AuxADC1
Agnd3
Tracking voltage input, or Auxiliary ADC input 3
Temperature sense input for Rail 1, or Auxiliary ADC input 1
Analog ground
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Table 1. PIN FUNCTIONS (continued)
PIN NO.
48
PIN LABEL
DESCRIPTION
ADC_Ref
ADC Reference. Tie to analog ground through 0.1µF capacitor
It is recommended that this pad be connected to analog ground
PowerPad
TYPICAL APPLICATION SCHEMATIC
Figure 3 shows the UCD9222 power supply controller as part of a system that provides the regulation of two
independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding
into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate
drivers for each power stage.
The ±Vsense rail signals must be routed to the EAp/EAn input that matches the DPWM number that controls the
output power stage. For example, the power stage driven by DPWM1A must have its feedback routed to EAP1
and EAN1.
UCD7242
UCD9222
Figure 3. Typical Application Schematic
10
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FUNCTIONAL OVERVIEW
The UCD9222 contains two Fusion Power Peripherals (FPP). Each FPP consists of:
•
•
•
•
•
A differential input error voltage amplifier.
A 10-bit DAC used to set the output regulation reference voltage.
A fast ADC with programmable input gain to digitally measure the error voltage.
A dedicated 3-pole/3-zero digital filter to compensate the error voltage
A digital PWM (DPWM) engine that generates the PWM pulse width based on the compensator output.
Each controller is configurable through the PMBus serial interface.
PMBus Interface
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD9222 supports revision 1.2 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD9222, MFR_SPECIFIC commands are defined to configure or activate those features.
These commands are defined in the UCD92xx PMBUS Command Reference.
The UCD9222 is PMBus compliant, in accordance with the "Compliance" section of the PMBus specification. The
firmware is also compliant with the SMBus 2.0 specification, including support for the SMBus ALERT function.
The hardware can support 100 kHz, 400 kHz, or 1 MHz PMBus operation.
Resistor Programmed PMBus Address Decode
The PMBus Address is selected using resistors attached to the ADDR0 and ADDR1 pins. At power-up, the
device applies a bias current to each address detect pin. The measured voltage on each pin determines the
PMBus address as defined in Table 2. For example, a 133kΩ resistor on ADDR1 and a 75kΩ on ADDR0 will
select PMBus address = 100. Resistors are chosen from the standard EIA-E96 series, and should have accuracy
of 1% or better.
V33
UCD9222
ADDR - 0,
ADDR - 1 pins
10 mA
IBIAS
Resistor to
set PMBus
Address
To 12 -bit ADC
Figure 4. PMBus Address Detection Method
A short or open on either address pin causes the PMBus address to default to address 126. To avoid potential
conflicts between multiple devices, it is best to avoid using address 126.
Some addresses should be avoided; see Table 2 for details.
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Table 2. PMBus Address Bins(1)
ADDR0
(short)
< 36.5k
(open)
> 237k
42.2k 48.7k 56.2k 64.9k
75k
86.6k 100k 115k 133k 154k 178k 205k
< 36.5k
(short)
126
126
126
126
126
126
126
126
126
126
126
126
126
126
42.2k
48.7k
56.2k
64.9k
75k
126
126
126
126
126
126
126
126
126
126
126
126
126(2)
126(2)
24
1
2
3
4
5
6
18
7
19
8
20
9
10
22
11(3)
33
126
126
126
126
126
126
126
126
126
126
126
126
13
14
15
16
17
21
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
86.6k
100k
115k
133k
154k
178k
205k
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
112
124
126
101
113
125
126
102
114
103
115
104
116
105
117
126
126
106
118
126
126
107
119
126
126
108
120
126
109
121
126
110
122
126
111
123
126
126 126(2) 126
126
126
126
> 237k
(open)
126
126
126
126
126
126
126
126
126
126
126
126
126
126
(1) Shaded addresses are not recommended as they will cause conflict when multiple devices are used.
(2) Reserved. Do not use.
(3) Conflicts with ROM. Do not use.
VID Interface
The UCD9222 supports VID (Voltage Identification) inputs from up to two external VID enabled devices. The VID
codes may be 4-, 6-, or 8-bit values; the format is selected using the VID_CONFIG PMBus command. In 4- and
6-bit mode, each host uses four VID input signals (VID_A, VID_B, VID_C, and VID_S) to send VID codes to the
UCD9222. In 8-bit mode, the PMBus input is used to receive VID commands from the VID devices’ I2C
interfaces.
VID Device #1
VCNTL[0]
VCNTL[1]
VCNTL[2]
VCNTL[3]
VID Device #2
VCNTL[0]
VCNTL[1]
VCNTL[2]
VCNTL[3]
UCD9222
VID2A
VID1A
VID1B
VID1C
VID1S
VID2B
VID2C
VID2S
Figure 5. One UCD9222 Controlled by Two DSP/ASICs Using 4-bit or 6-bit VID Format
Regardless of which VID mode is used, the commanded output voltage reference is set according to this formula:
Vref_cmd = (VID_CODE × VID_Slope) + VID_Offset,
where
VID_Slope = (VID_Vout_High – VID_Vout_Low) / ((2^VID_Format) -1),
and
VID_Offset = VID_Vout_Low.
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The VID_Vout_High, VID_Vout_Low, and VID_Format values are set using the VID_CONFIG PMBus command.
The same command is used to set the initial VID code that will be used at power-up. In addition, the
VID_CONFIG command also sets the initial voltage that the device ramps to at the end of the soft start; and
defines a lockout interval over which the VID is ignored during the soft start.
VID Lockout Interval: Because the VID signals may be originating from a device that is being powered by the
UCD9222, the voltage levels on the VID signal may not be valid logic levels until the supply voltage at the
powered device has stabilized. For this reason a configurable lockout interval is applied each time the regulated
output voltage is turned on. The lockout interval timer starts when the output voltage reaches the top of the soft-
start ramp. Positive values range from 1 to 32767 ms, with 1 ms resolution. A value of 0 will enable the VID
inputs immediately at the top of the start ramp. Negative values disable the lockout, allowing the VID inputs to
remain active all the time regardless of the output voltage state. The default value is 0.
4-Bit VID Mode: In 4-bit VID mode, the four VID input signals are used to provide the four bits of VID data, as
shown in the table below. The VID lines are level-sensitive, and are periodically polled every 400µs. When the
VID lines are changed to command a new voltage, there may be a delay of 500 to 600µs while the UCD9222
confirms that the VID signal levels are stable. The output voltage will then slew to the new setpoint voltage at the
rate specified by the PMBus VOUT_TRANSITION_RATE command.
PIN
PURPOSE
RAIL 1
VID1A
VID1B
VID1C
VID1S
RAIL 2
VID2A
VID2B
VID2C
VID2S
VID_A
VID_B
VID_C
VID_S
Data bit 0 (least significant bit)
Data bit 1
Data bit 2
Data bit 3 (most significant bit)
6-Bit VID Mode: In 6-bit VID mode, the four VID input signals are used to provide the six bits of VID data, as
shown in the table below. Each of the three data lines (VID_A, VID_B, and VID_C) carries two bits of data per
VID code. The bits are clocked and selected by the VID_S select line.
PIN
PURPOSE
RAIL 1
RAIL 2
VID_A
Data bit 0 when VID_S is low,
Data bit 3 when VID_S is high
VID1A
VID2A
VID_B
VID_C
VID_S
Data bit 1 when VID_S is low,
Data bit 4 when VID_S is high
VID1B
VID1C
VID1S
VID2B
VID2C
VID2S
Data bit 2 when VID_S is low,
Data bit 5 when VID_S is high
Select Line:
Low= LSB, High = MSB
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The falling edge of the VID_S line triggers the UCD9222 to read bits 2:0 on the three VID data lines. The rising
edge of VID_S triggers the UCD9222 to read bits 5:3 on the three VID data lines and calculate a new VOUT
setpoint. This calculation takes from 35 to 135µs. The output voltage will then slew to the new setpoint voltage at
the rate specified by the VOUT_TRANSITION_RATE PMBus command.
VID_S
Lower Half
VID_A = bit 0
VID_B = bit 1
UpperHalf
VID_A = bit 3
VID_B = bit 4
Lower Half
VID_A = bit 0
VID_B = bit 1
Upper Half
VID_A = bit 3
VID_B = bit 4
VID_A
VID_B
VID_C
VID_C = bit 2 VID_C = bit 5
VID_C = bit 2 VID_C = bit 5
VOUT
Figure 6. 6-Bit VID Data Transfer
The set-up time on the data lines is 0 µs. All four VID lines must hold at the same level for some time after a
change in the VID_S line to allow the UCD9222 to read and validate the data signals and perform necessary
voltage calculations. The UCD9222 can tolerate single hold times as short as 70µs, but does not have sufficient
computation power to sustain continuous VID messaging that quickly. It is expected that the hold time will be at
least 125µs for sustained operations. It is recommended that the DSP only send VID messages when the
regulated voltage needs to change; sending the same VID code repeatedly and continuously provides no benefit.
Figure 7 and Table 3 illustrate the critical timing measurements as they apply to the 6-bit VID interface.
Tsu
Thd
Tchi
Tclo
VID_S
VID_A,
VID_B,
VID_C
Tr
Tf
Tvo
VOUT
Figure 7. 6-bit VID Timing
14
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Table 3. 6-bit VID Timing
SYMBO
L
PARAMETER
MIN
TYP
MAX
UNITS
Tr
Data and clock rise time
–
–
2.5
0.3
µs
µs
µs
µs
µs
µs
µs
Tf
Data and clock fall time
Data setup before changing clock
Data hold until next clock change
Clock high time
Tsu
Thd
Tchi
Tclo
Tvo
0
70
70
70
35
125
125
Clock low time
Response time from rising edge of VID_S to start of
Vout slewing to new setpoint
135
8-Bit VID Mode: In 8-bit VID mode, the four VID input signals are not used. Instead, an 8-bit VID code is
transmitted to the UCD9222 through the PMBus / I2C port using one of the VID_CODE_RAILn commands,
where n is the rail number from 1 to 2.
NAME
DESCRIPTION(1)
CODE
0xBB
0xBC
0xBD
VID_CONFIG
Selects the VID mode, sets the upper and lower voltage limits, and the starting voltage code at power-up.
VID_CODE_RAIL1 Selects the VID code used to set the output voltage for Rail 1.
VID_CODE_RAIL2 Selects the VID code used to set the output voltage for Rail 2.
(1) For a complete description of the serial VID commands, see the UCD92xx PMBus Command Reference (SLUU337)
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VOUT
TMSGVO
TMSG
TVO
Addr
Cmd
Data
PEC
Start
Stop
PMBus Clock
PMBus Data
ACK
ACK
ACK
ACK
Figure 8. PMBus Timing for VID_CODE_RAILn Command
Table 4. Typical PMBus Timing for VID_CODE_RAILn Command @ 400kHz
SYMBOL
PARAMETER
CONDITIONS
TYP
UNITS
TmsgPEC
Message Transmit Time, with PEC
Message Transmit Time, without PEC
End of message until Vout starts changing
Start of message until Vout start changing
400 kHz clock, PEC enabled
400 kHz clock, PEC enabled
162 – 256
126 – 221
28 – 140
169 – 314
µs
Tvo
µs
µs
Tmsgvo
400 kHz clock, PEC disabled
The total time to transmit the serial VID command will vary depending on the other tasks that the UCD92xx
processor is performing. Typical packet times varied from 162 to 256µs when the PMBus is configured for a 400
kb/s transfer rate running and the optional PEC byte is enabled. Disabling the PEC byte saves about 35µs and
the transfer times are from 126 to 221µs. Note that these are not specified best-case/worst-case timings, but
indicate a range given the typical acknowledge overhead in the host and controller.
After the VID packet has been received by the controller there is a delay before the set-point reference DAC is
updated. This delay time varies from ~28µs to 140µs (typical ) depending on the existing priority of updating set-
point reference DAC when the command is received.
With a 221µs packet transfer time, it would seem possible to send 4500 VID messages per second to the device.
Very short bursts at this rate might be acceptable, but doing so for sustained periods could overwhelm the
available processing resources in the UCD92xx, causing it to be delayed in performing its other monitoring and
fault response tasks. In addition, if multiple hosts are trying to talk on the PMBus at such high rates then bus
contention will occur with great regularity.
To prevent these issues, it is prudent to limit the total VID messaging rate to less than 4 messages per
millisecond. In a system with four independent hosts, each host might need to be limited to less than 1 message
per millisecond. Therefore, to minimize PMBus traffic, it is best to only issue the VID command when a voltage
change is required. There is no benefit to sending the same VID code continuously and repeatedly.
JTAG Interface
The JTAG interface can provide an alternate interface for programming the device. Two of the JTAG pins (TDI
and TDO) are shared with the SyncIn and SyncOut function. JTAG is disabled by default. There are three
conditions under which the JTAG interface is enabled:
1. When the ROM_MODE PMBus command is issued.
2. On power-up if the Data Flash is blank. This allows JTAG to be used for writing the configuration parameters
to a programmed device with no PMBus interaction.
3. When an invalid address is detected at power-up. By opening or shorting one of the address pins to ground,
an invalid address can be generated that enables JTAG.
When the JTAG port is enabled the shared pins are not available for use as Sync pins.
If JTAG is to be used, an external mechanism such as jumpers or a mux must be used to prevent conflict
between JTAG and the Sync pins.
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Bias Supply Generator (Shunt Regulator Controller)
The I/O and analog circuits in the UCD9222 require 3.3V to operate. This can be provided using a stand-alone
external 3.3V supply, or it can be generated from the main input supply using an internal shunt regulator and an
external transistor. Regardless of which method is used to generate the 3.3V supply, bypass capacitors of 0.1 µF
and 4.7 µF should be connected from V33A and V33D to ground near the device. An additional bypass capacitor
from 0.1 to 1 µF must be connected from the BPCap pin to ground for the internal 1.8V supply to the device’s
logic circuits.
Figure 9 shows a typical application using the external transistor. The base of the transistor is driven by a resistor
R1 to Vin and a transconductance amplifier whose output is on the V33FB pin. The NPN emitter becomes the
3.3V supply for the chip.
To Power Stage
Vin
FCX491A
+3.3V
4.7μ
0.1μ
R1
+1.8V
0.1μ
0.1μ
UCD9222
Figure 9. 3.3V Shunt Regulator Controller I/O
In order to generate the correct voltage on the base of the external pass transistor, the internal transconductance
amplifier sinks current into the V33FB pin and a voltage is produced across R1. This resistor value should be
chosen so that ISINK is in the range from 0.2 to 0.4mA. R1 is defined as
V - 3.3 - Vbe
in
R1 =
IE
+ISINK
b +1
( )
(1)
Where ISINK is the current into the V33FB pin; Vin is the power supply input voltage, typically 12V; IE is the current
draw of the device and any pull up resistors tied to the 3.3V supply; and β is the beta of the pass transistor. For
ISINK = 0.3 mA, Vin=12V, β=99, Vbe = 0.7V and IE=50mA, this formula selects R1 = 10kΩ. Weaker transistors or
larger current loads will require less resistance to maintain the desired ISINK current. For example, lowering β to
40 would require R1 = 5.23 kΩ; likewise, an input voltage of 5V requires a value of 1.24 kΩ for R1.
Power-On Reset
The UCD9222 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the
POR circuit detects the V33D rise. When V33D is greater than VRESET, the device initiates an internal startup
sequence. At the end of the startup sequence, the device begins normal operation, as defined by the
downloaded device PMBus configuration.
External Reset
The device can be forced into the reset state by an external circuit connected to the nRESET pin. A logic low
voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a 10kΩ pull up
resistor to 3.3V is recommended.
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ON_OFF_CONFIG
The ON_OFF_CONFIG command is used to select the method of turning rails on and off. It can be configured so
that the rail:
•
•
•
•
•
stays off,
turns on automatically,
responds to the PMBus_Cntrl pin,
responds to OPERATION command, or
responds to logical-AND of the PMBus_Cntrl pin and the OPERATION command.
The ON_OFF_CONFIG command also sets the active polarity of the PMBus_Cntrl pin.
EN1/EN2
In addition to the PMBus_Cntrl pin supported by all UCD92xx products, the UCD9222 also supports separate
Enable pins for each rail. The polarity of the EN1/EN2 pin is user-configurable, and will be the same as the
polarity chosen for the PMBus_Cntrl pin by the ON_OFF_CONFIG command. When the ON_OFF_CONFIG
setting is configured to respond the PMBus_Cntrl pin, the PMBus_Cntrl pin signal will be logically ANDed with
the rail’s EN pin signal.
PG1/PG2
In addition to the PowerGood output signal supported by all UCD92xx products, the UCD9222 also supports
separate PG indicators for each rail. The PowerGood signal is the logical-AND of all rails, while PG1 and PG2
indicate the status of a single rail. All three of these indicators are open-drain outputs, so they require pull-up
resistors. When driving external circuits with logic voltages less than 3.3V, the pull-ups may be tied to that lower
supply voltage, thus avoiding the need for level-shifters.
Output Voltage Adjustment
The output voltage may be set to maintain a steady voltage or it may be controlled dynamically by the VID
interface, depending on the VID_CONFIG setting. When not being commanded by the VID interface, the nominal
output voltage is programmed by a combination of PMBus settings: VOUT_COMMAND, VOUT_CAL_OFFSET,
VOUT_SCALE_LOOP, and VOUT_MAX. Their relationship is shown in Figure 10. These PMBus parameters
need to be set such that the resulting Vref DAC value does not exceed the maximum value of Vref.
Output voltage margining is configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands.
The OPERATION command selects between the nominal output voltage and either of the margin voltages. The
OPERATION command also includes an option to suppress certain voltage faults and warnings while operating
at the margin settings.
OPERATION Command
VOUT
VOUT_CAL_OFFSET
VOUT_MARGIN_HIGH
R1
VSense
3:1
Mux
VOUT_COMMAND
VOUT_MARGIN_LOW
VID_CODE_RAILx
4-wire VID interface
VOUT_MAX
R2
VOUT_
SCALE_
LOOP
3:1
Mux
Limiter
Vref DAC
eADC
+
+
VOUT_OV_FAULT_LIMIT
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
digital
compensator
VID_CONFIG
Figure 10. PMBus Voltage Adjustment Mechanisms
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For a complete description of the commands supported by the UCD9222 see the UCD92xx PMBUS Command
Reference (SLUU337). Each of these commands can also be issued from the Texas Instruments Fusion Digital
Power™ Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands
to configure the UCD9222 device.
Calibration
To optimize the operation of the UCD9222, PMBus commands are supplied to enable fine calibration of output
voltage, output current, and temperature measurements. The supported commands and related calibration
formulas may be found in the UCD92xx PMBUS Command Reference (SLUU337).
Analog Front End (AFE)
GAFE = 1, 2, 4, or 8
Vead
VEAP
VEAN
VEA
6-bit
result
EADC
GeADC = 8mV/LSB
Vref DAC
CPU
Vref = 1.563 mV/LSB
PMBus
Figure 11. Analog Front End Block Diagram
The UCD9222 senses the power supply output voltage differentially through the EAP and EAN pins. The error
amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage
sense signals. The fully differential nature of the error amplifier also ensures low offset performance.
The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus
command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then
transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by
the 10-bit Vref DAC as shown in Figure 11. The resulting error voltage is then amplified by a programmable gain
circuit before the error voltage is converted to a digital value by the error ADC (EADC). This programmable gain
is configured through the PMBus and affects the dynamic range and resolution of the sensed error voltage as
shown in Table 5. The internal reference gains and offsets are factory-trimmed at the 4x gain setting, so it is
recommended that this setting be used whenever possible.
Table 5. Analog Front End Resolution
AFE_GAIN for
PMBus Command
EFFECTIVE ADC
RESOLUTION (mV)
DIGITAL ERROR VOLTAGE
DYNAMIC RANGE (mV)
AFE Gain
0
1x
2x
4x
8x
8
4
2
1
–256 to 248
–128 to 124
–64 to 62
1
2 (Recommended)
3
–32 to 31
The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by
issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank
for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This
allows the user to trade-off resolution and dynamic range for each operational mode.
The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time.
However, its range is limited as shown in Table 5. If the output voltage is different from the reference by more
than this, the EADC repoºrts a saturated value at –32 LSBs or 31 LSBs. The UCD9222 overcomes this limitation
by adjusting the Vref DAC up or down in order to bring the error voltage out of saturation. In this way, the
effective range of the ADC is extended. When the EADC saturates, the Vref DAC is slewed at a rate of 0.156
V/ms, referred to the EA differential inputs.
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19
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ZHCSBS2 –OCTOBER 2013
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The differential feedback error voltage is defined as VEA = VEAP – VEAN. An attenuator network using resistors R1
and R2 (Figure 12) should be used to ensure that VEA does not exceed the maximum value of Vref when
operating at the commanded voltage level. The commanded voltage level is determined by the PMBus settings
described in the Output Voltage Adjustment section.
R1
EAP
+Vout
-Vout
C2
R2
Rin
Ioff
EAN
Figure 12. Input Offset Equivalent Circuit
Voltage Sense Filtering
Conditioning should be provided on the EAP and EAN signals. Figure 12 shows a divider network between the
output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output
voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the
signal conditioned by the low-pass filter formed by R1 and C2.
As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly
across an output capacitor as close to the load as possible. Route the positive and negative differential sense
signals as a balanced pair of traces or as a twisted pair cable back to the controller. Put the divider network close
to the controller. This ensures that there is low impedance driving the differential voltage sense signal from the
voltage rail output back to the controller. The resistance of the divider network is a trade-off between power loss
and minimizing interference susceptibility. A parallel resistance (Rp) of 1kΩ to 4kΩ is a good compromise. Once
RP is chosen, R1 and R2 can be determined from the following formulas.
RP
R1 =
K
RP
R2 =
1-K
VEA
where K =
@ VOUT_SCALE_LOOP
VOUT
(2)
It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an
additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter,
the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as:
1
C2 =
2p´0.35´FSW ´RP
(3)
To obtain the best possible accuracy, the input resistance and offset current on the device should be considered
when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the
UCD9222. The input resistance and input offset current are specified in the parametric tables in this datasheet.
VEA = VEAP – VEAN in the equation below.
R2
R1R2
VEA
=
VOUT
+
IOFFSET
æ
ç
ö
÷
ø
æ
ç
ö
÷
ø
R1R2
REA
R1R2
REA
R + R +
R + R +
1
2
1
2
è
è
(4)
The effect of the offset current can be reduced by making the resistance of the divider network low.
20
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Digital Compensator
Each voltage rail controller in the UCD9222 includes a digital compensator. The compensator consists of a
nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter
section cascaded with a first order IIR filter section.
The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the
compensator coefficients. The design tool allows the compensator to be described in terms of the pole
frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power™
Designer can be used to characterize the power stage so that the compensator coefficients can be chosen based
on the total loop gain for each feedback system. The coefficients of the filter sections are generated through
modeling the power stage and load.
Additionally, the UCD9222 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or
tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is
below the configured light load threshold.
Figure 13. Digital Compensator
To calculate the values of the digital compensation filter continuous-time design parameters KDC, FZ ands QZ are
entered into the Fusion Digital Power Designer software (or it calculates them automatically). Where the
compensating filter transfer function is
S2
s
+
+1
2
w
w QZ
Z
Z
H s = K
( )
DC
æ
ö
÷
ø
s
s
+1
ç
w
è
P2
(5)
There are approximate limits the design parameters KDC, FZ ands QZ. Though design parameters beyond these
upper a lower bounds can be used to calculate the discrete-time filter coefficients, there will be significant round-
off error when the continuous-time floating-point design parameters are converted to the discrete-time fixed-point
integer coefficients to be downloaded to the controller.
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APPROXIMATE
DESIGN PARAMETER
UNITS
LOWER BOUND
UPPER BOUND
KDC
FZ
60
3 kHz
0.1
103
Fsw/5
5.0
dB
kHz
n/a
QZ
The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from
zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and
Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to
be symmetrical. For example, the four limit registers could all be set to positive values causing the Gain 0 value
to set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.
The cascaded 1st order filter section is used to generate the third zero and third pole.
DPWM Engine
The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse
width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty
cycle as a digital number representing a percentage from 0 to 100%. The duty cycle value is multiplied by the
configured period to generate a comparator threshold value. This threshold is compared against the high speed
switching period counter to generate the desired DPWM pulse width. This is shown in Figure 14.
Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the SyncIn
and SyncOut pins. Configuration of the synchronization function is done through a MFR_SPECIFIC PMBus
command. See the DPWM Synchronization section for more details.
DPWM Engine (1 of 2)
Clk
SysClk
SyncIn
high res
ramp
reset counter
PWM gate drive output
S
R
Switch period
Current balance adj
Compensator output
EADC trigger
SyncOut
(Calculated duty cycle)
EADC trigger
threshold
Figure 14. DPWM Engine
Rail/Power Stage Configuration
Unlike many other products in the UCD92xx family, the UCD9222 does not support assigning power stages to
arbitrary rails, or combining multiple power stages on the same rail. The UCD9222 supports up to two single-
phase rails, and the channel number of each rail’s DPWM output must match that of its EAP/EAN feedback
inputs.
22
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DPWM Phase Synchronization
DPWM synchronization provides a method to link the timing between voltage rails controlled by the UCD92xx
device--either internally or between devices. The configuration of the synchronization between rails is performed
by the issuing the SYNC_CONFIG command. For details of issuing this command, see the UCD92xx PMBUS
Command Reference (SLUU337). The synchronization behavior can also be configured using the Fusion Digital
Power Designer software. Below is a summary of the function.
Each digital pulse width modulator (PWM) engine in the UCD92xx controller can accept a sync signal that resets
the PWM ramp generator. The ramp generator can be set to free-run, accept a reset signal from another internal
PWM engine, or accept a reset signal from the external SyncIn pin (UCD9222 only). In addition, each digital
PWM engine can generate a phase delayed sync signal that can be directed to another PWM reset input or
directed to the external SyncOut pin. In this way the PWM timers can be "daisy-chained" to set up the desired
phase relationship between power stages.
The PWM engine reset input can accept the following inputs
Table 6. Sync Trigger Inputs
None (free run)
DPWM 1
DPWM 2
SyncIn Pin
When configuring a PWM engine to run synchronous to another internal PWM output, set the switching
frequency of each PWM output to the same value using the FREQUENCY_SWITCH PMBus command. Set the
time point where the controller samples the voltage to be regulated by setting the EADC_SAMPLE_TRIGGER
value to the minimum value (228-240 nsec before the end of the switching period).
When configuring a PWM engine to run synchronous to run an external sync signal, the switching period must be
set to be longer than the period of the sync signal by setting the value of the FREQUENCY_SWITCH command
to be lower than the frequency of the sync signal. This way the external sync signal will reset the PWM ramp
counter before it is internally reset. In this operating condition, the error ADC sample trigger time must be set to:
1
0.95
EADC_SAMPLE_TRIGGER ³
-
+ 248ns
F
F
SW
sync
(6)
where FSW is the switching frequency set by FREQUENCY_SWITCH and Fsync is the minimum synchronization
frequency. The factor of 0.95 is due to the 5% tolerance on the internal clock in the controller. This will ensure
that the regulation voltage is sampled "just in time" to calculate the appropriate control effort for each switching
period. This is shown in Figure 15.
ADC sample = Period-EADC trigger
Early sync
Sync-in
EADC Threshold
Convert ADC
sample and
insufficient time
to convert ADC
sample
calculate
compensated
error
Compensated error
previous
control
effort
PWM pulse
Figure 15. Relationship of EADC Trigger to external Sync
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If two rails share a common sync source other than the SyncIn pin, they must have the same delay. When the
SyncIn pin is used as a sync source, the delay is applied using a different register (EV1) than when using the
other sources (which use the PhaseTrig registers). Using the EV1 register introduces delay in the control loop
calculation that will introduce phase loss that must be taken into consideration when calculating the loop
compensation. Therefore, under most conditions it will be desirable to set the delay to zero for the PWM signal
synchronized by the SyncIn pin.
Output Current Measurement
Pins CS1A and CS2A are used to measure either output current or inductor current in each of the controlled
power stages. PMBus commands IOUT_CAL_GAIN and IOUT_CAL_OFFSET are used to calibrate each
measurement. See the UCD92xx PMBus Command Reference (SLUU337) for specifics on configuring this
voltage to current conversion.
When the measured current is outside the range of either the over-current or under-current fault threshold, a
current limit fault is declared and the UCD9222 performs the PMBus configured fault recovery. ADC current
measurements are digitally averaged before they are compared against the over-current and under-current
warning and fault thresholds. The output current is measured at a rate of one output rail per tIout microseconds.
The current measurements are then passed through a digital smoothing filter to reduce noise on the signal and
prevent false errors. The output of the smoothing filter asymptotically approaches the input value with a time
constant that is approximately 3.5 times the sampling interval.
Table 7. Output Current Filter Time Constants
NUMBER OF
OUTPUT CURRENT
FILTER
OUTPUT RAILS
SAMPLING INTERVALS (µs)
TIME CONSTANT τ (ms)
1
2
200
400
0.7
1.4
This smoothed current measurement is used for output current fault detection; see the Over-current Detection
section. The smoothed current measurement is also reported in response to a PMBus request for a current
reading.
Current Sense Input Filtering
Each power stage current is monitored by the device at the CS pins. The device monitors the current with a 12-
bit ADC and also monitors the current with a digitally programmable analog comparator. The comparator can be
disabled by writing a zero to the FAST_OC_FAULT_LIMIT.
Because the current sense signal is both digitally sampled and compared to the programmable over-current
threshold, it should be conditioned with an RC network acting as an anti-alias filter. If the comparator is disabled,
the CS input should be filtered at 35% of the sampling rate. An RC network with this characteristic can be
calculated as
NrailsT
Iout
R = 0.45
C
(7)
where Nrails is the number of rails configured and TIout is the sample period for the current sense inputs.
Therefore, when the comparator is not used, the recommended component values for the RC network are C = 10
nF and R = 35.7 kΩ.
When the fast over-current comparator is used, the filter corner frequency based on the ADC sample rate may
be too slow and a corner frequency that is a compromise between the requirements of fast over-current detection
and attenuating aliased content in the sampled current must be sought. In this case, the filter corner frequency
can be calculated based on the time to cross the over-current threshold.
VOC_thres = VCS_nom + DVImon(1- e-t t
)
(8)
where VOC_thres is the programmed OC comparator threshold, VCS_nom is the nominal CS voltage, ΔVImon is the
change in CS voltage due to an over-current fault and τ is the filter time constant. Using the equation for the
comparator voltage above, the RC network values can be calculated as
24
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ZHCSBS2 –OCTOBER 2013
Tdet
1
R =
´
C
ln DV
(
- ln DVImon - VOC_thres + VCS_nom
(
)
)
Imon
(9)
where Tdet is the time to cross the over-current comparator threshold. For Tdet = 10 µs, ΔVImon = 1.5V, VOC_thres
=
2.0V and VCS_nom = 1.5V, the corner frequency is 6.4 kHz and the recommended RC network component values
are C = 10 nF and R = 2.49 kΩ.
Over-Current Detection
Several mechanisms are provided to sense output current fault conditions. This allows for the design of power
systems with multiple layers of protection.
1. Integrated gate drivers such as the UCD72xx family can be used to generate the FLT signal. The driver
monitors the voltage drop across the high side FET and if it exceeds a resistor/voltage programmed
threshold, the driver activates its fault output. A logic high signal on the FLT input causes a hardware
interrupt to the internal CPU, which then disables the DPWM output. This process takes about 14
microseconds.
2. Inputs CS1A and CS2A each drive an internal analog comparator. These comparators can be used to detect
the voltage output of a current sense circuit. Each comparator has a separate threshold that can be set by
the FAST_OC_FAULT_LIMIT PMBus command. Though the command is specified in amperes, the
hardware threshold is programmed with a value between 31mV and 2V in 64 steps. The relationship
between amperes to sensed volts is configured by the IOUT_CAL_GAIN command. When the current sense
voltage exceeds the threshold, the corresponding DPWM output is driven low on the voltage rail with the
fault.
3. Each Current Sense input to the UCD9222 is also monitored by the 12-bit ADC. Each measured value is
scaled using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands and then passed through a digital
smoothing filter. The smoothed current measurements are compared to fault and warning limits set by the
IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT commands. The action taken when an OC fault is
detected is defined by the IOUT_OC_FAULT_RESPONSE command.
Because the current measurement is averaged with a smoothing filter, the response time to an over-current
condition depends on a combination of the time constant (τ) from Table 7, the recent measurement history, and
how much the measured value exceeds the over-current limit. When the current steps from a current (I1) that is
less than the limit to a higher current (I2) that is greater than the limit, the output of the smoothing filter is
Ismoothed t = I + I -I 1- e-t t
( )
(
)
(
)
1
2
1
(10)
At the point when Ismoothed exceeds the limit, the smoothing filter lags time, tlag is
æ
ç
è
ö
÷
ø
I2 -I1
I2 -I
tlag = tln
limit
(11)
The worst case response time to an over-current condition is the sum of the sampling interval (Table 7) and the
smoothing filter lag, tlag from Equation 11.
Current Foldback Mode
When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the
UCD9222 attempts to continue to operate by reducing the output voltage in order to maintain the output current
at the value set by IOUT_OC_FAULT_LIMIT. This continues indefinitely as long as the output voltage remains
above the minimum value specified by IOUT_OC_LV_FAULT_LIMIT. If the output voltage is pulled down to less
than that value, the device responds as programmed by the IOUT_OC_LV_FAULT_RESPONSE command.
Input Voltage Monitoring
The VinMon pin on the UCD9222 monitors the input voltage. The VinMon pin is monitored using the internal 12-
bit ADC which has a dynamic range of 0 to 2.5V. The fault thresholds for the input voltage are set using the
VIN_OV_FAULT_LIMIT and VIN_UV_FAULT_LIMIT commands. The scaling for Vin is set using the
VIN_SCALE_MONITOR command.
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Input UV Lockout
The input supply lock-out voltage thresholds are configured with the VIN_ON and VIN_OFF commands. When
input supply voltage drops below the value set by VIN_OFF, the device starts a normal soft stop ramp. When the
input supply voltage drops below the voltage set by VIN_UV_FAULT_LIMIT, the device performs as configured
by the VIN_UV_FAULT_RESPONSE command. For example, when the bias supply for the controller is derived
from another source, the response code can be set to "Continue" or "Continue with delay," and the controller
attempts to finish the soft stop ramp. If the bias voltages for the controller and gate driver are uncertain below
some voltage, the user can set the UV fault limit to that voltage and specify the response code to be "shut down
immediately," disabling all DPWM outputs. VIN_OFF sets the voltage at which the output voltage soft-stop ramp
is initiated, and VIN_UV_FAULT_LIMIT sets the voltage where power conversion is stopped.
Temperature Monitoring
The UCD9222 monitors temperature using the 12-bit ADC. The ADC12 is read every 100us and combined into a
running sum. At the end of each 100ms monitoring interval, the ~1000 sample in the running sum are averaged
together and the running sum is restarted. These averaged values are used to calculate the temperature from
external temperature sensors. These same values may be read directly using the READ_AUX_ADCS PMBus
command.
The averaged values are passed through an additional digital smoothing filter to further reduce the chance of
reporting false over-temperature events. The smoothing filter has a time constant of 1.55 seconds.
Auxiliary ADC Input Monitoring
Unused external temperature sensor inputs may be used for general-purpose analog monitoring. The
READ_AUX_ADCS PMBus command returns a block of four 16-bit values, each of which is the average of
multiple raw measurements from the AuxADC inputs. These AuxADC inputs share usage with other signals such
as Temp1, Temp2, Vtrack, and IinMon. A value of 0 corresponds to 0.00V and a value of 65535 corresponds to
2.50V. Unlike many other variables that can be monitored via PMBus, no mechanism is provided for adjusting
the gain or offset of the Aux ADC measurements.
When using the temperature sensor inputs as Auxiliary ADCs, the temperature warning and faults should be
disabled to prevent shut-downs due to non-existent over-temperature conditions.
Soft Start, Soft Stop Ramp Sequence
The UCD9222 performs soft start and soft stop ramps under closed-loop control.
Performing a start or stop ramp or tracking is considered a separate operational mode. The other operational
modes are normal regulation and light load regulation. Each operational mode can be configured to have an
independent loop gain and compensation. Each set of loop gain coefficients is called a "bank" and is configured
using the CLA_GAINS PMBus command.
Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal
reference toward the commanded reference voltage at the rate specified by the TON_RISE time and
VOUT_COMMAND. The DPWM outputs are enabled when the internal ramp reference equals the preexisting
voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width specified by
DRIVER_MIN_PULSE. This ensures that a constant ramp rate is maintained, and that the ramp is completed at
the same time it would be if there had not been a pre-bias condition.
Figure 16 shows the operation of soft-start ramps and soft-stop ramps.
26
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UCD9222-EP
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ZHCSBS2 –OCTOBER 2013
Figure 16. Start and Stop Ramps
When a voltage rail is in its idle state, the DPWM outputs are disabled, and the differential voltage on the
EAP/EAN pins are monitored by the controller. During idle the Vref DAC is adjusted to match the feedback
voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the
start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is
required to match the measured voltage on the rail. Nominally this is calculated as Vout / Vin. If the pre-bias
voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the
DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage
has increased to the point where the required duty cycle exceeds the specified minimum duty.
Once a soft start/stop ramp has begun, the output is controlled by adjusting the Vref DAC at a fixed rate and
allowing the digital compensator control engine to generate a duty cycle based on the error. The Vref DAC
adjustments are made at a rate of 10 kHz and are based on the TON_RISE or TOFF_FALL PMBus configuration
parameters.
Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when
the DPWM signals become active, the time from when the controller starts processing the turn-on command to
the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or minimum duty
cycle.
During a normal ramp (i.e. no tracking, no current limiting events and no EADC saturation), the set point slews at
a pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the
compensator follows this ramp up to the regulation point.
Because the EADC in the controller has a limited range, it may saturate due to a large transient during a
start/stop ramp. If this occurs, the controller overrides the calculated set point ramp value, and adjusts the Vref
DAC in the direction to minimize the error. It continues to step the Vref DAC in this direction until the EADC
comes out of saturation. Once it is out of saturation, the start ramp continues, but from this new set point voltage;
and therefore, has an impact on the ramp time.
Non-volatile Memory Error Correction Coding
The UCD9222 uses Error Correcting Code (ECC) to improve data integrity and provide high reliability storage of
Data Flash contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written
into the Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array.
These extra check bits, along with the hardware ECC algorithm, allow for any single bit error to be detected and
corrected when the Data Flash is read.
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UCD9222-EP
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APPLICATION INFORMATION
Automatic System Identification ( Auto-ID™)
By using digital circuits to create the control function for a switch-mode power supply, additional features can be
implemented. One of those features is the measurement of the open loop gain and stability margin of the power
supply without the use of external test equipment. This capability is called automatic system identification or
Auto-ID™. To identify the frequency response, the UCD9222 internally synthesizes a sine wave signal and
injects it into the loop at the Vref DAC. This signal excites the system, and the closed-loop response to that
excitation can be measured at another point in the loop. The UCD9222 measures the response to the excitation
at the output of the digital compensator. From the closed-loop response, the open-loop transfer function is
calculated. The open-loop transfer function may be calculated from the closed-loop response.
Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be
divided out of the measured open-loop gain. In this way the UCD9222 can accurately measure the power
stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and
send the measurement data back to a host through the PMBus interface without the need for external test
equipment. Details of the Auto-ID™ PMBus measurement commands can be found in the UCD92xx PMBus
Command Reference (SLUU337).
Data Logging
The UCD9222 maintains a data log in non-volatile memory. This log tracks the peak internal and external
temperature sensor measurements, peak current measurements and fault history. The PMBus commands and
data format for the Data Logging can be found in the UCD92xx PMBus Command Reference (SLUU337).
28
Copyright © 2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCD9222WRGZREP
V62/13622-01XE
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 115
-55 to 115
UCD9222EP
UCD9222EP
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
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PACKAGE OUTLINE
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
A
7.1
6.9
B
(0.1) TYP
7.1
6.9
SIDE WALL DETAIL
OPTIONAL METAL THICKNESS
PIN 1 INDEX AREA
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
2X 5.5
5.15±0.1
(0.2) TYP
13
24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
SYMM
2X
5.5
1
36
0.30
0.18
PIN1 ID
(OPTIONAL)
48X
48
37
SYMM
0.1
C A B
C
0.5
0.3
48X
0.05
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
5.15)
SYMM
(
48X (0.6)
37
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
24
13
2X (1.065)
2X (1.26)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RGZ0048A
PLASTIC QUADFLAT PACK- NO LEAD
2X (6.8)
SYMM
(
1.06)
37
48X (0.6)
48
48X (0.24)
44X (0.5)
1
36
SYMM
2X
2X
(5.5)
(6.8)
2X
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
24
13
2X
(1.26)
2X (0.63)
2X (5.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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